Display panel and display terminal

Abstract

The invention relates to a display panel and a display terminal. The display panel comprises a substrate, a first metal layer and a second metal layer, the first metal layer comprises a scanning line and an electrode line which extend along a first direction; the second metal layer comprises a data line and a shared electrode line which extend along a second direction; the display panel comprises a plurality of sub-pixel groups, one sub-pixel group comprises at least two adjacent sub-pixels arranged in the first direction, the number of shared electrode wires in one sub-pixel group is smaller than that of the sub-pixels in the same sub-pixel group, and the shared electrode wires are electrically connected with electrode wires. According to the display panel, the number of the shared electrode wires in one sub-pixel group is set to be smaller than the number of the sub-pixels in the same sub-pixel group, so that the shared electrode wires of other sub-pixels in the sub-pixel group can be omitted, the aperture opening ratio of the display panel can be increased by omitting the shared electrode wires, and the light transmittance of the display panel can be increased.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display terminal. Background Art

[0002] As technology develops rapidly, future application scenarios are moving towards "display everywhere". Display products are no longer limited to traditional TV and computer screens, but are gradually penetrating into every corner of our lives, from the micro-displays of smart wearable devices, to the screens of smart home appliances in the home environment, to the ubiquitous electronic billboards in public areas. Display technology has become a key bridge connecting people and information. As a mature and widely used display technology, LCD occupies an important position in the field of large-size displays and has a huge market share.

[0003] With the rapid rise of the ESG (environmental, social and corporate governance) concept around the world, environmental protection and sustainable development have become the focus of attention in all walks of life. In the display field, higher requirements are placed on the energy efficiency of display panels. Higher energy efficiency means lower energy consumption and carbon emissions, which is in line with the concept of environmental protection. At the same time, it can also bring higher premium space for products and enhance the market competitiveness of products. The key to improving energy efficiency lies in improving the transmittance of the display panel. The higher the transmittance of the display panel, the lower the required backlight brightness can be when the whole machine reaches the same brightness, effectively saving power consumption.

[0004] Therefore, how to improve the light transmittance of a display panel is one of the technical problems that technicians in this field need to solve urgently. Summary of the invention

[0005] The embodiments of the present application provide a display panel and a display terminal to solve the technical problem of how to improve the light transmittance of the display panel.

[0006] In order to achieve the above object, according to a first aspect of the present application, a display panel is provided, comprising:

[0007] substrate;

[0008] A first metal layer is disposed on one side of the substrate, the first metal layer comprising scanning lines and electrode lines both extending along a first direction;

[0009] A second metal layer is disposed on a side of the first metal layer away from the substrate, the second metal layer comprising a data line and a shared electrode line both extending along a second direction;

[0010] Among them, the display panel includes a plurality of sub-pixel groups. One sub-pixel group includes at least two adjacent sub-pixels arranged along the first direction. The number of shared electrode lines in one sub-pixel group is less than the number of sub-pixels in the same sub-pixel group, and the shared electrode lines are electrically connected to the electrode lines.

[0011] Optionally, one sub-pixel group includes three adjacent sub-pixels arranged along the first direction. The shared electrode line is disposed within one of the sub-pixels, and the three sub-pixels share one shared electrode line.

[0012] Optionally, the first metal layer includes an extension portion connected to the electrode line. The extension portion is located on a side of the electrode line close to the scan line. The shared electrode line is connected to the electrode line through a first via hole, and a positive projection of the first via hole on the substrate is located within a positive projection of the extension portion on the substrate.

[0013] Optionally, the display panel includes a semiconductor layer disposed between the first metal layer and the second metal layer. The semiconductor layer includes a semiconductor portion covering a surface of the second metal layer close to the substrate.

[0014] Among them, the first metal layer includes a light-shielding portion. A positive projection of the shared electrode line on the substrate overlaps with a positive projection of the light-shielding portion on the substrate.

[0015] Optionally, a width of the light-shielding portion in the first direction is greater than a width of the shared electrode line in the first direction.

[0016] Optionally, the first metal layer includes an auxiliary portion. The auxiliary portion and the light-shielding portion are located in different sub-pixels.

[0017] The display panel further includes a pixel electrode layer disposed on a side of the second metal layer away from the substrate. The pixel electrode layer includes pixel electrodes corresponding to the sub-pixels.

[0018] Among them, the pixel electrode includes a main electrode extending along the second direction. Both the light-shielding portion and the auxiliary portion overlap with the main electrode.

[0019] Optionally, a width of the auxiliary portion in the first direction is less than a width of the main electrode in the first direction.

[0020] Optionally, the light-shielding portion includes a first sub-segment extending along the second direction and a second sub-segment extending along the first direction. The first sub-segment and the second sub-segment are connected. The auxiliary portion extends along the second direction.

[0021] Optionally, the sub-pixel includes at least a first transistor and a second transistor. The first transistor includes a first drain disposed on the second metal layer, and the second transistor includes a second drain disposed on the second metal layer;

[0022] The sub-pixel includes a main pixel region and a sub-pixel region arranged along the second direction, and the scanning line and the electrode line are disposed between the main pixel region and the sub-pixel region;

[0023] Wherein, the first drain and the pixel electrode corresponding to the main pixel region are electrically connected through a second via hole, the second drain and the pixel electrode corresponding to the sub-pixel region are electrically connected through a third via hole, and neither the second via hole nor the third via hole overlaps with the first metal layer.

[0024] Optionally, the first via hole, the second via hole, and the third via hole are arranged along the first direction.

[0025] Optionally, the sub-pixel includes a third transistor, and the third transistor includes a third source and a third drain disposed on the second metal layer;

[0026] The third source is connected to the second drain, and the third drain is connected to the shared electrode line.

[0027] Optionally, the pixel electrode layer includes a connection portion disposed in the first via hole. One surface of the connection portion close to the substrate contacts one surface of the shared electrode line far from the substrate, and one surface of the connection portion close to the substrate contacts the extension portion.

[0028] According to a second aspect of the present application, a display terminal is provided, including the above-mentioned display panel.

[0029] In the display panel of the embodiment of the present application, by setting the number of shared electrode lines in a sub-pixel group to be less than the number of sub-pixels in the same sub-pixel group, the shared electrode lines of other sub-pixels in the sub-pixel group can be omitted. Omitting the shared electrode lines can increase the aperture ratio of the display panel, and thus can increase the light transmittance of the display panel.

[0030] Other features and advantages of the present application will be described in detail in the subsequent specific implementation section. Description of the Drawings

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0032] To more fully understand the present application and its beneficial effects, the following description will be made in conjunction with the accompanying drawings, where the same reference numerals in the following description represent the same parts.

[0033] Figure 1 is a top-view structural schematic diagram of a display panel provided in an exemplary embodiment of the present disclosure;

[0034] Figure 2A is Figure 1 a partially enlarged structural schematic diagram of a pixel group in

[0035] Figure 2B is Figure 1 a cross-sectional structural schematic diagram of the display panel in

[0036] Figure 3A is Figure 2A a structural schematic diagram of a sub-pixel in the pixel group in

[0037] Figure 3B is Figure 3A a structural schematic diagram of the sub-pixel after adding a pixel electrode in

[0038] Figure 3C is Figure 3A an enlarged structural schematic diagram of multiple thin-film transistors in

[0039] Figure 3D is Figure 3B a cross-sectional structural schematic diagram at C-C in

[0040] Figure 3E is Figure 3B another cross-sectional structural schematic diagram at C-C in

[0041] Figure 3F is Figure 3B a decomposed structural schematic diagram of the film layer in

[0042] Figure 4A is Figure 2A a structural schematic diagram of another sub-pixel in the pixel group in

[0043] Figure 4B is Figure 4A a structural schematic diagram of the sub-pixel after adding a pixel electrode in

[0044] Figure 4C is Figure 4B a decomposed structural schematic diagram of the film layer in

[0045] Figure 5 is Figure 4A another structural schematic diagram of the sub-pixel in

[0046] Figure 6 is the equivalent circuit diagram of the storage capacitor provided in the exemplary embodiment of the present disclosure;

[0047] Figure 7 is a pixel architecture diagram provided in the exemplary embodiment of the present disclosure;

[0048] Figure 8 is a schematic structural diagram of a display terminal provided in the exemplary embodiment of the present disclosure.

[0049] Description of reference numerals:

[0050] 1 - display panel; AA - display area; NA - non - display area; 11 - sub - pixel group; 111 - sub - pixel; 11a - main pixel area; 11b - sub - pixel area;

[0051] 10 - substrate; 12 - counter substrate; 13 - liquid crystal layer; 14 - common electrode layer; 15 - color filter layer;

[0052] 20 - first metal layer; 21 - scan line; 22 - electrode line; 23 - extension; 24 - light - shielding part; 241 - first sub - segment; 242 - second sub - segment; 25 - auxiliary part; 26 - plate part; 261 - first plate part; 262 - second plate part;

[0053] 30 - second metal layer; 31 - data line; 32 - shared electrode line; 331a - first source; 331b - first drain; 332a - second source; 332b - second drain; 333a - third source; 333b - third drain;

[0054] 40 - semiconductor layer; 41 - semiconductor part; 42 - channel part;

[0055] 50 - pixel electrode layer; 51 - pixel electrode; 511 - main trunk electrode; 512 - branch electrode; 52 - connection part;

[0056] 60 - insulating layer;

[0057] T1 - first transistor; T2 - second transistor; T3 - third transistor;

[0058] HL1 - first via; HL2 - second via; HL3 - third via;

[0059] D1 - first direction; D2 - second direction;

[0060] w1 - width of the light - shielding part 24 in the first direction D1; w2 - width of the shared electrode line 32 in the first direction D1; w3 - width of the auxiliary part 25 in the first direction D1; w4 - width of the main trunk electrode 511 in the first direction D1;

[0061] 2 - Display terminal; 3 - Terminal body. Detailed implementation manners

[0062] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0063] To achieve the above object, according to the first aspect of the present application, as Figures 1 to 2B shown, a display panel 1 is provided, including a substrate 10, a first metal layer 20, and a second metal layer 30; the first metal layer 20 is disposed on one side of the substrate 10, and the first metal layer 20 includes a scan line 21 and an electrode line 22 both extending along a first direction D1; the second metal layer 30 is disposed on the side of the first metal layer 20 away from the substrate 10, and the second metal layer 30 includes a data line 31 and a common electrode line 32 both extending along a second direction D2; wherein, the display panel 1 includes a plurality of sub - pixel groups 11, a sub - pixel group 11 includes at least two adjacent sub - pixels 111 arranged along the first direction D1, the number of common electrode lines 32 in a sub - pixel group 11 is less than the number of sub - pixels 111 in the same sub - pixel group 11, and the common electrode line 32 is electrically connected to the electrode line 22.

[0064] The display panel 1 may be an LCD panel. The LCD panel is a non - self - emitting panel, and a backlight module is required to provide a backlight source for the display panel 1. The backlight source is a white planar light source. The display panel 1 may be any one of a vertical alignment (VA) type, a twisted nematic (TN) type, a super twisted nematic (STN) type, an in - plane switching (IPS) type, and a fringe field switching (FFS) type.

[0065] As Figure 2B shown, the display panel 1 includes a substrate 10 and a counter substrate 12 that are opposite and spaced apart, and a liquid crystal layer 13 is disposed between the substrate 10 and the counter substrate 12. By applying different electric fields to the liquid crystal molecules in the liquid crystal layer 13, their orientations are changed, thereby controlling the light transmittance of the display panel 1, and further controlling the brightness and darkness of the display screen.

[0066] A color filter layer 15 is provided on either the first substrate 10 or the counter substrate 12. The color filter layer 15 can convert the white light of the backlight module into colored light, thereby presenting a color image.

[0067] Specifically, the color filter layer 15 includes a red color resist, a green color resist, and a blue color resist. The red color resist only allows red light to pass through, the green color resist only allows green light to pass through, and the blue color resist only allows blue light to pass through. The white light source of the backlight module is converted into corresponding colored light after passing through the color filter layer 15, thereby presenting a color image.

[0068] In some embodiments, a light-shielding structure may be provided between two adjacent color resists of different colors. The light-shielding structure may be a black matrix or other light-shielding materials. The light-shielding structure blocks the transmission of light of various colors, and can reduce the light crosstalk between sub-pixels 111 of different colors.

[0069] As Figure 1 shown, the display panel 1 includes a display area AA and a non-display area NA provided on the periphery of the display area AA. The display area AA may be provided with a plurality of sub-pixels 111. The sub-pixels 111 may include red sub-pixels, green sub-pixels, and blue sub-pixels. The red sub-pixels generally correspond to the red color resist area, the green sub-pixels generally correspond to the green color resist area, and the blue sub-pixels generally correspond to the blue color resist area. The non-display area NA may be provided with a driving circuit, such as a gate driving circuit, etc. The driving circuit can provide driving signals for the sub-pixels 111.

[0070] In some embodiments, as Figure 2B shown, the first substrate 10 may be an array substrate, and the counter substrate 12 may be a color filter substrate. At this time, the driving circuit of the display panel 1 is provided on the first substrate 10, and the color filter layer 15 is provided on the counter substrate 12.

[0071] In some embodiments, the display panel 1 may be a COA (Color Filter On Array) panel. At this time, the driving circuit and the color filter layer 15 may both be provided on the first substrate 10.

[0072] In some embodiments, the substrate 10 may be a rigid substrate, such as a glass substrate, a quartz substrate, or a silicon wafer, etc.

[0073] In some embodiments, the substrate 10 may be a flexible substrate, such as one of polyimide (PI), polycarbonate (PC), polynorbornene (PNB), and polyethylene terephthalate (PET), etc.

[0074] As Figure 2AAs shown, the first metal layer 20 includes scan lines 21 that extend along the first direction D1; the second metal layer 30 includes data lines 31 that extend along the second direction D2. The scan lines 21 and the data lines 31 intersect to form a grid. One scan line 21 corresponds to a row of sub-pixels 111 arranged along the first direction D1, and one data line 31 corresponds to a column of sub-pixels 111 arranged along the second direction D2.

[0075] In some embodiments, both the first metal layer 20 and the second metal layer 30 are made of conductive materials, such as any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. The first metal layer 20 and the second metal layer 30 are non-transparent metals.

[0076] It should be noted that the aperture ratio of the display panel 1 refers to the ratio of the light-transmitting portion in the sub-pixel 111 to the area of the sub-pixel 111. Among them, the sub-pixel 111 includes a light-transmitting portion and a non-light-transmitting portion. The light-transmitting portion is the portion that allows light to pass through, and the material of the light-transmitting portion can be a transparent metal oxide, etc. The non-light-transmitting portion is the portion that does not allow light to pass through, and the material of the non-light-transmitting portion can be a non-transparent metal, etc.

[0077] In order to increase the aperture ratio of the display panel 1, it is necessary to increase the area of the light-transmitting portion in the sub-pixel 111 and reduce the area of the non-light-transmitting portion in the sub-pixel 111. Increasing the aperture ratio can increase the light transmittance of the display panel 1.

[0078] The first metal layer 20 further includes electrode lines 22 that can be connected to a fixed voltage signal, and the electrode lines 22 are used to provide a common voltage for multiple sub-pixels 111.

[0079] The second metal layer 30 further includes a shared electrode line 32 (Sharebar) that can be connected to a fixed voltage signal, and the shared electrode line 32 can provide a common voltage for the sub-pixels 111.

[0080] It should be understood that, as Figure 2B shown, an insulating layer 60 is provided between the first metal layer 20 and the second metal layer 30 to achieve insulation between the two metal materials. When the pattern of the first metal layer 20 needs to be conducted with the pattern of the second metal, it can be achieved through vias that penetrate the insulating layer 60, and a conductive material can be deposited in the vias.

[0081] In some embodiments, the material of the insulating layer 60 can be silicon oxide, silicon nitride, silicon oxynitride, etc.

[0082] As Figure 2AAs shown, both the scan line 21 and the electrode line 22 extend along the first direction D1. The scan line 21 can be arranged adjacent to the electrode line 22. The data line 31 and the shared electrode line 32 both extend along the second direction D2. The electrode line 22 and the shared electrode line 32 intersect to form a grid.

[0083] In some embodiments, the first direction D1 and the second direction D2 form an acute or right angle. In this application, a right angle is taken as an example for illustration, and it should not be construed as a limitation on the embodiments of this application.

[0084] The display panel 1 can adopt a liquid crystal panel with a multi-domain display technology. The multi-domain display technology can reduce the large viewing angle color shift of the liquid crystal panel. In the multi-domain display technology, each sub-pixel 111 includes a main pixel region 11a and a sub-pixel region 11b. The shared electrode line 32 can provide a suitable driving signal for the liquid crystal molecules in the sub-pixel region 11b, adjust the arrangement state of the liquid crystal molecules, and thus control the intensity and direction of light passing through the liquid crystal layer 13, reduce the large viewing angle color shift of the display panel 1, and improve the display effect.

[0085] As Figure 1 and Figure 2A shown, the display panel 1 includes a plurality of sub-pixel groups 11. A sub-pixel group 11 includes at least two adjacent sub-pixels 111 arranged along the first direction D1. For example, a sub-pixel group 11 can include two adjacent sub-pixels 111, three sub-pixels 111, four sub-pixels 111, etc. As Figure 2A shows a case where a sub-pixel group 11 includes three adjacent sub-pixels 111. The light-emitting color of the sub-pixels 111 in a sub-pixel group 11 can be any color.

[0086] As Figure 2A shown, the number of shared electrode lines 32 in a sub-pixel group 11 is less than the number of sub-pixels 111 in the same sub-pixel group 11. That is to say, there is at least one sub-pixel 111 in a sub-pixel group 11 that does not have a shared electrode line 32. The shared electrode line 32 is electrically connected to the electrode line 22, that is, the shared electrode line 32 and the electrode line 22 are connected to the same fixed voltage signal. Since there is at least one sub-pixel 111 in a sub-pixel group 11 that does not have a shared electrode line 32, some shared electrode lines 32 are omitted. Through the above arrangement, the area of the non-light-transmitting part of the sub-pixel 111 can be reduced, thereby improving the aperture ratio of the display panel 1, and further improving the light transmittance of the display panel 1.

[0087] In some embodiments, a sub-pixel group 11 includes two adjacent sub-pixels 111 arranged along the first direction D1. At this time, a sub-pixel group 11 is provided with only one shared electrode line 32. The shared electrode line is located within one of the sub-pixels 111, and the two sub-pixels 111 share one shared electrode line 32.

[0088] In some other embodiments, a sub-pixel group 11 includes three adjacent sub-pixels 111 arranged along the first direction D1. At this time, a sub-pixel group 11 may be provided with a shared electrode line 32, and the shared electrode line 32 is located within one of the sub-pixels 111, and the three sub-pixels 111 share one shared electrode line 32.

[0089] In some other embodiments, a sub-pixel group 11 includes three adjacent sub-pixels 111 arranged along the first direction D1. At this time, a sub-pixel group 11 may be provided with two shared electrode lines 32, and the two shared electrode lines 32 are respectively located within two different sub-pixels 111. The three sub-pixels 111 share two shared electrode lines 32.

[0090] In some other embodiments, the number of sub-pixels 111 arranged along the first direction D1 in a sub-pixel group 11 and the number of shared electrode lines 32 may also be set as required.

[0091] Optionally, as Figure 3A shown, Figure 3A is Figure 2A a schematic structural diagram of a sub-pixel 111 in the pixel group 11 in Figure 3A , and the sub-pixel 111 in

[0092] is the sub-pixel 111 corresponding to the shared electrode line 32. The first metal layer 20 includes an extension 23 connected to the electrode line 22. The extension 23 is located on the side of the electrode line 22 close to the scanning line 21. The shared electrode line 32 is connected to the electrode line 22 through a first via hole HL1, and the orthographic projection of the first via hole HL1 on the substrate 10 is located within the orthographic projection of the extension 23 on the substrate 10. Figure 3F As

[0093] shown, Figure 3A , Figure 3D and Figure 3F shown, Figure 3D shows Figure 3A a cross-sectional view at the first via hole HL1 in

[0094] Optionally, please refer to Figure 2B and Figure 3F, the display panel 1 includes a semiconductor layer 40 disposed between a first metal layer 20 and a second metal layer 30. The semiconductor layer 40 includes a semiconductor portion 41 covering a surface of the second metal layer 30 close to the substrate 10. Among them, the first metal layer 20 includes a light-shielding portion 24, and the orthographic projection of the shared electrode line 32 on the substrate 10 overlaps with the orthographic projection of the light-shielding portion 24 on the substrate 10.

[0095] In some embodiments, the material of the semiconductor layer 40 may be amorphous silicon, low-temperature polycrystalline silicon, metal oxide semiconductor, etc.

[0096] As Figure 2B and Figure 3F shown, the semiconductor layer 40 is disposed between the first metal layer 20 and the second metal layer 30. The semiconductor layer 40 includes a semiconductor portion 41. The semiconductor portion 41 can be formed by the same patterning process as the second metal layer 30, thereby reducing the number of photomasks and lowering the manufacturing cost of the display panel 1. That is to say, the second metal layer 30 and the semiconductor portion 41 have the same pattern. Specifically, the semiconductor portion 41 is disposed on one side of both the data line 31 and the shared electrode line 32 close to the substrate 10.

[0097] Since the semiconductor portion 41 leaks electricity when irradiated by the light source of the backlight module, the leakage will affect the storage capacitor of the display panel 1 and make the potential of the display panel 1 unstable, which will cause display unevenness (Mura) of the display panel 1. To improve this problem, a light-shielding portion 24 can be disposed on one side of the semiconductor portion 41 close to the substrate 10. The light-shielding portion 24 is a non-transparent material.

[0098] As Figure 3A shown, the orthographic projection of the light-shielding portion 24 on the substrate 10 overlaps with the orthographic projection of the shared electrode line 32 on the substrate 10, so that the light-shielding portion 24 can at least block part of the light incident from the backlight module from irradiating the shared electrode line 32.

[0099] In some embodiments, the light-shielding portion 24 can be made of the material of the first metal layer 20, thereby reducing the number of photomasks of the display panel 1 and simplifying the manufacturing process of the display panel 1.

[0100] As Figure 2B and Figure 3F shown, the semiconductor layer 40 further includes a channel portion 42, and the channel portion 42 serves as the active portion of the thin-film transistor in the driving circuit.

[0101] Optionally, as Figure 2AAs shown, the width w1 of the light-shielding portion 24 in the first direction D1 is greater than the width w2 of the shared electrode line 32 in the first direction D1. With the above arrangement, the size of the light-shielding portion 24 in the first direction D1 can be increased, so that the light-shielding portion 24 completely shields the shared electrode line 32 in the first direction D1, preventing the light incident from the backlight module from hitting the shared electrode line 32.

[0102] In some embodiments, as Figure 2A shown, the width w1 of the light-shielding portion 24 in the first direction D1 is larger than the width w2 of the shared electrode line 32 in the first direction D1. For example, the unilateral width of the light-shielding portion 24 and the shared electrode line 32 is greater than or equal to 0.5 microns. For example, the unilateral width of the light-shielding portion 24 and the shared electrode line 32 is 0.5 microns, 0.6 microns, 0.7 microns, 0.8 microns, 0.9 microns, 1.0 microns, 1.1 microns, 1.2 microns, etc. Herein, the unilateral width refers to the distance between the left boundary of the light-shielding portion 24 and the left boundary of the shared electrode line 32, or the distance between the right boundary of the light-shielding portion 24 and the right boundary of the shared electrode line 32. The left and right sides are on both sides of the center line of the shared electrode line 32. In Figure 3A the center line of the shared electrode line 32 extends along the second direction D2. The width direction of the shared electrode line 32 is perpendicular to the extension direction of the shared electrode line 32.

[0103] In some embodiments, the unilateral width of the light-shielding portion 24 and the shared electrode line 32 is 1.2 microns to 1.8 microns. For example, the unilateral width of the light-shielding portion 24 and the shared electrode line 32 is 1.2 microns, 1.3 microns, 1.4 microns, 1.5 microns, 1.6 microns, 1.7 microns, 1.8 microns, etc.

[0104] Optionally, as Figure 3A 、 Figure 3B 、 Figure 4A and Figure 4B shown, Figure 4A is Figure 2A a schematic structural diagram of a sub-pixel 111 in a pixel group 11 in

[0105] As Figure 3F and Figure 4CAs shown, the first metal layer 20 includes an auxiliary portion 25, that is, both the auxiliary portion 25 and the light-shielding portion 24 are located in the first metal layer 20, and the two are formed by the same patterning process.

[0106] As Figure 2A shown, the auxiliary portion 25 and the light-shielding portion 24 are located in different sub-pixels 111. That is to say, the light-shielding portion 24 is located in one sub-pixel 111 of the sub-pixel group 11, and the light-shielding portion 24 and the shared electrode line 32 are located in the same sub-pixel 111. The auxiliary portion 25 is located in another sub-pixel 111 of the same sub-pixel group 11.

[0107] It should be noted that since there is no shared electrode line 32 in the sub-pixel 111 where the auxiliary portion 25 is located, the auxiliary portion 25 is not used to shield the shared electrode line 32. The auxiliary portion 25 can form a capacitor with the pixel electrode 51, so that the capacitance value of the storage capacitor of the sub-pixel 111 meets the requirements.

[0108] It should be understood that in some embodiments, when it is necessary to reduce the storage capacitor of the sub-pixel 111, the area of the auxiliary portion 25 can also be reduced, or even the auxiliary portion 25 can be omitted. As Figure 5 shown, the structure of the sub-pixel 111 when the auxiliary portion 25 is omitted is shown.

[0109] As Figure 2B 、 Figure 3B and Figure 4B shown, the pixel electrode layer 50 is provided with pixel electrodes 51 corresponding to the sub-pixels 111, and the area of the pixel electrodes 51 roughly corresponds to the area of the color resist. The pixel electrodes 51 provide pixel voltages for the liquid crystal molecules in the sub-pixels 111. The display panel 1 further includes a common electrode layer 14, and the common electrode layer 14 provides a common voltage for the liquid crystal molecules in the sub-pixels 111. The liquid crystal molecules deflect in the electric field formed by the pixel voltage and the common voltage. By controlling the magnitude of the pixel voltage, the deflection angle of the liquid crystal molecules can be controlled, so as to control the transmission and blocking of light, and further control the brightness of the display screen.

[0110] The pixel electrode layer 50 is a transparent material, such as a transparent metal oxide, etc. The transparent metal oxide includes ITO (indium tin oxide), IZO (indium zinc oxide), IZTO (indium zinc tin oxide), IAZO (indium aluminum zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin oxide), AZO (aluminum zinc oxide), ATO (antimony tin oxide), IGZTO (indium gallium zinc tin oxide), IGO (indium gallium oxide), InO (indium oxide), etc.

[0111] Since the pixel electrode layer 50 is a transparent material, the area corresponding to the pixel electrode 51 is a light-transmitting portion.

[0112] In some embodiments, such asFigure 3B and Figure 4B As shown in Figure 4B , the pixel electrode 51 includes a main electrode 511 extending along the second direction D2 and branch electrodes 512. The branch electrodes 512 are connected to the main electrode 511 and extend away from the main electrode 511. A slit is formed between two adjacent branch electrodes 512. The extending directions of the branch electrodes 512 of the same pixel electrode 51 can be different, forming a multi-domain display technology.

[0113] The light-shielding portion 24 and the auxiliary portion 25 may overlap with the main electrode 511. That is to say, the orthographic projection of the light-shielding portion 24 on the substrate 10 overlaps with the orthographic projection of the main electrode 511 on the substrate 10, and the orthographic projection of the auxiliary portion 25 on the substrate 10 overlaps with the orthographic projection of the main electrode 511 on the substrate 10. Through the above arrangement, it is possible to prevent the light-shielding portion 24 and the auxiliary portion 25 from overlapping with the branch electrodes 512 and affecting the deflection of liquid crystal molecules.

[0114] Optionally, as shown in Figure 4A and Figure 4B , the width w3 of the auxiliary portion 25 in the first direction D1 is smaller than the width w4 of the main electrode 511 in the first direction D1. Through the above arrangement, it is possible to prevent the auxiliary portion 25 from exceeding the main electrode 511 and blocking the branch electrodes 512, thus affecting the deflection of the liquid crystal molecules corresponding to the branch electrodes 512.

[0115] In some embodiments, the width w3 of the auxiliary portion 25 in the first direction D1 is 1.5 micrometers to 8 micrometers. For example, the width w3 of the auxiliary portion 25 in the first direction D1 is 1.5 micrometers, 2.0 micrometers, 2.5 micrometers, 3.0 micrometers, 3.5 micrometers, 4.0 micrometers, 4.5 micrometers, 5.0 micrometers, 5.5 micrometers, 6.0 micrometers, 6.5 micrometers, 7.0 micrometers, 7.5 micrometers, 8.0 micrometers, etc.

[0116] In some embodiments, as shown in Figure 5 , when it is necessary to reduce the capacitance value of the storage capacitor, the auxiliary portion 25 can be omitted, that is, the auxiliary portion 25 is not provided.

[0117] Optionally, as shown in Figure 3A , Figure 3B and Figure 3F , the light-shielding portion 24 includes a first sub-segment 241 extending along the second direction D2 and a second sub-segment 242 extending along the first direction D1. The first sub-segment 241 and the second sub-segment 242 are connected, and the auxiliary portion 25 extends along the second direction D2.

[0118] Both the first sub-segment 241 and the second sub-segment 242 overlap with the shared electrode line 32. Through the above arrangement, it is possible to make the light-shielding portion 24 block more shared electrode lines 32 and reduce the light incident from the backlight module onto the shared electrode lines 32. ​​​​​​​​​​​​

[0119] In some embodiments, such as Figure 3A , Figure 3F , Figure 4A and Figure 4C shown, the first metal layer 20 is further provided with a plate portion 26 corresponding to the edge of the pixel electrode 51. The plate portion 26 may be in a frame shape, and the plate portion 26 is connected to the electrode line 22. The plate portion 26 can form a capacitor with the pixel electrode 51 to adjust the capacitance value of the storage capacitor of the sub-pixel 111. When it is necessary to increase the capacitance value of the storage capacitor, the area of the plate portion 26 can be increased; when it is necessary to decrease the capacitance value of the storage capacitor, the area of the plate portion 26 can be decreased.

[0120] In some embodiments, the plate portion 26 includes a first plate portion 261 corresponding to the main pixel region 11a and a second plate portion 262 corresponding to the sub-pixel region 11b. The first plate portion 261 is arranged corresponding to the contour line of the pixel electrode 51 in the main pixel region 11a. The second plate portion 262 is arranged corresponding to the contour line of the pixel electrode 51 in the sub-pixel region 11b. Along the first direction D1, the first plate portions 261 of two adjacent sub-pixels 111 are connected, and the second plate portions 262 of two adjacent sub-pixels 111 are connected. Through the above arrangement, the electrode line 22 can form a vertically and horizontally connected network structure in the entire display panel 1.

[0121] Optionally, as Figure 3A , Figure 3C and Figure 4A shown, the sub-pixel 111 at least includes a first transistor T1 and a second transistor T2. The first transistor T1 includes a first drain 331b disposed on the second metal layer 30, and the second transistor T2 includes a second drain 332b disposed on the second metal layer 30; the sub-pixel 111 includes a main pixel region 11a and a sub-pixel region 11b arranged along the second direction D2, and the scan line 21 and the electrode line 22 are disposed between the main pixel region 11a and the sub-pixel region 11b; wherein, the first drain 331b and the pixel electrode 51 corresponding to the main pixel region 11a are electrically connected through a second via hole HL2, and the second drain 332b and the pixel electrode 51 corresponding to the sub-pixel region 11b are electrically connected through a third via hole HL3, and both the second via hole HL2 and the third via hole HL3 do not overlap with the first metal layer 20.

[0122] In some embodiments, the sub-pixel 111 of the display panel 1 can be a multi-domain structure. The multi-domain structure means that the sub-pixel 111 of the display panel 1 includes multiple domain regions, and the branch electrodes 512 of each domain region extend in different directions, thereby reducing the large viewing angle color shift of the liquid crystal panel. For example, the display panel 1 can be an 8-domain structure.

[0123] Each sub-pixel 111 includes a main pixel region 11a and a sub-pixel region 11b arranged along the second direction D2. The scan line 21 and the electrode line 22 are disposed between the main pixel region 11a and the sub-pixel region 11b. The first transistor T1 is configured to control the pixel voltage of the pixel electrode 51 in the main pixel region 11a, and the second transistor T2 is configured to control the pixel voltage of the pixel electrode 51 in the sub-pixel region 11b.

[0124] It should be noted that both the first transistor T1 and the second transistor T2 are thin film transistors. The thin film transistor includes structures such as a gate, a source, a drain, and an active portion. The gate is located in the first metal layer 20, the source and the drain are located in the second metal layer 30, and the active portion is located in the semiconductor layer 40.

[0125] Specifically, Figure 7 is a pixel architecture diagram provided in an exemplary embodiment of the present disclosure. For the connection manner of the first transistor T1 and the second transistor T2, please refer to Figure 7 . The data line 31 is used to transmit the Data signal, and the scan line 21 is used to transmit the Gate signal. The pixel electrode 51 in the main pixel region 11a forms a liquid crystal capacitor C with the common electrode layer 14 lc_main . The pixel electrode 51 in the main pixel region 11a forms a storage capacitor C with the first plate portion 261 st_main . The pixel electrode 51 in the sub-pixel region 11b forms a liquid crystal capacitor C with the common electrode layer 14 lc_sub . The pixel electrode 51 in the sub-pixel region 11b forms a storage capacitor C with the second plate portion 262 st_sub . The pixel voltage in the main pixel region 11a is V main pixel , and the pixel electrode 51 in the sub-pixel region 11b is V sub pixel . A com is the voltage of the electrode line 22, and CF Com is the voltage of the common electrode layer 14. The first transistor T1 includes a first gate, a first source 331a, a first drain 331b, and a first active portion. The first source 331a is connected to the data line 31 (Data), and the first drain 331b can be electrically connected to the pixel electrode 51 corresponding to the main pixel region 11a through the second via hole HL2. The data signal input from the data line 31 (Data) is input to the pixel electrode 51 corresponding to the main pixel region 11a through the first transistor T1, thereby controlling the deflection of the liquid crystal molecules in the main pixel region 11a. The first gate is disposed on the same layer as the scan line 21 and is connected.

[0126] As Figure 3CAs shown, the second transistor T2 includes a second gate, a second source 332a, a second drain 332b, and a second active portion. The second gate is on the same layer as the scan line 21 and is connected thereto. The second source 332a is connected to the first source 331a, and the second drain 332b is electrically connected to the pixel electrode 51 corresponding to the sub-pixel region 11b through a third via hole HL3. The data signal input from the data line 31 (Data) is input to the pixel electrode 51 corresponding to the pixel region through the second transistor T2, thereby controlling the deflection of the liquid crystal molecules in the sub-pixel region 11b.

[0127] It should be understood that both the second via hole HL2 and the third via hole HL3 pass through the insulating layer 60 disposed between the first metal layer 20 and the second metal layer 30.

[0128] As Figure 3A and Figure 4A shown, neither the second via hole HL2 nor the third via hole HL3 overlaps with the first metal layer 20. That is to say, the orthographic projection of the second via hole HL2 on the substrate 10 is located outside the orthographic projection of the first metal layer 20 on the substrate 10, and the orthographic projection of the third via hole HL3 on the substrate 10 is located outside the orthographic projection of the first metal layer 20 on the substrate 10. Through the above arrangement, at the second via hole HL2, the first metal layer 20 and the second metal layer 30 do not overlap, so that a storage capacitor is not formed. At the third via hole HL3, the first metal layer 20 and the second metal layer 30 do not overlap, so that a storage capacitor is not formed. By not forming a storage capacitor, the capacitance value of the storage capacitor of the sub-pixel 111 can be reduced, the leakage of the storage capacitor can be reduced, and the display effect of the display panel 1 can be improved.

[0129] As Figure 6 shown, Figure 6 is an equivalent circuit diagram of the storage capacitor provided in the exemplary embodiment of the present disclosure. As Figure 3F and Figure 4C shown, since a semiconductor portion 41 is provided on the surface of the second metal layer 30 (M2) close to the substrate 10, two discharge circuits are formed when the first metal layer 20 (M1), the semiconductor portion 41, and the second metal layer 30 (M2) overlap. Among them, the second metal layer 30 (M2) and the semiconductor portion 41 form a discharge circuit, and the discharge circuit includes a capacitor (C a-Si ).) and a resistor (R a-Si) ). The first metal layer 20 (M1) and the insulating layer 60 form another discharge circuit, and the discharge circuit includes a capacitor (C SiNx ).) and a resistor (R SiNx ).

[0130] The inventor found in experiments that when the semiconductor part 41 (such as amorphous silicon) is irradiated by light, it will leak electricity, and the current in the discharge circuit of the semiconductor part 41 is large, resulting in the storage capacitor being unable to maintain the potential of the pixel voltage well, causing the pixel voltage to be unstable and resulting in uneven display. Therefore, in this application, the pattern of the first metal layer 20 at the second via hole HL2 is cancelled, so as to prevent the first metal layer 20 and the second metal layer 30 from forming a storage capacitor at the second via hole HL2.

[0131] Optionally, as Figure 3A and Figure 4A shown, the first via hole HL1, the second via hole HL2 and the third via hole HL3 are arranged along the first direction D1. Through the above setting, it is possible to avoid increasing the distance between the pixel electrode 51 corresponding to the main pixel area 11a and the pixel electrode 51 corresponding to the sub-pixel area 11b, thereby reducing the area of the non-transmissive part and improving the aperture ratio of the display panel 1.

[0132] Optionally, as Figure 3A 、 Figure 3C and Figure 4A shown, the sub-pixel 111 includes a third transistor T3, and the third transistor T3 includes a third source electrode 333a and a third drain electrode 333b provided on the second metal layer 30; the third source electrode 333a is connected to the second drain electrode 332b, and the third drain electrode 333b is connected to the shared electrode line 32.

[0133] As Figure 7 shown, the display panel 1 includes a first transistor T1, a second transistor T2 and a third transistor T3, that is, the display panel 1 is a 3T pixel architecture. Among them, the third transistor T3 is a shared transistor, the third source electrode 333a is connected to the second drain electrode 332b, and the third drain electrode 333b is connected to the shared electrode line 32. By connecting the third transistor T3 to the electrode line 22, the voltage of the electrode line 22 for the pixel electrode 51 corresponding to the sub-pixel area 11b can be divided, so that the display brightness of the sub-pixel area 11b is lower than that of the main pixel area 11a. That is to say, the third transistor T3 can realize the voltage difference between the pixel electrode 51 of the main pixel area 11a and the pixel electrode 51 of the sub-pixel area 11b, so that the liquid crystal molecules in the main pixel area 11a and the liquid crystal molecules in the sub-pixel area 11b can achieve different deflection angles, thereby reducing the viewing angle deviation of the display panel 1 and achieving a better display effect.

[0134] Optionally, as Figure 3D and Figure 3FAs shown, the pixel electrode layer 50 includes a connection portion 52 disposed within the first via hole HL1. One surface of the connection portion 52 close to the substrate 10 is in contact with one surface of the shared electrode line 32 away from the substrate 10, and one surface of the connection portion 52 close to the substrate 10 is in contact with the extension portion 23. That is to say, the extension portion 23 located in the first metal layer 20 and the shared electrode line 32 located in the second metal layer 30 are connected through the connection portion 52 located in the pixel electrode layer 50.

[0135] Specifically, the first via hole HL1 exposes part of the shared electrode line 32 and part of the extension portion 23 at the same time. The connection portion 52 is located within the first via hole HL1. The connection portion 52 is in contact with the exposed shared electrode line 32, and the connection portion 52 is in contact with the exposed extension portion 23. Through the above arrangement, the first via hole HL1 can be formed in a semi-overlapping hole form, thereby reducing the occupied area of the first via hole HL1 and improving the aperture ratio of the display panel 1.

[0136] In some other embodiments, as Figure 3E shown, the shared electrode line 32 can be electrically connected to the extension portion 23 in a deep and shallow hole form. Specifically, the deep and shallow hole form includes two via holes. One of the via holes is a deep hole that exposes the extension portion 23, and the other via hole is a shallow hole that exposes the shared electrode line 32. The connection portion 52 is deposited in the deep hole and the shallow hole, and the connection portion 52 between the deep hole and the shallow hole is continuously arranged, so as to connect the shared electrode line 32 and the extension portion 23 through the connection portion 52. Compared with the semi-overlapping hole form, the via holes in the deep and shallow hole form require more occupied area.

[0137] According to the second aspect of the present application, as Figure 8 shown, a display terminal 2 is provided, including the above-mentioned display panel 1.

[0138] In this embodiment, as Figure 8 shown, the display terminal 2 includes a display panel 1 and a terminal body 3, and the display panel 1 and the terminal body 3 are combined into one.

[0139] In this embodiment, the display terminal 2 can be: any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0140] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.

[0141] In the above embodiments, the descriptions of the respective embodiments each have their own focuses. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0142] Among the embodiments, implementation manners and related technical features of the present application, they can be combined and replaced with each other without conflict.

[0143] The above are only the preferred embodiments of the present application, and do not impose any form of limitation on the present application. However, any simple modifications, equivalent changes and decorations made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A display panel (1), characterized in that: include: base(10); A first metal layer (20) is disposed on one side of the substrate (10), the first metal layer (20) comprising scanning lines (21) and electrode lines (22) both extending along a first direction (D1); A second metal layer (30) is arranged on a side of the first metal layer (20) facing away from the substrate (10), the second metal layer (30) comprising a data line (31) and a shared electrode line (32) both extending along a second direction (D2); The display panel (1) comprises a plurality of sub-pixel groups (11), one of the sub-pixel groups (11) comprises at least two adjacent sub-pixels (111) arranged along the first direction (D1), the number of the shared electrode lines (32) in one of the sub-pixel groups (11) is less than the number of the sub-pixels (111) in the same sub-pixel group (11), and the shared electrode lines (32) are electrically connected to the electrode lines (22).

2. The display panel (1) according to claim 1, characterized in that: A sub-pixel group (11) comprises three adjacent sub-pixels (111) arranged along the first direction (D1), the shared electrode line (32) is arranged in one of the sub-pixels (111), and the three sub-pixels (111) share one shared electrode line (32).

3. The display panel (1) according to claim 1, characterized in that: The first metal layer (20) comprises an extension portion (23) connected to the electrode line (22), the extension portion (23) being located on a side of the electrode line (22) close to the scanning line (21), the shared electrode line (32) being connected to the electrode line (22) via a first via hole (HL1), and an orthographic projection of the first via hole (HL1) on the substrate (10) being located within an orthographic projection of the extension portion (23) on the substrate (10).

4. The display panel (1) according to claim 3, characterized in that: The display panel (1) comprises a semiconductor layer (40) arranged between the first metal layer (20) and the second metal layer (30), and the semiconductor layer (40) comprises a semiconductor portion (41) covering a surface of one side of the second metal layer (30) close to the substrate (10); The first metal layer (20) includes a light shielding portion (24), and the orthographic projection of the shared electrode line (32) on the substrate (10) overlaps with the orthographic projection of the light shielding portion (24) on the substrate (10).

5. The display panel (1) according to claim 4, characterized in that: The width (w1) of the light shielding portion (24) in the first direction (D1) is greater than the width (w2) of the common electrode line (32) in the first direction (D1).

6. The display panel (1) according to claim 4, characterized in that: The first metal layer (20) comprises an auxiliary portion (25), wherein the auxiliary portion (25) and the light shielding portion (24) are located in different sub-pixels (111); The display panel (1) further comprises a pixel electrode layer (50) arranged on a side of the second metal layer (30) facing away from the substrate (10), the pixel electrode layer (50) comprising a pixel electrode (51) corresponding to the sub-pixel (111); The pixel electrode (51) comprises a main electrode (511) extending along the second direction (D2), and the light shielding portion (24) and the auxiliary portion (25) both overlap with the main electrode (511).

7. The display panel (1) according to claim 6, characterized in that: The width (w3) of the auxiliary portion (25) in the first direction (D1) is smaller than the width (w4) of the main electrode (511) in the first direction (D1).

8. The display panel (1) according to claim 7, characterized in that: The shading portion (24) comprises a first sub-segment (241) extending along the second direction (D2) and a second sub-segment (242) extending along the first direction (D1), the first sub-segment (241) and the second sub-segment (242) being connected, and the auxiliary portion (25) extending along the second direction (D2).

9. The display panel (1) according to claim 7, characterized in that: The sub-pixel (111) comprises at least a first transistor (T1) and a second transistor (T2), the first transistor (T1) comprising a first drain electrode (331b) arranged on the second metal layer (30), and the second transistor (T2) comprising a second drain electrode (331b) arranged on the second metal layer (30). (332b) ; The sub-pixel (111) comprises a main pixel region (11a) and a sub-pixel region (11b) arranged along the second direction (D2), and the scanning line (21) and the electrode line (22) are arranged between the main pixel region (11a) and the sub-pixel region (11b); The first drain electrode (331b) and the pixel electrode (51) corresponding to the main pixel area (11a) are electrically connected via a second via hole (HL2), and the second drain electrode (332b) and the pixel electrode (51) corresponding to the secondary pixel area (11b) are electrically connected via a third via hole (HL3), and the second via hole (HL2) and the third via hole (HL3) do not overlap with the first metal layer (20).

10. The display panel (1) according to claim 9, characterized in that: The first via hole (HL1), the second via hole (HL2) and the third via hole (HL3) are arranged along the first direction (D1).

11. The display panel (1) according to claim 9, characterized in that: The sub-pixel (111) comprises a third transistor (T3), and the third transistor (T3) comprises a third source (333a) and a third drain (333b) arranged on the second metal layer (30); The third source (333a) is connected to the second drain (332b), and the third drain (333b) is connected to the common electrode line (32).

12. The display panel (1) according to claim 7, characterized in that: The pixel electrode layer (50) comprises a connecting portion (52) arranged in the first via hole (HL1), wherein a side surface of the connecting portion (52) close to the substrate (10) contacts a side surface of the shared electrode line (32) away from the substrate (10), and a side surface of the connecting portion (52) close to the substrate (10) contacts the extending portion (23).

13. A display terminal (2), characterized in that: Comprising the display panel (1) according to any one of claims 1 to 12.

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