Coding and decoding method and device and electronic equipment

Abstract

The invention discloses a coding and decoding method and device and electronic equipment. The method comprises the following steps: S1, coding; s2, a data selection step; and S3, a decoding step. And weight reduction coding and decoding are combined with ECC coding and decoding. According to the first method, the encoding mode of ECC is changed, and the ECC encoding and decoding have a weight reduction function by separately negating a user data bit and a check bit. According to the second method, the input data and the coding mode of the ECC are changed at the same time, firstly, the input data of the ECC are changed through the first layer of weight reduction coding, so that the ECC can generate a check bit with smaller Hamming weight, and then the ECC coding and decoding further have the weight reduction function by negating the check bit.

Description

Technical Field

[0001] The present invention relates to encoding and decoding methods, and in particular, to an encoding and decoding method, apparatus, and electronic device. Background Art

[0002] Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) stands out among new storage technologies due to its non-volatility, high durability, high storage density, and full compatibility with CMOS processes, becoming the future preferred solution in the field of embedded Nonvolatile Memories (eNVM). However, during the use of STT-MRAM, faults such as write failures, read disturbances, and short-circuit hard errors will occur, affecting its reliability, and all three faults have asymmetric behaviors.

[0003] 1) Write failure fault. The writing of stored data in STT-MRAM is an asymmetric process. Under the same write current amplitude, the time for "0→1" writing is longer than that for "1→0" writing. Therefore, the write reliability of STT-MRAM cells mainly depends on the failure rate of "0→1" writing.

[0004] 2) Read disturbance fault. To improve reliability, the direction of the read current in STT-MRAM is usually designed to be the same as the current direction for "1→0" writing. Therefore, the read disturbance fault only affects the high-resistance state cells storing "1", and does not affect the low-resistance state cells storing "0".

[0005] 3) Short-circuit hard error. STT-MRAM is continuously used during its life cycle, causing oxide barrier breakdown or oxide thickness change, resulting in short-circuit hard errors in the storage cells, manifested as a permanent fault of being stuck at "0" (Stuck-at-0).

[0006] By reducing the Hamming weight of the stored codewords, the asymmetry of STT-MRAM faults can be utilized to effectively reduce the probabilities of "0→1" writing and reading "1", thereby reducing write failure faults and read disturbance faults. At the same time, this method can increase the probability of writing "0" to the short-circuit bits, so that the correct data can be directly read out from the short-circuit bits, alleviating the error correction pressure of ECC on short-circuit hard errors.

[0007] However, traditional ECC encoding and decoding do not have the ability to reduce Hamming weight. Summary of the Invention

[0008] To solve the above problems, the present application provides an encoding and decoding method, apparatus, and electronic device.

[0009] The present invention provides the following technical solutions: A coding and decoding method, comprising the following steps: S1. Acquisition step Acquire binary data to form source code. The binary data described in this application can be a set of discretized digital information with any bit width from any data source existing in any storage form. Among them, any storage form includes but is not limited to electron charge storage form, magnetic domain orientation storage form, photon modulation storage form, resistive switching effect storage form, etc. Among them, any data source includes but is not limited to computing device generation source, physical environment perception source, biological signal source, human-computer interaction source, etc.

[0010] S2. Encoding step S2.1. Generate ECC check bits through ECC encoding according to the source code, and add a first flag bit for marking the data state of the ECC check bits, and splice the source code, ECC check bits and the first flag bit to form a first group of data; take the inverse of the ECC check bits to obtain the inverse code of the ECC check bits, and at the same time, take the inverse of the first flag bit to obtain the inverse code of the first flag bit, and splice the source code, the inverse code of the ECC check bits and the inverse code of the first flag bit to form a second group of data; the data state of the ECC check bits is the original state or the inverted state. S2.2. Add a second flag bit for marking the data state of the source code after the first group of data as the first group of output data; take the inverse of the first group of output data to obtain the inverse code of the first group of output data as the second group of output data; add the second flag bit after the second group of data as the third group of output data; take the inverse of the third group of output data to obtain the inverse code of the third group of output data as the fourth group of output data; the data state of the source code is the original state or the inverted state. S3. Data selection step Calculate the Hamming weights of the first group of output data, the second group of output data, the third group of output data, and the fourth group of output data respectively, and select the group of data with the smallest Hamming weight as the stored data; if there are more than one group of data with the smallest Hamming weight, the selection priority order is: the first group of output data > the third group of output data > the fourth group of output data > the second group of output data. S4. Decoding step S4.1. Restore the ECC check bits and the source code respectively according to the first flag bit and the second flag bit of the stored data. S4.2. Perform ECC decoding according to the restored source code and ECC check bits.

[0011] A device for implementing the above-mentioned coding and decoding method at least includes: An acquisition module, configured to acquire binary data to form source code. Encoding module: Generate ECC check bits through ECC encoding based on the source code, add a first flag bit for marking the data status of the ECC check bits, and splice the source code, ECC check bits, and the first flag bit to form a first set of data; invert the ECC check bits to obtain the complement code of the ECC check bits. At the same time, invert the first flag bit to obtain the complement code of the first flag bit, and splice the source code, the complement code of the ECC check bits, and the complement code of the first flag bit to form a second set of data; the data status of the ECC check bits is the original status or the inverted status; add a second flag bit for marking the data status of the source code after the first set of data as the first set of output data; invert the first set of output data to obtain the complement code of the first set of output data as the second set of output data; add the second flag bit after the second set of data as the third set of output data; invert the third set of output data to obtain the complement code of the third set of output data as the fourth set of output data; the data status of the source code is the original status or the inverted status; Data selection module: Calculate the Hamming weight of the first set of output data, the second set of output data, the third set of output data, and the fourth set of output data respectively, and select the set of data with the smallest Hamming weight as the stored data; if there are more than one set of data with the smallest Hamming weight, the selection priority order is: the first set of output data > the third set of output data > the fourth set of output data > the second set of output data; Decoding module: Restore the ECC check bits and the source code respectively according to the first flag bit and the second flag bit of the stored data; perform ECC decoding according to the restored source code and ECC check bits.

[0012] A coding and decoding method, comprising the following steps: S1. Acquisition step Acquire binary data to form the source code; S2. Encoding step S2.1. Form at least one set of encoded data through at least one encoding method based on the source code, and add a first flag bit for marking the encoding method of the source code and the encoded data. Splice the source code and the first flag bit to form a first set of data; splice the encoded data and the first flag bit to form encoded flag data; S2.2. Generate ECC check bits respectively through ECC encoding based on the first group of data and the encoding flag data, and add a second flag bit for marking the data state of the ECC check bits; splice the first group of data, the corresponding ECC check bits and the corresponding second flag bits as the first group of output data; invert the ECC check bits to obtain the complementary code of the ECC check bits. At the same time, invert the second flag bit to obtain the complementary code of the second flag bit, and splice the first group of data, the complementary code of the corresponding ECC check bits and the complementary code of the corresponding second flag bits as the second group of output data; splice the encoding flag data, the corresponding ECC check bits and the second flag bits as the first encoded flag data output data; invert the ECC check bits of the encoding flag data to obtain the complementary code of the ECC check bits. At the same time, invert the second flag bit of the encoding flag data to obtain the complementary code of the second flag bit, and splice the encoding flag data, the complementary code of the corresponding ECC check bits and the complementary code of the corresponding second flag bits as the second encoded flag data output data; the data state of the ECC check bits is the original state or the inverted state; S3. Data selection step Calculate the Hamming weights of the first group of output data, the second group of output data, the first encoded flag data output data, and the second encoded flag data output data respectively, and select the group of data with the smallest Hamming weight as the stored data; if there are more than one group of data with the smallest Hamming weight, the selection priority order is: the first group of output data > the second group of output data > the first encoded flag data output data and the second encoded flag data output data. The decoding method complexities corresponding to them are arranged in ascending order; S4. Decoding step S4.1. Restore the ECC check bits according to the second flag bit of the stored data; S4.2. Perform ECC decoding according to the restored ECC check bits; S4.3. Restore the source code according to the first flag bit of the ECC decoded data.

[0013] Furthermore, the encoding method includes at least one of complementary code, Gray code, backward exclusive OR encoding, and cyclic shift encoding. The above decoding method complexities are arranged in ascending order as complementary code, Gray code, backward exclusive OR encoding, and cyclic shift encoding.

[0014] A device for implementing the above encoding and decoding method at least includes: An acquisition module for acquiring binary data to form source code; An encoding module, which is used to form at least one set of encoded data through at least one encoding method according to the source code, and add a first flag bit for marking the encoding method of the source code and the encoded data, and splice the source code and the first flag bit to form a first set of data; splice the encoded data and the first flag bit to form encoded flag data; generate ECC check bits respectively through ECC encoding according to the first set of data and the encoded flag data, and add a second flag bit for marking the data state of the ECC check bits; splice the first set of data, the corresponding ECC check bits and the corresponding second flag bits as the first set of output data; take the inverse of the ECC check bits to obtain the inverse code of the ECC check bits, and at the same time, take the inverse of the second flag bit to obtain the inverse code of the second flag bit, and splice the first set of data, the corresponding inverse code of the ECC check bits and the corresponding inverse code of the second flag bits as the second set of output data; splice the encoded flag data, the corresponding ECC check bits and the second flag bits as the first encoded flag data output data; take the inverse of the ECC check bits of the encoded flag data to obtain the inverse code of the ECC check bits, and at the same time, take the inverse of the second flag bit of the encoded flag data to obtain the inverse code of the second flag bit, and splice the encoded flag data, the corresponding inverse code of the ECC check bits and the corresponding inverse code of the second flag bits as the second encoded flag data output data; the data state of the ECC check bits is the original state or the inverted state; A data selection module, which calculates the Hamming weight of the first set of output data, the second set of output data, the first encoded flag data output data, and the second encoded flag data output data respectively, and selects the set of data with the smallest Hamming weight as the stored data; if there are more than one set of data with the smallest Hamming weight, the selection priority order is: the first set of output data > the second set of output data > the first encoded flag data output data and the second encoded flag data output data, and the decoding method complexities corresponding to them are arranged in ascending order; A decoding module, which restores the ECC check bits according to the second flag bit of the stored data; performs ECC decoding according to the restored ECC check bits; restores the source code according to the first flag bit of the ECC decoded data.

[0015] An electronic device, comprising: One or more processors; A memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described above.

[0016] A computer-readable storage medium, on which computer instructions are stored, and when the instructions are executed by a processor, the steps of the method as described above are implemented.

[0017] The beneficial effects of the present invention are as follows: (1) Combine weight reduction encoding and decoding with ECC encoding and decoding. Method 1 changes the encoding method of ECC. By separately inverting the user data bits and parity bits, the ECC encoding and decoding have the weight reduction function. Method 2 changes both the input data and the encoding method of ECC. First, through the first-layer weight reduction encoding, the input data of ECC is changed so that ECC can generate parity bits with a smaller Hamming weight. Then, by inverting the parity bits, the ECC encoding and decoding further have the weight reduction function.

[0018] (2) Provide multiple selectable encoding and decoding schemes. According to the characteristics of different input data sets, the weight reduction encoding method and the encoding and decoding order with the optimal weight reduction effect can be flexibly selected in advance according to the software simulation results, so as to minimize the Hamming weight.

[0019] (3) Small redundancy overhead and low complexity. The present invention only adds two flag bits to represent the inversion method or weight reduction decoding method to be performed on the stored data, and the area overhead is small. In Method 1 and Method 2, two groups of parallel data are generated through the first-layer encoding, and the second-layer encoding is performed in parallel, without generating redundant delay overhead. The inversion operation can be directly implemented through the exclusive OR operation in the digital circuit implementation, with low complexity and high efficiency. Brief Description of the Drawings

[0020] Figure 1 It is the schematic diagram of Embodiment 1 of an encoding and decoding method of the present invention; Figure 2 It is the schematic diagram of Embodiment 3 of an encoding and decoding method of the present invention. Detailed Embodiment

[0021] To further elaborate on the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, the following combines the drawings and preferred embodiments to detail the specific implementation manner, structure, features and their effects of the present invention as follows.

[0022] The present invention combines weight reduction encoding and decoding with ECC encoding and decoding, and adds a first flag bit and a second flag bit, thereby providing a reference for restoration and decoding, and selecting the data with the smallest Hamming weight for storage during the storage process, that is, the data with the most 0s and the fewest 1s in the binary data, so as to reduce the write failure fault and read interference fault.

[0023] The following further illustrates the embodiments of the present invention through multiple embodiments.

[0024] Embodiment 1 When writing data, input the source code input[m:0] to the ECC encoder. In the ECC encoder, first perform ECC encoding on the source code input to generate the ECC parity bit parity, and then connect parity after input and add the first flag bit E 0= "0", as the first group of data input + parity + "0", denoted as ecc0[n+1:0]; invert parity, concatenate it after input and add the first flag bit E 0 = "1", as the second group of data input + ~parity + "1", denoted as ecc1[n+1:0].

[0025] Input ecc0 and ecc1 into the weight reduction encoder. In the weight reduction encoder, add the second flag bit E after ecc0 1 = "0", as the first group of output data input + parity + "0" + "0", denoted as ecc_r0[n+2:0]; invert ecc_r0, as the second group of output data ~input + ~parity + "1" + "1", denoted as ecc_r1[n+2:0]; add the second flag bit E after ecc1 1 = "0", as the third group of output data input + ~parity + "1" + "0", denoted as ecc_r2[n+2:0]; invert ecc_r2, as the fourth group of output data ~input + parity + "0" + "1", denoted as ecc_r3[n+2:0].

[0026] Calculate the Hamming weights of the four groups of data ecc_r0~eccr3, select the group of data with the smallest Hamming weight as the stored data, denoted as ecc_r[n+2:0]; if there are more than one group of data with the smallest Hamming weight, the selection priority order is: ecc_r0 > ecc_r2 > ecc_r3 > ecc_r1.

[0027] When reading data, read the stored data ecc_r into the weight reduction decoder. In the weight reduction decoder, the first flag bit E 0 Perform an exclusive OR operation with the ECC check bit to restore parity, and the second flag bit E 1 Perform an exclusive OR operation with the ECC user data bit to restore input, and obtain the output data input + parity of the weight reduction decoder, denoted as ecc[n:0].[[]END]

[0028] Input ecc[n:0] into the ECC decoder. In the ECC decoder, perform ECC decoding on the restored input according to the restored parity to obtain the read data output[m:0].[[]END]

[0029] A device for implementing the above encoding and decoding method at least includes: An acquisition module for acquiring binary data to form source code; The encoding module generates ECC check bits through ECC encoding based on the source code, and adds a first flag bit for marking the data status of the ECC check bits, and splices the source code, the ECC check bits and the first flag bit to form a first group of data; takes the inverse of the ECC check bits to obtain the inverse code of the ECC check bits, and at the same time, takes the inverse of the first flag bit to obtain the inverse code of the first flag bit, and splices the source code, the inverse code of the ECC check bits and the inverse code of the first flag bit to form a second group of data; the data status of the ECC check bits is the original status or the inverted status; adds a second flag bit for marking the data status of the source code after the first group of data as the first group of output data; takes the inverse of the first group of output data to obtain the inverse code of the first group of output data as the second group of output data; adds the second flag bit after the second group of data as the third group of output data; takes the inverse of the third group of output data to obtain the inverse code of the third group of output data as the fourth group of output data; the data status of the source code is the original status or the inverted status; The data selection module calculates the Hamming weights of the first group of output data, the second group of output data, the third group of output data, and the fourth group of output data respectively, and selects the group of data with the smallest Hamming weight as the stored data; if there are more than one group of data with the smallest Hamming weight, the selection priority order is: the first group of output data > the third group of output data > the fourth group of output data > the second group of output data; The decoding module restores the ECC check bits and the source code respectively according to the first flag bit and the second flag bit of the stored data; performs ECC decoding according to the restored source code and ECC check bits.

[0030] An electronic device, comprising: One or more processors; A memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described above.

[0031] In the embodiments provided in the present application, it should be understood that the disclosed methods and systems can also be implemented in other ways. The method and system embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of the methods, systems, methods, and computer program products according to multiple embodiments of the present application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0032] In addition, in each embodiment of the present application, the various functional modules may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0033] On the other hand, a computer-readable storage medium stores computer instructions, and when the instructions are executed by a processor, the steps of the above-described method are implemented. When the computer program is executed by the processor, the method according to any one of the above first aspects is implemented. If the function is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory 101 (ROM, Read-Only Memory), random access memory 101 (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0034] Embodiment 2 Taking numerical examples, specifically as follows: In this embodiment, the input codeword set is 16-bit full data, and the BCH code with 2-bit error correction and 3-bit error detection is selected for ECC encoding and decoding. There are 16 data storage bits, 11 ECC check bits, and 2 flag bits in one storage address.

[0035] The input source code input[15:0] is 16’d1101011101011011. After ECC encoding, the ECC check bit parity[10:0] is 11’d10111101100. Connect parity after input and add the first flag bit E 0 = “0”, and the first group of data ecc0[27:0] is 28’d1101011101011011_10111101100_0; Take the inverse of parity, connect it after input and add the first flag bit E 0 = “1”, and the second group of data ecc1[27:0] is 28’d1101011101011011_01000010011_1.

[0036] Input ecc0 and ecc1 to the weight reduction encoder. In the weight reduction encoder, add the second flag bit E after ecc0 1 = “0”, and the first group of output data ecc_r0[28:0] is 29’d1101011101011011_10111101100_0_0; Take the inverse of ecc_r0, and the second group of output data ecc_r1[28:0] is 29’d0010100010100100_0100001010011_1_1; Add the second flag bit E after ecc1 1 = “0”, and the third group of output data ecc_r2[28:0] is 29’d1101011101011011_01000010011_1_0; Take the inverse of ecc_r2, and the fourth group of output data ecc_r3[28:0] is 29’d0010100010100100_10111101100_0_1.

[0037] Calculate and compare the Hamming weights of the four groups of data after two-layer encoding. The Hamming weight of the codeword * is represented by H(*). H(ecc_r0)=18, H(ecc_r1)=11, H(ecc_r2)=16, H(ecc_r3)=13. So, select ecc_r1 as the stored data, denoted as ecc_r.

[0038] Assume that two soft errors occur during the storage of data ecc_r, and it becomes 29’d0011100010100100_11000010011_1_1. When the data is read, ecc_r is read into the weight reduction decoder. In the weight reduction decoder, the first flag bit "1" is XORed with the ECC check bit "11000010011" to restore the parity to "00111101100"; the second flag bit "1" is XORed with the ECC user data bit "0011100010100100" to restore the input to "1100011101011011", and the output data ecc[26:0] of the weight reduction decoder is 27’d1100011101011011_00111101100.

[0039] The input ecc[26:0] is sent to the ECC decoder. In the ECC decoder, a BCH decoding operation of correcting 2 and detecting 3 is performed on the restored input according to the restored parity, and the correct read data output[15:0] is 16’d1101011101011011.

[0040] The encoding method of ECC is changed. By separately inverting the data bits and check bits, the ECC encoding and decoding have the weight reduction function. The number of times of writing "0→1" is reduced from 18 times to 11 times, reducing the writing failure rate; the number of times of reading "1" is reduced from 18 times to 13 times, reducing the read interference failure rate.

[0041] Only two flag bits are added to indicate the inversion method to be performed on the stored data, and the area overhead is small. Two groups of parallel data are generated through the first-layer encoding, and the second-layer encoding is performed in parallel, without generating redundant delay overhead. The inversion operation is directly implemented through XOR operation in the digital circuit implementation, with low complexity and high efficiency.

[0042] Embodiment 3 When data is written, the source code input[m:0] is input to the weight reduction encoder. In the weight reduction encoder, the first flag bit E 0 =“000” is added to the source code input, as the first group of data input+“000”, denoted as input0[m+3:0]; the source code input is subjected to weight reduction encoding and the first flag bit E 0 is added as the encoding flag data input_rx+E 0 , denoted as inputx[m+3:0]. Among them, the weight reduction encoding methods are ones' complement, Gray code, backward XOR encoding, and cyclic shift encoding, corresponding to x being 1, 2, 3, 4 respectively, corresponding to the first flag bit E 0They are 001, 010, 011, and 100 respectively. According to the number of coding methods to be marked, the first flag bit can be 1 bit (able to mark two coding methods), 2 bits (able to mark four coding methods), 3 bits (able to mark eight coding methods), or more bits, which can be set according to actual needs. In this embodiment, the first flag bit uses 3 bits and marks 5 different coding methods (including the source code).

[0043] Input input0, input1, input2, input3, and input4 to the ECC encoder. In the ECC encoder, first perform ECC encoding on input0 to generate the ECC check bit parity, connect parity after input0 and add the second flag bit E 1 = "0", as the first group of output data input + "000" + parity + "0", denoted as ecc_r0[n + 4:0]; take the inverse of parity, connect it after input0 and add the second flag bit E 1 = "1", as the second group of output data input + "000" + ~parity + "1", denoted as ecc_r1[n + 4:0]. Then perform ECC encoding on input1 to generate the ECC check bit parity_r1, connect parity_r1 after input1 and add the second flag bit E 1 = "0", as the output data of the first group of the first coding flag data input_r1 + "001" + parity_r1 + "0", denoted as ecc_r11[n + 4:0]; take the inverse of parity_r1, connect it after input1 and add the second flag bit E 1 = "1", as the output data of the first group of the second coding flag data input_r1 + "001" + ~parity_r1 + "1", denoted as ecc_r12[n + 4:0]. Then perform ECC encoding on input2 to generate the ECC check bit parity_r2, connect parity_r2 after input2 and add the second flag bit E 1 = "0", as the output data of the second group of the first coding flag data input_r2 + "010" + parity_r2 + "0", denoted as ecc_r21[n + 4:0]; take the inverse of parity_r2, connect it after input2 and add the second flag bit E 1= "1", the output data of the second encoding flag data in the second group is input_r2 + "010" + ~parity_r2 + "1", denoted as ecc_r22[n+4:0]. Then perform ECC encoding on input3 to generate the ECC check bit parity_r3, connect parity_r3 after input3 and add the second flag bit E 1 = "0", the output data of the first encoding flag data in the third group is input_r3 + "011" + parity_r3 + "0", denoted as ecc_r31[n+4:0]; take the inverse of parity_r3, connect it after input3 and add the second flag bit E 1 = "1", the output data of the second encoding flag data in the third group is input_r3 + "011" + ~parity_r3 + "1", denoted as ecc_r32[n+4:0]. Then perform ECC encoding on input4 to generate the ECC check bit parity_r4, connect parity_r4 after input4 and add the second flag bit E 1 = "0", the output data of the first encoding flag data in the fourth group is input_r4 + "100" + parity_r4 + "0", denoted as ecc_r41[n+4:0]; take the inverse of parity_r4, connect it after input4 and add the second flag bit E 1 = "1", the output data of the second encoding flag data in the fourth group is input_r4 + "100" + ~parity_r4 + "1", denoted as ecc_r42[n+4:0].

[0044] Calculate the Hamming weights of the 10 groups of data ecc_r0, eccr1, ecc_r11, ecc_r12, ecc_r21, ecc_r22, ecc_r31, ecc_r32, ecc_r41, ecc_r42. Select the group of data with the smallest Hamming weight as the stored data, denoted as ecc_r[n+4:0]; if there are more than one group of data with the smallest Hamming weight, the selection priority order is: the output data of the first group > the output data of the second group > the decoding method complexity corresponding to the output data of the first encoding flag data and the output data of the second encoding flag data is arranged from low to high.

[0045] When reading data, read the stored data ecc_r into the ECC decoder. In the ECC decoder, first the second flag bit E 1Exclusive OR operation with the ECC check bits to restore parity or parity_r1 or parity_r2 or parity_r3 or parity_r4. Perform ECC decoding on the first group of data or the encoded flag data according to the restored ECC check bits to obtain the output data of the ECC decoder as output + "000" or output_r1 + "001" or output_r2 + "010" or output_r3 + "011" or output_r4 + "100", denoted as output_r[m + 3:0].

[0046] Input output_r to the weight reduction decoder. In the weight reduction decoder, according to the first flag bit E 0 Select the corresponding weight reduction decoding method, and obtain the read data output[m:0] through the weight reduction decoding operation.

[0047] A device for implementing the above encoding and decoding method at least includes: An acquisition module for acquiring binary data to form source code; An encoding module for forming at least one group of encoded data according to the source code through at least one encoding method, and adding a first flag bit for marking the encoding method of the source code and the encoded data, and splicing the source code and the first flag bit to form the first group of data; splicing the encoded data and the first flag bit to form the encoded flag data; generating ECC check bits respectively according to the first group of data and the encoded flag data through ECC encoding, and adding a second flag bit for marking the data state of the ECC check bits; splicing the first group of data and the corresponding ECC check bits and the corresponding second flag bits as the first group of output data; taking the inverse of the ECC check bits to obtain the inverse code of the ECC check bits, and at the same time, taking the inverse of the second flag bit to obtain the inverse code of the second flag bit, and splicing the first group of data and the corresponding inverse code of the ECC check bits and the corresponding inverse code of the second flag bits as the second group of output data; splicing the encoded flag data and the corresponding ECC check bits and the second flag bits as the first encoded flag data output data; taking the inverse of the ECC check bits of the encoded flag data to obtain the inverse code of the ECC check bits, and at the same time, taking the inverse of the second flag bit of the encoded flag data to obtain the inverse code of the second flag bit, and splicing the encoded flag data and the corresponding inverse code of the ECC check bits and the corresponding inverse code of the second flag bits as the second encoded flag data output data; the data state of the ECC check bits is the original state or the inverted state; The data selection module calculates the Hamming weights of the first set of output data, the second set of output data, the first encoded flag data output data, and the second encoded flag data output data respectively, and selects the set of data with the smallest Hamming weight as the stored data; if there are more than one set of data with the smallest Hamming weight, the selection priority order is: the first set of output data > the second set of output data > the decoding method complexities corresponding to the first encoded flag data output data and the second encoded flag data output data are arranged in ascending order; The decoding module restores the ECC check bits according to the second flag bit of the stored data; performs ECC decoding according to the restored ECC check bits; restores the source code according to the first flag bit of the ECC decoded data.

[0048] Embodiment 4 Taking numerical examples, specifically as follows: In this embodiment, the input codeword set is 8-bit full data, the weight reduction encoding and decoding methods select ones' complement, Gray code, backward exclusive OR encoding, and cyclic shift encoding, and the ECC encoding and decoding method selects Hamming code that corrects 1 bit. There are 8 data storage bits, 4 ECC check bits, and 4 flag bits in one storage address.

[0049] The written source code input[7:0] is 8’b11100111. In the weight reduction encoder, add the first flag bit E 0 =“000” to the source code input, and the first set of data input0[10:0] is 11’b11100111_000; perform ones' complement encoding on the source code input and add the first flag bit E 0 =“001”, and the first set of encoded flag data input1[10:0] is 11’b00011000001; perform Gray encoding on the source code input and add the first flag bit E 0 =“010”, and the second set of encoded flag data input2[10:0] is 11’b10010100010; perform backward exclusive OR encoding on the source code input and add the first flag bit E 0 =“011”, and the third set of encoded flag data input3[10:0] is 11’b00101001_011; perform cyclic shift encoding on the source code input and add the first flag bit E 0 =“100”, and the fourth set of encoded flag data input4[10:0] is 11’b01111110_100.

[0050] Input input0, input1, input2, input3, and input4 are fed into the ECC encoder. In the ECC encoder, first, input0 is ECC-encoded to generate ECC parity bits parity[3:0] as 4’b1000. The parity is concatenated after input0 and a second flag bit E 1 = “0” is added as the first group of output data ecc_r0[15:0] which is 16’11100111_0001000_0. The parity is inverted, concatenated after input0, and a second flag bit E 1 = “1” is added as the second group of output data ecc_r1[15:0] which is 16’11100111_0000111_1. Then input1 is ECC-encoded to generate ECC parity bits parity_r1[3:0] as 0100. The parity_r1 is concatenated after input1 and a second flag bit E 1 = “0” is added as the output data ecc_r11[15:0] of the first group of first encoded flag data which is 16’00011000 _001_0100_0. The parity_r1 is inverted, concatenated after input1, and a second flag bit E 1 = “1” is added as the output data ecc_r12[15:0] of the first group of second encoded flag data which is 16’00011000 _001_1011_1. Then input2 is ECC-encoded to generate ECC parity bits parity_r2[3:0] as 1100. The parity_r2 is concatenated after input2 and a second flag bit E 1 = “0” is added as the output data ecc_r21[15:0] of the second group of first encoded flag data which is 16’10010100 _0101100_0. The parity_r2 is inverted, concatenated after input2, and a second flag bit E 1 = “1” is added as the output data ecc_r22[15:0] of the second group of second encoded flag data which is 16’10010100 _0100011_1. Then input3 is ECC-encoded to generate ECC parity bits parity_r3[3:0] as 0111. The parity_r3 is concatenated after input3 and a second flag bit E 1 = “0” is added as the output data ecc_r31[15:0] of the third group of first encoded flag data which is 16’00101001 _0110111_0. The parity_r3 is inverted, concatenated after input3, and a second flag bit E 1= "1", the output data ecc_r32[15:0] as the second encoding flag data of the third group is 16'00101001_0111000_1. Then perform ECC encoding on input4 to generate the ECC check bits parity_r4[3:0] as 0001, connect parity_r4 after input4 and add the second flag bit E 1 = "0", the output data ecc_r41[15:0] as the first encoding flag data of the fourth group is 16'01111110_1000001_0; invert parity_r4, connect it after input4 and add the second flag bit E 1 = "1", the output data ecc_r42[15:0] as the second encoding flag data of the fourth group is 16'01111110_1001110_1.

[0051] Calculate and compare the Hamming weights of the 10 groups of codewords after two-layer encoding, H(ecc_r0)=7, H(ecc_r1)=10, H(ecc_r11)=4, H(ecc_r12)=7, H(ecc_r21)=6, H(ecc_r22)=7, H(ecc_r31)=8, H(ecc_r32)=7, H(ecc_r41)=8, H(ecc_r41)=11. So select ecc_r11 as the stored codeword, denoted as ecc_r.

[0052] Assume that three-bit short-circuit hard errors occur during the storage of the data ecc_r, and it becomes 16’b00001000_0010100_0. When reading the data, read ecc_r into the ECC decoder. In the ECC decoder, first perform an exclusive OR operation on the second flag bit "0" and the ECC check bit "0100" to restore parity_r1 as "0100", and then perform Hamming code decoding with one error correction on the data 15’b00001000_0010100 to obtain the output data output_r[10:0] of the ECC decoder as 11’b00011000_001.

[0053] Input output_r[10:0] to the weight reduction decoder. In the weight reduction decoder, select the inversion as the weight reduction decoding method according to the first flag bit "001", and obtain the correct read data output[7:0] as 8’b11100111 through the weight reduction decoding operation.

[0054] Both the input data and the encoding method of ECC are changed. The input data of ECC is changed through the first-layer weight reduction encoding, enabling ECC to generate parity bits with a smaller Hamming weight. Then, by inverting the parity bits, the ECC encoding and decoding further have the weight reduction function. The number of "0→1" writes is reduced from 8 times to 4 times, reducing the write failure rate; the number of reads of "1" is reduced from 6 times to 2 times, reducing the read interference failure rate. Only two flag bits are added to indicate the inversion method and the weight reduction decoding method to be performed on the stored data, with a small area overhead. Two sets of parallel data are generated through the first-layer encoding and the second-layer encoding is performed in parallel, without generating extra delay overhead. The inversion operation is directly implemented through exclusive OR operation in digital circuit implementation, with low complexity and high efficiency.

[0055] In addition, since DATA4 is stored in the short-circuit bit cell, an error occurs in the data of this bit. Although DATA5 and DATA0 are also stored in the short-circuit bit cell, since the written data is "0", which is the same as the data after the short-circuit error occurs, the data of these two bits does not show an error. Finally, the ECC decoder detects 1 bit error and corrects it. If no encoding and decoding are performed, the DATA4 data is correct, and the DATA5 and DATA0 data are incorrect, with a total of 2 errors, which cannot be correctly corrected by the Hamming code ECC that corrects 1 error.

[0056] The above is only a preferred embodiment of the present invention, and it is not intended to limit the present invention in any form. Although the present invention has been disclosed above with the preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or equivalents of equivalent changes within the scope of the technical solution of the present invention by using the disclosed technical content above. However, as long as it does not depart from the technical solution content of the present invention, any brief modification, equivalent change and modification made to the above embodiment based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A coding and decoding method, characterized in that: The steps include: S1. Collection steps Collect binary data to form source code; S2. Encoding steps S2.

1. Generate an ECC check bit through ECC encoding according to the source code, and add a first flag bit for marking the data state of the ECC check bit, and splice the source code, the ECC check bit and the first flag bit to form a first group of data; invert the ECC check bit to obtain the inverse code of the ECC check bit, and at the same time, invert the first flag bit to obtain the inverse code of the first flag bit, and splice the source code, the inverse code of the ECC check bit and the inverse code of the first flag bit to form a second group of data; the data state of the ECC check bit is the original state or the inverted state; S2.2, add a second flag bit for marking the data state of the source code after the first group of data as the first group of output data; invert the first group of output data to obtain the inverse code of the first group of output data as the second group of output data; add a second flag bit after the second group of data as the third group of output data; invert the third group of output data to obtain the inverse code of the third group of output data as the fourth group of output data; the data state of the source code is the original state or the inverted state; S3. Data selection steps Calculate the Hamming weights of the first group of output data, the second group of output data, the third group of output data, and the fourth group of output data respectively, and select the group of data with the smallest Hamming weight as the storage data; if there are more than one group of data with the smallest Hamming weight, the priority order of selection is: the first group of output data> the third group of output data> the fourth group of output data> the second group of output data; S4. Decoding steps S4.1, restore the ECC check bit and the source code respectively according to the first flag bit and the second flag bit of the stored data; S4.

2. Perform ECC decoding based on the restored source code and ECC check bits.

2. A device for implementing a coding and decoding method as claimed in claim 1, characterized in that: At least: The acquisition module is used to collect binary data and form source code; The encoding module generates an ECC check bit through ECC encoding according to the source code, and adds a first flag bit for marking the data state of the ECC check bit, and splices the source code, the ECC check bit and the first flag bit to form a first group of data; the ECC check bit is inverted to obtain the inverse code of the ECC check bit, and at the same time, the first flag bit is also inverted to obtain the inverse code of the first flag bit, and the source code, the inverse code of the ECC check bit and the inverse code of the first flag bit are spliced ​​to form a second group of data; the data state of the ECC check bit is the original state or the inverted state; the second flag bit for marking the data state of the source code is added after the first group of data as the first group of output data; the first group of output data is inverted to obtain the inverse code of the first group of output data as the second group of output data; the second flag bit is added after the second group of data as the third group of output data; the third group of output data is inverted to obtain the inverse code of the third group of output data as the fourth group of output data; the data state of the source code is the original state or the inverted state; The data selection module calculates the Hamming weights of the first group of output data, the second group of output data, the third group of output data, and the fourth group of output data respectively, and selects the group of data with the smallest Hamming weight as the storage data; if there are more than one group of data with the smallest Hamming weight, the priority order of selection is: the first group of output data> the third group of output data> the fourth group of output data> the second group of output data; The decoding module restores the ECC check bit and the source code according to the first flag bit and the second flag bit of the stored data respectively; and performs ECC decoding according to the restored source code and the ECC check bit.

3. A coding and decoding method, characterized in that: The steps include: S1. Collection steps Collect binary data to form source code; S2. Encoding steps S2.

1. Form at least one set of coded data by at least one coding method according to the source code, add a first flag for marking the source code and the coding method of the coded data, concatenate the source code and the first flag to form a first set of data; concatenate the coded data and the first flag to form coded flag data; S2.2, generate ECC check bits respectively through ECC encoding according to the first group of data and the coding mark data, and add a second mark bit for marking the data state of the ECC check bit; splice the first group of data and the corresponding ECC check bits and the corresponding second mark bits as the first group of output data; invert the ECC check bits to obtain the inverse code of the ECC check bits, and at the same time, invert the second mark bit to obtain the inverse code of the second mark bit, splice the first group of data and the inverse code of the corresponding ECC check bits and the inverse code of the corresponding second mark bit as the second group of output data; splice the coding mark data and the corresponding ECC check bits and the second mark bit as the first coding mark data output data; invert the ECC check bits of the coding mark data to obtain the inverse code of the ECC check bits, and at the same time, invert the second mark bit of the coding mark data to obtain the inverse code of the second mark bit, splice the coding mark data and the corresponding ECC check bits and the inverse code of the corresponding second mark bit as the second coding mark data output data; the data state of the ECC check bits is the original state or the inverted state; S3. Data selection steps Calculate the Hamming weights of the first group of output data, the second group of output data, the first coding mark data output data, and the second coding mark data output data respectively, and select the group of data with the smallest Hamming weight as the storage data; If there are more than one group of data with the smallest Hamming weight, the priority order of selection is: the first group of output data> the second group of output data> the first coding mark data output data and the second coding mark data output data. The complexity of the decoding method corresponding to the data is arranged from low to high; S4. Decoding steps S4.1, restore the ECC check bit according to the second flag bit of the stored data; S4.2, performing ECC decoding according to the restored ECC check bits; S4.

3. Restore the source code according to the first flag bit of the ECC decoded data.

4. The method according to claim 3, characterized in that The encoding method includes at least one of inverse code, Gray code, backward XOR coding, and cyclic shift coding.

5. A device for implementing a coding and decoding method as claimed in claim 3 or 4, characterized in that: At least: The acquisition module is used to collect binary data and form source code; The encoding module is used to form at least one group of encoded data according to the source code through at least one encoding method, and add a first flag bit for marking the encoding method of the source code and the encoded data, splice the source code and the first flag bit to form a first group of data; splice the encoded data and the first flag bit to form encoded flag data; generate ECC check bits according to the first group of data and the encoded flag data through ECC encoding, and add a second flag bit for marking the data state of the ECC check bit; splice the first group of data and the corresponding ECC check bits and the corresponding second flag bits as the first group of output data; invert the ECC check bits to obtain the inverse code of the ECC check bits At the same time, the second flag bit is also inverted to obtain the inverse of the second flag bit, and the first group of data and the inverse of the corresponding ECC check bit and the inverse of the corresponding second flag bit are spliced ​​as the second group of output data; the coding flag data and the corresponding ECC check bit and the second flag bit are spliced ​​as the first coding flag data output data; the ECC check bit of the coding flag data is inverted to obtain the inverse of the ECC check bit, and at the same time, the second flag bit of the coding flag data is also inverted to obtain the inverse of the second flag bit, and the coding flag data and the inverse of the corresponding ECC check bit and the inverse of the corresponding second flag bit are spliced ​​as the second coding flag data output data; The data state of the ECC check bit is the original state or the inverted state; A data selection module, which respectively calculates the Hamming weights of the first group of output data, the second group of output data, the first coded mark data output data, and the second coded mark data output data, and selects a group of data with the smallest Hamming weight as storage data; If there are more than one group of data with the smallest Hamming weight, the priority order of selection is: the first group of output data> the second group of output data> the first coding mark data output data and the second coding mark data output data. The complexity of the decoding method corresponding to the data is arranged from low to high; A decoding module restores an ECC check bit according to the second flag bit of the stored data; and performs ECC decoding according to the restored ECC check bit; The source code is restored according to the first flag bit of the ECC decoded data.

6. An electronic device, characterized in that: include: one or more processors; A memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claim 1, claim 3, or claim 4.

7. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the instruction is executed by the processor, the steps of the method as claimed in any one of claim 1, claim 3 or claim 4 are implemented.

Images