Logic comprehensive optimization operator sequence generation method

Abstract

The invention belongs to the field of electronic design automation (EDA), particularly provides a logic comprehensive optimization operator sequence generation method, and effectively solves the problems of high calculation complexity, low generation efficiency, high implementation cost and the like of other schemes. In the aspect of optimization effect, an exhaustive search strategy is adopted in the previous stage to obtain a global optimal solution, so that the overall optimization quality is improved; in the aspect of generation efficiency, a grouping exploration strategy is adopted for local rapid search in the later stage, and the generation time of an optimization operator sequence is remarkably shortened; in conclusion, the method gets rid of dependence on large-scale annotation data and a complex training process, and the generation efficiency of the optimization operator sequence is remarkably improved while the optimization quality is ensured.

Description

Technical Field

[0001] The present invention belongs to the field of electronic design automation (EDA), and specifically provides a method for generating a sequence of logic synthesis optimization operators. Background Art

[0002] In integrated circuit design, logic synthesis is a key step in converting register transfer level (RTL) hardware description language into a gate-level netlist. Its core objective is to generate a physical implementation solution that meets the design constraints by optimizing parameters such as circuit structure, timing, area, and power consumption. Logic optimization is accomplished through a number of optimization operators. During the logic synthesis process, numerous operators form an operator sequence and continuously optimize the circuit in sequence. Due to the complex interactions between different optimization operations, their permutations and combinations will significantly affect core metrics such as the final circuit's timing margin, area utilization, and dynamic power consumption. As the process node continues to shrink and the design complexity rapidly grows, traditional methods based on fixed rules or single optimization strategies are difficult to meet the requirements of multi-objective optimization. Therefore, how to organize optimization operators and generate a high-quality sequence of optimization operators has become an important issue for breaking through design bottlenecks and enhancing chip competitiveness.

[0003] Currently, the mainstream methods for generating a sequence of logic synthesis optimization operators can be divided into three categories: rule-based methods based on expert experience, heuristic search methods, and machine learning methods that have emerged in recent years. Among them, the rule-based method relies on designers to manually write the optimization process. Its advantage lies in strong interpretability, but it is severely limited by the accumulation of engineers' domain knowledge and is difficult to handle new processes or complex design scenarios. Heuristic algorithms, such as genetic algorithms and simulated annealing, etc., perform automatic search by establishing a mapping model between the sequence of optimization operators and circuit quality metrics. Although they can break through the limitations of manual experience, they have problems such as high computational complexity, long time consumption, and insufficient generalization ability. Machine learning methods train an optimization strategy prediction model through historical data and show potential in some benchmark tests, but face practical problems such as the need for a large amount of labeled data, high training costs, and poor model generalization. In summary, the existing methods for generating a sequence of logic synthesis optimization operators have obvious deficiencies in one or more aspects such as optimization effect, computational complexity, and generalization ability. Summary of the Invention

[0004] The purpose of the present invention is to address the above-mentioned deficiencies of the existing technologies and provide a method for generating a sequence of logic synthesis optimization operators that can efficiently generate an optimization operator sequence for different circuits without the need for labeled data, effectively improving the logic synthesis optimization effect.

[0005] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0006] A method for generating a sequence of logic synthesis optimization operators, characterized by comprising the following steps:

[0007] A1. Generate a global m-operator sequence;

[0008] Let the logic synthesis optimization operator set W = {w 1 , w 2 ,..., w I}, where w i is the i-th logic synthesis optimization operator, 1 ≤ i ≤ I, and I is the number of logic synthesis optimization operators;

[0009] Arbitrarily arrange the optimization operators in the logic synthesis optimization operator set W to generate an operator sequence of length m, denoted as the m-operator sequence, and a total of I m m-operator sequences are generated;

[0010] A2. Select the optimal m-operator sequence;

[0011] A2-1. For each m-operator sequence: Use the current operator sequence to perform sequential logic optimization on the input circuit to obtain the optimized circuit of the sequence, and calculate the index parameters of the circuit;

[0012] A2-2. Select the sequence with the largest index parameter as the optimal m-operator sequence, and denote the optimized circuit of this sequence as the current target circuit;

[0013] A2-3. Add each optimization operator in the optimal m-operator sequence to the optimization operator sequence R in sequence order;

[0014] A3. Generate a local n-operator sequence group;

[0015] A3-1. Arbitrarily arrange the optimization operators in the logic synthesis optimization operator set W to generate an operator sequence of length n, denoted as the n-operator sequence, and save all the generated n-operator sequences in the operator sequence set B;

[0016] A3-2. For each optimization operator in the logic synthesis optimization operator set W: For the i-th optimization operator w i , randomly select k operator sequences from the operator sequence set B, modify the first optimization operator of each operator sequence to w i , and form a group with the k modified operator sequences, denoted as the i-th group of n-operator sequences, denoted as C i ;

[0017] A4. Select the optimal n-operator sequence;

[0018] A4-1. For each operator sequence group, do the following: Use each operator sequence in the group to perform sequential logic optimization on the current target circuit respectively to obtain the optimized circuit of the sequence, and calculate the index parameters of this circuit; Calculate the average value of the index parameters of each operator sequence in the group, which is denoted as the average index parameter of this operator sequence group.

[0019] A4-2. Select the operator sequence group with the largest average index parameter as the optimal operator sequence group, select the operator sequence with the largest index parameter in this group and denote it as the current optimal n-operator sequence, and update the optimized circuit of this sequence to the current target circuit.

[0020] A4-3. Append each optimized operator in the current optimal n-operator sequence to the optimized operator sequence R in sequence order.

[0021] A5. Determine whether the sequence length meets the requirements: If the length of the optimized operator sequence R is less than the set sequence length, then go to step A3; otherwise, output the optimized operator sequence R.

[0022] Further, in step A2-1, the process of sequential logic optimization is as follows:

[0023] A2-1-1. Use the first operator of the operator sequence to perform logic optimization on the current circuit to obtain the optimized circuit.

[0024] A2-1-2. In sequence order, sequentially execute the subsequent operators to perform a set of continuous logic optimizations on the circuit. Each operator acts on the circuit optimized by its previous operator until all operators in the sequence are executed, and the optimized circuit of this operator sequence is obtained.

[0025] Further, in step A1, the value range of the sequence length m of the global m-operator sequence is: 1 ≤ m ≤ 5.

[0026] Further, in step A3-1, the value range of the sequence length n of the local n-operator sequence is: 3 ≤ n ≤ 15.

[0027] Further, in step A3-2, the value range of the number k of operator sequence searches is: 10 ≤ k ≤ 100.

[0028] Based on the above technical solutions, the beneficial effects of the present invention are as follows:

[0029] The present invention provides a method for generating a sequence of logic synthesis optimization operators, which effectively solves the problems existing in other solutions, such as high computational complexity, low generation efficiency, and high implementation cost. In terms of the optimization effect, an exhaustive search strategy is adopted in the previous stage to obtain the global optimal solution, improving the overall optimization quality. In terms of the generation efficiency, a grouped exploration strategy is adopted in the later stage for local rapid search, significantly shortening the generation time of the optimization operator sequence. In summary, the present invention gets rid of the dependence on large-scale labeled data and complex training processes, and while ensuring the optimization quality, significantly improves the generation efficiency of the optimization operator sequence. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic flowchart of the method for generating a sequence of logic synthesis optimization operators in the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] In order to make the objectives, technical solutions, and beneficial effects of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the drawings and embodiments.

[0032] This embodiment provides a method for generating a sequence of logic synthesis optimization operators, and its process is as Figure 1 shown, and the specific steps are as follows:

[0033] A1. Generate a global m-operator sequence;

[0034] Suppose there is a set of logic synthesis optimization operators W = {w 1 , w 2 ,..., w I}, where w i is the i-th logic synthesis optimization operator, 1 ≤ i ≤ I, and I is the number of logic synthesis optimization operators; the optimization operators in W are arranged arbitrarily to generate an operator sequence of length m, where the operators can appear repeatedly, then a total of I m operator sequences of length m are generated, that is, a total of I m m-operator sequences are generated;

[0035] In this embodiment, there are a total of I = 6 logic synthesis optimization operators in the set W of logic synthesis optimization operators, which are Rewrite, rewrite-z, refactor, refactor-z, resub-K-8, and dc2 respectively; the value range of the sequence length m is: 1 ≤ m ≤ 5, and in this embodiment, the value is 3; the 6 operators are arranged arbitrarily to generate an operator sequence of length 3, and the optimization operators can appear repeatedly, then a total of I m= 216 3-operator sequences: rewrite → rewrite-z → refactor, refactor → dc2 → rewrite, ……, refactor-z → resub-K-8 → dc2;

[0036] A2. Select the optimal m-operator sequence;

[0037] A2-1. For each operator sequence: Use the current operator sequence to perform sequential logic optimization on the input circuit, obtain the optimized circuit of this sequence, and calculate the metric parameters of this circuit;

[0038] In this embodiment, the input circuit is denoted as G 0 , whose format is AIG (And-Inverter Graph), contains 482 input ports, 257 output ports, the number of AND gates in the circuit is 28910, and the metric parameter uses the number of AND gates reduced; Use each operator sequence to perform sequential logic optimization on G 0 to obtain the optimized circuit of this sequence, and calculate the number of AND gates reduced by this circuit relative to G 0 ;

[0039] Taking the operator sequence rewrite → rewrite-z → refactor as an example, the sequential logic optimization specifically includes the following sub-steps:

[0040] A2-1-1. Execute the first operator of the operator sequence to perform logic optimization on the current circuit to obtain the optimized circuit;

[0041] In this embodiment, execute the first operator rewrite of the operator sequence rewrite → rewrite-z → refactor to perform logic optimization on the input circuit G0 to obtain the optimized circuit G 1 ;

[0042] A2-1-2. In the order of the sequence, sequentially execute the subsequent operators to perform a set of continuous logic optimizations on the circuit. Each operator acts on the circuit optimized by its previous operator until all operators in the sequence are executed, and finally obtain the optimized circuit of this operator sequence;

[0043] In this embodiment, in the order of the sequence, sequentially execute the subsequent operators to perform a set of continuous logic optimizations on the circuit: First, execute the second operator rewrite-z of the operator sequence rewrite → rewrite-z → refactor to perform logic optimization on the circuit G 1 to obtain the optimized circuit G 2, then execute the third operator refactor in the operator sequence rewrite→rewrite-z→refactor for the circuit G 2 to perform logical optimization and obtain the optimized circuit G 3 ;

[0044] A2-2. Select the sequence with the largest index parameter and denote it as the optimal m-operator sequence, and denote the optimized circuit of this sequence as the current target circuit;

[0045] In this embodiment, calculate the number of AND gate reductions for all 216 3-operator sequences and compare their magnitudes. The sequence with the largest number of AND gate reductions is dc2→dc2→rewrite. Then, take dc2→dc2→rewrite as the optimal 3-operator sequence, and denote its optimized circuit G best as the current target circuit;

[0046] A2-3. Add each optimized operator in the optimal m-operator sequence to the optimization operator sequence R in sequence order;

[0047] In this embodiment, the dc2, dc2, and rewrite operators in the optimal 3-operator sequence dc2→dc2→rewrite are added to the optimization operator sequence R in sequence. Since R is initially empty, after addition, R is updated to dc2→dc2→rewrite;

[0048] A3. Generate a local n-operator sequence group;

[0049] A3-1. Arbitrarily arrange the optimization operators in the logical synthesis optimization operator set W to generate an operator sequence of length n, denoted as the n-operator sequence, where the operators can appear repeatedly. Save all the generated n-operator sequences in the operator sequence set B;

[0050] In this embodiment, the value range of the sequence length n is: 3≤n≤15, and the value in this embodiment is 9; Arbitrarily arrange the 6 operators in the operator set W to generate an operator sequence of length 9, such as: dc2→rewrite→rewrite→resub-K-8→refactor→rewrite-z→refactor-z→rewrite→dc2. Add all the generated 9-operator sequences to the set B, and the operator sequence set B is initially empty;

[0051] A3-2. For each optimization operator in the logical synthesis optimization operator set W: For the i-th optimization operator w i , randomly select k operator sequences from the operator sequence set B, and modify the first optimization operator of each operator sequence to w i, and form a group with the modified k operator sequences, denoted as the i-th group of n-operator sequences, denoted as C i , where k is the preset number of operator sequence searches;

[0052] In this embodiment, the value range of the operator sequence search number k is: 10 ≤ k ≤ 100, and the value in this embodiment is 20; the same processing is performed on each operator in the operator set W. Taking the first operator rewrite in W as an example, 20 operator sequences are randomly selected from the set B, and the first operator of each operator sequence is modified to rewrite, that is, these operator sequences start with the rewrite operator, and these 20 operator sequences are formed into a group, denoted as the first group of 9-operator sequences, denoted as C 1 ; then the above processing is sequentially performed on other operators in the operator set W, and finally 6 groups of 9-operator sequences are obtained, which are: C 1 , C 2 , …, C 6 ;

[0053] A4. Select the optimal n-operator sequence;

[0054] A4-1. Perform the following operations on each operator sequence group:

[0055] A4-1-1. Use each operator sequence in the group to perform sequential logic optimization on the current target circuit respectively, obtain the optimized circuit of the sequence, and calculate the index parameters of the circuit;

[0056] In this embodiment, for the i-th group of operator sequences, use the j-th operator sequence c in the group i,j , perform sequential logic optimization on the current target circuit G best , obtain the optimized circuit of the sequence, and calculate the number of AND gate reductions z 0 of this circuit relative to the input circuit G i,j ;

[0057] A4-1-2. Calculate the average value of the index parameters of each operator sequence in the group, denoted as the average index parameter of the operator sequence group;

[0058] In this embodiment, for the i-th group of operator sequences, the index parameters of each operator sequence in the group are z i,1 , z i,2 , …, z i,20 , calculate the average value of these 20 index parameters and denote it as the average index parameter of the operator sequence group;

[0059] A4-2. Select the operator sequence group with the largest average index parameter as the optimal operator sequence group. Select the operator sequence with the largest index parameter in this group and denote it as the current optimal n-operator sequence, and update the optimized circuit of this sequence to the current target circuit;

[0060] In this embodiment, compare the average index parameters of each operator sequence group, and select the operator sequence group with the largest value as the optimal operator sequence group, specifically the second group. Compare the number of AND gate reductions of each operator sequence within the second group of operator sequences, and find that the operator sequence with the largest number of AND gate reductions is resub-K-8→dc2→rewrite→resub-K-8→refactor-z→dc2→refactor→rewrite→rewrite-z, and denote it as the current optimal 9-operator sequence, and update the optimized circuit of this operator sequence to the current target circuit;

[0061] A4-3. Append each optimized operator in the current optimal n-operator sequence to the optimized operator sequence R in sequence order;

[0062] In this embodiment, append the resub-K-8, dc2, rewrite, resub-K-8, refactor-z, dc2, refactor, rewrite, and rewrite-z operators in the current optimal 9-operator sequence resub-K-8→dc2→rewrite→resub-K-8→refactor-z→dc2→refactor→rewrite→rewrite-z to the optimized operator sequence R in sequence. In the first iteration, after appending, R is updated to dc2→dc2→rewrite→resub-K-8→dc2→rewrite→resub-K-8→refactor-z→dc2→refactor→rewrite→rewrite-z;

[0063] A5. Determine whether the sequence length meets the requirements: If the length of the optimized operator sequence R is less than the set sequence length, go to step A3; otherwise, end the entire process and output the optimized operator sequence R;

[0064] In this embodiment, the set sequence length is 120. Determine whether the sequence length of the current optimized operator sequence R meets the requirements: when the length of R is less than 120, go to step A3; otherwise, end the entire process and output the optimized operator sequence R with a length of 120: dc2 → dc2 → rewrite → resub-K-8 → dc2 → rewrite → resub-K-8 → refactor-z → dc2 → refactor → rewrite → rewrite-z → …… → refactor → dc2 → rewrite-z → resub-K-8 → refactor → rewrite → dc2 → resub-K-8 → rewrite-z.

[0065] Take the sequence generation method based on reinforcement learning as a comparative example, compare the performance of the present invention with that of the comparative example. The generation efficiency and optimization effect are measured by two indicators: generation time and the number of AND gates reduced. The present invention and the comparative example use the same input circuit as the test circuit to generate an optimized operator sequence with a length of 120. The comparison results of the sequence generation performance are shown in Table 1;

[0066] Table 1

[0067] Method Generation time Number of AND gates reduced Comparative example 10 minutes and 4 seconds 8434 The present invention 4 minutes and 5 seconds 9139

[0068] As can be seen from the table, compared with the reinforcement learning method, the generation time of the present invention is greatly shortened, and the indicator of the number of AND gates reduced is also significantly improved, indicating that the present invention can obtain a better sequence optimization effect in a shorter time.

[0069] The above is only the specific implementation manner of the present invention. Any feature disclosed in this specification, unless specifically described, can be replaced by other equivalent or similar-purpose alternative features; all the features disclosed, or all the steps in any method or process, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A method for generating a logic synthesis optimization operator sequence, characterized in that: The following steps are involved: A1. Generate a global m-operator sequence; Assume that the logic synthesis optimization operator set W = {w1,w2,...,w I }, where w i is the i-th logic synthesis optimization operator, 1≤i≤I, I is the number of logic synthesis optimization operators; Arrange the optimization operators in the logic synthesis optimization operator set W arbitrarily to generate an operator sequence of length m, recorded as m-operator sequence, and generate a total of I m A sequence of m-operators; A2. Select the optimal m-operator sequence; A2-1. For each m-operator sequence, perform sequential logic optimization on the input circuit using the current operator sequence to obtain the optimized circuit of the sequence and calculate the index parameters of the circuit; A2-2. Select the sequence with the largest index parameter as the optimal m-operator sequence, and record the optimized circuit of the sequence as the current target circuit; A2-3. Add each optimization operator in the optimal m-operator sequence to the optimization operator sequence R in sequence order; A3. Generate a local n-operator sequence group; A3-1. Arrange the optimization operators in the logic synthesis optimization operator set W arbitrarily to generate an operator sequence of length n, recorded as an n-operator sequence, and save all the generated n-operator sequences in the operator sequence set B; A3-2. For each optimization operator in the logic synthesis optimization operator set W, perform the following operations on the i-th optimization operator w i , randomly select k operator sequences from the operator sequence set B, and modify the first optimization operator of each operator sequence to w i , and group the modified k operator sequences into a group, denoted as the i-th group of n-operator sequences, denoted as C i ; A4. Select the optimal n-operator sequence; A4-1. For each operator sequence group, perform sequence logic optimization on the current target circuit using each operator sequence in the group, obtain the optimized circuit of the sequence, and calculate the index parameters of the circuit; calculate the average value of the index parameters of each operator sequence in the group, and record it as the average index parameter of the operator sequence group; A4-2. Select the operator sequence group with the largest average index parameter as the optimal operator sequence group, select the operator sequence with the largest index parameter in the group as the current optimal n-operator sequence, and update the optimized circuit of the sequence as the current target circuit; A4-3. Append each optimization operator in the current optimal n-operator sequence to the optimization operator sequence R in sequence order; A5. Determine whether the sequence length meets the requirements: If the length of the optimized operator sequence R is less than the set sequence length, go to step A3; otherwise, output the optimized operator sequence R.

2. The method for generating a logic synthesis optimization operator sequence according to claim 1, characterized in that: In step A2-1, the process of sequence logic optimization is as follows: A2-1-1. Use the first operator of the operator sequence to perform logic optimization on the current circuit to obtain an optimized circuit; A2-1-2. Execute subsequent operators in sequence to perform a set of continuous logic optimization on the circuit. Each operator acts on the circuit optimized by its previous operator until all operators in the sequence are executed, and the optimized circuit of the operator sequence is obtained.

3. The method for generating a logic synthesis optimization operator sequence according to claim 1, characterized in that: In step A1, the value range of the sequence length m of the m-operator sequence is: 1≤m≤5.

4. The method for generating a logic synthesis optimization operator sequence according to claim 1, characterized in that: In step A3-1, the value range of the sequence length n of the n-operator sequence is: 3≤n≤15.

5. The method for generating a logic synthesis optimization operator sequence according to claim 1, characterized in that: In step A3-2, the value range of the operator sequence search number k is: 10≤k≤100.

Images