LIO pre-charge control circuit of dynamic random access memory

Abstract

The invention provides an LIO pre-charge control circuit of a dynamic random access memory. In the LIO pre-charging control circuit, a refresh state transmission unit receives a refresh state signal and a function control signal and outputs a first signal; the LIO pre-charging control unit receives the first signal, the read enable signal and the write enable signal, and outputs an LIO pre-charging enable signal based on the first signal, the read enable signal and the write enable signal, and the LIO pre-charging enable signal controls the pre-charging operation of the memory on the LIO signal line; wherein when the function control signal is a high level signal, the refresh state transmission unit outputs a first signal based on the refresh state signal; when the function control signal and the refresh state signal are both high-level signals, the first signal is a high-level signal, the LIO pre-charging enable signal is a low-level signal, and the LIO signal line is not pre-charged, so that extra power consumption caused by pre-charging of the LIO signal line in the refresh cycle can be saved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor circuit design, and particularly to a local input / output (LIO) precharge control circuit for a dynamic random access memory. Background Art

[0002] A dynamic random access memory (DRAM) is a type of semiconductor memory. A storage cell in a DRAM typically includes a transistor and a capacitor, and it usually uses a transistor and a capacitor to represent a binary bit (bit). Its main principle of operation is to use the amount of charge stored in the capacitor to represent whether a bit is 1 or 0. In reality, since there is a leakage current phenomenon in the transistor, the amount of charge stored in the capacitor is not sufficient to correctly distinguish the data, resulting in data corruption. To maintain the correctness of the data, it is necessary to periodically refresh the DRAM and recharge it.

[0003] A DRAM chip is composed of several banks, and each bank includes several word lines (WLs) and several bit lines (BLs). Each bit line is connected to a sense amplifier. Figure 1 FIG. is a circuit schematic diagram of a sense amplifier. As Figure 1 shown, the sense amplifier includes a first-stage sense circuit 11 and a second-stage sense circuit 12. Among them, the first-stage sense circuit 11 includes two LIO signal lines (i.e., LIOB and LIOT), and the two LIO signal lines are precharged to a high level before a read operation and a write operation (i.e., before the read enable signal or the write enable signal is enabled); during a read operation, the write enable signal (LIOMUXENT) is an invalid low-level signal, and the read enable signal (LSAENT) is a valid high-level signal. The voltage difference of the two LIO signal lines causes a discharge difference and is transmitted to the input terminals MIOB and MIOT of the second-stage sense circuit 12 for the next-stage amplification. During a write operation, the read enable signal (LSAENT) is an invalid low-level signal, and the write enable signal (LIOMUXENT) is a valid high-level signal, and the write driver (WRDRV) drives the writing. During a refresh operation, the LIO signal lines of the first-stage sense circuit 11 are not selected to be connected to the bit lines but are still precharged, which will cause additional power consumption. Summary of the Invention

[0004] The present invention provides an LIO precharge control circuit for a dynamic random access memory, which can prevent precharging of the LIO signal lines during the refresh cycle, thereby saving the additional power consumption caused by precharging the LIO signal lines during the refresh cycle.

[0005] To achieve the above object, the LIO precharge control circuit of the dynamic random access memory provided by the present invention includes a refresh status transfer unit and an LIO precharge control unit. The refresh status transfer unit receives a refresh status signal and a function control signal and outputs a first signal; the LIO precharge control unit receives the first signal, a read enable signal, and a write enable signal, and outputs an LIO precharge enable signal based on the first signal, the read enable signal, and the write enable signal. The dynamic random access memory performs a precharge operation on the LIO signal line of the dynamic random access memory based on the LIO precharge enable signal; wherein, when the function control signal is a high-level signal, the refresh status transfer unit outputs the first signal based on the refresh status signal; when both the function control signal and the refresh status signal are high-level signals, the first signal is a high-level signal, the LIO precharge enable signal is a low-level signal, and the dynamic random access memory does not precharge the LIO signal line.

[0006] Optionally, when the function control signal is a low-level signal, the first signal remains a low-level signal, and the polarity of the LIO precharge enable signal is determined by the polarities of the read enable signal and the write enable signal.

[0007] Optionally, when any one of the first signal, the read enable signal, and the write enable signal is a high-level signal, the LIO precharge enable signal is a low-level signal, and the dynamic random access memory does not precharge the LIO signal line.

[0008] Optionally, when the first signal, the read enable signal, and the write enable signal are all low-level signals, the LIO precharge enable signal is a high-level signal, and the dynamic random access memory precharges the LIO signal line.

[0009] Optionally, the refresh status transfer unit includes a multiplexer. The first input terminal of the multiplexer receives the refresh status signal, the second input terminal of the multiplexer is grounded, the first control terminal of the multiplexer receives the function control signal, and the output terminal of the multiplexer outputs the first signal.

[0010] Optionally, the multiplexer further includes a second control terminal, and the second control terminal receives the inverted signal of the function control signal. The inverted signal of the function control signal and the function control signal jointly control the output of the multiplexer.

[0011] Optionally, the refresh status transfer unit includes an AND gate. The first input terminal of the AND gate receives the refresh status signal, the second output terminal of the AND gate receives the function control signal, and the output terminal of the AND gate outputs the first signal.

[0012] Optionally, the LIO precharge control unit includes a three-input NOR gate. The three input terminals of the three-input NOR gate respectively receive the first signal, the read enable signal, and the write enable signal, and the output terminal of the three-input NOR gate outputs the LIO precharge enable signal.

[0013] Optionally, the dynamic random access memory includes a sense amplifier. The sense amplifier includes the LIO signal line. The LIO signal line is electrically connected to the corresponding bit line during the read operation and the write operation of the dynamic random access memory, and the LIO signal line is not connected to the bit line during the refresh operation of the dynamic random access memory.

[0014] Optionally, when the refresh status signal is a high-level signal, it indicates that the dynamic random access memory is performing a refresh operation; when the refresh status signal is a low-level signal, it indicates that the dynamic random access memory is not performing a refresh operation.

[0015] The LIO precharge control circuit of the dynamic random access memory provided by the present invention includes a refresh status transfer unit and an LIO precharge control unit. The refresh status transfer unit receives the refresh status signal and the function control signal and outputs a first signal. The LIO precharge control unit receives the first signal, the read enable signal, and the write enable signal, and outputs the LIO precharge enable signal based on the first signal, the read enable signal, and the write enable signal. The dynamic random access memory precharges the LIO signal line based on the LIO precharge enable signal. Among them, when the function control signal is a high-level signal, the refresh status transfer unit outputs the first signal based on the refresh status signal; when both the function control signal and the refresh status signal are high-level signals, it indicates that the refresh status transfer unit is functioning and the memory is performing a refresh operation. At this time, the first signal is a high-level signal, and the LIO precharge enable signal is a low-level signal, so that the LIO signal line is floating and not precharged for the LIO signal line. In this way, the LIO signal line can be not precharged during the refresh cycle, and the extra power consumption brought by the precharge of the LIO signal line during the refresh cycle can be saved, that is, the power consumption during the refresh process is reduced, and the performance of the DRAM system is improved.

[0016] Furthermore, when the function control signal is a high-level signal, the refresh status transfer unit outputs the first signal based on the refresh status signal. When the function control signal is a low-level signal, the first signal remains a low-level signal. In this way, the function control signal can control the opening and closing of the refresh status transfer unit, that is, the function control signal can control whether the refresh status transfer unit outputs the first signal based on the refresh status signal, so that the influence of the refresh status on the precharging operation of the LIO signal line can be controlled more flexibly, and the flexibility of the LIO precharge control circuit is relatively high. Brief Description of the Drawings

[0017] Figure 1 It is a schematic circuit diagram of a sense amplifier.

[0018] Figure 2 It is an existing LIO precharge control circuit of a dynamic random access memory.

[0019] Figure 3 It is a schematic circuit diagram of the LIO precharge control circuit of the dynamic random access memory provided by an embodiment of the present invention.

[0020] Figure 4 It is a schematic circuit diagram of the LIO precharge control circuit of the dynamic random access memory provided by another embodiment of the present invention. Detailed Description of the Embodiments

[0021] The charge voltage of the storage unit of a dynamic random access memory (DRAM) is very low. If no appropriate amplification process is performed, the read signal will be very weak and vulnerable to interference, resulting in an increase in the error rate. Therefore, a sense amplifier is provided in the dynamic random access memory. The sense amplifier amplifies the signal by comparing the difference between the charge voltage of the storage unit and the reference voltage, thereby improving the signal quality and reducing interference. After the transistor accessing the storage unit is turned on, the capacitor in the storage unit shares the stored charge with the bit line, causing the capacitor to discharge. For the next read operation, the sense amplifier must restore the amplified voltage value to the capacitor of the storage unit, that is, after the sensing and amplification operations, the sense amplifier restores the value of the storage unit.

[0022] Reference Figure 1 As shown, the sense amplifier of the dynamic random access memory includes two LIO signal lines (i.e., LIOB and LIOT). The two LIO signal lines are electrically connected to the corresponding bit lines during the read operation and write operation of the dynamic random access memory, and the two LIO signal lines are precharged to a high level before reading and writing (i.e., before the read enable signal or write enable signal is enabled), while the two LIO signal lines are not connected to the bit lines during the refresh operation of the dynamic random access memory.

[0023] Figure 2 It is an existing LIO precharge control circuit of a dynamic random access memory. As Figure 2 shown, the LIO precharge control circuit of the dynamic random access memory includes a two-input NOR gate 13. The two input terminals of the two-input NOR gate 13 are respectively connected to the read enable signal and the write enable signal, and the output terminal of the two-input NOR gate 13 outputs the LIO precharge enable signal.

[0024] Reference Figure 2As shown, in the prior art, a precharge operation is performed on the LIO signal line during the read, write, and refresh operations of the DRAM chip. The LIO precharge enable signal is jointly controlled by the read enable signal and the write enable signal. The control logic is that when the read and write cycles are valid, that is, when the read enable signal or the write enable signal is enabled (is a high-level signal), the LIO precharge enable signal is an invalid low-level signal, and the LIO signal line is not precharged; after the read and write cycles are completed and during the refresh operation, the LIO precharge enable signal is a valid high-level signal, and a precharge operation is performed on the LIO signal line. However, at this time, the LIO signal line is not connected to the selected bit line and does not require precharging, which will cause additional power consumption.

[0025] To this end, the present invention provides an LIO precharge control circuit for a dynamic random access memory. The LIO precharge control circuit includes a refresh status transfer unit and an LIO precharge control unit. The refresh status transfer unit can select whether to output a first signal based on the refresh status signal through the control of the function control signal. The refresh status signal indicates whether the dynamic random access memory (hereinafter simply referred to as the memory) is performing a refresh operation. The LIO precharge control unit outputs an LIO precharge enable signal according to the first signal, the read enable signal, and the write enable signal. The memory performs a precharge operation on the LIO signal line according to the LIO precharge enable signal. In this way, the LIO signal line can be precharged according to the refresh status of the memory. Specifically, the LIO signal line is not precharged during the refresh cycle, thereby saving the additional power consumption caused by the precharge of the LIO signal line during the refresh cycle, that is, reducing the power consumption during the refresh process and improving the performance of the DRAM system.

[0026] The following further details the LIO precharge control circuit for a dynamic random access memory proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0027] Figure 3 It is a circuit schematic diagram of an LIO precharge control circuit for a dynamic random access memory provided by an embodiment of the present invention.

[0028] As Figure 3As shown, the LIO precharge control circuit of the dynamic random access memory provided by this application includes a refresh status transfer unit 21 and an LIO precharge control unit 22. The refresh status transfer unit 21 receives a refresh status signal and a function control signal and outputs a first signal; the LIO precharge control unit 22 receives the first signal, a read enable signal, and a write enable signal, and outputs an LIO precharge enable signal based on the first signal, the read enable signal, and the write enable signal. The dynamic random access memory precharges the LIO signal line of the dynamic random access memory based on the LIO precharge enable signal. Among them, when the function control signal is a high-level signal, the refresh status transfer unit 21 outputs a first signal based on the refresh status signal; when both the function control signal and the refresh status signal are high-level signals, the first signal is a high-level signal, and the LIO precharge enable signal is a low-level signal, and the dynamic random access memory does not precharge the LIO signal line.

[0029] Specifically, the dynamic random access memory includes a sense amplifier. The sense amplifier includes an LIO signal line. The LIO signal line is electrically connected to a corresponding bit line during a read operation and a write operation of the dynamic random access memory, and the LIO signal line is not connected to the bit line during a refresh operation of the dynamic random access memory.

[0030] The refresh status signal represents the refresh status of the memory. Specifically, when the refresh status signal is a high-level signal, it represents that the dynamic random access memory is performing a refresh operation; when the refresh status signal is a low-level signal, it represents that the dynamic random access memory is not performing a refresh operation.

[0031] When the function control signal is a high-level signal, the refresh status transfer unit 21 enables the refresh status signal transfer function. The refresh status transfer unit 21 outputs a first signal based on the refresh status signal, and the LIO precharge control unit 22 outputs an LIO precharge enable signal based on the first signal, the read enable signal, and the write enable signal; when the function control signal is a low-level signal, the refresh status transfer unit 21 turns off the refresh status signal transfer function, and the first signal output by the refresh status transfer unit 21 continuously remains a low-level signal, that is, the first signal is an invalid signal, and the polarity of the LIO precharge enable signal is determined by the polarities of the read enable signal and the write enable signal.

[0032] In one embodiment, as Figure 3 shown, the refresh status transfer unit 21 includes a multiplexer 211. The multiplexer 211 has two input terminals, at least one control terminal, and one output terminal. The first input terminal of the multiplexer 211 receives the refresh status signal, the second input terminal of the multiplexer 211 is grounded, and the output terminal of the multiplexer 211 outputs the first signal.

[0033] Exemplarily, referring toFigure 3 As shown, the multiplexer 211 may have a first control terminal and a second control terminal. The first control terminal receives a function control signal, and the second control terminal receives the inverse signal of the function control signal. The function control signal and the inverse signal of the function control signal jointly control the output of the multiplexer 211. In this way, the control signal of the multiplexer 211 is relatively stable. Exemplarily, when the function control signal is 0 and the inverse signal of the function control signal is 1, they jointly control the multiplexer 211 to select the signal received by one of the first input terminal and the second input terminal of the multiplexer 211 as the output; when the function control signal is 1 and the inverse signal of the function control signal is 0, they jointly control the multiplexer 211 to select the signal received by the other of the first input terminal and the second input terminal of the multiplexer 211 as the output.

[0034] In some embodiments, the multiplexer 211 may be provided with only one control terminal, and this control terminal receives a function control signal.

[0035] Figure 4 The circuit schematic diagram of the LIO precharge control circuit of the dynamic random access memory provided by another embodiment of the present invention. In one embodiment, as Figure 4 shown, the refresh state transfer unit 21 may include an AND gate 212. The first input terminal of the AND gate 212 receives a refresh state signal, the second output terminal of the AND gate 212 receives a function control signal, and the output terminal of the AND gate 212 outputs a first signal. Among them, when the function control signal is a low-level signal, the first signal output by the AND gate 212 is a low-level signal. At this time, the refresh state transfer unit 21 turns off the refresh state signal transfer function; when the function control signal is a high-level signal and the refresh state signal is a high-level signal, the first signal output by the AND gate 212 is a high-level signal; when the function control signal is a high-level signal and the refresh state signal is a low-level signal, the first signal output by the AND gate 212 is a low-level signal.

[0036] It should be noted that when the refresh state transfer unit is the multiplexer 211 or the AND gate 212, the circuit is relatively simple; of course, the refresh state transfer unit is not limited to the multiplexer 211 and the AND gate 212, and may also be composed of other logic electronic components as long as its function can be realized.

[0037] Refer to Figure 3 and Figure 4 shown. In some embodiments of the present application, the LIO precharge control unit includes a three-input NOR gate 221. The three input terminals of the three-input NOR gate 221 respectively receive the first signal, a read enable signal, and a write enable signal. The output terminal of the three-input NOR gate outputs an LIO precharge enable signal, and the dynamic random access memory performs a precharging operation on the LIO signal line based on the LIO precharge enable signal.

[0038] Among them, when the read enable signal is a high-level signal, it indicates that the memory is performing a read operation; when the read enable signal is a low-level signal, it indicates that the memory is not performing a read operation. When the write enable signal is a high-level signal, it indicates that the memory is performing a write operation; when the write enable signal is a low-level signal, it indicates that the memory is not performing a write operation.

[0039] Table 1 is the control logic truth table of the LIO precharge control circuit when the function control signal of the refresh status transfer unit is high. Among them, H represents a high-level signal and L represents a low-level signal. The control logic of the LIO precharge control circuit when the function control signal is a high-level signal will be described below in conjunction with Table 1. As shown in Table 1, when the function control signal is a high-level signal, the polarity of the first signal output by the refresh status transfer unit 21 is the same as the polarity of the refresh status signal. As shown in Group 5, when the refresh status signal is a high-level signal and both the read enable signal and the write enable signal are low-level signals, the memory is performing a refresh operation and not performing read and write operations. At this time, the first signal and the refresh status signal are both high-level signals, and the LIO precharge enable signal output by the LIO precharge control unit 22 is a low-level signal, and the LIO signal line is not precharged, which can save the extra power consumption caused by LIO signal line precharging during the refresh cycle; as shown in Group 1, when the refresh status signal, the read enable signal, and the write enable signal are all low-level signals, the memory has no refresh operation, read operation, or write operation. At this time, the first signal and the refresh status signal are both low-level signals, and the LIO precharge enable signal is a high-level signal, and the memory precharges the LIO signal line to prepare for subsequent read and write operations; as shown in Group 2, when the refresh status signal and the read enable signal are both low-level signals and the write enable signal is a high-level signal, the memory is performing a write operation, and the LIO precharge enable signal is a low-level signal, and the memory does not precharge the LIO signal line; as shown in Group 3, when the refresh status signal and the write enable signal are both low-level signals and the read enable signal is a high-level signal, the memory is performing a read operation, and the LIO precharge enable signal is a low-level signal, and the memory does not precharge the LIO signal line; since the memory will not perform more than two of the refresh operation, read operation, and write operation at the same time, there are no situations in Groups 4, 6, 7, and 8.

[0040] Table 1

[0041]

[0042] Table 2 is the control logic truth table of the LIO precharge control circuit when the function control signal of the refresh status transfer unit is low. Here, H represents a high-level signal and L represents a low-level signal. The control logic of the LIO precharge control circuit when the function control signal is a low-level signal is described below in conjunction with Table 2. As shown in Table 2, when the function control signal is a low-level signal, the first signal output by the refresh status transfer unit 21 remains a low-level signal, and the refresh status transfer unit 21 turns off the refresh status signal transfer function. The polarity of the LIO precharge enable signal is determined by the polarities of the read enable signal and the write enable signal. Referring to Table 2, as shown in Group 1 and Group 5, when both the read enable signal and the write enable signal are low-level signals, the memory is not performing a read operation or a write operation. At this time, the LIO precharge enable signal is a high-level signal, and the memory precharges the LIO signal line to prepare for subsequent read or write operations. Comparing Group 1 and Group 5, it can be seen that at this time, regardless of whether the refresh status signal is high or low, it does not affect the LIO precharge enable signal; as shown in Group 2, when the read enable signal is a low-level signal and the write enable signal is a high-level signal, the memory is performing a write operation and not a read operation, and the LIO precharge enable signal is a low-level signal, and the memory does not precharge the LIO signal line; as shown in Group 3, when the write enable signal is a low-level signal and the read enable signal is a high-level signal, the memory is performing a read operation and not a write operation, and the LIO precharge enable signal is a low-level signal, and the memory does not precharge the LIO signal line; since the memory will not perform more than two of the refresh operation, read operation, and write operation simultaneously, the situations of Group 4, Group 6, Group 7, and Group 8 do not exist.

[0043] Table 2

[0044]

[0045] It can be seen from Table 1 and Table 2 that when any one of the first signal, the read enable signal, and the write enable signal is a high-level signal, the LIO precharge enable signal is a low-level signal, and the memory does not precharge the LIO signal line; when the first signal, the read enable signal, and the write enable signal are all low-level signals, the LIO precharge enable signal is a high-level signal, and the memory precharges the LIO signal line.

[0046] The LIO precharge control circuit of the dynamic random access memory provided by the present invention includes a refresh status transfer unit 21 and an LIO precharge control unit 22. The refresh status transfer unit 21 receives a refresh status signal and a function control signal and outputs a first signal. The LIO precharge control unit 22 receives the first signal, a read enable signal, and a write enable signal, and outputs an LIO precharge enable signal based on the first signal, the read enable signal, and the write enable signal. The dynamic random access memory performs a precharge operation on the LIO signal line based on the LIO precharge enable signal. Among them, when the function control signal is a high-level signal, the refresh status transfer unit outputs a first signal based on the refresh status signal; when both the function control signal and the refresh status signal are high-level signals, it indicates that the refresh status transfer unit 21 is functioning and the memory is performing a refresh operation. At this time, the first signal is a high-level signal, and the LIO precharge enable signal is a low-level signal, so that the LIO signal line is floating and not precharged for the LIO signal line. In this way, the LIO signal line can be not precharged during the refresh cycle, and the extra power consumption brought by the precharge of the LIO signal line during the refresh cycle can be saved, that is, the power consumption during the refresh process is reduced, and the performance of the DRAM system is improved.

[0047] Further, when the function control signal is a high-level signal, the refresh status transfer unit outputs a first signal based on the refresh status signal. When the function control signal is a low-level signal, the first signal remains a low-level signal. In this way, the function control signal can control the opening and closing of the function of the refresh status transfer unit, that is, the function control signal can control whether the refresh status transfer unit outputs a first signal based on the refresh status signal, so that the influence of the refresh status on the precharge operation of the LIO signal line can be controlled more flexibly, and the flexibility of the LIO precharge control circuit is relatively high.

[0048] The above description is only a description of the preferred embodiments of the present invention, and does not limit any scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes, and decorations made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solutions of the present invention all belong to the protection scope of the technical solutions of the present invention.

Claims

1. A LIO precharge control circuit for a dynamic random access memory, characterized in that: include: A refresh state transmission unit receives a refresh state signal and a function control signal and outputs a first signal; as well as An LIO precharge control unit receives the first signal, a read enable signal, and a write enable signal, and outputs an LIO precharge enable signal based on the first signal, the read enable signal, and the write enable signal, and the dynamic random access memory performs a precharge operation on the LIO signal line of the dynamic random access memory based on the LIO precharge enable signal; Among them, when the function control signal is a high-level signal, the refresh state transmission unit outputs the first signal based on the refresh state signal; when the function control signal and the refresh state signal are both high-level signals, the first signal is a high-level signal, the LIO pre-charge enable signal is a low-level signal, and the dynamic random access memory does not pre-charge the LIO signal line.

2. The LIO precharge control circuit of a dynamic random access memory according to claim 1, characterized in that: When the function control signal is a low level signal, the first signal continues to be a low level signal, and the polarity of the LIO precharge enable signal is determined by the polarity of the read enable signal and the polarity of the write enable signal.

3. The LIO precharge control circuit of a dynamic random access memory according to claim 1, characterized in that: When any one of the first signal, the read enable signal and the write enable signal is a high level signal, the LIO precharge enable signal is a low level signal, and the dynamic random access memory does not precharge the LIO signal line.

4. The LIO precharge control circuit of a dynamic random access memory according to claim 1, wherein: When the first signal, the read enable signal and the write enable signal are all low level signals, the LIO precharge enable signal is a high level signal, and the dynamic random access memory precharges the LIO signal line.

5. The LIO precharge control circuit of a dynamic random access memory according to claim 1, wherein: The refresh state transfer unit includes a multiplexer, a first input terminal of the multiplexer receives the refresh state signal, a second input terminal of the multiplexer is grounded, a first control terminal of the multiplexer receives the function control signal, and an output terminal of the multiplexer outputs the first signal.

6. The LIO precharge control circuit of a dynamic random access memory according to claim 5, characterized in that: The multiplexer further includes a second control terminal, the second control terminal receives an inverted signal of the function control signal, and the inverted signal of the function control signal and the function control signal jointly control the output of the multiplexer.

7. The LIO precharge control circuit of a dynamic random access memory according to claim 1, wherein: The refresh state transfer unit includes an AND gate, a first input terminal of the AND gate receives the refresh state signal, a second output terminal of the AND gate receives the function control signal, and an output terminal of the AND gate outputs the first signal.

8. The LIO precharge control circuit of a dynamic random access memory according to claim 1, wherein: The LIO precharge control unit includes a three-input NOR gate, wherein three input ends of the three-input NOR gate respectively receive the first signal, the read enable signal and the write enable signal, and an output end of the three-input NOR gate outputs the LIO precharge enable signal.

9. The LIO precharge control circuit of a dynamic random access memory according to claim 1, wherein: The dynamic random access memory includes a sense amplifier, the sense amplifier includes the LIO signal line, the LIO signal line is electrically connected to the corresponding bit line when the dynamic random access memory performs a read operation and a write operation, and the LIO signal line is not connected to the bit line when the dynamic random access memory performs a refresh operation.

10. The LIO precharge control circuit of a dynamic random access memory according to claim 1, wherein: When the refresh status signal is a high level signal, it indicates that the dynamic random access memory is undergoing a refresh operation; when the refresh status signal is a low level signal, it indicates that the dynamic random access memory is not undergoing a refresh operation.

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