Digital multi-bit rram computing method and apparatus for protecting high-weight data

Abstract

The application relates to a digital multi-bit RRAM computing method and device for protecting high-weight data, wherein the method comprises the following steps: the output of a multi-bit RRAM is separately processed, so that a plurality of weight data are stored in one RRAM, and the high bits are protected by bit protection or direct output, so as to guarantee the accuracy of the data; in combination with the fault tolerance of a neural network convolution, the computing power consumption is greatly reduced in the inspection process, the accuracy and the power consumption are balanced, the multiply-accumulate calculation is more flexible, and the reliability of the data is greatly guaranteed. Therefore, the problems that the RRAM output is very dense, the instability of the RRAM itself exists, drift may exist, and partial data flipping is prone to occur are solved.

Description

Technical Field

[0001] This application relates to the field of digital multi-bit RRAM storage technology, and in particular to a digital multi-bit RRAM calculation method and apparatus for protecting high-weight data. Background Technology

[0002] Resistive Random Access Memory (RRAM) is a highly suitable non-volatile memory for accelerating neural network hardware, offering high density and facilitating in-memory computing. Currently, binary digitization (BID) is a more feasible and reliable approach.

[0003] However, because RRAM outputs are very dense, data transmission errors may occur during transmission, causing some of the output data to flip. In addition, the drift of adjacent conductance states in RRAM devices can cause data errors, and the intermediate conductance state is relatively more unstable. At the same time, RRAM is usually only usable once after being written to store one or more bits or one bit of data for stability.

[0004] In summary, due to the very dense output of RRAM and its inherent instability, drift may occur, which can easily lead to partial data flipping, and this problem urgently needs to be solved. Summary of the Invention

[0005] This application provides a digital multi-bit RRAM calculation method and apparatus for protecting high-weight data, in order to solve the problems that may occur due to the very dense output of RRAM and its inherent instability, such as drift and easy flipping of some data.

[0006] The first aspect of this application provides a method for calculating digital multi-bit RRAMs to protect high-weight data, comprising the following steps: determining the number of calculation cycles and the number of RRAMs corresponding to the multiple target multi-bit weight data based on the number of bits of the multiple target multi-bit weight data, and controlling each RRAM to output multiple columns of current values ​​in each calculation cycle; converting each column of current values ​​into two bits of data in the corresponding target multi-bit weight data, and determining the high-order and low-order bits of the two bits of data in each calculation cycle for each target multi-bit weight data; determining multiple check RRAMs in all RRAMs, and using the... The multiple check bits RRAM perform data verification operations on the high-order bits of each target multi-bit weight data in each calculation cycle, and perform multiply-add operations on the low-order bits and the low-order bits of the preset stored data, and then perform multiply-add operations on the high-order bits after the data verification operation and the high-order bits of the preset stored data to obtain low-order weight multiply-add results and high-order weight multiply-add results; perform a preset shift operation on the high-order weight multiply-add results to obtain shifted data of each target multi-bit weight data in each calculation cycle, and then add the shifted data and the low-order weight multiply-add results to obtain the data multiply-add results corresponding to the multiple target multi-bit weight data.

[0007] Optionally, in one embodiment of this application, controlling each preset RRAM to output multiple columns of current values ​​in each calculation cycle includes: determining the target bit line corresponding to each calculation cycle, and applying a preset voltage to the target bit line to control each RRAM to output the multiple columns of current values ​​in each calculation cycle.

[0008] Optionally, in one embodiment of this application, the step of converting each column of current values ​​in the multi-column current values ​​into two bits of corresponding target multi-bit weighted data includes: converting each column of current values ​​into a corresponding target voltage value based on a preset SA structure, and generating two bits of data corresponding to the target voltage value using a preset digital-to-analog converter.

[0009] Optionally, in one embodiment of this application, the step of determining multiple check bit RRAMs in all RRAMs, and using the multiple check bit RRAMs to perform data verification operations on the high-bit data of each target multi-bit weight data in each calculation cycle, and performing multiply-add operations on the low-bit data and the low-bit data of the preset storage data, and performing multiply-add operations on the high-bit data after the data verification operation and the high-bit data of the preset storage data to obtain the low-bit weight multiply-add result and the high-bit weight multiply-add result, includes: determining the multiple check bit RRAMs in all RRAMs, and obtaining the corresponding check bit data according to the multiple check bit RRAMs; transmitting the high-bit data to the preset storage data. In the established verification unit, the high-bit data is subjected to ECC data verification using the verification bit data to repair high-bit data with a preset flip error; the high-bit data after the data verification operation is sent to a preset high-weight multiply-accumulate unit, where the high-bit data after the data verification operation and the high-bit data of the preset stored data are multiplied and accumulated to obtain the high-weight multiply-accumulate result; the low-bit data is sent to a preset low-weight multiply-accumulate unit, where the low-bit data and the low-bit data of the preset stored data are multiplied and accumulated to obtain the low-weight multiply-accumulate result.

[0010] Optionally, in one embodiment of this application, the step of performing a preset shift operation on the high-order weight multiplication and addition result to obtain shifted data for each target multi-bit weight data in each calculation cycle, and adding the shifted data and the low-order weight multiplication and addition result to obtain the data multiplication and addition result corresponding to the plurality of target multi-bit weight data, includes: performing a preset shift operation on the high-order weight multiplication and addition result in each calculation cycle to obtain shifted data and displacement count signal corresponding to each calculation cycle; adding the shifted data and the low-order weight multiplication and addition result to obtain a high-low order addition result, and performing a preset optional displacement operation on the high-low order addition result according to the displacement count signal corresponding to each calculation cycle to obtain an optional displacement result for each target multi-bit weight data in each calculation cycle; and sending the optional displacement result corresponding to each target multi-bit weight data to a preset accumulator to obtain the data multiplication and addition result corresponding to the plurality of target multi-bit weight data.

[0011] A second aspect of this application provides a digital multi-bit RRAM computing device for protecting high-weight data, comprising: a control module, configured to determine the number of calculation cycles and the number of RRAMs corresponding to the multiple target multi-bit weight data based on the number of bits of the multiple target multi-bit weight data, and control each RRAM to output multiple columns of current values ​​in each calculation cycle; a conversion module, configured to convert each column of current values ​​in the multiple columns of current values ​​into two bits of data in the corresponding target multi-bit weight data, and determine the high-order bit and low-order bit of the two bits of data in each calculation cycle of the multiple target multi-bit weight data; and a verification module, configured to determine multiple verification bits in all RRAMs. The calculation module performs a data verification operation on the high-order bits of each target multi-bit weight data in each calculation cycle using the multiple verification bits RRAM, and performs a multiplication-addition operation on the low-order bits and the low-order bits of the preset stored data, and performs a multiplication-addition operation on the high-order bits after the data verification operation and the high-order bits of the preset stored data to obtain the low-order weight multiplication-addition result and the high-order weight multiplication-addition result; the calculation module performs a preset shift operation on the high-order weight multiplication-addition result to obtain the shifted data of each target multi-bit weight data in each calculation cycle, and adds the shifted data and the low-order weight multiplication-addition result to obtain the data multiplication-addition result corresponding to the multiple target multi-bit weight data.

[0012] Optionally, in one embodiment of this application, the control module includes: a determination unit, configured to determine the target bit line corresponding to each calculation cycle, and apply a preset voltage to the target bit line to control each RRAM to output the multi-column current values ​​in each calculation cycle.

[0013] Optionally, in one embodiment of this application, the conversion module includes: a generation unit, used to convert each column of current values ​​into a corresponding target voltage value based on a preset SA structure, and to generate two bits of data corresponding to the target voltage value using a preset digital-to-analog converter.

[0014] Optionally, in one embodiment of this application, the verification module includes: an acquisition unit, configured to determine the plurality of verification bit RRAMs in all RRAMs, and acquire corresponding verification bit data according to the plurality of verification bit RRAMs; a repair unit, configured to transmit the high-bit data to a preset verification unit, so as to perform ECC data verification operation on the high-bit data using the verification bit data in the verification unit, so as to repair the high-bit data with a preset flip error; a first multiply-accumulate unit, configured to send the high-bit data after the data verification operation to a preset high-weight multiply-accumulate unit, so as to perform multiply-accumulate operation on the high-bit data after the data verification operation and the high-bit data of the preset stored data in the preset high-weight multiply-accumulate unit, so as to obtain the high-weight multiply-accumulate result; and a second multiply-accumulate unit, configured to send the low-bit data to a preset low-weight multiply-accumulate unit, and perform multiply-accumulate operation on the low-bit data and the low-bit data of the preset stored data in the preset low-weight multiply-accumulate unit, so as to obtain the low-weight multiply-accumulate result.

[0015] Optionally, in one embodiment of this application, the calculation module includes: a first shift unit, configured to perform a preset shift operation on the high-order weight multiplication and addition result in each calculation cycle to obtain shift data and displacement count signal corresponding to each calculation cycle; a second shift unit, configured to add the shift data and the low-order weight multiplication and addition result to obtain a high-low order addition result, and perform a preset optional displacement operation on the high-low order addition result according to the displacement count signal corresponding to each calculation cycle to obtain an optional displacement result for each target multi-bit weight data in each calculation cycle; and an accumulation unit, configured to send the optional displacement result corresponding to each target multi-bit weight data to a preset accumulator to obtain a data multiplication and addition result corresponding to the plurality of target multi-bit weight data.

[0016] A third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the digital multi-bit RRAM calculation method for protecting high-weight data as described in the above embodiments.

[0017] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method for calculating digital multi-bit RRAM to protect high-weight data.

[0018] A fifth aspect of this application provides a computer program product, including a computer program that is executed to implement the above-described method for calculating digital multi-bit RRAM for protecting high-weight data.

[0019] Therefore, the embodiments of this application have the following beneficial effects:

[0020] The embodiments of this application can determine the number of calculation cycles and the number of RRAMs corresponding to multiple target multi-bit weight data based on the number of bits in multiple target multi-bit weight data, and control each RRAM to output multiple columns of current values ​​in each calculation cycle; convert each column of current values ​​into two bits of data in the corresponding target multi-bit weight data, and determine the high-order and low-order bits of the two bits of data in each calculation cycle for each target multi-bit weight data; determine multiple check RRAMs in all RRAMs, and use the multiple check RRAMs to check each In each calculation cycle, the high-bit data of the target multi-bit weight data undergoes a data verification operation. A multiplication-addition operation is then performed on the low-bit data and the low-bit data of the preset storage data. The high-bit data after the data verification operation is then multiplied and added to the high-bit data of the preset storage data to obtain the low-bit weight multiplication-addition result and the high-bit weight multiplication-addition result. A preset shift operation is then performed on the high-bit weight multiplication-addition result to obtain the shifted data for each target multi-bit weight data in each calculation cycle. The shifted data and the low-bit weight multiplication-addition result are then added to obtain the data multiplication-addition result corresponding to multiple target multi-bit weight data. This application effectively utilizes ECC (Error-Correcting Code) to verify and correct the high-bit data, thereby improving calculation accuracy. Simultaneously, a single RRAM cell can be used for both high-bit and low-bit storage, increasing the RRAM density and achieving RRAM reuse with high-precision output. This solves the problems of high RRAM output density and inherent instability, such as drift and potential data flipping.

[0021] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0022] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0023] Figure 1 This is a flowchart illustrating a digital multi-bit RRAM calculation method for protecting high-weight data according to an embodiment of this application;

[0024] Figure 2 A schematic diagram of an 8-bit data storage structure provided for one embodiment of this application;

[0025] Figure 3 A schematic diagram illustrating the protection of high-weight output information is provided as an embodiment of this application;

[0026] Figure 4 A schematic diagram of the output computing structure of a multi-bit RRAM memory cell is provided as an embodiment of this application;

[0027] Figure 5 A schematic diagram illustrating a multiplication and addition operation using eight 8-bit numbers, provided as an embodiment of this application;

[0028] Figure 6 This is an example diagram of a digital multi-bit RRAM computing device for protecting high-weight data according to an embodiment of this application;

[0029] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0030] Among them, 10-a digital multi-bit RRAM computing device for protecting high-weight data; 100-control module, 200-conversion module, 300-verification module, 400-computation module; 701-memory, 702-processor, 703-communication interface. Detailed Implementation

[0031] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0032] The following description, with reference to the accompanying drawings, describes a method and apparatus for calculating digital multi-bit RRAMs to protect high-weight data according to embodiments of this application. Addressing the problems mentioned in the background art, this application provides a method for calculating digital multi-bit RRAMs to protect high-weight data. In this method, the number of calculation cycles and the number of RRAMs corresponding to multiple target multi-bit weight data are determined based on the number of bits in multiple target multi-bit weight data. Within each calculation cycle, each RRAM outputs multiple columns of current values. Each column of current values ​​is converted into two bits of the corresponding target multi-bit weight data, and the high-order and low-order bits of the two bits in each calculation cycle of the multiple target multi-bit weight data are determined. The method also determines the multiple... This application employs a check RRAM and utilizes multiple check RRAMs to perform data verification operations on the high-bit data of each target multi-bit weight data in each calculation cycle. It also performs multiplication and addition operations on the low-bit data and the low-bit data of the preset storage data, and then performs multiplication and addition operations on the high-bit data after the data verification operation and the high-bit data of the preset storage data to obtain the low-bit weight multiplication and addition results and the high-bit weight multiplication and addition results. A preset shift operation is then performed on the high-bit weight multiplication and addition results to obtain the shifted data of each target multi-bit weight data in each calculation cycle. Finally, the shifted data and the low-bit weight multiplication and addition results are added to obtain the data multiplication and addition results corresponding to multiple target multi-bit weight data. This application effectively utilizes ECC to verify and correct the high-bit values ​​to improve calculation accuracy. Simultaneously, it allows a single RRAM cell to be used for both high-bit and low-bit storage, increasing the RRAM density and achieving RRAM reuse with high-precision output. Therefore, it solves the problems of high-density RRAM output and its inherent instability, such as drift and potential data flipping.

[0033] Specifically, Figure 1 A flowchart illustrating a digital multi-bit RRAM calculation method for protecting high-weight data, provided in an embodiment of this application.

[0034] like Figure 1 As shown, the method for calculating digital multi-bit RRAM to protect high-weight data includes the following steps:

[0035] In step S101, the number of calculation cycles and the number of RRAMs corresponding to the multiple target multi-bit weight data are determined according to the number of bits of the multiple target multi-bit weight data, and each RRAM is controlled to output multiple columns of current values ​​within each calculation cycle.

[0036] The embodiments of this application can first determine the number of subsequent calculation cycles based on the number of bits of the multi-bit weighted data. For example, 8-bit data requires a total of four RRAMs and four calculation cycles, and each RRAM is controlled to output multiple columns of current values ​​within each calculation cycle.

[0037] Optionally, in one embodiment of this application, controlling each preset RRAM to output multiple columns of current values ​​in each calculation cycle includes: determining the target bit line corresponding to each calculation cycle and applying a preset voltage to the target bit line to control each RRAM to output multiple columns of current values ​​in each calculation cycle.

[0038] Specifically, Figure 2 This is a schematic diagram of an 8-bit data storage structure. Figure 2 As can be seen, the RRAM has a 1T1R structure. In each computation cycle, the embodiments of this application can select the row to be output via bit lines. Under the control of the input voltage, each RRAM can output the stored data information according to the pre-written weight information, and according to... Output the current for each column.

[0039] In step S102, each column of current values ​​in the multiple columns of current values ​​is converted into two bits of data in the corresponding target multi-bit weight data, and the high bit data and low bit data in the two bits of each target multi-bit weight data in the multiple target multi-bit weight data are determined in each calculation cycle.

[0040] Furthermore, embodiments of this application convert each column of current values ​​into corresponding two-bit data, and determine the high-bit data and low-bit data in the two-bit data of each target multi-bit weight data in each calculation cycle.

[0041] Optionally, in one embodiment of this application, converting each column of current values ​​in the multi-column current values ​​into two bits of data in the corresponding target multi-bit weighted data includes: converting each column of current values ​​into the corresponding target voltage value based on a preset SA structure, and generating two bits of data corresponding to the target voltage value using a preset digital-to-analog converter.

[0042] In one possible approach, embodiments of this application can convert each column of current values ​​into corresponding voltages using an SA structure, and then compare the converted voltages in an analog-to-digital converter to output 2-bit data, thereby reading 2-bit digital data from the RRAM.

[0043] It should be noted that outputting 8 bits of data requires a total of 4 RRAMs. In subsequent embodiments of this application, an additional 6 bits of information can be read from the control bit lines in other calculation cycles. In summary, embodiments of this application can read 2 bits of data in each calculation cycle, and a total of 8 bits of data can be read in 4 cycles.

[0044] It is understandable that although an RRAM stores 2 bits of data, the weight of these 2 bits of data is not continuous in the whole. In the first cycle, the low-order bit reads data[0] and the high-order bit reads data[4]. Similarly, in the second cycle, data[1] is output from the low-order bit of the RRAM and data[5] is output from the high-order bit. In the next two cycles, data[2], data[6] and data[3], data[7] are output. Two data are processed in one cycle, but the high-order data is given higher weight information in the processing. For example, when processing 8 bits of data, the high-order data on the same RRAM needs to be shifted left by 4 bits relative to the low-order data. Figure 2 As shown, the first RRAM stores 10, and the second, third, and fourth RRAMs store 01, 01, and 10, respectively. During the first cycle, WL... <0> After activation, the embodiments of this application can obtain xxx1xxx0; the second cycle WL <1> After activation, you can get xx01xx10; in the third cycle, you can get x001x110; in the fourth cycle, you can get the complete 8-bit number 10010110.

[0045] In step S103, multiple check bits RRAMs are determined in all RRAMs, and data verification operations are performed on the high-bit data of each target multi-bit weight data in each calculation cycle using the multiple check bits RRAMs. Multiply-add operations are performed on the low-bit data and the low-bit data of the preset storage data, and multiply-add operations are performed on the high-bit data after the data verification operation and the high-bit data of the preset storage data to obtain the low-bit weight multiply-add result and the high-bit weight multiply-add result.

[0046] Those skilled in the art should understand that in multi-bit programming, because the intermediate conductance state of RRAM is relatively more unstable, it may shift during the read and output processes, resulting in the high or low bits of the output being flipped. If two bits are checked simultaneously, the verification method used is more complex, and the drift of adjacent conductance states will only cause 1 LSB error. It is impossible to make corresponding adjustments according to the data distribution, which can easily lead to inaccurate correction and high power consumption in the verification.

[0047] As can be seen from the above 2-bit RRAM reading method, although they all come from the same RRAM, their weight information in the overall data is different. If the high-order data is flipped, it obviously has a significant impact on the result. Although both data can be checked and protected, the power consumption of the check is high. Therefore, in the embodiments of this application, only the high-order data is checked and protected in the storage structure circuit, thereby improving the calculation accuracy.

[0048] Optionally, in one embodiment of this application, multiple check bit RRAMs are determined in all RRAMs, and data verification operations are performed on the high-order bits of each target multi-bit weight data in each calculation cycle using the multiple check bit RRAMs. Furthermore, multiplication and addition operations are performed on the low-order bits of the low-order bits and the low-order bits of the preset stored data, and multiplication and addition operations are performed on the high-order bits of the data after the data verification operation and the high-order bits of the preset stored data to obtain the low-order weight multiplication and addition results and the high-order weight multiplication and addition results. This includes: determining multiple check bit RRAMs in all RRAMs, obtaining the corresponding check bit data according to the multiple check bit RRAMs; and transmitting the high-order bits of the data to... In the preset verification unit, ECC data verification is performed on the high-order bits of the data using the verification bit data to repair the high-order bits of the data with preset flip errors. The high-order bits of the data after the verification operation are sent to the preset high-order weight multiply-add unit, where the high-order bits of the data after the verification operation and the high-order bits of the preset stored data are multiplied and added to obtain the high-order weight multiply-add result. The low-order bits of the data are sent to the preset low-order weight multiply-add unit, where the low-order bits of the data and the low-order bits of the preset stored data are multiplied and added to obtain the low-order weight multiply-add result.

[0049] It should be noted that, as Figure 3 As shown, when outputting the entire line of RRAM, the last few RRAM bits are used as check bits, according to 2 m >n determines the number of check bits, where n is the number of data bits and m is the minimum number of check RRAMs.

[0050] In actual implementation, the embodiments of this application only need to provide a check code when the high-weight bits are output, and do not work when the low-weight bits are output. Figure 3 There are a total of 11 columns of RRAM. In the first clock cycle, WL <0> When enabled, the first row and 11 columns of RRAM output current, which is then output as 2-bit data through the SA and ADC modules. The high-order bits of this 2-bit data, as shown by the black line, enter the 8+3 check module. This check module uses Hamming code for verification to correct the flipped bits. After that, the corrected 8 high-order bits are output, while the low-order bits are output as shown. Figure 2The blue line section is directly output, resulting in 8 corrected high-bit data and 8 directly output low-bit data, which are respectively used as data[4] and data[0] of 8 8-bit numbers; WL is enabled in the second clock cycle. <1> And shut down WL <0> Similarly, the outputs are the data[5] and data[1] of eight 8-bit numbers; the third cycle outputs the remaining data[6], data[2], data[7], and data[3]. Through four cycles, two bits of each number are output in each cycle, and the high-bit number is checked and protected.

[0051] Therefore, the RRAM storage method of the embodiments of this application, by including ECC check bits, enables RRAM to be used simultaneously for storage structures with high weights and low weights, increasing the density of RRAM and having a greater utilization rate. In addition, the embodiments of this application reduce the probability of errors in high-weight data by performing ECC check on the high bits. In the context of large-scale computations such as neural networks, the output of small weights can be ignored in the results, and checking only the high weights can balance the accuracy of the results and power consumption.

[0052] In step S104, a preset shift operation is performed on the high-bit weight multiplication and addition result to obtain the shifted data of each target multi-bit weight data in each calculation cycle, and the shifted data and the low-bit weight multiplication and addition result are added to obtain the data multiplication and addition result corresponding to multiple target multi-bit weight data.

[0053] It should be noted that, Figure 4 The output calculation structure of multi-bit RRAM storage unit is shown. Taking 8 8-bit numbers as an example, the embodiment of this application can output the low weight bit to the low weight multiply-add module, input 8 bits in_low are multiplied one by one, and the output result is stored in the accumulator. The high bit data is output to the high weight multiply-add module through the verification module and multiplied by in_high. Since the high bit has a larger weight, it actually corresponds to data[4] in the 8-bit data. It needs to be shifted left by 4 bits through the shift module before being transmitted to the accumulator.

[0054] In the specific implementation process, the embodiment of this application saves the two multiply-accumulate results to the accumulator in the first clock cycle, and performs the same operation in the second clock cycle, storing the low-bit and high-bit results to the accumulator. However, since the output results of the second clock cycle are data[5] and data[1], it is necessary to shift left by one bit and add the original result inside the accumulator. The next two cycles are similar, and it is necessary to shift left by 2 bits and left by 3 bits respectively and accumulate them to the accumulator, thereby completing the multiply-accumulate output calculation of 8 8-bit numbers.

[0055] Optionally, in one embodiment of this application, a preset shift operation is performed on the high-order weight multiplication and addition result to obtain shifted data for each target multi-bit weight data in each calculation cycle, and the shifted data and the low-order weight multiplication and addition result are added to obtain data multiplication and addition results corresponding to multiple target multi-bit weight data. This includes: performing a preset shift operation on the high-order weight multiplication and addition result in each calculation cycle to obtain shifted data and displacement count signal corresponding to each calculation cycle; adding the shifted data and the low-order weight multiplication and addition result to obtain high- and low-order addition results, and performing a preset optional displacement operation on the high- and low-order addition results according to the displacement count signal corresponding to each calculation cycle to obtain optional displacement results for each target multi-bit weight data in each calculation cycle; and sending the optional displacement results corresponding to each target multi-bit weight data to a preset accumulator to obtain data multiplication and addition results corresponding to multiple target multi-bit weight data.

[0056] It should be noted that, Figure 5 The process of performing a multiplication-addition operation on eight 8-bit numbers is demonstrated, with a total of eight data<7:0> data. Due to the presence of 8-bit numbers, this embodiment requires four cycles for the calculation, with WL (Working Level) enabled separately in each of the four cycles. <0> WL <1> WL <2> WL <3> The first cycle, WL <0> The activation of the first row of MOS enables the RRAM to work and outputs 11 columns of current values. The current of each column is converted into 11 voltages through the SA8+3 module, and the voltages are converted into 11 2-bit data through the ADC. The 2-bit data is output separately, and the high-order bits are used as the high 4 bits of the 8-bit data. The high-order bits of the 13 2-bit numbers are imported into the verification module for verification and output 8 verified high-order data. At this time, it is the first cycle. The high-order bits correspond to data[4], while the low 4 bits (the first cycle corresponds to data[0]) directly output the low-order data of the first 8 columns. Since no verification is required, the data of the last 3 columns of RRAM does not work when outputting the low-order bits.

[0057] Subsequently, in the embodiments of this application, 8 data[4] can be imported into the multiply-accumulate module and multiplied and added together with 8 data from in_high. At the same time, the low-order data data[0] is also multiplied and added. Since data[4] has a higher weight, it needs to be shifted left by 4 bits, and then added to the multiply-accumulate result of the low-order data after passing through the left-shifted 4-bit module. In the optional shift module, the corresponding data[0] and data[4] are already the corresponding weight data, so the shift count signal sent is 0, and the result is stored in the accumulator. The second clock cycle is the same, and WL is opened. <1> Turn off WL <0> At this point, there are 8 data[5] and data[1]. When the shift module is selected, the signal needs to control the overall shift by 1 bit, then add it to the accumulator, and add it to the result of the first clock cycle, and add it to the result of the third and fourth cycles. After four cycles, the accumulator result is the result of multiplying and adding 8 8-bit numbers and 8 8-bit in data.

[0058] Therefore, the multi-bit RRAM storage cell structure of this application protects data accuracy by processing the output of the multi-bit RRAM separately and protecting the high-order bits. Compared with the traditional RRAM full-bit check structure, this application embodiment combines the fault tolerance of neural network convolution, reducing power consumption in the check module by more than half, achieving a balance between accuracy and power consumption. Storing multiple weight data in one RRAM and protecting or directly outputting them makes the multiply-accumulate module more flexible, improves data reliability, and effectively reduces power consumption.

[0059] The digital multi-bit RRAM calculation method for protecting high-weight data proposed in this application determines the number of calculation cycles and the number of RRAMs corresponding to multiple target multi-bit weight data based on the number of bits in multiple target multi-bit weight data. Within each calculation cycle, each RRAM outputs multiple columns of current values. Each column of current values ​​is converted into two bits of the corresponding target multi-bit weight data, and the high-order and low-order bits of the two bits in each calculation cycle of the multiple target multi-bit weight data are determined. Multiple check RRAMs are determined in all RRAMs. This invention utilizes multiple check bits in a Replica RAM (RRAM) to perform data verification on the high-bit data of each target multi-bit weight data within each calculation cycle. It also performs multiplication and addition operations on the low-bit data and the low-bit data of the preset storage data, and then performs multiplication and addition operations on the high-bit data after the data verification operation and the high-bit data of the preset storage data to obtain the low-bit weight multiplication and addition results and the high-bit weight multiplication and addition results. A preset shift operation is then performed on the high-bit weight multiplication and addition results to obtain the shifted data of each target multi-bit weight data within each calculation cycle. Finally, the shifted data and the low-bit weight multiplication and addition results are added to obtain the data multiplication and addition results corresponding to multiple target multi-bit weight data. This application effectively utilizes ECC (Extracorporeal Counter) to verify and correct the high-bit data, thereby improving calculation accuracy. Simultaneously, it allows a single RRAM cell to be used for both high-bit and low-bit storage, increasing RRAM density and achieving RRAM reuse with high-precision output.

[0060] Secondly, a digital multi-bit RRAM computing apparatus for protecting high-weight data according to an embodiment of this application will be described with reference to the accompanying drawings.

[0061] Figure 6 This is a block diagram of a digital multi-bit RRAM computing device for protecting high-weight data according to an embodiment of this application.

[0062] like Figure 6 As shown, the digital multi-bit RRAM computing device 10 for protecting high-weight data includes: a control module 100, a conversion module 200, a verification module 300, and a computing module 400.

[0063] The control module 100 is used to determine the number of calculation cycles and the number of RRAMs corresponding to the multiple target multi-bit weight data based on the number of bits of the multiple target multi-bit weight data, and to control each RRAM to output multiple columns of current values ​​in each calculation cycle.

[0064] The conversion module 200 is used to convert each column of current values ​​in the multiple columns of current values ​​into two bits of data in the corresponding target multi-bit weight data, and to determine the high bit data and low bit data of the two bits of data in each calculation cycle of the multiple target multi-bit weight data.

[0065] The verification module 300 is used to determine multiple verification bits in all RRAMs, and to perform data verification operations on the high-bit data of each target multi-bit weight data in each calculation cycle using the multiple verification bits RRAMs. It also performs multiply-add operations on the low-bit data and the low-bit data of the preset storage data, and performs multiply-add operations on the high-bit data after the data verification operation and the high-bit data of the preset storage data to obtain the low-bit weight multiply-add result and the high-bit weight multiply-add result.

[0066] The calculation module 400 is used to perform a preset shift operation on the high-bit weight multiplication and addition result to obtain the shifted data of each target multi-bit weight data in each calculation cycle, and to add the shifted data and the low-bit weight multiplication and addition result to obtain the data multiplication and addition result corresponding to multiple target multi-bit weight data.

[0067] Optionally, in one embodiment of this application, the control module 100 includes: a determination unit, configured to determine the target bit line corresponding to each calculation cycle and apply a preset voltage to the target bit line to control each RRAM to output multiple columns of current values ​​in each calculation cycle.

[0068] Optionally, in one embodiment of this application, the conversion module 200 includes: a generation unit, used to convert each column of current values ​​into corresponding target voltage values ​​based on a preset SA structure, and to generate two bits of data corresponding to the target voltage values ​​using a preset digital-to-analog converter.

[0069] Optionally, in one embodiment of this application, the verification module 300 includes: an acquisition unit, a repair unit, a first multiply-accumulate unit, and a second multiply-accumulate unit.

[0070] The acquisition unit is used to determine multiple check bit RRAMs in all RRAMs and acquire the corresponding check bit data based on the multiple check bit RRAMs.

[0071] The repair unit is used to transmit high-bit data to a preset verification unit, where the verification unit uses the verification bit data to perform ECC data verification on the high-bit data to repair the high-bit data that has a preset flip error.

[0072] The first multiply-add unit is used to send the high-bit data after the data verification operation to the preset high-weight multiply-add unit, so that the high-bit data after the data verification operation and the high-bit data of the preset stored data are multiplied and added in the preset high-weight multiply-add unit to obtain the high-weight multiply-add result.

[0073] The second multiply-add unit is used to send the low-bit data to the preset low-weight multiply-add unit, and to perform multiply-add operations on the low-bit data and the low-bit data of the preset stored data in the preset low-weight multiply-add unit to obtain the low-weight multiply-add result.

[0074] Optionally, in one embodiment of this application, the calculation module 400 includes: a first shift unit, a second shift unit, and an accumulation unit.

[0075] The first shift unit is used to perform a preset shift operation on the high-order weight multiplication and addition result in each calculation cycle to obtain the shift data and displacement number signal corresponding to each calculation cycle.

[0076] The second shift unit is used to add the shifted data and the low-bit weight multiplication result to obtain the high-low bit addition result, and to perform a preset optional shift operation on the high-low bit addition result according to the shift number signal corresponding to each calculation cycle to obtain the optional shift result of each target multi-bit weight data in each calculation cycle.

[0077] The accumulation unit is used to send the optional shift result corresponding to each target multi-bit weight data to a preset accumulator to obtain the data multiplication and addition result corresponding to multiple target multi-bit weight data.

[0078] It should be noted that the foregoing explanation of the embodiment of the digital multi-bit RRAM calculation method for protecting high-weight data also applies to the digital multi-bit RRAM calculation device for protecting high-weight data in this embodiment, and will not be repeated here.

[0079] The digital multi-bit RRAM computing device for protecting high-weight data according to the embodiments of this application includes a control module 100, used to determine the number of calculation cycles and the number of RRAMs corresponding to the multiple target multi-bit weight data based on the number of bits of the multiple target multi-bit weight data, and to control each RRAM to output multiple columns of current values ​​in each calculation cycle; a conversion module 200, used to convert each column of current values ​​in the multiple columns of current values ​​into two bits of the corresponding target multi-bit weight data, and to determine the high-order and low-order bits of the two bits of each target multi-bit weight data in each calculation cycle; and a verification module 300, used to determine the multiple weight data in all RRAMs. This application utilizes multiple check bits in a Rectified Random Access Memory (RRAM) to perform data verification operations on the high-bit data of each target multi-bit weight data in each calculation cycle. It also performs multiply-add operations on the low-bit data and the low-bit data of the preset storage data, and then performs multiply-add operations on the high-bit data after the data verification operation and the high-bit data of the preset storage data to obtain the low-bit weight multiply-add result and the high-bit weight multiply-add result. A calculation module 400 performs a preset shift operation on the high-bit weight multiply-add result to obtain the shifted data of each target multi-bit weight data in each calculation cycle, and adds the shifted data and the low-bit weight multiply-add result to obtain the data multiply-add result corresponding to multiple target multi-bit weight data. This application effectively utilizes ECC to verify and correct the high-bit data to improve calculation accuracy. Simultaneously, it allows a single RRAM unit to be used for both high-bit and low-bit storage, increasing the RRAM density and thus achieving RRAM reuse and high-precision output.

[0080] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device may include:

[0081] The memory 701, the processor 702, and the computer program stored on the memory 701 and executable on the processor 702.

[0082] When the processor 702 executes the program, it implements the digital multi-bit RRAM calculation method for protecting high-weight data provided in the above embodiments.

[0083] Furthermore, electronic devices also include:

[0084] Communication interface 703 is used for communication between memory 701 and processor 702.

[0085] The memory 701 is used to store computer programs that can run on the processor 702.

[0086] The memory 701 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0087] If the memory 701, processor 702, and communication interface 703 are implemented independently, then the communication interface 703, memory 701, and processor 702 can be interconnected via a bus to complete communication between them. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 7 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0088] Optionally, in a specific implementation, if the memory 701, processor 702, and communication interface 703 are integrated on a single chip, then the memory 701, processor 702, and communication interface 703 can communicate with each other through an internal interface.

[0089] The processor 702 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0090] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method for calculating digital multi-bit RRAM to protect high-weight data.

[0091] This application also provides a computer program product, including a computer program, which, when executed, is used to implement the above-described method for calculating digital multi-bit RRAM to protect high-weight data.

[0092] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0093] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0094] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0095] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0096] It should be understood that the various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0097] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it includes one or a combination of the steps of the method embodiments.

[0098] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0099] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A method for calculating digital multi-bit RRAM to protect high-weight data, characterized in that, Includes the following steps: The number of calculation cycles and the number of RRAMs corresponding to the multiple target multi-bit weight data are determined based on the number of bits of the multiple target multi-bit weight data, and each RRAM is controlled to output multiple columns of current values ​​within each calculation cycle; Each current value in the multiple columns of current values ​​is converted into two bits of data in the corresponding target multi-bit weight data, and the high-bit data and low-bit data in the two bits of data in each of the multiple target multi-bit weight data are determined in each calculation cycle; Multiple check bits RRAMs are determined in all RRAMs, and the multiple check bits RRAMs are used to perform data verification operations on the high bits of each target multi-bit weight data in each calculation cycle. Multiply-add operations are performed on the low bits and the low bits of the preset storage data, and multiply-add operations are performed on the high bits after the data verification operation and the high bits of the preset storage data to obtain the low-bit weight multiply-add result and the high-bit weight multiply-add result. A preset shift operation is performed on the high-order weight multiplication and addition result to obtain the shifted data of each target multi-bit weight data in each calculation cycle, and the shifted data and the low-order weight multiplication and addition result are added to obtain the data multiplication and addition result corresponding to the multiple target multi-bit weight data.

2. The method according to claim 1, characterized in that, The control of pre-set multiple columns of current values ​​for each RRAM output within each calculation cycle includes: The target bit line corresponding to each calculation cycle is determined, and a preset voltage is applied to the target bit line to control each RRAM to output the multi-column current value in each calculation cycle.

3. The method according to claim 1, characterized in that, The step of converting each column of current values ​​in the multi-column current values ​​into two bits of data in the corresponding target multi-bit weighted data includes: Based on the preset SA structure, the current value of each column is converted into the corresponding target voltage value, and the two-bit data corresponding to the target voltage value is generated using a preset digital-to-analog converter.

4. The method according to claim 3, characterized in that, The process of determining multiple check bits in all RRAMs, and using these check bits to perform data verification on the high-order bits of each target multi-bit weight data in each calculation cycle, and performing multiply-add operations on the low-order bits and the low-order bits of the preset stored data, and then performing multiply-add operations on the high-order bits after the data verification and the high-order bits of the preset stored data, to obtain low-order weight multiply-add results and high-order weight multiply-add results, includes: Determine the plurality of check bit RRAMs in all the RRAMs, and obtain the corresponding check bit data according to the plurality of check bit RRAMs; The high-bit data is transmitted to a preset verification unit, where the verification bit data is used to perform ECC data verification on the high-bit data to repair the high-bit data with a preset flip error. The high-bit data after the data verification operation is sent to the preset high-weight multiply-add unit, so that the high-bit data after the data verification operation and the high-bit data of the preset stored data are multiplied and added in the preset high-weight multiply-add unit to obtain the high-weight multiply-add result. The low-bit data is sent to a preset low-weight multiply-accumulate unit, and the low-bit data of the preset stored data are multiplied and accumulated in the preset low-weight multiply-accumulate unit to obtain the low-weight multiply-accumulate result.

5. The method according to claim 4, characterized in that, The step of performing a preset shift operation on the high-order weight multiplication and addition result to obtain the shifted data of each target multi-bit weight data in each calculation cycle, and adding the shifted data and the low-order weight multiplication and addition result to obtain the data multiplication and addition result corresponding to the multiple target multi-bit weight data, includes: Within each calculation cycle, a preset shift operation is performed on the high-order weight multiplication and addition result to obtain the shift data and displacement count signal corresponding to each calculation cycle; The shifted data and the low-order weight multiplication result are added together to obtain the high-low order addition result. Then, according to the number of displacements corresponding to each calculation cycle, a preset optional displacement operation is performed on the high-low order addition result to obtain the optional displacement result of each target multi-bit weight data in each calculation cycle. The optional shift result corresponding to each target multi-bit weight data is sent to a preset accumulator to obtain the data multiplication and addition result corresponding to the multiple target multi-bit weight data.

6. A digital multi-bit RRAM computing device for protecting high-weight data, characterized in that, include: The control module is used to determine the number of calculation cycles and the number of RRAMs corresponding to the multiple target multi-bit weight data based on the number of bits of the multiple target multi-bit weight data, and to control each RRAM to output multiple columns of current values ​​in each calculation cycle; The conversion module is used to convert each column of current values ​​in the multiple columns of current values ​​into two bits of data in the corresponding target multi-bit weight data, and to determine the high bit data and low bit data in the two bits of data in each calculation cycle of the multiple target multi-bit weight data. The verification module is used to determine multiple verification bits RRAM in all RRAMs, and use the multiple verification bits RRAM to perform data verification operation on the high bit data of each target multi-bit weight data in each calculation cycle, and perform multiply-add operation on the low bit data and the low bit data of the preset storage data, and perform multiply-add operation on the high bit data after the data verification operation and the high bit data of the preset storage data to obtain the low bit weight multiply-add result and the high bit weight multiply-add result; The calculation module is used to perform a preset shift operation on the high-bit weight multiplication and addition result to obtain the shifted data of each target multi-bit weight data in each calculation cycle, and to add the shifted data and the low-bit weight multiplication and addition result to obtain the data multiplication and addition result corresponding to the multiple target multi-bit weight data.

7. The apparatus according to claim 6, characterized in that, The control module includes: The determining unit is used to determine the target bit line corresponding to each calculation cycle and apply a preset voltage to the target bit line to control each RRAM to output the multi-column current value in each calculation cycle.

8. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, the processor executing the program to implement the digital multi-bit RRAM calculation method for protecting high-weight data as described in any one of claims 1-5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, The program is executed by the processor to implement the digital multi-bit RRAM calculation method for protecting high-weight data as described in any one of claims 1-5.

10. A computer program product, comprising a computer program, characterized in that, The computer program is executed to implement the digital multi-bit RRAM calculation method for protecting high-weight data as described in any one of claims 1-5.

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