EFUSE storage unit, programming reading circuit and programming reading method

Abstract

The invention discloses an EFUSE storage unit, a programming reading circuit and a programming reading method, and belongs to the technical field of integrated circuits, and the EFUSE storage unit comprises a constant current source module which is used for connecting a programming control signal port and a bias voltage signal port and providing a first current greater than a preset value before programming, the constant current source module provides a second current smaller than the preset value after burning, and the constant current source module comprises an electronic fuse; a Latch circuit module; and the numerical control current mirror module comprises a phase inverter, a transmission gate and a current mirror. The logic state of the first node is latched by the Latch circuit module and is output to a latch data output port of the Latch circuit module, if the latch data output port is 1, it is indicated that the EFUSE storage unit is not burnt, and if the latch data output port is 0, it is indicated that the EFUSE storage unit is burnt, and therefore the problems existing in a conventional EFUSE storage unit can be solved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to an EFUSE storage unit, a programming and reading circuit, and a programming and reading method. Background Art

[0002] The full name of EFUSE is "electronic fuse", which is a programmable electronic fuse and a non-volatile storage device for storing information and protecting chips. Compared with other one-time programmable (OTP) memories such as fuse and laser fuse, efuse has the advantages of not requiring additional equipment for fusing, good process compatibility, and small occupied area, so it has been widely used.

[0003] A traditional EFUSE storage unit is as shown in Figure 1 where R fuse is an electronic fuse, generally composed of a very thin polysilicon. Before programming, its resistance value is small, for example, dozens of ohms. The first NMOS transistor N1 is an NMOS transistor with a large width-to-length ratio, and its gate is controlled by the programming signal Din. When Din = 1, N1 conducts, and at this time, a relatively large current will flow through R fuse and N1 to Gnd (ground). The heat generated by this large current on the fuse will, in an ideal situation, cause the fuse to be completely blown, thus presenting an open circuit, and the equivalent resistance of R fuse is close to infinity.

[0004] The gate of the second NMOS transistor N2 is connected to a bias voltage VBIAS. The second NMOS transistor N2 is equivalent to a constant current source, and its current value is set as I; the third NMOS transistor N3, the first PMOS transistor P1, and the inverter INV3 form a transmission gate. The input terminal of the inverter INV3 and the gate of the third NMOS transistor N3 are connected to the read control signal Read. When Read = 1, this transmission gate conducts. For an unprogrammed efuse storage unit, the resistance value of R fuse is very small, and the voltage of the NetA node is equal to VDD - I×R fuse , which is a value very close to VDD, so the NetA node shows logic 1; while for a programmed eufse storage unit, in an ideal situation, R fuse is completely blown and presents an open circuit, so the voltage of the NetA node will be equal to Gnd, that is, it shows logic 0.

[0005] Figure 1 The Latch in Figure 2As shown, its sampling clock signal CP is connected to the read control signal Read. When Read = 1, the latch samples the logic state of the NetA node. When Read = 0, the logic state of the NetA node is latched and output from its Dout port.

[0006] However, due to the existence of some non-ideal situations, there will be an R fuse After programming, it is not completely blown, but will present as a relatively large resistor, such as several thousand ohms to several tens of thousand ohms. At this time, even if programming is performed again, because at this time R fuse has a large resistance and the current flowing through it is too small, the heat generated is not sufficient to completely blow it. In this case, when the read control signal Read = 1 and the transmission gate composed of the third NMOS transistor N3, the first PMOS transistor P1, and the inverter INV3 is turned on, due to R fuse is not completely blown, but is equivalent to a resistor with a resistance value of several thousand ohms to several tens of thousand ohms. If the current I of the constant current source is relatively small, the voltage of the NetA node will be equal to VDD - I×R fuse , which is a voltage between VDD and GND. In extreme cases, it may even be near the intermediate value between VDD and GND, which will cause the subsequent Latch latch circuit to be unable to determine whether the logic state of the NetA node is 0 or 1, resulting in a read error.

[0007] Generally, the method of increasing the current I of the constant current source is adopted to make the value of I×R fuse greater than VDD, so that the voltage of the NetA node is equal to Gnd (i.e., it shows as logic 0). Therefore, in order to read the correct value, a relatively large constant current source current I must be set, which will result in a relatively large power consumption during reading.

[0008] It should be noted that the information disclosed in the background art part of this invention is only intended to deepen the understanding of the general background technology of this invention, and should not be regarded as an admission or any form of implication that this information constitutes the prior art known to those skilled in the art. Summary of the Invention

[0009] The purpose of the present invention is to provide an EFUSE memory cell, a programming and reading circuit, and a programming and reading method to solve the problem that the Latch latch cannot accurately judge the state of the NetA node due to the incomplete blowing of R fuse , that is, it cannot judge the circuit condition or the condition of R fuse .

[0010] To solve the above technical problems, the present invention provides an EFUSE memory cell, including:

[0011] A constant current source module is used to connect to a programming control signal port and a bias voltage signal port, and provides a first current greater than a preset value before programming and a second current less than the preset value after programming. The constant current source module includes an electronic fuse;

[0012] A Latch circuit module, wherein the latch data input port of the Latch circuit module is connected to a first node, and the sampling clock port is connected to a read control signal;

[0013] A numerically controlled current mirror module includes an inverter, a transmission gate, and a current mirror. The input end of the inverter is connected to the read control signal. The input end and the output end of the inverter are respectively connected to the first control input end and the second control input end of the transmission gate. The signal input end of the transmission gate is connected to a bias current input port, and the bias current input port is used to provide a bias current signal with the preset value. The signal output end of the transmission gate is connected to the reference current input end of the current mirror. The replicated current input end of the current mirror is connected to the first node, and the first node is also connected to the second end of the electronic fuse. Among them, the gate interconnection node in the current mirror is also connected to the drain of a fourth switching transistor. The gate of the fourth switching transistor is connected to the output end of the inverter, and the source of the fourth switching transistor is commonly connected to the ground with the reference current output end and the replicated current output end of the current mirror.

[0014] Preferably, the constant current source module further includes a second control transistor. The first end of the electronic fuse is connected to the power supply voltage, the second end is connected to the source of the second control transistor. The drain of the second control transistor is connected to the first node, and the gate is connected to the bias voltage signal port. The programming control signal port is connected to the gate of a first switching transistor. The drain of the first switching transistor is connected to the second end of the electronic fuse, and the source of the first switching transistor is grounded.

[0015] Preferably, the transmission gate includes a fifth switching transistor and a first control transistor. The drains of the fifth switching transistor and the first control transistor are interconnected as the signal input end to be connected to the bias current input port. The gate of the fifth switching transistor is used as the first control input end to be connected to the input end of the inverter. The sources of the fifth switching transistor and the first control transistor are interconnected as the signal output end to be connected to the reference current input end of the current mirror. The gate of the first control transistor is used as the second control input end to be connected to the output end of the inverter.

[0016] Preferably, the current mirror includes a third switching transistor and a second switching transistor. The gates of the third switching transistor and the second switching transistor are interconnected and serve as the gate interconnection node. The drain and gate of the third switching transistor are interconnected to serve as the reference current input terminal. The drain of the second switching transistor serves as the copied current input terminal and is connected to the first node. The sources of the second switching transistor and the third switching transistor are the copied current output terminal and the reference current output terminal, respectively.

[0017] The present application also provides an EFUSE programming and reading circuit, including:

[0018] A common bias unit for providing a bias current signal to a bias current input port and a bias voltage signal to a bias voltage signal port;

[0019] At least one EFUSE storage unit, and the EFUSE storage unit includes:

[0020] A constant current source module for connecting a programming control signal port and a bias voltage signal port, and providing a first current greater than a preset value before programming and a second current less than the preset value after programming. The constant current source module includes an electronic fuse;

[0021] A Latch circuit module, where the latch data input port of the Latch circuit module is connected to the first node, and the sampling clock port is connected to a read control signal;

[0022] A digitally controlled current mirror module, including an inverter, a transmission gate, and a current mirror. The input terminal of the inverter is connected to the read control signal. The input terminal and the output terminal of the inverter are respectively connected to the first control input terminal and the second control input terminal of the transmission gate. The signal input terminal of the transmission gate is connected to a bias current input port for providing a bias current signal with the preset value. The signal output terminal of the transmission gate is connected to the reference current input terminal of the current mirror. The copied current input terminal of the current mirror is connected to the first node, and the first node is also connected to the second end of the electronic fuse. Among them, the gate interconnection node in the current mirror is also connected to the drain of a fourth switching transistor. The gate of the fourth switching transistor is connected to the output terminal of the inverter. The source of the fourth switching transistor is commonly connected to the reference current output terminal and the copied current output terminal of the current mirror and grounded.

[0023] Preferably, the common bias unit includes a first resistor, a second resistor, a third control transistor, and a fourth control transistor. The first ends of the first resistor and the second resistor are commonly connected and connected to a power supply voltage. The source of the third control transistor is connected to the second end of the first resistor. The gate and the drain of the third control transistor are commonly connected for accessing an external bias current signal. The source of the fourth control transistor is connected to the second end of the second resistor. The gates of the third control transistor and the fourth control transistor are commonly connected and connected to the bias voltage signal port to provide a bias voltage signal. The drain of the fourth control transistor is used to output the bias current signal to the bias current input port.

[0024] Preferably, the constant current source module further includes a second control transistor. The first end of the electronic fuse is connected to the power supply voltage, and the second end is connected to the source of the second control transistor. The drain of the second control transistor is connected to the first node, and the gate is connected to the bias voltage signal port. The programming control signal port is connected to the gate of the first switching transistor. The drain of the first switching transistor is connected to the second end of the electronic fuse, and the source of the first switching transistor is grounded.

[0025] Preferably, the transmission gate includes a fifth switching transistor and a first control transistor. The drains of the fifth switching transistor and the first control transistor are interconnected as the signal input end to be connected to the bias current input port. The gate of the fifth switching transistor is used as the first control input end to be connected to the input end of the inverter. The sources of the fifth switching transistor and the first control transistor are interconnected as the signal output end to be connected to the reference current input end of the current mirror. The gate of the first control transistor is used as the second control input end to be connected to the output end of the inverter.

[0026] Preferably, the current mirror includes a third switching transistor and a second switching transistor. The gates of the third switching transistor and the second switching transistor are interconnected and used as the gate interconnection node. The drain and the gate of the third switching transistor are interconnected as the reference current input end. The drain of the second switching transistor is used as the copied current input end to be connected to the first node. The sources of the second switching transistor and the third switching transistor are the copied current output end and the reference current output end, respectively.

[0027] The present disclosure also provides a programming and reading method for an EFUSE programming and reading circuit. Using the above-mentioned EFUSE programming and reading circuit to program and read an EFUSE storage unit, the method further includes the following steps:

[0028] When programming: a read control signal is provided to the EFUSE storage unit, and when the read control signal is at a first level, the EFUSE storage unit is programmed sequentially, and the programming status of the EFUSE storage unit is determined by the level signal of the latched data output port of the Latch circuit module;

[0029] When reading: a read control signal is provided to the EFUSE storage unit, and when the read control signal is at a second level, the EFUSE storage unit is read sequentially.

[0030] In the EFUSE storage unit provided by the present invention, when the read control signal Read changes from 1 to 0, the logical state of the first node NetA is latched by the Latch circuit module and output to its latched data output port Dout. If the latched data output port Dout is logic 1, it means that this EFUSE storage unit has not been programmed. If the latched data output port Dout is logic 0, it means that this EFUSE storage unit has been programmed, thus avoiding the problem of reading errors caused by incomplete programming of the electronic fuse R fuse The problem of reading errors caused by incomplete programming. Further, the magnitude of the preset value does not affect the output result of the first node NetA. Therefore, the bias current signal I can be set to a relatively small value, which can greatly reduce the power consumption during the reading process.

[0031] The EFUSE programming and reading circuit and the programming and reading method provided by the present invention belong to the same inventive concept as the EFUSE memory cell provided by the present invention. Therefore, the EFUSE programming and reading circuit and the programming and reading method provided by the present invention have at least all the advantages of the EFUSE memory cell provided by the present invention, which will not be elaborated herein. The common bias unit is used to provide a bias current signal to the bias current input port and a bias voltage signal to the bias voltage signal port; at least one EFUSE memory cell, the EFUSE memory cell includes: a constant current source module, which is used to connect the programming control signal port and the bias voltage signal port, and provides a first current greater than a preset value before programming and a second current less than the preset value after programming, the constant current source module includes an electronic fuse; a Latch circuit module, the latch data input port of the Latch circuit module is connected to the first node, and the sampling clock port is connected to the read control signal; a numerically controlled current mirror module, including an inverter, a transmission gate and a current mirror, the input end of the inverter is connected to the read control signal, the input end and the output end of the inverter are respectively connected to the first control input end and the second control input end of the transmission gate, the signal input end of the transmission gate is connected to the bias current input port, the bias current input port is used to provide a bias current signal with the preset value, the signal output end of the transmission gate is connected to the reference current input end of the current mirror, the copy current input end of the current mirror is connected to the first node, the first node is also connected to the second end of the electronic fuse, wherein, the gate interconnection node in the current mirror is also connected to the drain of the fourth switching transistor, the gate of the fourth switching transistor is connected to the output end of the inverter, and the source of the fourth switching transistor is commonly connected to the ground with the reference current output end and the copy current output end of the current mirror. Description of the Drawings

[0032] Figure 1 is the circuit diagram of a traditional EFUSE memory cell;

[0033] Figure 2 is the circuit diagram of a traditional Latch module;

[0034] Figure 3 is the circuit diagram of the EFUSE memory cell proposed in an embodiment of the present invention;

[0035] Figure 4 is the circuit diagram of the common bias unit proposed in an embodiment of the present invention;

[0036] Figure 5 is the schematic diagram of the connection relationship between the EFUSE memory cell and the common bias unit in the 4bit EFUSE memory proposed in an embodiment of the present invention;

[0037] Figure 6It is a timing diagram of the programming operation for the 4-bit EFUSE memory shown in Figure 5 ;

[0038] Figure 7 It is a timing diagram of the read operation for the 4-bit EFUSE memory shown in Figure 5 ;

[0039] In the figure: 100, common bias unit; 200, EFUSE memory cell; 201, constant current source module; 202, digitally controlled current mirror module. Detailed implementation manners

[0040] The EFUSE memory cell, programming / reading circuit and programming / reading method proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to explain certain principles of the present invention in the drawings of the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein, such as specific dimensions, directions, positions and shapes, will be partially determined by the specific application and usage environment. Also, in the embodiments described below, sometimes the same reference numerals are used commonly between different drawings to represent the same or parts with the same functions, and the repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0041] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0042] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0043] The inventors' research found that when a conventional EFUSE storage unit is in use, there is a situation where it is not completely blown, which always causes the latch in the Latch module connected thereto to be unable to read the state of the electronic fuse. And the method of increasing the current in the constant current source part has the defect of requiring a large amount of power consumption.

[0044] Based on this, the core idea of the present invention is to provide an EFUSE storage unit that can latch the logical state of the first node by the Latch circuit module and output it to its latched data output port Dout. And if the Dout port is 1, it means that this EFUSE storage unit has not been programmed. If the Dout port is 0, it means that this EFUSE storage unit has been programmed, thereby being able to solve the problems existing in the conventional EFUSE storage unit.

[0045] Specifically, please refer to Figures 3 - 7 , which is a schematic diagram of an embodiment of the present invention. As Figure 3 shown, an EFUSE storage unit includes:

[0046] A constant current source module 201, which is used to connect to the programming control signal port Din and the bias voltage signal port VBP, and provides a first current I greater than a preset value before programming 1 , and provides a second current I less than a preset value after programming 2 , and the constant current source module 201 includes an electronic fuse R fuse ;

[0047] A Latch circuit module (not labeled), the latched data input port D of the Latch circuit module is connected to the first node NetA, and the sampling clock port CP is connected to the read control signal Read;

[0048] The numerically controlled current mirror module 202 includes an inverter INV3, a transmission gate, and a current mirror. The input end of the inverter INV3 is connected to the read control signal Read. The input end and the output end of the inverter INV3 are respectively connected to the first control input end and the second control input end of the transmission gate. The signal input end of the transmission gate is connected to the bias current input port IBIAS, and the bias current input port IBIAS is used to provide a bias current signal I with the preset value. The signal output end of the transmission gate is connected to the reference current input end of the current mirror. The replicated current input end of the current mirror is connected to the first node NetA, and the first node NetA is also connected to the second end of the electronic fuse R fuse Among them, the gate interconnection node in the current mirror is also connected to the drain of the fourth switching transistor N4. The gate of the fourth switching transistor N4 is connected to the output end of the inverter INV3, and the source of the fourth switching transistor N4 is commonly connected to the ground Gnd with the reference current output end and the replicated current output end of the current mirror.

[0049] When the read control signal Read = 0, or when the read control signal Read is at a low level, Figure 3 the transmission gate in it is disconnected, the bias current input port IBIAS is in a high-impedance state, and at the same time the fourth switching transistor N4 is turned on, the current mirror is disconnected, and no current flows through the current mirror.

[0050] Relatively, when the read control signal Read = 1, or when the read control signal Read is at a high level, the transmission gate is turned on, the gate voltage of the fourth switching transistor N4 is 0, the fourth switching transistor N4 is turned off, and the inflow currents at the reference current input end and the replicated current input end of the current mirror are the same, that is, equal to the bias current signal I input by the bias current input port IBIAS.

[0051] According to the above analysis, for the unburned EFUSE storage unit 200, the first current I provided by the constant current source module 201 1 is greater than the preset value, that is, the first current I 1 is greater than the bias current signal I, so the node voltage of the first node NetA is at a high level, that is, it is represented as logic 1; for the burned EFUSE storage unit 200, the second current I provided by the constant current source module 201 2is less than the preset value, so the node voltage of the first node NetA is at a low level, which is represented as logic 0. Therefore, when the read control signal Read changes from 1 to 0, the logic state of the first node NetA is latched by the Latch circuit module and output to its latched data output port Dout. If the latched data output port Dout is logic 1, it means that this EFUSE storage unit 200 has not been programmed. If the latched data output port Dout is logic 0, it means that this EFUSE storage unit 200 has been programmed, thus avoiding the problem of reading errors caused by the electronic fuse R fuse not being fully programmed.

[0052] It can be understood that the magnitude of the preset value does not affect the output result of the first node NetA. Therefore, the bias current signal I can be set to a relatively small value, such as 10 uA, which can greatly reduce the power consumption during the reading process.

[0053] Specifically, the constant current source module 201 further includes a second control transistor P2, and the first end of the electronic fuse R fuse is connected to the power supply voltage VDD, the second end is connected to the source of the second control transistor P2, the drain of the second control transistor P2 is connected to the first node NetA, the gate is connected to the bias voltage signal port VBP, the programming control signal port Din is connected to the gate of the first switching transistor N1, the drain of the first switching transistor N1 is connected to the second end of the electronic fuse R fuse and the source of the first switching transistor N1 is grounded.

[0054] As Figure 3 shown, the constant current source module 201 is composed of the second control transistor P2 and the electronic fuse R fuse . The gate voltage of the second control transistor P2 is connected to the bias voltage signal port VBP. The electronic fuse R fuse is a polysilicon fuse. The constant current source module 201 is also externally connected to the bias voltage signal port VBP and the programming control signal port Din.

[0055] Among them, if it is not programmed, the resistance value of the electronic fuse R fuse is relatively small, and thus a relatively large current, that is, a first current I 1 greater than the bias current signal I, can be generated based on the externally connected signal; if it has been programmed, the resistance value of the resistance fuse R fuse increases, and thus a second current I 2 less than the bias current signal I is generated.

[0056] Specifically, the transmission gate includes a fifth switching transistor N5 and a first control transistor P1. The drains of the fifth switching transistor N5 and the first control transistor P1 are interconnected as the signal input terminal to be connected to the bias current input port. The gate of the fifth switching transistor N5 serves as the first control input terminal to be connected to the input terminal of the inverter INV3. The sources of the fifth switching transistor N5 and the first control transistor P1 are interconnected as the signal output terminal to be connected to the reference current input terminal of the current mirror. The gate of the first control transistor P1 serves as the second control input terminal to be connected to the output terminal of the inverter INV3.

[0057] The transmission gate is used to transmit the current of the input bias current input port IBIAS to the current mirror, and the transmission gate is controlled by the read control signal Read. When the read control signal Read = 0, the transmission gate composed of the fifth switching transistor N5, the first control transistor P1 and the inverter INV3 is turned off, and the bias current input port IBIAS is in a high-impedance state. At the same time, the gate voltage of the fourth switching transistor N4 is a high voltage, the fourth switching transistor N4 is turned on, and the current mirror is turned off. If Read = 1, the transmission gate composed of the fifth switching transistor N5, the first control transistor P1 and the inverter INV3 is turned on.

[0058] Specifically, the current mirror includes a third switching transistor N3 and a second switching transistor N2. The gates of the third switching transistor N3 and the second switching transistor N2 are interconnected and serve as the gate interconnection node. The drain and gate of the third switching transistor N3 are interconnected as the reference current input terminal. The drain of the second switching transistor N2 serves as the copied current input terminal to be connected to the first node NetA. The sources of the second switching transistor N2 and the third switching transistor N3 are the copied current output terminal and the reference current output terminal, respectively.

[0059] In one example, the second switching transistor N2 and the third switching transistor N3 have the same size, forming a current mirror with a mirror ratio of 1:1. The currents flowing through both are the same and are equal to the current I flowing into the bias current input port IBIAS.

[0060] The transistors used in all embodiments of the present application can be thin-film transistors, field-effect transistors or other devices with the same characteristics. According to their functions in the circuit, the transistors used in the embodiments of the present application are mainly CMOS transistors (Complementary Metal Oxide Semiconductor). The switching transistors are NMOS transistors, and the control transistors are PMOS transistors.

[0061] Based on the same inventive concept, the present application also provides an EFUSE programming and reading circuit, including:

[0062] A common bias unit 100, configured to provide a bias current signal I to a bias current input port IBIAS, and a bias voltage signal to a bias voltage signal port VBP;

[0063] At least one EFUSE storage unit 200, where the EFUSE storage unit 200 includes:

[0064] A constant current source module 201, including an electronic fuse R fuse , configured to connect a programming control signal port Din and the bias voltage signal port VBP, and provide currents with different magnitudes before and after programming: a first current I greater than a preset value before programming 1 , and a second current I less than the preset value after programming 2 ;

[0065] A Latch circuit module, where a latch data input port D of the Latch circuit module is connected to a first node NetA, and a sampling clock port CP is connected to a read control signal Read;

[0066] A digitally controlled current mirror module 202, including an inverter INV3, a transmission gate, and a current mirror. An input end of the inverter INV3 is connected to the read control signal Read. The input end and the output end of the inverter INV3 are respectively connected to a first control input end and a second control input end of the transmission gate. A signal input end of the transmission gate is connected to the bias current input port IBIAS, and the bias current input port IBIAS is configured to provide a bias current signal I with the preset value. A signal output end of the transmission gate is connected to a reference current input end of the current mirror. A replicated current input end of the current mirror is connected to the first node. The first node NETA is also connected to a second end of the electronic fuse R fuse . Wherein, a gate interconnection node in the current mirror is further connected to a drain of a fourth switching transistor. A gate of the fourth switching transistor N4 is connected to an output end of the inverter INV. A source of the fourth switching transistor N4 is commonly connected to a reference current output end and a replicated current output end of the current mirror and grounded to Gnd.

[0067] When the read control signal Read = 0, or when the read control signal Read is at a low level, Figure 3 the transmission gate in it is disconnected, the bias current input port IBIAS is in a high impedance state, and at the same time the fourth switching transistor N4 is turned on, the current mirror is disconnected, and no current flows through the current mirror.

[0068] In contrast, when the read control signal Read = 1, or when the read control signal Read is at a high level, the transmission gate is turned on, the gate voltage of the fourth switching transistor N4 is 0, the fourth switching transistor N4 is turned off, and the inflow currents at the reference current input terminal and the replicated current input terminal of the current mirror are the same, that is, equal to the bias current signal I input by the bias current input port IBIAS.

[0069] According to the above analysis, for the unburned EFUSE storage unit 200, the first current I provided by the constant current source module 201 1 is greater than the preset value, that is, the first current I 1 is greater than the bias current signal I. Therefore, the node voltage of the first node NetA is at a high level, that is, it is represented as logic 1; for the burned EFUSE storage unit 200, the second current I provided by the constant current source module 201 2 is less than the preset value. Therefore, the node voltage of the first node NetA is at a low level, that is, it is represented as logic 0. Therefore, when the read control signal Read jumps from 1 to 0, the logic state of the first node NetA is latched by the Latch circuit module and output to its latched data output port Dout. If the latched data output port Dout is logic 1, it means that this EFUSE storage unit 200 has not been burned, and if the latched data output port Dout is logic 0, it means that this EFUSE storage unit 200 has been burned, thus avoiding the problem of read errors caused by the electronic fuse R fuse not being completely burned.

[0070] The burning process of the EFUSE programming and reading circuit provided by the present disclosure has no difference from that of a conventional efuse storage unit. When the programming signal Din = 1, the programming transistor N1 is turned on, and a large current will flow through the electronic fuse R fuse and due to heat generation, R fuse will be completely blown or its resistance value will increase to several thousand ohms to several tens of thousand ohms.

[0071] Specifically, the common bias unit 100 includes a first resistor R1, a second resistor R2, a third control transistor P3, and a fourth control transistor P4. The first ends of the first resistor R1 and the second resistor R2 are commonly connected and connected to the power supply voltage VDD. The source of the third control transistor P3 is connected to the second end of the first resistor R1. The gate and the drain of the third control transistor P3 are commonly connected for accessing an external bias current signal IBIN. The source of the fourth control transistor P4 is connected to the second end of the second resistor R2. The gates of the third control transistor P3 and the fourth control transistor P4 are commonly connected and connected to the bias voltage signal port VBP to provide a bias voltage signal. The drain of the fourth control transistor P4 is used to output the bias current signal I to the bias current input port IBIAS.

[0072] As Figure 4 shown, it is the circuit diagram of the common bias unit 100. IBIN is the bias current input port of the common bias unit 100, IBOUT is the bias current output port of the common bias unit 100, and VBP is the bias voltage output port of the common bias unit 100.

[0073] In an embodiment, the resistance values of the first resistor R1 and the second resistor R2 are the same, and their resistance values are slightly larger than the unburned resistor fuse R in the EFUSE storage unit 200 fuse resistance value (for example, if the resistance value of the unburned resistor fuse R fuse is 50 ohms, then the resistance values of the first resistor R1 and the second resistor R2 are set to 200 ohms). The third control transistor P3 and the fourth control transistor P4 are two PMOS transistors with exactly the same size, thus forming a current mirror. The current flowing through the fourth control transistor P4 and the second resistor R2 will be equal to the current flowing through the third control transistor P3 and the first resistor R1. Suppose the magnitude of the bias current input through the bias current input port IBIN of the common bias unit 100 is a current I with a preset value. Then the current flowing through the third control transistor P3 and the first resistor R1 is equal to I, and the current flowing through the fourth control transistor P4 and the second resistor R2 is also equal to I. The current output from the bias current output port IBOUT of the common bias unit 100 is equal to I. That is, in the EFUSE storage unit 200, the bias current input port IBIAS is connected to the bias current output port IBOUT of the common bias unit 100

[0074] Specifically, the constant current source module 201 further includes a second control transistor P2, and the electronic fuse R fuseThe first terminal of is connected to the power supply voltage VDD, the second terminal is connected to the source of the second control transistor P2, the drain of the second control transistor P2 is connected to the first node NetA, the gate is connected to the bias voltage signal port VBP, the programming control signal port Din is connected to the gate of the first switching transistor N1, the drain of the first switching transistor N1 is connected to the second terminal of the electronic fuse R fuse and the source of the first switching transistor N1 is grounded.

[0075] In one embodiment, the constant current source module 201 is composed of the second control transistor P2 and the electronic fuse R fuse . The gate voltage of the second control transistor P2 is connected to the bias voltage signal port VBP, that is, connected to the bias voltage signal port VBP of the common bias unit 100. The electronic fuse R fuse is a polysilicon fuse. The second control transistor P2 has the same size as the third control transistor P3 and the fourth control transistor P4 in the common bias unit 100, and their gates are all connected to the bias voltage signal port VBP. The bias current output port IBOUT of the common bias unit 100 is connected to the bias current input port IBIAS of all EFUSE storage units 200.

[0076] It can be understood that for the unprogrammed EFUSE storage unit 200, the resistance value of the electronic fuse R fuse is less than Figure 4 the resistance values of the first resistor R1 and the second resistor R2 in . Therefore, the first current I 1 provided by the constant current source module 201 will be greater than the current flowing through the first resistor R1 and the second resistor R2, that is, greater than the bias current signal I. After programming, the resistance value of the electronic fuse R fuse will be greater than Figure 4 the resistance values of the first resistor R1 and the second resistor R2 in . The second current I 2 provided by the constant current source module 201 will be less than the current flowing through the first resistor R1 and the second resistor R2, that is, less than the bias current signal I.

[0077] Specifically, the transmission gate includes a fifth switching transistor N5 and a first control transistor P1. The drains of the fifth switching transistor N5 and the first control transistor P1 are interconnected as the signal input end to be connected to the bias current input port. The gate of the fifth switching transistor N5 is used as the first control input end to be connected to the input end of the inverter INV3. The sources of the fifth switching transistor N5 and the first control transistor P1 are interconnected as the signal output end to be connected to the reference current input end of the current mirror. The gate of the first control transistor P1 is used as the second control input end to be connected to the output end of the inverter INV3.

[0078] The transfer gate is used to transfer the current of the input bias current input port IBIAS to the current mirror, and the transfer gate is controlled by the read control signal Read. When the read control signal Read = 0, the transfer gate composed of the fifth switching transistor N5, the first control transistor P1 and the inverter INV3 is turned off, and the bias current input port IBIAS is in a high-impedance state. At the same time, the gate voltage of the fourth switching transistor N4 is a high voltage, the fourth switching transistor N4 is turned on, and the current mirror is turned off. If Read = 1, the transfer gate composed of the fifth switching transistor N5, the first control transistor P1 and the inverter INV3 is turned on.

[0079] Specifically, the current mirror includes a third switching transistor N3 and a second switching transistor N2. The gates of the third switching transistor N3 and the second switching transistor N2 are interconnected and used as the gate interconnection node. The drain and gate of the third switching transistor N3 are interconnected as the reference current input terminal. The drain of the second switching transistor N2 is used as the copied current input terminal to be connected to the first node NetA. The sources of the second switching transistor N2 and the third switching transistor N3 are the copied current output terminal and the reference current output terminal respectively.

[0080] In one example, the second switching transistor N2 and the third switching transistor N3 have the same size, forming a current mirror with a mirror ratio of 1:1. The currents flowing through both are the same and are both equal to the current I flowing into the bias current input port IBIAS. Since the bias current input port IBIAS is connected to the IBOUT port of the common bias unit 100, the current flowing into the bias current input port IBIAS is equal to I.

[0081] Based on the same inventive concept, the present application also provides a programming and reading method for an EFUSE programming and reading circuit. Using the above EFUSE programming and reading circuit, the EFUSE storage unit is programmed and read, and the method further includes the following steps:

[0082] When programming: providing a read control signal to the EFUSE storage unit 200, and when the read control signal Read is at a first level, programming the EFUSE storage unit 200 in sequence, and judging the programming state of the EFUSE storage unit through the level signal of the latch data output port Dout of the Latch circuit module;

[0083] When reading: providing a read control signal to the EFUSE storage unit 200, and when the read control signal is at a second level, reading the EFUSE storage unit 200 in sequence.

[0084] Among them, the first level is, for example, a low level, and the second level is, for example, a high level.

[0085] As Figure 5 shown, as shown in the figure, the entire memory is composed of a common bias circuit and several EFUSE memory cells 200. The IBIN port is a bias current input port and needs to be externally connected to a reference current source. The common bias unit 100 generates a bias voltage signal (VBP) and a bias current signal (IBOUT). VBP is connected to the bias voltage signal port VBP of all EFUSE memory cells 200, and IBOUT is connected to the IBIAS port of all EFUSE memory cells 200. The VBP port of the EFUSE memory cell 200 is a bias voltage input port, IBIAS is a bias current input port, Read is a read control signal, Din is a programming control signal port, and Dout is a locked storage data output port.

[0086] Among them, Figure 5 it is only an example of a 4-bit effuse memory. If a larger-capacity effuse memory is needed, the EFUSE memory cells 200 can be simply expanded according to this connection relationship.

[0087] When programming, for example, the EFUSE memory cell 200 to be programmed is Figure 5 the first, third, and fourth from top to bottom, then its timing is as Figure 6 shown. The read control signal Read of all EFUSE memory cells 200 is equal to 0, or a low level. Then, first make the programming control signal Din<3> of the first EFUSE memory cell 200 equal to 1 to program the first EFUSE memory cell 200. After programming is completed, restore Din<3> to 0. Since the second EFUSE memory cell 200 is not programmed, make the programming control signal Din<2> of the second EFUSE memory cell 200 constantly remain 0. Then make the programming control signal Din<1> of the third EFUSE memory cell 200 equal to 1 to program the third memory cell. After programming is completed, make Din<1> restore to 0. Finally, make the programming signal Din<0> of the fourth memory cell equal to 1 to program the fourth memory cell. After programming is completed, make Din<0> restore to 0.

[0088] The timing for performing a read operation is as Figure 7As shown, set all programming control signals Din to 0. First, read the first EFUSE memory cell 200 by setting Read<3> to 1 and setting the read control signals Read of other EFUSE memory cells 200 to 0. At this time, the IBIAS ports of other EFUSE memory cells 200 except the first one are in a high-impedance state. The bias current signal output by the common bias unit 100 only flows into the bias current input port IBIAS of the first EFUSE memory cell 200. After a period of time, let Read<3> transition from 1 to 0, and the read operation of the first EFUSE memory cell 200 is completed. The data stored in the first EFUSE memory cell 200 will be latched to the Dout<3> port. Then, follow the same steps to complete the reading of other memory cells one by one.

[0089] Among them, Figure 4 is the circuit diagram of the common bias unit 100. IBIN is the bias current input port of the common bias unit 100, IBOUT is the bias current output port of the common bias unit 100, and VBP is the bias voltage output port of the common bias unit 100. The resistance values of the first resistor R1 and the second resistor R2 are the same, and their resistance values are slightly larger than the resistance value of the unprogrammed electronic fuse R fuse in the EFUSE memory cell 200 (for example, if the resistance value of the unprogrammed electronic fuse R fuse is 50 ohms, then set the resistance values of the first resistor R1 and the second resistor R2 to 200 ohms). The third control transistor P3 and the fourth control transistor P4 are two PMOS transistors with exactly the same size, so they form a current mirror. The current flowing through the fourth control transistor P4 and the second resistor R2 will be equal to the current flowing through the third control transistor P3 and the first resistor R1. Assume that the magnitude of the bias current input at the IBIN port is I. Then the current flowing through the third control transistor P3 and the first resistor R1 is equal to I, the current flowing through the fourth control transistor P4 and the second resistor R2 is also equal to I, and the current output at the IBOUT port is equal to I.

[0090] The constant current source module 201 consists of the second control transistor P2 and the electronic fuse R fuse where the gate voltage of the second control transistor P2 is connected to the VBP port of the common bias unit 100, and R fuse is a polysilicon fuse. Figure 3 The second control transistor P2 in Figure 4 has the same size as the third control transistor P3 and the fourth control transistor P4 in fuse and their gate electrodes are all connected to the bias current input port VBP of the common bias unit 100. If it has not been programmed, the resistance value of the electronic fuse R fuse is less thanFigure 4 the resistance values of the first resistor R1 and the second resistor R2 in Figure 3 the current provided by the constant current source module 201 in Figure 4 the first current I flowing through the third control transistor P3 and the first resistor R1 in 1 , that is, greater than I; after programming, the resistance of the electronic fuse R fuse will be greater than Figure 4 the resistance values of the first resistor R1 and the second resistor R2 in Figure 3 the second current I of the constant current source module 201 in 2 will be less than Figure 4 the current flowing through the third control transistor P3 and the first resistor R1 in , that is, less than I.

[0091] If the read control signal Read = 0, then Figure 3 the transmission gate composed of the fifth switching transistor N5, the first control transistor P1 and the inverter INV3 in is turned off, the IBIAS port is in a high-impedance state, at the same time the gate voltage of the fourth switching transistor N4 is high, the fourth switching transistor N4 is turned on, the gate voltages of the second switching transistor N2 and the third switching transistor N3 are pulled to the ground Gnd, the second switching transistor N2 and the third switching transistor N3 are both turned off, and no current will flow through the second switching transistor N2 and the third switching transistor N3.

[0092] If the read control signal Read = 1, then Figure 3 the transmission gate composed of the fifth switching transistor N5, the first control transistor P1 and the inverter INV3 in is turned on, the gate voltage of the fourth switching transistor N4 is 0, the fourth switching transistor N4 is turned off, since the sizes of the second switching transistor N2 and the third switching transistor N3 are equal, the second switching transistor N2 and the third switching transistor N3 form a current mirror with a mirror ratio of 1:1, and the currents flowing through both are the same, both equal to the current flowing into the IBIAS port. Since the IBIAS port is connected to the IBOUT port of the common bias unit 100, the current flowing into the IBIAS port is equal to I, so the currents flowing through the second switching transistor N2 and the third switching transistor N3 are both equal to I.

[0093] Based on the above analysis, for the unprogrammed EFUSE storage unit 200, Figure 3 the constant current source current in is greater than I, so the voltage of the first node NetA will be at a high level, that is, it shows as logic 1; for the programmed EFUSE storage unit 200, Figure 3If the current output by the constant current source module 201 in is less than I, the voltage of the first node NetA will be at a low level, i.e., it will represent logic 0. The magnitude of I does not affect the output result of the first node NetA. Therefore, I can be set to a relatively small value, such as 10 μA, which greatly reduces the power consumption during the reading process. When the read control signal Read changes from 1 to 0, the logical state of the first node NetA is latched by the latch circuit module and output to the Dout port. If the Dout port is 1, it indicates that this EFUSE storage unit 200 has not been programmed. If the Dout port is 0, it indicates that this EFUSE storage unit 200 has been programmed.

[0094] In summary, in the EFUSE storage unit, programming / reading circuit, and programming / reading method provided by the embodiments of the present invention, when the read control signal Read changes from 1 to 0, the logical state of the first node NetA is latched by the latch circuit module and output to its latched data output port Dout. If the latched data output port Dout is logic 1, it indicates that this EFUSE storage unit has not been programmed. If the latched data output port Dout is logic 0, it indicates that this EFUSE storage unit has been programmed, thus avoiding the problem of fuse reading errors caused by the electronic fuse not being fully programmed. Further, the magnitude of the preset value does not affect the output result of the first node NetA. Therefore, the bias current signal I can be set to a relatively small value, which can greatly reduce the power consumption during the reading process.

[0095] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. An EFUSE storage cell, characterized in that, it includes: A constant current source module, which is used to connect the programming control signal port and the bias voltage signal port, and provides a first current greater than a preset value before programming and a second current less than the preset value after programming. The constant current source module includes an electronic fuse; A Latch circuit module, where the latch data input port of the Latch circuit module is connected to the first node, and the sampling clock port is connected to the read control signal; A digitally controlled current mirror module, including an inverter, a transmission gate, and a current mirror. The input end of the inverter is connected to the read control signal. The input end and the output end of the inverter are respectively connected to the first control input end and the second control input end of the transmission gate. The signal input end of the transmission gate is connected to the bias current input port, and the bias current input port is used to provide a bias current signal with the preset value. The signal output end of the transmission gate is connected to the reference current input end of the current mirror. The replicated current input end of the current mirror is connected to the first node, and the first node is also connected to the second end of the electronic fuse. Among them, the gate interconnection node in the current mirror is also connected to the drain of the fourth switching transistor. The gate of the fourth switching transistor is connected to the output end of the inverter, and the source of the fourth switching transistor is commonly connected to the ground with the reference current output end and the replicated current output end of the current mirror.

2. The EFUSE storage cell according to claim 1, characterized in that, The constant current source module further includes a second control transistor. The first end of the electronic fuse is connected to the power supply voltage, the second end is connected to the source of the second control transistor, the drain of the second control transistor is connected to the first node, the gate is connected to the bias voltage signal port, the programming control signal port is connected to the gate of the first switching transistor, the drain of the first switching transistor is connected to the second end of the electronic fuse, and the source of the first switching transistor is grounded.

3. The EFUSE storage cell according to claim 1, characterized in that, The transmission gate includes a fifth switching transistor and a first control transistor. The drains of the fifth switching transistor and the first control transistor are interconnected as the signal input end to be connected to the bias current input port. The gate of the fifth switching transistor is used as the first control input end to be connected to the input end of the inverter; the sources of the fifth switching transistor and the first control transistor are interconnected as the signal output end to be connected to the reference current input end of the current mirror. The gate of the first control transistor is used as the second control input end to be connected to the output end of the inverter.

4. The EFUSE storage cell according to claim 2, characterized in that, The current mirror includes a third switching transistor and a second switching transistor. The gates of the third switching transistor and the second switching transistor are interconnected and serve as the gate interconnection node. The drain and the gate of the third switching transistor are interconnected to serve as the reference current input terminal. The drain of the second switching transistor serves as the copied current input terminal and is connected to the first node. The sources of the second switching transistor and the third switching transistor are the copied current output terminal and the reference current output terminal, respectively.

5. An EFUSE programming and reading circuit characterized in that it includes: A common bias unit for providing a bias current signal to a bias current input port and a bias voltage signal to a bias voltage signal port; At least one EFUSE storage unit, where the EFUSE storage unit includes: A constant current source module for connecting a programming control signal port and a bias voltage signal port, and providing a first current greater than a preset value before programming and a second current less than the preset value after programming. The constant current source module includes an electronic fuse; A Latch circuit module, where the latched data input port of the Latch circuit module is connected to the first node, and the sampling clock port is connected to a read control signal; A numerically controlled current mirror module, including an inverter, a transmission gate, and a current mirror. The input terminal of the inverter is connected to the read control signal. The input terminal and the output terminal of the inverter are respectively connected to the first control input terminal and the second control input terminal of the transmission gate. The signal input terminal of the transmission gate is connected to the bias current input port for providing a bias current signal with the preset value. The signal output terminal of the transmission gate is connected to the reference current input terminal of the current mirror. The copied current input terminal of the current mirror is connected to the first node. The first node is also connected to the second terminal of the electronic fuse. Among them, the gate interconnection node in the current mirror is also connected to the drain of a fourth switching transistor. The gate of the fourth switching transistor is connected to the output terminal of the inverter. The source of the fourth switching transistor is commonly connected to the reference current output terminal and the copied current output terminal of the current mirror and grounded.

6. The EFUSE programming and reading circuit according to claim 5, characterized in that the common bias unit includes a first resistor, a second resistor, a third control transistor, and a fourth control transistor. The first ends of the first resistor and the second resistor are commonly connected and connected to a power supply voltage. The source of the third control transistor is connected to the second end of the first resistor. The gate and the drain of the third control transistor are commonly connected for accessing an external bias current signal. The source of the fourth control transistor is connected to the second end of the second resistor. The gates of the third control transistor and the fourth control transistor are commonly connected and connected to the bias voltage signal port to provide a bias voltage signal. The drain of the fourth control transistor is used to output the bias current signal to the bias current input port.

7. The EFUSE programming and reading circuit according to claim 5, characterized in that The constant current source module further includes a second control transistor. The first end of the electronic fuse is connected to the power supply voltage, the second end is connected to the source of the second control transistor. The drain of the second control transistor is connected to the first node, and the gate is connected to the bias voltage signal port. The programming control signal port is connected to the gate of the first switching transistor. The drain of the first switching transistor is connected to the second end of the electronic fuse, and the source of the first switching transistor is grounded.

8. The EFUSE programming and reading circuit according to claim 5, wherein, the transmission gate includes a fifth switching transistor and a first control transistor. The drains of the fifth switching transistor and the first control transistor are interconnected as the signal input terminal to be connected to the bias current input port. The gate of the fifth switching transistor is used as the first control input terminal to be connected to the input terminal of the inverter. The sources of the fifth switching transistor and the first control transistor are interconnected as the signal output terminal to be connected to the reference current input terminal of the current mirror. The gate of the first control transistor is used as the second control input terminal to be connected to the output terminal of the inverter.

9. The EFUSE programming and reading circuit according to claim 5, wherein, the current mirror includes a third switching transistor and a second switching transistor. The gates of the third switching transistor and the second switching transistor are interconnected and used as the gate interconnection node. The drain and the gate of the third switching transistor are interconnected as the reference current input terminal. The drain of the second switching transistor is used as the copied current input terminal to be connected to the first node. The sources of the second switching transistor and the third switching transistor are respectively the copied current output terminal and the reference current output terminal.

10. A programming and reading method for an EFUSE programming and reading circuit, wherein, using the EFUSE programming and reading circuit according to any one of claims 5-9 to program and read the EFUSE storage unit, further comprising the following steps: When programming: providing a read control signal to the EFUSE storage unit, and when the read control signal is at a first level, programming the EFUSE storage unit in sequence, and judging the programming state of the EFUSE storage unit through the level signal of the latch data output port of the Latch circuit module; When reading: providing a read control signal to the EFUSE storage unit, and when the read control signal is at a second level, reading the EFUSE storage unit in sequence.

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