High density one-time programmable memory

Abstract

The high-density one-time programmable memory comprises an array formed by arranging M * N memory units, M and N are preset natural numbers, each memory unit comprises an anti-fuse memory tube and a selection tube, a grid electrode of the anti-fuse memory tube is connected with a first row line WP, a grid electrode of the selection tube is connected with a second row line WS, and the first row line WP is connected with the second row line WS. The first current end of the selection tube is connected with the second current end of the anti-fuse storage tube, and the second current end of the selection tube is connected with the first column line BL; the selection tube comprises a source region of a second conduction type, a drain region and a substrate of a first conduction type, and is characterized in that the source region of the selection tube comprises a second conduction type region and a second conduction type lightly doped region, the drain region only comprises the second conduction type region, the doping concentration of the second conduction type region of the source region is the same as that of the second conduction type region of the drain region, and the doping concentration of the first conduction type region is the same as that of the second conduction type region. The doping concentration of the second conductive type lightly doped region is lower than that of the second conductive type region. The method has lower load leakage current, so that the writing voltage can be improved, and higher writing yield can be obtained.

Description

Technical Field

[0001] The present invention relates to integrated circuit technology, and in particular to memory technology. Background Art

[0002] Patent documents CN1351380A, US8259518B2, and CN2006101425 disclose anti-fuse memory technology based on MOS tubes. Figure 1 The MOS tube structure of the prior art is shown. The GIDL breakdown voltage of the conventional MOSFET is relatively low. GIDL is the gate-induced drain leakage current, which occurs below the gate-drain overlap region. In the conventional CMOS transistor, LDD provides a short connection path under the sidewall between the inversion channel under the Gate and the drain. Since the LDD region is very close to the Gate, even from the projection, the two overlap. When the GD reverse voltage is large, because the Gate and the source and drain must be aligned from the device structure, but it is impossible to align them absolutely in reality, there must be overlap. Below the region where the Drain overlaps the Gate (taking NMOS as an example), when a negative bias is applied to the gate or a strong positive bias is applied to the drain, the holes as the majority carriers of the substrate accumulate near the surface drain LDD, depleting / deeply depleting the original N-type silicon, tending to invert the region. As a result, the depletion region of the drain LDD expands toward the drain, the effect is just like p+ doping, and a strong band bending occurs due to the induced electric field. At this time, when the band bending becomes larger than the band gap, that is, when the valence band Ev becomes higher than the conduction band Ec, electrons flow into the drain through the tunnel effect and generate leakage current. And due to the EHP generated by heat, holes flow into the substrate and electrons flow into the drain, increasing the leakage current. In addition, if the device degrades due to NBTI, PBTI or HCI stress, traps in the interface will generate trap-assisted tunneling current, further increasing the GIDL current. Multiple factors form GIDL leakage.

[0003] US Patent Document US20090090980A1 discloses an asymmetric LDD-type MOS tube, which is compatible with standard CMOS technology and does not require additional masks. In order to create a large voltage drop area on the drain side, the drain LDD is removed by blocking the LDD / Halo injection. Only one logic operation layer is required to form the LDD / Halo injection through the mask tool, so no additional process steps are required. The huge improvement in BVdss is due to the design of a wide depletion region below the sidewall area and between the drain and the substrate, which reduces the peak electric field on the drain side and can support a larger reverse bias drain voltage than in traditional cases. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a high-density one-time programmable memory with a simple structure and a small area.

[0005] The technical solution adopted by the present invention to solve the technical problem is that a high-density one-time programmable memory includes an array formed by arranging M×N storage units, M and N are preset natural numbers, the storage unit includes an anti-fuse storage tube and a selection tube, the gate of the anti-fuse storage tube is connected to the first row line WP, the gate of the selection tube is connected to the second row line WS, the first current end of the selection tube is connected to the second current end of the anti-fuse storage tube, and the second current end of the selection tube is connected to the first column line BL; the selection tube includes a second conductive type source region, a drain region and a first conductive type substrate, characterized in that the source region of the selection tube includes a second conductive type region and a second conductive type lightly doped region, the drain region has only a second conductive type region, the doping concentration of the second conductive type region of the source region and the drain region is the same, and the doping concentration of the second conductive type lightly doped region is lower than that of the second conductive type region.

[0006] Furthermore, the storage unit also includes a detection MOS tube, the connection point between the selection tube and the anti-fuse storage tube is connected to the gate of the detection MOS tube, the first current end of the detection tube is connected to the first column line BL, and the second current end is connected to the second column line BR.

[0007] Furthermore, the second current end of the detection tube is connected to the second column line BR through an isolation tube, and the gate of the isolation tube is connected to the third row line WR.

[0008] Furthermore, the anti-fuse storage tube is an intrinsic MOS tube.

[0009] Beneficial effects of the present invention: Through simulation comparison, for a 16X16 memory cell array, when all cells are 0, the static leakage current can be reduced by about 11% compared with the original solution after adopting the solution of the present invention; when all cells are written as 1, the static leakage current can be reduced by about 41% compared with the original solution after adopting the solution of the present invention. It can be seen that under the condition of limited write power consumption, the present invention has a lower load leakage current, thereby increasing the write voltage and obtaining a higher write yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the MOS tube structure.

[0011] Figure 2 It is a schematic diagram of the structure of the asymmetric MOS tube used in the present invention.

[0012] Figure 3 It is a circuit diagram of embodiment 1 of the present invention.

[0013] Figure 4 It is a circuit diagram of embodiment 2 of the present invention.

[0014] Figure 5 It is a circuit diagram of embodiment 3 of the present invention. DETAILED DESCRIPTION

[0015] A high-density one-time programmable memory comprises an array formed by arranging M×N storage cells, where M and N are preset natural numbers, and the storage cell comprises an anti-fuse storage tube and a selection tube, wherein the gate of the anti-fuse storage tube is connected to the first row line WP, the gate of the selection tube is connected to the second row line WS, the first current end of the selection tube is connected to the second current end of the anti-fuse storage tube, and the second current end of the selection tube is connected to the first column line BL; the selection tube comprises a second conductive type source region, a drain region and a first conductive type substrate, and is characterized in that the source region of the selection tube comprises a second conductive type region and a second conductive type lightly doped region, the drain region has only a second conductive type region, the doping concentrations of the second conductive type regions of the source region and the drain region are the same, and the doping concentration of the second conductive type lightly doped region is lower than that of the second conductive type region.

[0016] For example, the gate of the anti-fuse storage tube is connected to the first row line WP, the gate of the selection tube is connected to the second row line WS, the first current end (drain end) of the selection tube is connected to the second current end (source end) of the anti-fuse storage tube, and the second current end (source end) of the selection tube is connected to the first column line BL; the selection tube includes a source region and a drain region of the second conductivity type (N-type doping) and a substrate of the first conductivity type (P-type doping), the source region of the selection tube includes a second conductivity type region (N+ region) and a second conductivity type lightly doped region (N- region), the drain region has only a second conductivity type region (N+ region), the doping concentrations of the second conductivity type region (N+ region) of the source region and the drain region are the same, and the doping concentration of the second conductivity type lightly doped region (N- region) is lower than that of the second conductivity type region (N+ region).

[0017] Example 1

[0018] See also Figure 3 , Figure 3 The circuit shown is the circuit of Chinese patent document CN1351380A. On this basis, the present embodiment improves the selection tube (shown by the dotted line) and adopts a MOS tube with an asymmetric LDD structure as the selection tube. The source region of the selection tube includes a second conductivity type region (N+ region) and a second conductivity type lightly doped region (N- region, i.e., NLDD); the drain region only has a second conductivity type region (N+ region), and the drain region is not provided with a second conductivity type lightly doped region (N- region).

[0019] As a further improvement of Example 1, the anti-fuse storage tube can adopt an intrinsic MOS tube, because the intrinsic MOS tube has a lower threshold voltage than the conventional MOS tube. The medium between the gate and the channel of the programmed storage tube forms a high-resistance conduction between the gate and the channel due to breakdown, and the conduction between the channel and the source depends on the formation of the channel. Only when both are available can the detection current reach the detection circuit through the gate-channel-source. Only when the voltage applied between the gate and the source of the MOS tube is higher than its threshold voltage can a channel be formed, and the voltage obtained at the source has a threshold voltage drop loss compared to the gate voltage. The use of an intrinsic MOS tube can reduce the voltage drop loss caused by the threshold voltage of the storage tube when the detection current passes through the storage tube. Under the same excitation voltage, a larger detection current can be obtained, and the sensitivity of the detection can be improved; or under the same detection sensitivity requirements, the excitation voltage required for detection can be reduced.

[0020] Example 2

[0021] See also Figure 4 , Figure 4 The storage unit shown is the storage unit of US Pat. No. 8,797,820B2. On this basis, the present embodiment improves the selection tube (shown by the dotted line) and adopts a MOS tube with an asymmetric LDD structure as the selection tube. The source region of the selection tube includes a second conductivity type region (N+ region) and a second conductivity type lightly doped region (N- region); the drain region only has the second conductivity type region (N+ region), and the drain region is not provided with a second conductivity type lightly doped region (N- region).

[0022] Example 3

[0023] See also Figure 5 , Figure 5 The storage unit shown is the storage unit of Chinese patent document CN2006101425131. On this basis, the present embodiment improves the selection tube (shown by the dotted line portion) and adopts a MOS tube with an asymmetric LDD structure as the selection tube. The source region of the selection tube includes a second conductivity type region (N+ region) and a second conductivity type lightly doped region (N- region); the drain region only has the second conductivity type region (N+ region), and the drain region is not provided with a second conductivity type lightly doped region (N- region).

[0024] Embodiment 2 and embodiment 3 can be further improved by using an intrinsic MOS tube as an anti-fuse storage tube, because the intrinsic MOS tube has a lower threshold voltage than the conventional MOS tube. The medium between the gate and the channel of the programmed storage tube forms a high-resistance conduction between the gate and the channel due to breakdown, and the conduction between the channel and the source depends on the formation of the channel. Only when both are available can the detection current reach the detection circuit through the gate-channel-source. Only when the voltage applied between the gate and the source of the MOS tube is higher than its threshold voltage can a channel be formed and turned on. After the conduction, the voltage obtained at the source has a threshold voltage drop loss compared to the gate voltage. The use of an intrinsic MOS tube in the storage tube can reduce the voltage drop loss caused by the threshold voltage when the detection current passes through, so that a higher detection voltage can be obtained at the gate of the detection tube NR, reducing the excitation voltage required for detection.

Claims

1. A high-density one-time programmable memory, comprising an array formed by arranging M×N memory cells, wherein M and N are preset natural numbers, wherein the memory cell comprises an anti-fuse memory tube and a selection tube, wherein the gate of the anti-fuse memory tube is connected to a first row line WP, the gate of the selection tube is connected to a second row line WS, the first current end of the selection tube is connected to a second current end of the anti-fuse memory tube, and the second current end of the selection tube is connected to a first column line BL; the selection tube comprises a source region and a drain region of a second conductivity type and a substrate of a first conductivity type, wherein: The source region of the selection tube includes a second conductivity type region and a second conductivity type lightly doped region, and the drain region only has a second conductivity type region. The doping concentrations of the second conductivity type regions in the source region and the drain region are the same, and the doping concentration of the second conductivity type lightly doped region is lower than that of the second conductivity type region.

2. The high-density one-time programmable memory according to claim 1, characterized in that: The storage unit also includes a detection MOS tube, the connection point of the selection tube and the anti-fuse storage tube is connected to the gate of the detection MOS tube, the first current end of the detection tube is connected to the first column line BL, and the second current end is connected to the second column line BR.

3. The high-density one-time programmable memory according to claim 1, characterized in that: The second current end of the detection tube is connected to the second column line BR through an isolation tube, and the gate of the isolation tube is connected to the third row line WR.

4. The high-density one-time programmable memory according to claim 1, 2 or 3, characterized in that: The anti-fuse storage tube is an intrinsic MOS tube.

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