Chip fan-out type packaging structure and chip manufacturing method

Abstract

The invention relates to a chip fan-out type packaging structure and a chip manufacturing method, and relates to the technical field of semiconductor packaging, the chip fan-out type packaging structure comprises a recombined silicon wafer, the recombined silicon wafer comprises a separation blade and a chip, and the chip is located in a groove penetrating through the separation blade along a first direction; a plastic package layer and a rewiring layer, the plastic package layer is located at one side of the recombined silicon wafer along the first direction, the plastic package layer comprises a plastic package material, and the plastic package material fills a gap between the chip and the groove along the second direction; the redistribution layer is located on at least one side of the recombined silicon wafer in the first direction; a ball grid array serving as a conductive bump is also arranged on the rewiring layer on one side of the active surface of the chip; therefore, the flatness and consistency of the chip can be ensured without accurately controlling the etching precision, the production difficulty and cost are reduced, the deviation and warpage of the chip are reduced, and the production stability is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and in particular to a chip fan-out packaging structure and a chip manufacturing method. Background Art

[0002] Fan-Out technology is an advanced semiconductor packaging method that achieves higher pin density and better electrical performance by extending the chip's pins at the wafer level and extending the chip's effective area beyond the boundaries of the original silicon wafer. Fan-Out technology first forms a layer of plastic material on the wafer as a carrier, and then builds a redistribution layer (RDL) and bumps on it to rearrange and expand the chip's I / O pins. In this way, even if the chip itself is small in size, it can have more connection points, improving signal transmission efficiency and reliability.

[0003] After the chip is reassembled and plastic-sealed, the different thermal expansion of the plastic-sealing compound and the silicon substrate causes the chip spacing to change and the silicon wafer to warp. If not properly handled, it may cause product defects due to misalignment, seriously affecting product quality and yield.

[0004] Therefore, how to achieve accurate control of chip spacing and reduce silicon wafer warping has become a technical problem that needs to be urgently solved by technical personnel in this field. Summary of the invention

[0005] In order to solve the above technical problems, the present disclosure provides a chip fan-out packaging structure and a chip manufacturing method, which are used to achieve chip spacing accuracy control during the chip reassembly and plastic packaging process and reduce silicon wafer warping after plastic packaging.

[0006] In a first aspect, the present disclosure provides a chip fan-out packaging structure, comprising a reconstructed silicon wafer, wherein the reconstructed silicon wafer comprises a baffle and a chip, wherein the baffle comprises grooves arranged in an array, wherein the grooves penetrate the baffle, wherein the chip is located in the grooves, and wherein the plane of the chip is parallel to the baffle;

[0007] The packaging structure further includes a plastic sealing layer and a redistribution layer. Along a first direction, the plastic sealing layer is located at least on one side of the reconstructed silicon chip. The plastic sealing layer includes a plastic sealing material. Along a second direction, the plastic sealing material fills the gap between the chip and the groove. The first direction is perpendicular to the baffle, and the second direction is parallel to the baffle.

[0008] Along the first direction, the redistribution layer is located on at least one side of the reconstructed silicon chip; the chip includes an active surface, and the redistribution layer located on one side of the chip active surface also includes a ball grid array as a conductive bump.

[0009] Optionally, the chip includes a first through-silicon via that is perpendicular to the plane of the chip and electrically connected to the redistribution layer; and / or, the spacer includes a second through-silicon via that is perpendicular to the plane of the spacer and electrically connected to the redistribution layer.

[0010] Optionally, the thickness of the reconstituted silicon wafer is greater than or equal to 100 μm and less than or equal to 1200 μm; the thickness of the encapsulation layer is less than or equal to 60 μm.

[0011] In a second aspect, the present disclosure provides a method for fabricating a chip, which is used to fabricate the chip fan-out package structure as described in the first aspect, and includes:

[0012] Take a carrier, and form a first adhesive layer on one side of the carrier;

[0013] Attach a spacer on the first adhesive layer, grind and thin the spacer, and etch to form a groove;

[0014] Mount the chip in the groove, and the chip is directly attached to the first adhesive layer; the chip and the spacer form a reconstituted silicon wafer;

[0015] Encapsulate the reconstituted silicon wafer with encapsulant to form an encapsulation layer, and grind and thin the encapsulation layer;

[0016] Remove the carrier;

[0017] At least on the active surface side of the chip, form a redistribution layer by coating, developing, exposing, and electroplating, and form a ball grid array as a conductive bump on the redistribution layer on the active surface side of the chip;

[0018] Form a plurality of embedded chip fan-out packages by cutting.

[0019] Optionally, the direct attachment of the chip to the first adhesive layer is specifically:

[0020] The chip includes an active surface, and the active surface of the chip is directly attached to the first adhesive layer, or, the surface of the chip opposite to the active surface is directly attached to the first adhesive layer.

[0021] Optionally, the active surface of the chip faces away from the first adhesive layer, and the active surface of the chip includes copper pillars; after the surface of the chip opposite to the active surface is directly attached to the first adhesive layer and the reconstituted silicon wafer is encapsulated with encapsulant to form an encapsulation layer, grinding and thinning the encapsulation layer specifically means thinning the encapsulation layer until the copper pillars are exposed on the surface of the encapsulation layer.

[0022] Optionally, a redistribution layer is formed on the surface of the chip opposite to the active surface.

[0023] Optionally, the first adhesive layer includes at least one of polyimide, polyacrylate, polyurethane, polyvinyl alcohol, and polyvinyl butyral.

[0024] Optionally, the thickness of the spacer after grinding and thinning is greater than or equal to 100 μm and less than or equal to 1000 μm.

[0025] Optionally, the thickness of the encapsulation layer after grinding and thinning is less than or equal to 60 μm.

[0026] The technical solutions provided by the embodiments of the present disclosure have the following advantages compared with the prior art: The present disclosure proposes a completely new technical path, significantly improving the accuracy of chip recombination, enabling it to meet the product requirements of higher process levels, and effectively solving the problems of chip deviation and warping caused by different thermal expansion coefficients of different materials, thereby greatly improving the process capability and production stability. Under the same process requirements, compared with the traditional method, this solution shows better stability and higher yield. In addition, the present disclosure also introduces a new method of double-sided circuit connection, providing a higher-precision, more stable process flow and better yield guarantee for applications that require double-sided circuit connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure and used together with the specification to explain the principles of the present disclosure.

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0029] Figure 1 Shown is a cross-sectional view of a chip fan-out package structure provided by an embodiment of the present disclosure;

[0030] Figure 2 Shown is a cross-sectional view of another chip fan-out package structure provided by an embodiment of the present disclosure;

[0031] Figure 3 Shown is a cross-sectional view of yet another chip fan-out package structure provided by an embodiment of the present disclosure;

[0032] Figure 4 Shown is a cross-sectional view of yet another chip fan-out package structure provided by an embodiment of the present disclosure;

[0033] Figure 5 Shown is a schematic diagram of a chip manufacturing step provided by an embodiment of the present disclosure;

[0034] Figure 6 The following is a schematic flow chart of fabricating a chip with its active surface facing down according to an embodiment of the present disclosure;

[0035] Figure 7 The following is a schematic flow chart of fabricating a chip with its active surface facing up according to an embodiment of the present disclosure;

[0036] Figure 8 The following is a schematic flow chart of fabricating a chip including through - silicon vias according to an embodiment of the present disclosure;

[0037] Figure 9 The following is a schematic flow chart of fabricating a chip when the spacer includes through - silicon vias according to an embodiment of the present disclosure;

[0038] Figure 10 The following is a schematic flow chart of fabricating a chip and a spacer both including through - silicon vias according to an embodiment of the present disclosure;

[0039] Figure 11 The following is a schematic structural diagram of a first glue layer according to an embodiment of the present disclosure. Detailed implementation manners

[0040] In order to more clearly understand the above - mentioned objects, features and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that, without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other.

[0041] Many specific details are set forth in the following description in order to fully understand the present disclosure, but the present disclosure may be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present disclosure, rather than all the embodiments.

[0042] Figure 1 The following is a cross - sectional view of a chip fan - out package structure according to an embodiment of the present disclosure, Figure 2 The following is a cross - sectional view of another chip fan - out package structure according to an embodiment of the present disclosure, Figure 3 The following is a cross - sectional view of yet another chip fan - out package structure according to an embodiment of the present disclosure, Figure 4 The following is a cross - sectional view of yet another chip fan - out package structure according to an embodiment of the present disclosure; please refer to Figures 1 to 4 ; The present disclosure provides a chip fan - out package structure 100, including a reconstituted silicon wafer 10, the reconstituted silicon wafer 10 includes a spacer 02 and a chip 05, the spacer 02 includes a plurality of grooves 04 arranged in an array, the grooves 04 penetrate through the spacer 02, the chip 05 is located in the grooves 04, and the plane of the chip 05 is parallel to the spacer 02.

[0043] The chip fan-out package structure 100 further includes a molding layer 06 and a redistribution layer 07. Along the first direction D1, the molding layer 06 is at least located on one side of the reconstituted silicon wafer 10. The molding layer 06 includes molding compound 061. Along the second direction D2, the molding compound 061 fills the gap between the chip 05 and the groove 04. The first direction D1 is perpendicular to the spacer 02, and the second direction D2 is parallel to the spacer 02.

[0044] Along the first direction D1, the redistribution layer 07 is located on at least one side of the reconstituted silicon wafer 10. The chip 05 includes an active surface, and a ball grid array serving as a conductive bump 08 is further included on the redistribution layer 07 on the side of the active surface of the chip 05.

[0045] Specifically, please refer to Figure 1 , in an optional embodiment provided by the present disclosure, the chip fan-out package structure 100 includes a reconstituted silicon wafer 10, a molding layer 06, and a redistribution layer 07. The reconstituted silicon wafer 10 includes a spacer 02 and a chip 05. The spacer 02 includes a plurality of grooves 04. The grooves 04 penetrate through the spacer 02 along a direction perpendicular to the plane where the spacer 02 is located. The present disclosure does not limit the arrangement form and quantity of the grooves 04, and specifically depends on the actual process. The chip 05 is located in the groove 04. The molding layer 06 covers one side of the reconstituted silicon wafer 10 along the first direction D1 to provide physical protection for the chip 05. Along the direction parallel to the plane where the spacer 02 is located, the gap between the chip 05 and the groove 04 where the chip 05 is located further includes molding compound 061, and the molding compound 061 fills the gap to fix the chip 05, prevent the chip 05 from slipping during the packaging process, and improve the alignment accuracy. The redistribution layer 07 is located on at least one side of the chip 05. Optionally, the redistribution layer 07 is located on the side of the active surface of the chip 05. The redistribution layer 07 is used to change the contact position of the original circuit contact points of the chip 05 through a wafer-level metal wiring process and a bump process, playing a role in electrical extension and interconnection, so that the chip 05 can be applicable to different packaging forms.

[0046] On the side of the redistribution layer 07 facing away from the chip 05, there is also a ball grid array serving as the conductive bump 08. It should be noted that the accompanying drawings of the embodiments of the present disclosure only illustrate the ball grid array on the active surface side of the chip 05. Those skilled in the art should understand that when redistribution layers 07 are provided on both sides of the chip 05 along the first direction D1, ball grid arrays can be provided on the redistribution layers 07 on both sides of the chip 05, and the present disclosure does not limit this. Optionally, the manufacturing process of the conductive bump 08 includes but is not limited to stencil printing process, ball mounting process, reflow soldering process, etc. The conductive bump 08 is electrically connected to the redistribution layer 07. Optionally, the redistribution layer 07 includes a metal pad corresponding to the position of the conductive bump 08, and the conductive bump 08 can be electrically connected to the redistribution layer 07 through the metal pad. Along the second direction D2, there is also a passivation layer (not shown in the figure) between adjacent metal pads, and the passivation layer is used to isolate the influence of water and air on the internal circuit of the chip 05.

[0047] Optionally, the spacer 02 includes but is not limited to a Dummy wafer, and the Dummy wafer is a test wafer / fake wafer made of a material similar to a wafer but without circuit elements.

[0048] In this way, by providing a plurality of grooves 04 penetrating the spacer 02 along the first direction D1 on the spacer 02, the depths of the grooves 04 can be made the same, and the heights of the chips 05 located in different grooves 04 are consistent, which is beneficial to improving the control of the height consistency of the active surface of the chip 05, and thus improving the packaging yield. Forming the redistribution layer 07 on at least one side of the chip 05 along the first direction D1 is beneficial to expanding the range of electrical extension and interconnection, and meeting the requirements of different packaging forms.

[0049] Please refer to Figures 2 to 4 , optionally, the chip 05 includes a first through-silicon via 091, the first through-silicon via 091 is perpendicular to the plane of the chip 05 and is electrically connected to the redistribution layer 07; and / or, the spacer 02 includes a second through-silicon via 092, the second through-silicon via 092 is perpendicular to the plane of the spacer 02 and is electrically connected to the redistribution layer 07.

[0050] Please refer to Figure 2, specifically, in an alternative embodiment provided by the present disclosure, the chip 05 in the chip fan-out package structure 100 includes a first through-silicon via 091. When the chip 05 includes the first through-silicon via 091, the first through-silicon via 091 is filled with a conductive material including but not limited to copper. Redistribution layers 07 can be provided on both sides of the chip 05 along the first direction D1. That is, a redistribution layer 07 is provided on one side of the active surface of the chip 05, and a redistribution layer 07 is also provided on the other surface opposite to the active surface of the chip 05. When the chip 05 includes the first through-silicon via 091, the redistribution layer 07 on the other surface opposite to the active surface of the chip 05 is connected to the devices on the active surface of the chip 05 through the first through-silicon via 091 in the chip 05, realizing electrical connection with the chip 05, so as to expand the electrical extension and interconnection range on both sides of the chip 05 along the first direction D1 and meet different forms of packaging requirements.

[0051] It should be noted that when the chip 05 includes the first through-silicon via 091, and the active surface of the chip 05 is mounted face down in the groove 04, and redistribution layers 07 are provided on both sides of the chip 05 along the first direction D1, the molding compound layer 06 on the other surface opposite to the active surface of the chip 05 needs to be thinned by grinding until it is completely removed to expose the first through-silicon via 091 of the chip 05, so as to realize the production of the redistribution layer 07 on the side opposite to the active surface of the chip 05.

[0052] Please refer to Figure 3 , in an alternative embodiment provided by the present disclosure, the spacer 02 in the chip fan-out package structure 100 includes a second through-silicon via 092. When the spacer 02 includes the second through-silicon via 092, the second through-silicon via 092 is filled with a conductive material including but not limited to copper. Redistribution layers 07 can be provided on both sides of the chip 05 along the first direction D1. That is, a redistribution layer 07 is provided on one side of the active surface of the chip 05, and a redistribution layer 07 is also provided on the other surface opposite to the active surface of the chip 05. When the spacer 02 includes the second through-silicon via 092, the redistribution layer 07 on the other surface opposite to the active surface of the chip 05 is connected to the devices on the active surface of the chip 05 through the second through-silicon via 092 in the spacer 02, realizing electrical connection with the chip 05, so as to expand the electrical extension and interconnection range on both sides of the chip 05 along the first direction D1 and meet different forms of packaging requirements.

[0053] It should be noted that when the spacer 02 includes the second through-silicon via 092, and the active surface of the chip 05 is mounted face down in the groove 04, and redistribution layers 07 are provided on both sides of the chip 05 along the first direction D1, the molding compound layer 06 on the other surface opposite to the active surface of the chip 05 needs to be thinned by grinding until it is completely removed to expose the second through-silicon via 092 in the spacer 02, so as to realize the production of the redistribution layer 07 on the side opposite to the active surface of the chip 05.

[0054] Please refer toFigure 4 , in an alternative embodiment provided by the present disclosure, the chip 05 in the chip fan-out package structure 100 includes a first through-silicon via 091, and the spacer 02 includes a second through-silicon via 092. When the chip 05 includes the first through-silicon via 091 and the spacer 02 includes the second through-silicon via 092, the first through-silicon via 091 is filled with a conductive material including but not limited to copper and the like, and the second through-silicon via 092 is filled with a conductive material including but not limited to copper and the like. Redistribution layers 07 can be provided on both sides of the chip 05 along the first direction D1. That is, a redistribution layer 07 is provided on one side of the active surface of the chip 05, and a redistribution layer 07 is also provided on the other surface opposite to the active surface of the chip 05; when the chip 05 includes the first through-silicon via 091 and the spacer 02 includes the second through-silicon via 092, the redistribution layer 07 on the other surface opposite to the active surface of the chip 05 is connected to the devices on the active surface of the chip 05 through the first through-silicon via 091 in the chip 05 and the second through-silicon via 092 in the spacer 02, so as to realize electrical connection with the chip 05, further expanding the electrical extension and interconnection range on both sides of the chip 05 along the first direction D1 and meeting different forms of packaging requirements.

[0055] It should be noted that when the chip 05 includes the first through-silicon via 091, the spacer 02 includes the second through-silicon via 092, and the active surface of the chip 05 is mounted downward in the groove 04, and redistribution layers 07 are provided on both sides of the chip 05 along the first direction D1, the encapsulation layer 06 on the other surface opposite to the active surface of the chip 05 needs to be thinned by grinding until it is completely removed to expose the first through-silicon via 091 in the chip 05 and the second through-silicon via 092 in the spacer 02, so as to realize the fabrication of the redistribution layer 07 on the side opposite to the active surface of the chip 05.

[0056] In this way, when the chip 05 is encapsulated, if both the chip 05 and the spacer 02 include through-silicon vias 09, redistribution layers 07 can be provided on both sides of the chip 05. The conductive material in the through-silicon via 09 is used to connect the redistribution layer 07 on the side opposite to the active surface of the chip 05 to the devices on the active surface of the chip 05, realizing the 3D structure packaging of the chip 05 along the first direction D1, which is beneficial to expanding the electrical extension range of the chip 05 and meeting different forms of packaging requirements.

[0057] Optionally, please refer to Figure 1, the thickness H1 of the reconstructed silicon wafer 10 is greater than or equal to 100 μm and less than or equal to 1200 μm. It should be noted that the plane of the chip 05 is parallel to the spacer 02. Optionally, the plane of the chip 05 and the plane of the spacer 02 are in the same plane or not in the same plane. The thickness H1 of the reconstructed silicon wafer 10 refers to the maximum thickness formed as a whole after the chip 05 is mounted in the groove 04 of the spacer 02. Optionally, the thickness H1 of the reconstructed silicon wafer 10 is greater than or equal to 100 μm and less than or equal to 1000 μm, or the thickness H1 of the reconstructed silicon wafer 10 is greater than or equal to 200 μm and less than or equal to 1200 μm, or the thickness H1 of the reconstructed silicon wafer 10 is greater than or equal to 300 μm and less than or equal to 1200 μm... and so on, which will not be listed one by one here.

[0058] Optionally, please continue to refer to Figure 1 , when the redistribution layer 07 is only provided on one side of the active surface of the chip 05 and the chip 05 is encapsulated with the active surface facing down, the chip fan-out package structure 100 further includes a molding compound layer 06. Along the first direction D1, the molding compound layer 06 is located on the other side opposite to the active surface of the chip 05. As described above, within the thickness range of the reconstructed silicon wafer 10 being greater than or equal to 100 μm and less than or equal to 1200 μm, the reconstructed silicon wafer 10 needs to reserve at least 40 μm of process space to avoid damage to the product by the molding tool. That is, the original thickness of the molding compound layer 06 is greater than 40 μm, and after molding, the thickness H2 of the molding compound layer 06 is further ground and thinned. Optionally, the thickness H2 of the molding compound layer 06 is ground and thinned to be less than or equal to 60 μm. Specifically, for different product requirements, the final thickness after grinding and thinning of the molding compound layer 06 is different. For example, when the redistribution layer 07 is only provided on one side of the reconstructed silicon wafer 10, the thickness of the molding compound layer 06 can be 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, or even completely removed to 0 μm... That is to say, the final thickness after grinding and thinning of the molding compound layer 06 needs to be appropriately adjusted according to the thickness of the reconstructed silicon wafer 10 and the corresponding manufacturing process. The present disclosure does not specifically limit the final thickness after grinding and thinning of the molding compound layer 06, as long as it satisfies the range of being less than or equal to 60 μm. In this way, by reducing the thickness of the molding compound layer 06, the thickness of the reconstructed silicon wafer 10 can be made much greater than the thickness of the molding compound layer 06 after grinding and thinning, which can reduce the influence of the thermal expansion and contraction of the molding compound layer 06 on the overall warping of the reconstructed silicon wafer 10 and the change in the pitch of the chip 05.

[0059] It should be noted that, please refer to Figures 2 to 4, when the redistribution layers 07 are disposed on both sides of the chip 02 along the first direction D1, to facilitate the connection between the redistribution layer 07 and the through-silicon via 09, after the encapsulation process is completed, it is necessary to grind and thin the encapsulation layer 06 on the other side of the chip 05 opposite to the active surface until it is completely removed, that is, the thickness of the encapsulation layer 06 is 0 μm. At this time, the chip 05 is not covered by the encapsulation layer 06 along the first direction D1. Since there is no thermal expansion difference between different materials in the first direction D1, the warping of the chip 05 can be reduced in this way.

[0060] Figure 5 The figure shows a schematic diagram of a chip manufacturing step provided by an embodiment of the present disclosure. Please refer to Figure 5 , the present disclosure provides a chip manufacturing method for manufacturing the chip fan-out package structure 100 as described above, including: Step S1: Take a carrier 01 and form a first adhesive layer 03 on one side of the carrier 01; Step S2: Bond a spacer 02 on the first adhesive layer 03, grind and thin the spacer 02 and etch it to form a groove 04; Step S3: Mount the chip 05 in the groove 04, and the chip 05 is directly bonded to the first adhesive layer 03; the chip 05 and the spacer 02 form a reconstituted silicon wafer 10; Step S4: Encapsulate the reconstituted silicon wafer 10 with an encapsulant 061 to form an encapsulation layer 06, and grind and thin the encapsulation layer 06; Step S5: Remove the carrier 01; Step S6: Form a redistribution layer 07 on at least one side of the active surface of the chip 05 by coating, developing, exposing, and electroplating, and form a ball grid array as the conductive bump 08 on the redistribution layer 07 on one side of the active surface of the chip 05; Step S7: Form a plurality of embedded chip fan-out packages by cutting.

[0061] Specifically, in step S1, the carrier 01 includes, but is not limited to, a silicon wafer. The present disclosure does not specifically limit the material of the carrier 01, and the carrier 01 made of the required material can be adopted according to the actual situation. A first adhesive layer 03 is formed on one side of the carrier 01, and the first adhesive layer 03 is used to bond the spacer 02. In step S2, after the spacer 02 is bonded to the first adhesive layer 03, the side of the spacer 02 facing away from the carrier 01 is first ground and thinned to the required thickness, and then the ground and thinned spacer 02 is etched to form grooves 04. The arrangement and number of the grooves 04 can be limited according to the actual process. The thickness of the spacer 02 is adjusted adaptively according to the thickness of different types of chips, which is beneficial to forming the best silicon ratio, improving the process efficiency, and giving full play to the advantages of the present disclosure in controlling the warping of the reconstituted silicon wafer 10 and the chip accuracy; in addition, by increasing the ratio of the spacer 02 to increase the silicon ratio, the ratio of the encapsulation material is effectively reduced, thereby greatly reducing the influence of thermal expansion and contraction on the position of the chip 05. Optionally, the grooves 04 penetrate through the spacer 02, and the first adhesive layer 03 is exposed at the bottom of the grooves 04, that is, the plurality of grooves 04 formed by etching penetrate through the spacer 02 along the first direction D1, and the depths of the plurality of grooves 04 along the first direction D1 are the same, which can make the chips 05 located inside the plurality of different grooves 04 be in the same plane, which is beneficial to keeping the height of the active surface of the chip 05 consistent, and there is no need to strictly control the etching accuracy.

[0062] In the traditional technology of embedding the chip 05 into the silicon substrate, in order to ensure that the chip 05 can be accurately embedded in the predetermined position, the etching process of the silicon substrate must be extremely strictly controlled, which not only increases the complexity of the process, but also increases the production cost. In this embodiment, by first grinding and thinning the spacer 02 to a thickness suitable for the chip 05 to be encapsulated, and then etching the ground and thinned spacer 02 to form grooves 04 with the same depth and penetrating through the spacer 02, the flatness and consistency of the chip 05 can be ensured without precisely controlling the etching accuracy, greatly reducing the production difficulty and cost; ensuring the high consistency of the height of the chip 05 after recombination, not only meeting the requirements of high-end processes, but also providing a strong guarantee for the long-term stable operation of the product.

[0063] In step S3, since the groove 04 penetrates the baffle 02 along the first direction D1, the first adhesive layer 03 is exposed at the bottom of the groove 04. The first adhesive layer 03 can be used to adhere the chip 05, which is beneficial to the mounting of the chip 05. In step S4, after the chip 05 is attached to the first adhesive layer 03, the side of the recombinant silicon wafer 10 facing away from the carrier 01 is encapsulated with the encapsulant 061. Along the first direction D1, at least a part of the encapsulant 061 is located on the side of the baffle 02 facing away from the carrier 01. Along the second direction D2, at least a part of the encapsulant 061 fills the gap between the chip 05 and the groove 04. The encapsulant 061 located on the side of the baffle 02 facing away from the carrier 01 forms an encapsulation layer 06. Since the depths of the grooves 04 etched on the baffle 02 are the same, the chips 05 located in the grooves 04 can be in the same plane. Furthermore, the height of the surface of the encapsulation layer 06 facing away from the carrier 01 can be kept consistent.

[0064] It should be noted that in the traditional silicon wafer recombination process, the encapsulant 061 expands or contracts when the temperature changes. This change in physical properties will cause a small but non-negligible deviation in the position of the chip 05. These deviations not only affect the performance of the final product but may also cause a series of chain reactions in subsequent processing steps, reducing the qualified rate of the product. Since the materials of the encapsulant 061 and the chip 05 are different and their coefficients of thermal expansion are different, the present disclosure can reduce the thermal expansion difference between the two by grinding and thinning the encapsulation layer 06 or directly removing the encapsulation layer 06, thereby reducing the warping of the chip 05. In addition, even if the coefficients of thermal expansion of the encapsulant 061 between the chip 05 and the side wall of the groove 04 and the chip 05 are different, since the encapsulant 061 exists in the gap between the chip 05 and the side wall of the groove 04 along the second direction D2, the present disclosure restricts the part of the encapsulant 061 that affects the chip 05 spacing within the frame of the baffle 02, restricting the activity area of the encapsulant 061. This helps to disperse the cumulative effect of the thermal expansion and contraction of the encapsulant 061, reducing the influence of the thermal expansion and contraction of the encapsulant 061 on the position of the chip 05, reducing the influence of the thermal expansion difference between the chip 05 and the encapsulant 061 in the second direction D2 on the chip 05 spacing, reducing the change in the chip 05 spacing, thereby ensuring the accuracy and stability of the chip 05 during the recombination process, achieving the control of the chip 05 spacing accuracy, reducing product defects caused by misalignment, and improving the product yield.

[0065] In step S5, after the molding layer 06 is ground and thinned, the carrier 01 is removed. In step S6, a redistribution layer 07 is formed by spin coating, developing, exposing, and electroplating at least on one side of the active surface of the chip 05. Optionally, the redistribution layer 07 includes copper connection lines or traces for realizing electrical connection between various parts of the package. Optionally, the chip 05 includes an active surface, which is the surface of the chip 05 for making active devices. A ball grid array serving as conductive bumps 08 is formed on the redistribution layer 07 on one side of the active surface of the chip 05. Optionally, along the second direction D2, a passivation layer is further included between adjacent metal pads on the redistribution layer 07, and the ball grid array is electrically connected to the redistribution layer 07 through the metal pads. In step S7, a plurality of embedded chip fan-out packages are formed by cutting, and the processing of the chip 05 can be continued according to existing subsequent processes.

[0066] Thus, by grinding and thinning the molding layer 06 after molding, the thickness of the molding layer 06 can be reduced, thereby reducing the thermal expansion difference caused by different materials between the molding layer 06 and the chip 05 and reducing the warping of the chip 05. By forming a redistribution layer 07 on at least one side of the chip 05, a fan-out structure can be formed on at least one side of the chip 05, which is beneficial to increasing the types of fan-out structures of the chip 05 and adapting to different application scenarios.

[0067] Optionally, Figure 6 The figure shows a schematic flow chart of manufacturing a chip with its active surface facing down according to an embodiment of the present disclosure. Figure 7 The figure shows a schematic flow chart of manufacturing a chip with its active surface facing up according to an embodiment of the present disclosure. Please refer to Figure 6 and Figure 7 , the direct bonding between the chip 05 and the first adhesive layer 03 is specifically as follows: Please combine Figure 6 , the chip 05 includes an active surface, and the active surface of the chip 05 is directly bonded to the first adhesive layer 03, or, please refer to Figure 7 , the surface of the chip 05 opposite to the active surface is directly bonded to the first adhesive layer 03.

[0068] Please refer to Figure 1 and Figure 6, specifically, in an optional embodiment provided by the present disclosure, the active surface of the chip 05 is directly attached to the first adhesive layer 03 in the groove 04, that is, the active surface of the chip 05 faces the carrier 01 and is directly attached to the first adhesive layer 03. The reconstituted silicon wafer 10 is encapsulated with the encapsulant 061 to form an encapsulation layer 06. At this time, the encapsulation layer 06 is located on the side opposite to the active surface of the chip 05. The encapsulation layer 06 is ground and thinned to a required thickness to reduce the thermal expansion difference between the encapsulation layer 06 and the chip 05 and reduce the warping of the chip 05. The carrier 01 is removed. The methods for removing the carrier 01 include but are not limited to ultraviolet light irradiation, laser, thermal debonding, etc. The present disclosure does not specifically limit the method for removing the carrier 01, and it shall be subject to the actual process. Optionally, after the carrier 01 is removed, a redistribution layer 07 can be formed on the active surface of the chip 05 through processes such as glue coating, development, exposure, and electroplating. A spherical array serving as conductive bumps 08 is formed on the side of the redistribution layer 07 facing away from the chip 05.

[0069] Please refer to Figure 7 , in another optional embodiment provided by the present disclosure, the surface of the chip 05 opposite to the active surface is directly attached to the first adhesive layer 03 in the groove 04. The reconstituted silicon wafer 10 is encapsulated with the encapsulant 061 to form an encapsulation layer 06, that is, the surface of the chip 05 opposite to the active surface faces the carrier 01, the active surface of the chip 05 is located on the side facing the encapsulation layer 06, and the active surface of the chip 05 is in direct contact with the encapsulation layer 06. At this time, in order to implement the subsequent fan-out structure packaging, copper pillars 051 need to be processed in advance on the active surface of the chip 05. After the encapsulation layer 06 is ground and thinned until the copper pillars 051 are exposed, a redistribution layer 07 is formed on the side of the encapsulation layer 06 facing away from the chip 05 through glue coating, development, exposure, and electroplating in sequence. The copper pillars 051 can serve as a path for electrical connection between the redistribution layer 07 and the active surface of the chip 05. A ball grid array serving as conductive bumps 08 is formed on the side of the redistribution layer 07 facing away from the chip 05.

[0070] The attachment of the chip 05 to the first adhesive layer 03 includes the direct attachment of the active surface of the chip 05 to the first adhesive layer 03 and also includes the direct attachment of the surface of the chip 05 opposite to the active surface to the adhesive layer. In this way, through different attachment forms, different packaging structures with the active surface of the chip 05 facing up and the active surface of the chip 05 facing down can be formed, meeting the needs of different packaging forms in actual production and providing multiple choices for users.

[0071] Please continue to refer to Figure 7 , optionally, the active surface of the chip 05 faces away from the first adhesive layer 03, and the active surface of the chip 05 includes copper pillars 051; when the surface of the chip 05 opposite to the active surface is directly attached to the first adhesive layer 03, the spacer 02 and the chip 05 are encapsulated with the encapsulant 061 to form an encapsulation layer 06. Specifically, the encapsulation layer 06 is thinned until the copper pillars 051 are exposed on the surface of the encapsulation layer 06.

[0072] Specifically, in an alternative embodiment provided by the present disclosure, when the active surface of the chip 05 faces away from the carrier 01, that is, after the surface of the chip 05 opposite to the active surface is directly attached to the first adhesive layer 03, the active surface of the chip 05 faces upward. At this time, copper pillars 051 are pre-processed on the active surface of the chip 05. The spacer 02 and the chip 05 are encapsulated with an encapsulant 061 to form an encapsulation layer 06. The encapsulation layer 06 covers the spacer 02 and the chip 05, and the encapsulation layer 06 covers the copper pillars 051 on the active surface of the chip 05. When the encapsulation layer 06 is ground and thinned to the required thickness, the copper pillars 051 on the active surface of the chip 05 are exposed on the surface of the encapsulation layer 06. When forming the redistribution layer 07 on the thinned encapsulation layer 06 through a series of processes, the redistribution layer 07 can be in direct contact with the copper pillars 051 to form a conductive path, realizing the electrical connection between the redistribution layer 07 and the active surface of the chip 05. In this way, when the active surface of the chip 05 is not in direct contact with the first adhesive layer 03, since the active surface of the chip 05 is covered with the encapsulation layer 06 and copper pillars 051 are preset on the active surface of the chip 05, it is convenient to realize the electrical connection between the redistribution layer 07 and the active surface of the chip 05 in the subsequent packaging process.

[0073] Figure 8 The following is a schematic diagram of the manufacturing process of a chip including through-silicon vias provided by an embodiment of the present disclosure. Please refer to Figure 2 and Figure 8 In an alternative embodiment provided by the present disclosure, the chip 05 includes a first through-silicon via 091, and the spacer 02 does not include a second through-silicon via 092. When the active surface of the chip 05 is in direct contact with the first adhesive layer 03, the recombination wafer 10 is encapsulated with an encapsulant 061 to form an encapsulation layer 06. The encapsulation layer 06 is located on the side of the chip 05 away from the first adhesive layer 03. The encapsulation layer 06 is ground and thinned until it is completely removed to reduce the warping of the chip 05 and expose the first through-silicon via 091 in the chip 05, facilitating the subsequent connection with the redistribution layer 07. After removing the carrier 01, optionally, the redistribution layer 07 and the ball grid array serving as the conductive bumps 08 are sequentially formed on the active surface of the chip 05; optionally, since the chip 05 includes the first through-silicon via 091, the redistribution layer 07 can be formed on both the active surface of the chip 05 and the surface opposite to the active surface. The redistribution layer 07 includes copper connection lines or traces. Forming the redistribution layer 07 on both sides of the chip 05 is beneficial to improving the selectivity of the electrical connection between various parts of the package. The conductive bumps 08 are formed on the redistribution layer 07 on the side of the active surface of the chip 05.

[0074] Figure 9 The following is a schematic diagram of the chip manufacturing process when the spacer includes through-silicon vias provided by an embodiment of the present disclosure. Please refer to Figure 3 and Figure 9In an optional embodiment provided by the present disclosure, the blocking sheet 02 includes a second through silicon via 092, and the chip 05 does not include a first through silicon via 091. When the active surface of the chip 05 is in direct contact with the first adhesive layer 03, the reconstructed silicon wafer 10 is sealed with a plastic sealing material 061 to form a plastic sealing layer 06. The plastic sealing layer 06 is located on the side of the chip 05 away from the first adhesive layer 03. The plastic sealing layer 06 is ground and thinned until it is completely removed to reduce the warping of the chip 05 and expose the second through silicon via 092 in the blocking sheet 02, which is convenient for subsequent connection with the redistribution layer 07. After removing the carrier 01, optionally, the active surface of the chip 05 forms a redistribution layer 07 and a ball grid array as a conductive bump 08 in sequence; optionally, since the blocking piece 02 includes a second through silicon via 092, the active surface of the chip 05 and the other side opposite to the active surface can form a redistribution layer 07, and the redistribution layer 07 includes copper connecting wires or routings. The redistribution layer 07 is formed on both sides of the chip 05, which is beneficial to improving the selectivity of the electrical connection between the various parts of the package. The conductive bumps 08 are formed on the redistribution layer 07 on one side of the active surface of the chip 05.

[0075] Figure 10 FIG. 1 is a schematic diagram of a manufacturing process when both a chip and a baffle plate provided by an embodiment of the present disclosure include through silicon vias. Please refer to FIG. Figure 4 and Figure 10 In an optional embodiment provided by the present disclosure, the chip 05 includes a first through silicon via 091, and the blocking piece 02 includes a second through silicon via 092. When the active surface of the chip 05 is in direct contact with the first adhesive layer 03, the reconstructed silicon wafer 10 is sealed with a plastic sealing material 061 to form a plastic sealing layer 06. The plastic sealing layer 06 is located on the side of the chip 05 away from the first adhesive layer 03. The plastic sealing layer 06 is ground and thinned until it is completely removed to reduce the warping of the chip 05, and the first through silicon via 091 in the chip 05 and the second through silicon via 092 in the blocking piece 02 can be exposed, so as to facilitate the subsequent connection between the through silicon via 09 and the redistribution layer 07. After removing the carrier 01, optionally, the active surface of the chip 05 forms a redistribution layer 07 and a ball grid array as a conductive bump 08 in sequence; optionally, since the chip 05 includes a first through silicon via 091 and the baffle 02 includes a second through silicon via 092, the active surface of the chip 05 and the other side opposite to the active surface can form a redistribution layer 07, and the redistribution layer 07 includes copper connecting wires or routings. The redistribution layer 07 is formed on both sides of the chip 05, which is beneficial to improving the selectivity of the electrical connection between the various parts of the package. The conductive bump 08 is formed on the redistribution layer 07 on one side of the active surface of the chip 05.

[0076] In this way, by mounting chip 05 in the case where a first through silicon via 091 exists on chip 05, a second through silicon via 092 exists on baffle 02, or both chip 05 and baffle 02 have through silicon via 09, various forms of packaging can be formed, which is beneficial to increase the types of fan-out structures of chip 05 and meet various different packaging requirements.

[0077] Optionally, the method for fabricating a chip further includes forming a redistribution layer 07 on a side of the chip 05 opposite to the active surface.

[0078] Specifically, referring to Figure 2 and Figure 8 , in an optional embodiment provided by the present disclosure, when the chip 05 includes a first through-silicon via 091, after encapsulating the recombined silicon wafer 10 with an encapsulant 061, grinding and thinning the encapsulation layer 06 until it is completely removed, removing the carrier 01, optionally, a redistribution layer 07 is formed on one side of the active surface of the chip 05; optionally, redistribution layers 07 are formed on both sides of the chip 05 along the first direction D1, and a ball grid array serving as a conductive bump 08 is further formed on the redistribution layer 07 on the side of the active surface of the chip 05. It should be noted that Figure 8 only the case where redistribution layers 07 are formed on both sides of the chip 05 along the first direction D1 is schematically shown. Those skilled in the art should understand that there is also a case where a redistribution layer 07 is formed only on one side of the active surface of the chip 05.

[0079] Referring to Figure 3 and Figure 9 , in another optional embodiment provided by the present disclosure, when the spacer 02 includes a second through-silicon via 092, after encapsulating the recombined silicon wafer 10 with an encapsulant 061, grinding and thinning the encapsulation layer 06 until it is completely removed, removing the carrier 01, optionally, a redistribution layer 07 is formed on one side of the active surface of the chip 05; optionally, redistribution layers 07 are formed on both sides of the chip 05 along the first direction D1, and a ball grid array serving as a conductive bump 08 is further formed on the redistribution layer 07 on the side of the active surface of the chip 05. It should be noted that Figure 9 only the case where redistribution layers 07 are formed on both sides of the chip 05 along the first direction D1 is schematically shown. Those skilled in the art should understand that there is also a case where a redistribution layer 07 is formed only on one side of the active surface of the chip 05.

[0080] Referring to Figure 4 and Figure 10 , in yet another optional embodiment provided by the present disclosure, when the chip 05 includes a first through-silicon via 091 and the spacer 02 includes a second through-silicon via 092, after encapsulating the recombined silicon wafer 10 with an encapsulant 061, grinding and thinning the encapsulation layer 06 until it is completely removed, removing the carrier 01, optionally, a redistribution layer 07 is formed on one side of the active surface of the chip 05; optionally, redistribution layers 07 are formed on both sides of the chip 05 along the first direction D1, and a ball grid array serving as a conductive bump 08 is further formed on the redistribution layer 07 on the side of the active surface of the chip 05. It should be noted that Figure 10Only the case where the redistribution layers 07 are formed on both sides of the chip 05 along the first direction D1 is schematically shown. Those skilled in the art should understand that there is also a case where the redistribution layer 07 is formed only on one side of the active surface of the chip 05.

[0081] Thus, in the case where the chip 05 or the spacer 02 includes the through-silicon vias 09, forming the redistribution layer 07 on at least one side of the chip 05 along the first direction D1 is beneficial to improving the selectivity of the electrical connection between the various parts of the packaging structure and meeting various different process requirements.

[0082] Figure 11 The following is a schematic structural diagram of a first adhesive layer provided by an embodiment of the present disclosure. Please refer to Figures 3 to 11 , optionally, the first adhesive layer 03 includes at least one of polyimide, polyacrylate, polyurethane, polyvinyl alcohol, and polyvinyl butyral.

[0083] Specifically, the first adhesive layer 03 includes a first sub-layer 031 and a second sub-layer 032. The first sub-layer 031 includes one or more of polyimide, polyacrylate, and polyurethane. The first sub-layer 031 is used to paste the chip 05 and can also be used as an etching barrier layer to prevent the carrier 01 from being etched through when the spacer 02 is etched to form the groove 04. The second sub-layer 032 includes one or more of polyvinyl alcohol, polyvinyl butyral, polyacrylate, and polyurethane. The second sub-layer 032 is used to bond the carrier 01 and can also be used for debonding. Optionally, the first adhesive layer 03 can be debonded by means such as laser, ultraviolet light irradiation, and thermal debonding to remove the carrier 01. The present disclosure does not limit the specific composition of the first adhesive layer 03, as long as it satisfies the functions of bonding, anti-etching, and debonding.

[0084] Please refer to Figures 1 to 11, in an alternative embodiment provided by the present disclosure, the thickness range of the spacer 02 after grinding and thinning is greater than or equal to 100 μm and less than or equal to 1000 μm. It should be noted that the thickness of the spacer 02 refers to the thickness of the original spacer along the first direction D1 after grinding and thinning, and this thickness is jointly determined by the material strength and the size of the reconstituted silicon wafer. Specifically, the thickness of the original spacer is in the range of 700 - 1000 μm. In the embodiment of the present disclosure, the spacer 02 is ground and thinned to a thickness range greater than or equal to 100 μm and less than or equal to 1000 μm through the existing process, which can thin the thickness of the spacer 02, facilitating the etching of grooves 04 that penetrate the spacer 02 and have a consistent depth, and facilitating the control of the height consistency of the active surface of the chip 05 after the chip 05 is mounted in the grooves 04. Optionally, the thickness range of the spacer 02 after grinding and thinning is greater than or equal to 100 μm and less than or equal to 500 μm; or, the thickness range of the spacer 02 after grinding and thinning is greater than or equal to 300 μm and less than or equal to 600 μm; or, the thickness range of the spacer 02 after grinding and thinning is greater than or equal to 400 μm and less than or equal to 700 μm; or, the thickness range of the spacer 02 after grinding and thinning is greater than or equal to 500 μm and less than or equal to 800 μm; or, the thickness range of the spacer 02 after grinding and thinning is greater than or equal to 600 μm and less than or equal to 900 μm; or, the thickness range of the spacer 02 after grinding and thinning is greater than or equal to 700 μm and less than or equal to 1000 μm... and so on. Without listing them all here, as long as the thickness of the spacer 02 after grinding and thinning is in the range greater than or equal to 100 μm and less than or equal to 1000 μm, in this way, the spacer 02 after grinding and thinning is conducive to etching grooves 04 with a consistent depth, conducive to the height consistency of the chip 05 adhered inside the grooves 04, and thus conducive to improving the flatness of the chip 05 packaging; in addition, grinding and thinning is an existing process in the chip 05 packaging process. In this embodiment, grinding and thinning the spacer 02 does not require adding a new process and will not increase the process cost.

[0085] Please refer to Figure 1 , in an alternative embodiment provided by the present disclosure, the thickness H2 of the encapsulation layer 06 after grinding and thinning is less than or equal to 60 μm. The thickness H2 of the encapsulation layer 06 after grinding and thinning refers to the maximum thickness of the encapsulation layer 06 along the first direction D1. Specifically, please refer to Figure 6, when the active surface of the chip 05 faces downward for packaging, potting is performed on the side of the reconstructed silicon wafer 10 away from the carrier 01. The potting layer 06 covers the reconstructed silicon wafer 10, and then the potting layer 06 is ground and thinned. During the potting process, the thickness of the original potting layer is greater than 40 μm, and the overall thickness of the reconstructed silicon wafer 10 and the potting layer 06 is less than 1200 μm. After potting, the reconstructed silicon wafer is subjected to a grinding process. Optionally, the thickness H2 of the potting layer 06 after grinding and thinning is greater than or equal to 10 μm and less than or equal to 20 μm, or the thickness H2 of the potting layer 06 after grinding and thinning is greater than or equal to 15 μm and less than or equal to 25 μm, or the thickness H2 of the potting layer 06 after grinding and thinning is greater than or equal to 20 μm and less than or equal to 30 μm, or the thickness H2 of the potting layer 06 after grinding and thinning is greater than or equal to 25 μm and less than or equal to 35 μm, or the thickness H2 of the potting layer 06 after grinding and thinning is greater than or equal to 30 μm and less than or equal to 40 μm, or the thickness H2 of the potting layer 06 after grinding and thinning is greater than or equal to 40 μm and less than or equal to 60 μm, or the thickness H2 of the potting layer 06 after grinding and thinning is 0 μm... and so on. Without listing them all here, it only needs to satisfy that the thickness H2 of the potting layer 06 after grinding and thinning is less than or equal to 60 μm. In this way, by grinding and thinning the potting layer 06, the thickness H2 of the potting layer 06 can be reduced, and on the basis of the reduction of the thickness H2 of the potting layer 06, the warping caused by the different coefficients of thermal expansion between the potting layer 06 and the chip 05 can be reduced, which is beneficial to the flatness of the chip 05 packaging structure.

[0086] In another alternative embodiment provided by the present disclosure, please refer to Figure 7 , when the active surface of the chip 05 faces upward for packaging, the potting layer 06 covers the copper pillars on the active surface of the chip 05, and the potting layer 06 is ground and thinned until the copper pillars 051 are exposed. The thickness H2 of the potting layer 06 after grinding and thinning is greater than or equal to 0 μm and less than or equal to 60 μm. Specific thickness values are not listed here one by one, and it only needs to be within this range.

[0087] In yet another alternative embodiment provided by the present disclosure, please refer to Figures 2 - 4 , Figures 8 - 10 , when the active surface of the chip 05 faces downward for packaging, the chip 05 and / or the spacer 02 include through-silicon vias 09, and redistribution layers 07 are provided on both sides of the chip 05 along the first direction D1, it is necessary to grind and thin the potting layer 06 until it is completely removed, that is, the thickness H2 of the potting layer 06 is 0 μm, which is convenient for the connection between the through-silicon vias 09 and the redistribution layers 07, and will not be elaborated here.

[0088] In summary, for a chip fan-out package structure and a chip manufacturing method provided by the present disclosure, a spacer is used as the substrate of the fan-out structure. Grooves with a consistent depth are etched on the ground and thinned spacer, and the chip is embedded in the grooves. Then, the encapsulation layers on the chip and the spacer are ground and thinned to reduce warping without adding new processes. The first adhesive layer has the dual functions of pasting and preventing etching penetration and can be removed by ultraviolet light or other means. A redistribution layer is formed on at least one side of the chip in the first direction, and conductive bumps are formed on the redistribution layer on the active surface side of the chip, enabling fan-out on the side of the chip opposite to the active surface and meeting the diverse requirements of users for chip package forms. At least one of the chip and the spacer includes a through-silicon via. A redistribution layer can be formed on at least one side of the chip in the first direction, and conductive bumps are formed on the redistribution layer on the active surface side of the chip, expanding the fan-out form of the chip and meeting the diverse requirements of users for chip package forms. By increasing the proportion of the spacer, the present disclosure effectively reduces the proportion of the encapsulation material and increases the silicon proportion, thus significantly reducing the influence of thermal expansion and contraction on the chip position. By reducing the thickness of the encapsulation layer, the thickness of the filled silicon wafer is much greater than the remaining thickness of the encapsulation layer, thereby reducing the influence of the thermal expansion and contraction of the encapsulation material on the overall warping of the reconstituted silicon wafer and the change in the distance between chips. By restricting the part of the encapsulation material that affects the distance between chips within the frame of the spacer, the movement area of the encapsulation material is restricted, which helps to disperse the cumulative effect of the thermal expansion and contraction of the encapsulation material and further improves the control accuracy of the chip pitch.

[0089] The above are only specific embodiments of the present disclosure, enabling those skilled in the art to understand or implement the present disclosure. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to these embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip fan-out packaging structure, characterized in that: The reconstructed silicon wafer comprises a baffle and a chip, wherein the baffle comprises grooves arranged in an array, the grooves penetrate the baffle, the chip is located in the grooves, and the plane of the chip is parallel to the baffle; The packaging structure further includes a plastic sealing layer and a redistribution layer. Along a first direction, the plastic sealing layer is located at least on one side of the reconstructed silicon chip. The plastic sealing layer includes a plastic sealing material. Along a second direction, the plastic sealing material fills the gap between the chip and the groove. The first direction is perpendicular to the baffle, and the second direction is parallel to the baffle. Along the first direction, the redistribution layer is located on at least one side of the reconstructed silicon chip; the chip includes an active surface, and the redistribution layer located on one side of the chip active surface also includes a ball grid array as a conductive bump.

2. The chip fan-out packaging structure according to claim 1, characterized in that: The chip includes a first through silicon via, which is perpendicular to the plane of the chip and electrically connected to the redistribution layer; and / or the blocking plate includes a second through silicon via, which is perpendicular to the plane of the blocking plate and electrically connected to the redistribution layer.

3. The chip fan-out packaging structure according to claim 1, characterized in that: The thickness of the reconstructed silicon wafer is greater than or equal to 100 μm and less than or equal to 1200 μm; the thickness of the plastic encapsulation layer is less than or equal to 60 μm.

4. A chip manufacturing method, characterized in that: Used to manufacture the chip fan-out packaging structure according to any one of claims 1 to 3, comprising: Taking a carrier plate, forming a first adhesive layer on one side of the carrier plate; Laminating a blocking sheet on the first adhesive layer, grinding, thinning and etching the blocking sheet to form a groove; Mounting a chip in the groove, wherein the chip is directly bonded to the first adhesive layer; the chip and the baffle constitute a reconstructed silicon wafer; Using a plastic sealing material to plastic seal the reconstructed silicon wafer to form a plastic sealing layer, and grinding and thinning the plastic sealing layer; removing the carrier plate; Forming a redistribution layer at least on one side of the active surface of the chip by coating, developing, exposing, and electroplating, and forming a ball grid array as a conductive bump on the redistribution layer on the active surface of the chip; A plurality of embedded chip fan-out packages are formed by cutting.

5. The chip manufacturing method according to claim 4, characterized in that: The chip is directly bonded to the first adhesive layer as follows: The chip comprises an active surface, and the active surface of the chip is directly bonded to the first adhesive layer, or a surface of the chip opposite to the active surface is directly bonded to the first adhesive layer.

6. The chip manufacturing method according to claim 5, characterized in that: The active surface of the chip faces away from the first adhesive layer, and the active surface of the chip includes copper pillars; After the side of the chip opposite to the active surface is directly bonded to the first adhesive layer, the reconstructed silicon wafer is encapsulated with a plastic encapsulation material. After the plastic encapsulation layer is formed, the plastic encapsulation layer is ground and thinned, specifically, the plastic encapsulation layer is thinned until the copper pillar is exposed on the surface of the plastic encapsulation layer.

7. The chip manufacturing method according to claim 4, characterized in that: The method also includes forming a redistribution layer on a side of the chip opposite to the active side.

8. The chip manufacturing method according to claim 4, characterized in that: The first adhesive layer includes at least one of polyimide, polyacrylate, polyurethane, polyvinyl alcohol, and polyvinyl butyral.

9. The chip manufacturing method according to claim 4, characterized in that: The thickness of the baffle after grinding and thinning is greater than or equal to 100 μm and less than or equal to 1000 μm.

10. The chip manufacturing method according to claim 4, characterized in that: The thickness of the plastic sealing layer after grinding and thinning is less than or equal to 60 μm.

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