Self-adaptive biasing circuit and self-adaptive biasing method of radio frequency low-noise amplifier

Abstract

The invention relates to the field of radio frequency microwaves, in particular to a self-adaptive biasing circuit and a self-adaptive biasing method of a radio frequency low-noise amplifier. The circuit comprises a first power supply unit, a second power supply unit, a first transistor, a second transistor, a third transistor and a first impedance element, the first power supply unit, the first impedance element, the first transistor and the second transistor are connected in sequence; the first transistor is connected with the first power supply unit; the third transistor is connected with the first impedance element at the same time; and the second transistor is connected with the second power supply unit. According to the invention, the linearity of the radio frequency low-noise amplifier during large signal input work is improved from the perspective of the self-adaptive bias circuit structure, and the rollback phenomenon of output power is slowed down.

Description

Technical Field

[0001] This application relates to the field of radio frequency and microwave, and in particular, to an adaptive bias circuit and an adaptive bias method for a radio frequency low-noise amplifier. Background Art

[0002] In the field of microwave / millimeter-wave devices, the technological innovation based on group III-V compound semiconductors has continuously promoted the performance breakthrough of radio frequency front-ends. Gallium arsenide (GaAs) material, with its excellent semi-insulating property (resistivity > 10 7 Ω · cm), has become the preferred substrate material for microwave integrated circuits. Compared with silicon-based processes, GaAs devices show significant advantages in key indicators such as cut-off frequency (f_T > 100 GHz), power density (> 1 W / mm), and noise figure (NF < 0.5 dB), which is mainly due to its high electron mobility (μ_e ≈ 8000 cm 2 / (V·s)) and breakdown field strength ( ～ 4×10 5 V / cm) characteristics.

[0003] Pseudomorphic high electron mobility transistor (pHEMT) realizes two-dimensional electron gas (2DEG) transport through the AlGaAs / InGaAs heterojunction structure, and its carrier mobility can reach 2-3 times that of traditional MESFETs. Based on this, enhanced pHEMT (E-pHEMT) has made breakthroughs in the threshold voltage temperature coefficient and transconductance linearity (g_m change rate < 5% / V), supports single power supply (+3V to +5V), and can achieve excellent performance with a noise figure < 1 dB in the Ka band (26.5 - 40 GHz). This makes E-pHEMT the core device for high-end applications such as 5G millimeter-wave base stations and satellite communication receivers.

[0004] For the design of low-noise amplifiers (LNAs), the temperature stability and dynamic response characteristics of the bias circuit directly affect the overall performance of the system. The existing technologies mainly adopt the following two types of solutions:

[0005] (1) Passive bias architecture: Establish a static operating point through a resistor voltage division network, but there are two inherent defects: ① significant temperature drift (typical temperature coefficient reaches +0.3% / °C), resulting in a > 20% fluctuation in the drain current I_ds as the temperature rises; ② the voltage division resistors introduce additional noise (ΔNF ≈ 0.2 - 0.5 dB), deteriorating the system sensitivity;

[0006] (2) Current mirror active bias architecture: Such as Figure 1As shown, M1-M2 constitutes a current mirror structure, which can theoretically achieve temperature compensation of I_ds2 = (W2 / W1) · I_ds1. However, under actual large signal conditions, this architecture exposes three key problems: ① After the RF signal is rectified by the gate-source diode (V_bi≈0.7V), a DC offset ΔV_gs (typical value -50mV / dBm) inversely proportional to the input power is generated, resulting in a transconductance g_m drop of >30%; ② The dynamic impedance matching deteriorates. When the input power exceeds -10dBm, the S11 parameter deteriorates by >3dB; ③ The temperature compensation mechanism fails. In the range of -40℃ to +85℃, I_ds2 still produces a fluctuation of ±15%.

[0007] Experimental data shows (Figure 4) that the third-order intermodulation point (IIP3) of the traditional current mirror structure will drop by >3dB when the input power is >0dBm in the 2.4GHz frequency band, which seriously restricts the dynamic range of the system. This is mainly due to: ① static operating point drift caused by gate rectification effect; ② transconductance nonlinear distortion caused by hot carrier injection; ③ mirror current mismatch caused by process parameter discreteness (typical mismatch ±8%). Therefore, how to maintain stable bias characteristics under wide temperature range (-55℃ to +125℃) and large dynamic input (-20 to +15dBm) conditions has become a technical bottleneck that needs to be solved in millimeter-wave LNA design. Summary of the invention

[0008] The present invention provides an adaptive bias circuit and adaptive bias method for a radio frequency low noise amplifier, especially for the large dynamic input (-30dBm to +10dBm) scenario in the millimeter wave frequency band (24-44GHz). It is used to solve the problem that the bias circuit current is unstable when the input signal power becomes larger, and to ensure the linearity of the low noise amplifier when working with a larger signal input.

[0009] An adaptive bias circuit for a radio frequency low noise amplifier, the circuit at least comprising: a first power supply unit (Vbias), a second power supply unit (Vcc), a first transistor (M1), a second transistor (M2), a third transistor (M3) and a first impedance element (R1); wherein the drain of the first transistor (M1) is connected to the first power supply unit (Vbias), the gate is connected to the first power supply unit (Vbias) through the first impedance element (R1), the source of the first transistor (M1) and the gate of the second transistor (M2) form a bias control node (N1), the drain of the second transistor (M2) is connected to the second power supply unit (Vcc), the drain and gate of the third transistor (M3) are connected to one end of the first impedance element (R1), and the source of the second transistor (M2) forms a grounding point.

[0010] In some embodiments, the adaptive bias circuit further includes a fourth transistor (M4), whose gate and drain are connected to the source of the third transistor (M3), and the source of the fourth transistor (M4) forms a ground point.

[0011] In some embodiments, the adaptive bias circuit further includes a second impedance element (R2), whose first end is connected to the source of the first transistor (M1), and the second end is connected to the gate of the second transistor (M2), forming a gate bias feedback path.

[0012] In some embodiments, the adaptive bias circuit further includes a third impedance element (R3), which is connected across the first impedance element (R1) and the gate of the first transistor (M1) to form a gate voltage regulation network.

[0013] In some embodiments, the adaptive bias circuit further includes a blocking capacitor (C1), whose first end is connected to the RF signal input terminal (RFin), and the second end is connected to the gate of the second transistor (M2) to achieve AC signal coupling and DC isolation.

[0014] In some embodiments, the first to fourth transistors (M1 - M4) all adopt enhancement-mode GaAs-based pseudomorphic high electron mobility transistors (E-pHEMT).

[0015] In some embodiments, the adaptive bias circuit further includes a fifth transistor (M5), whose gate is connected to the third power supply unit (VB), the drain is connected to the second power supply unit (Vcc) through a first inductance element (L1), and the source is connected to the drain of the second transistor (M2) to form a dynamic current compensation branch.

[0016] The present invention also provides an adaptive biasing method for a radio frequency low-noise amplifier.

[0017] An adaptive biasing method for a radio frequency low-noise amplifier, which adopts an adaptive bias circuit of a radio frequency low-noise amplifier, the method includes the following steps: establishing a temperature-sensitive reference voltage through the parallel structure of the first transistor (M1) and the third transistor (M3); dynamically associating the gate bias of the RF amplifying transistor (M2) with the reference voltage by using the second impedance element (R2); when the input RF signal power increases, reducing its equivalent bias voltage through the rectification effect of the gate-source junction of M1; isolating the interference of the RF signal to the reference voltage node through the third impedance element (R3); compensating for the bias drift caused by the ambient temperature change by means of the negative temperature coefficient characteristic of the fourth transistor (M4).

[0018] Compared with the prior art, the present invention has the following advantages:

[0019] Compared with the traditional active bias circuit, the present invention utilizes the gate-drain PN junction diode of the GaAs-based pHEMT transistor to implement rectification for compensation in an adaptive bias technology. The third resistor R3 in the circuit can isolate the RF signal leaked from the first transistor M1. Even when the input power of the signal input terminal RFin increases, it can provide a stable DC voltage bias for the gate of the first transistor M1. When the input power of the signal input terminal RFin increases, the gate voltage of the first transistor M1 remains stable. The voltage VGS1 after rectification by the gate-drain PN junction diode of the first transistor M1 decreases, compensating for the gate voltage of the second transistor M2 and ensuring the linearity of the low-noise amplifier when operating with a large signal input. Description of the Drawings

[0020] Figure 1 is the current mirror active bias circuit in the prior art;

[0021] Figure 2 is the adaptive bias circuit of the RF low-noise amplifier provided by a specific embodiment of the present invention;

[0022] Figure 3 is the adaptive bias circuit of the RF low-noise amplifier provided by another specific embodiment of the present invention;

[0023] Figure 4A is the comparison diagram of the gate voltages of the current mirror active bias circuit in the prior art and the adaptive bias circuit of the present invention;

[0024] Figure 4B is the comparison diagram of the DC currents of the current mirror active bias circuit in the prior art and the adaptive bias circuit of the present invention;

[0025] Figure 4C is the comparison diagram of the output powers of the current mirror active bias circuit in the prior art and the adaptive bias circuit of the present invention. Detailed Embodiments

[0026] To make the above objects, features, and advantages of the present application more obvious and understandable, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0027] Generally speaking, the present invention discloses an adaptive bias circuit for an RF low-noise amplifier. In one embodiment, as Figure 2 shown, the circuit includes:

[0028] A power supply module, including a first power supply unit Vbias and a second power supply unit Vcc. The first power supply unit Vbias is a bias power supply, and the voltage is preferably +2.5V ± 5%. The second power supply unit Vcc is the main power supply, and the voltage is preferably +5V ± 5%;

[0029] The core transistor array includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. Preferably, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all enhanced GaAs-based pseudomorphic high electron mobility transistors (E-pHEMTs). Preferably, the threshold voltages V_th of M1 - M4 are +0.3V ± 5%, and the gate widths are configured as follows: M1(4×50μm), M2(12×50μm), M3(6×50μm), M4(8×50μm);

[0030] The compensation network includes a first impedance element R1, a second impedance element R2, a third impedance element R3, a second transistor M1, a third transistor M3, and a fourth transistor M4;

[0031] The first power supply unit Vbias, the first impedance element R1, the first transistor M1, and the second transistor M2 are connected in sequence; the first transistor M1 is connected to the first power supply unit Vbias; the third transistor M3 is simultaneously connected to the first impedance element R1; the second transistor M2 is connected to the second power supply unit Vcc; the second impedance element R2 is simultaneously connected to the first transistor M1 and the second transistor M2; the third impedance element R3 is simultaneously connected to the first transistor M1 and the third transistor M3; the fourth transistor M4 is connected to the third transistor M3.

[0032] The first end of the first impedance element R1 is simultaneously connected to the first power supply unit Vbias and the drain of the first transistor M1, and its second end is simultaneously connected to the drain of the third transistor M3, the gate of the third transistor M3, and the gate of the first transistor M1; the drain of the second transistor M2 is connected to the second power supply unit Vcc, its gate is connected to the source of the first transistor M1, and its source forms a ground point.

[0033] The first end of the second impedance element R2 is connected to the source of the first transistor M1, and its second end is connected to the gate of the second transistor M2. Between them is a bias control node N1, forming a gate bias feedback path. Preferably, the resistance value of R2 satisfies the relational expression:

[0034] R2 = (Vgs2 - Vth) / (α·I_ds1)

[0035] where α = 0.8 - 1.2 is a process correction coefficient, and Vth = +0.3V ± 5% is the transistor threshold voltage.

[0036] The first end of the third impedance element R3 is connected to the second end of the first impedance element R1, and the second end of the third impedance element R3 is connected to the gate of the first transistor M1, forming a gate voltage regulation network.

[0037] The first end of the DC-blocking capacitor C1 is connected to the RF signal input terminal RFin, and the second end is connected to the gate of the second transistor M2, realizing AC signal coupling and DC isolation.

[0038] Among them, the third transistor M3 and the fourth transistor M4 provide appropriate operating voltages for the first transistor M1 and the second transistor M2. The first impedance element R1 adjusts the quiescent operating point of the circuit, the second impedance element R2 adjusts the magnitude of the power of the input bias RF signal, and the DC-blocking capacitor C1 functions as RF DC blocking.

[0039] Preferably, a relatively large third impedance element R3 can be selected for the bias circuit. For example, 150Ω ± 5%; R3 isolates the RF signal leaked from the first transistor M1. The third transistor M3 and the fourth transistor M4 are connected in a diode configuration. Even when the input power at the signal input terminal RFin increases, a stable DC voltage bias can be provided to the gate of the first transistor M1. When the input power at the signal input terminal RFin port increases, the voltage VGS1 rectified by the gate-source PN junction diode of the first transistor M1 decreases, and the gate voltage of the first transistor M1 remains stable, compensating for the gate voltage of the second transistor M2. At the same time, in order to more effectively compensate for the gate voltage of the second transistor M2, the resistance value of the second impedance element R2 can be adjusted to make the magnitude of the RF signal coupled to the bias circuit just right.

[0040] In the small-signal state, for example, P_in ≤ -20dBm, M1 - M2 form a current mirror (I_ds2 = 3I_ds1), and R2 provides DC feedback to stabilize V_gs2 at 0.4V; the M3 - M4 diode group presents a high impedance (>10kΩ) under zero bias, and the compensation network is not activated.

[0041] In the large-signal state, for example, P_in ≥ -10dBm, the RFin signal is coupled to the gate of M2 through C1. Its positive half-cycle turns on the gate-drain diode of M1, generating a compensation current ΔI = β·(V_rf - V_d)^2 / R3 (β = 0.05A / V2); ΔI forms a compensation voltage ΔV_comp = ΔI·R1 on R1, reducing V_gs1 by ΔV_comp and maintaining I_ds2 constant; when M4 has a negative threshold voltage drift with increasing temperature (ΔT > 10℃), it is offset by the positive temperature coefficient (+0.8mV / ℃) of M3, achieving ΔV_gs / ΔT < 0.1mV / ℃.

[0042] In one embodiment, as Figure 3As shown in the figure, on the basis of Embodiment 1, a fifth transistor M5, a fourth impedance element R4, and a third power supply unit VB are added. The gate of the fifth transistor M5 is connected to the third power supply unit VB, its drain is connected to the first end of the fourth impedance element R4, and its source is connected to the drain of the second transistor M2; the second end of the fourth impedance element R4 is connected to the second power supply unit Vcc.

[0043] Preferably, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 all adopt enhancement-mode GaAs-based pseudomorphic high electron mobility transistors (E-pHEMTs).

[0044] M5 (W = 6×50μm) and R4 (200Ω ± 5%) form an active load, and its gate bias V_B is programmable (1.8 - 3.3V) to achieve dynamic matching of the output impedance Z_out (adjustable from 45 - 65Ω);

[0045] By adjusting V_B to make M5 operate in class AB state (θ = 110° - 130°), the OIP3 is increased by ≥5dB at the 28GHz frequency point.

[0046] The present invention also provides an adaptive biasing method for a radio frequency low noise amplifier.

[0047] An adaptive method for a radio frequency low noise amplifier, using an adaptive biasing circuit for a radio frequency low noise amplifier, the method includes the following steps: establishing a temperature-sensitive reference voltage through the parallel structure of the first transistor (M1) and the third transistor (M3); dynamically associating the gate bias of the radio frequency amplifying transistor (M2) with the reference voltage by using the second impedance element (R2); when the input radio frequency signal power increases, reducing its equivalent bias voltage through the rectification effect of the gate-source junction of M1; isolating the interference of the radio frequency signal to the reference voltage node through the third impedance element (R3); compensating for the bias drift caused by the environmental temperature change by means of the negative temperature coefficient characteristic of the fourth transistor (M4).

[0048] As Figure 4A 、 Figure 4B 、 Figure 4C As shown by the test curves of

[0049] It should be noted that the above embodiments are all preferred embodiments, and the relevant functional components can be replaced by other components. The units and modules involved are not necessarily essential to this application. Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is the difference from other embodiments. For the same and similar parts between the embodiments, reference can be made to each other.

[0050] The above has introduced in detail an adaptive bias circuit and an adaptive bias method for a radio frequency low noise amplifier provided by this application. Specific examples are used in this article to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application; at the same time, for those of ordinary skill in the art, according to the idea of this application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. An adaptive bias circuit for a radio frequency low noise amplifier, characterized in that: The circuit comprises: a first power supply unit (Vbias), a second power supply unit (Vcc), a first transistor (M1), a second transistor (M2), a third transistor (M3) and a first impedance element (R1); wherein the drain of the first transistor (M1) is connected to the first power supply unit (Vbias), the gate is connected to the first power supply unit (Vbias) through the first impedance element (R1), the source of the first transistor (M1) and the gate of the second transistor (M2) form a bias control node (N1), the drain of the second transistor (M2) is connected to the second power supply unit (Vcc), the drain and gate of the third transistor (M3) are connected to one end of the first impedance element (R1), and the source of the second transistor (M2) forms a grounding point.

2. The adaptive bias circuit according to claim 1, characterized in that: The invention also comprises a fourth transistor (M4), whose gate and drain are connected to the source of the third transistor (M3), and the source of the fourth transistor (M4) forms a grounding point.

3. The adaptive bias circuit of a radio frequency low noise amplifier according to claim 2, characterized in that: It also includes a second impedance element (R2), a first end of which is connected to the source of the first transistor (M1), and a second end of which is connected to the gate of the second transistor (M2), forming a gate bias feedback path.

4. The adaptive bias circuit according to claim 3, characterized in that: It further includes a third impedance element (R3) connected between the first impedance element (R1) and the gate of the first transistor (M1) to form a gate voltage regulation network.

5. The adaptive bias circuit according to claim 1, wherein: It also includes a DC isolation capacitor (C1), a first end of which is connected to the radio frequency signal input end (RFin), and a second end of which is connected to the gate of the second transistor (M2), so as to achieve AC signal coupling and DC isolation.

6. The adaptive bias circuit according to claim 2, wherein: The first to fourth transistors (M1-M4) are all enhanced-mode GaAs-based pseudo-modulated high electron mobility transistors (E-pHEMT).

7. The adaptive bias circuit according to claim 1, wherein: Also includes: The fifth transistor (M5) has a gate connected to the third power supply unit (VB), a drain connected to the second power supply unit (Vcc) via the first inductor L1, and a source connected to the drain of the second transistor (M2), forming a dynamic current compensation branch.

8. An adaptive bias method for a radio frequency low noise amplifier, implemented based on the circuit according to any one of claims 1 to 7, characterized in that: The following steps are involved: A temperature-sensitive reference voltage is established through a parallel structure of a first transistor (M1) and a third transistor (M3); a gate bias of a radio frequency amplifier tube (M2) is dynamically associated with the reference voltage using a second impedance element (R2); when the input radio frequency signal power increases, the equivalent bias voltage is reduced through the rectification effect of the gate-source junction of M1; interference of the radio frequency signal on the reference voltage node is isolated through the third impedance element (R3); and a bias drift caused by changes in ambient temperature is compensated by means of the negative temperature coefficient characteristic of a fourth transistor (M4).

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