Digital phase interpolator

Abstract

The invention discloses a digital phase interpolator. The digital phase interpolator comprises a first phase interpolation unit, a second phase interpolation unit, a first auxiliary interpolation unit, a second auxiliary interpolation unit and a buffer unit. The first auxiliary interpolation unit and the first phase interpolation unit are connected in parallel between the first input signal and the input end of the buffer unit. The second auxiliary interpolation unit and the second phase interpolation unit are connected in parallel between the second input signal and the input end of the buffer unit, and a preset phase difference exists between the first input signal and the second input signal. And the output end of the buffer unit is the output end of the digital phase interpolator. Wherein each of the first phase interpolation unit and the second phase interpolation unit comprises N basic interpolation units which are connected in parallel, the weight of each of the first auxiliary interpolation unit and the second auxiliary interpolation unit is 1 / 2 of the weight of each basic interpolation unit, and N is an integer greater than 1. The digital phase interpolator can greatly reduce power consumption and area.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, and particularly to a digital phase interpolator. Background Art

[0002] The phase adjustment of a signal is usually achieved by phase interpolation (PI). A traditional N-bit (N>1) digital phase interpolator generally performs interpolation in a way that N basic interpolation units are directly connected. Its principle is mainly to change the weight of the input clock so as to achieve the purpose of changing the output phase. In scenarios where high-precision digital phase interpolation is required, as the interpolation bit number increases, the number of required basic interpolation units will increase exponentially, resulting in an exponential increase in the power consumption and area of the phase interpolator.

[0003] Figure 1 is a circuit schematic diagram of a traditional 16-bit digital phase interpolator. Among them, the first input signal In_a and the second input signal In_b are respectively connected to 16 parallel basic interpolation units. Each basic interpolation unit includes an inverter and a switch connected in series with the inverter. The closing and turning off of each switch are controlled by a one-bit control code.

[0004] Figure 2 shows Figure 1 the interpolation result (Out) output by the traditional 16-bit digital phase interpolator of Figure 1 It can be seen that in the traditional 16-bit digital phase interpolator, a total of 32 basic interpolation units are required for the input signals In_a and In_b. Therefore, the circuit has high power consumption and large occupied area.

[0005] Therefore, it is necessary to further improve the existing digital phase interpolator. Summary of the Invention

[0006] The purpose of this application is to provide a digital phase interpolator to significantly reduce the power consumption and area of the digital phase interpolator.

[0007] An embodiment of this application discloses a digital phase interpolator, including:

[0008] a first phase interpolation unit, a second phase interpolation unit, a first auxiliary interpolation unit, a second auxiliary interpolation unit, and a buffer unit;

[0009] The first auxiliary interpolation unit is connected in parallel with the first phase interpolation unit between the first input signal and the input end of the buffer unit;

[0010] The second auxiliary interpolation unit and the second phase interpolation unit are connected in parallel between the second input signal and the input end of the buffer unit, and there is a preset phase difference between the first input signal and the second input signal;

[0011] The output end of the buffer unit is the output end of the digital phase interpolator;

[0012] Wherein, both the first phase interpolation unit and the second phase interpolation unit include N basic interpolation units connected in parallel, and the weights of both the first auxiliary interpolation unit and the second auxiliary interpolation unit are 1 / 2 of the weights of the basic interpolation units, where N is an integer greater than 1.

[0013] In another preferred example, the first auxiliary interpolation unit and the second auxiliary interpolation unit are controlled by the same control signal, so that the first auxiliary interpolation unit and the second auxiliary interpolation unit are turned on or off simultaneously.

[0014] In another preferred example, the basic interpolation unit includes a first inverter.

[0015] In another preferred example, the basic interpolation unit further includes a first switch, and the first inverter is connected in series with the first switch.

[0016] In another preferred example, both the first auxiliary interpolation unit and the second auxiliary interpolation unit include a second inverter.

[0017] In another preferred example, the first auxiliary interpolation unit and the second auxiliary interpolation unit further include a second switch, and the second inverter is connected in series with the second switch.

[0018] In another preferred example, the buffer unit includes a third inverter.

[0019] In another preferred example, the first phase interpolation unit is controlled by a first control signal, the second phase interpolation unit is controlled by a second control signal, and the second control signal is the inverted signal of the first control signal.

[0020] In another preferred example, both the first control signal and the second control signal are N-bit thermometer codes.

[0021] In another preferred example, the first control signal and the second control signal are translated by a decoding unit according to the binary code input to the digital phase interpolator.

[0022] In another preferred example, the decoding unit translates the binary code into two N-bit thermometer codes pe and po, selects one thermometer code from the two N-bit thermometer codes pe and po as the first control signal according to the least significant bit of the binary code, and uses the complement code of the selected thermometer code as the second control signal; where pe = po + 1.

[0023] In another preferred example, both the first auxiliary interpolation unit and the second auxiliary interpolation unit are controlled by the least significant bit of the binary code.

[0024] Compared with the prior art, the main differences and effects of the embodiments of the present invention are as follows:

[0025] A digital phase interpolator disclosed in the present application can perform 2×N-bit interpolation on two input signals with a preset phase difference to form a 2N-bit digital phase interpolator by connecting an auxiliary interpolation unit in parallel on each side of a traditional N-bit digital phase interpolator. Compared with the traditional 2×N-bit digital phase interpolator, the power consumption and area are significantly reduced, and the load at the signal input end is also lower.

[0026] A large number of technical features are recorded in the specification of the present application, distributed in various technical solutions. If all possible combinations of technical features (i.e., technical solutions) of the present application are listed, the specification will be too long. To avoid this problem, each technical feature disclosed in the above-mentioned invention content of the present application, each technical feature disclosed in the following embodiments and examples, and each technical feature disclosed in the drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, features A+B+C are disclosed, and in another example, features A+B+D+E are disclosed. Features C and D are equivalent technical means that play the same role and only one of them can be used technically and they cannot be used simultaneously. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been recorded because it is technically infeasible, while the solution of A+B+C+E should be regarded as having been recorded. Description of the Drawings

[0027] Figure 1 is a circuit schematic diagram of a traditional 16-bit digital phase interpolator;

[0028] Figure 2 is a schematic diagram of the interpolation result output by a traditional 16-bit digital phase interpolator;

[0029] Figure 3 is a circuit schematic diagram of a digital phase interpolator according to an embodiment of the present application;

[0030] Figure 4 It is a circuit schematic diagram of a 16-bit digital phase interpolator according to an embodiment of the present application. Specific implementation manners

[0031] In the following description, many technical details are presented for the reader to better understand the present application. However, those of ordinary skill in the art can understand that even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in each claim of the present application can be implemented.

[0032] To make the objectives, technical solutions, and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0033] An embodiment of the present application relates to a digital phase interpolator. Figure 3 It is a circuit schematic diagram of the digital phase interpolator.

[0034] Specifically, as Figure 3 shown, the digital phase interpolator includes: a first phase interpolation unit, a second phase interpolation unit, a first auxiliary interpolation unit, a second auxiliary interpolation unit, and a buffer unit. The input end of the first phase interpolation unit is used to receive a first input signal In_a, and the output end of the first phase interpolation unit is connected to the input end of the buffer unit. The input end of the second phase interpolation unit is used to receive a second input signal In_b, and the output end of the second phase interpolation unit is connected to the input end of the buffer unit; wherein, there is a preset phase difference between the first input signal In_a and the second input signal In_b. The first auxiliary interpolation unit is connected in parallel with the first phase interpolation unit. The second auxiliary interpolation unit is connected in parallel with the second phase interpolation unit. The output end of the buffer unit is the output end out of the digital phase interpolator. Wherein, the first phase interpolation unit and the second phase interpolation unit have the same structure, and both include N basic interpolation units connected in parallel, where N is an integer greater than 1. The first auxiliary interpolation unit and the second auxiliary interpolation unit have the same structure, and the weights of the first auxiliary interpolation unit and the second auxiliary interpolation unit can be equal. For example, they are both 1 / 2 of the weight of the basic interpolation unit.

[0035] In some embodiments, the first auxiliary interpolation unit and the second auxiliary interpolation unit are controlled by the same control signal, so that the first auxiliary interpolation unit and the second auxiliary interpolation unit are turned on or off simultaneously.

[0036] In some embodiments, each basic interpolation unit may include a first inverter, and the access and disconnection of the basic interpolation unit can be controlled by controlling the conduction and disconnection of the first inverter. In some other embodiments, each basic interpolation unit may include a first inverter and a first switch, the first inverter and the first switch are connected in series, and the access and disconnection of the basic interpolation unit can be controlled by controlling the closing and disconnection of the first switch.

[0037] In some embodiments, both the first auxiliary interpolation unit and the second auxiliary interpolation unit include a second inverter, and the access and disconnection of the first auxiliary interpolation unit and the second auxiliary interpolation unit can be controlled by controlling the conduction and disconnection of the corresponding second inverter. In some other embodiments, both the first auxiliary interpolation unit and the second auxiliary interpolation unit include a second inverter and a second switch, the second inverter and the second switch are connected in series, and the access and disconnection of the first auxiliary interpolation unit and the second auxiliary interpolation unit can be controlled by controlling the closing and disconnection of the second switch.

[0038] In some embodiments, the weights of both the first auxiliary interpolation unit and the second auxiliary interpolation unit are 1 / 2 of the weight of the basic interpolation unit, that is, the size of the second inverter can be approximately half of the size of the first inverter.

[0039] Figure 3 Taking the example that a switch is connected between the output terminal of each inverter and the input terminal of the buffer unit, the closing and turning off of each switch are controlled by one bit of the control signal. As Figure 3 shown, a first switch is connected to the output terminal of each first inverter in the first phase interpolation unit, which are switch A0, switch A1,..., switch AN-1 respectively; a first switch is also connected to the output terminal of each first inverter in the second phase interpolation unit, which are switch B0, switch B1,..., switch BN-1 respectively. The output terminal of the second inverter in the first auxiliary interpolation unit is connected to a second switch, that is, switch C, and the output terminal of the second inverter in the second auxiliary interpolation unit is connected to a second switch, that is, switch D. The number 0.5 marked on the second inverter in the first auxiliary interpolation unit and the second inverter in the second auxiliary interpolation unit indicates that the weights of both the first auxiliary interpolation unit and the second auxiliary interpolation unit are 1 / 2 of the weight of the basic interpolation unit.

[0040] Each first switch (switches A0 - AN-1) in the first phase interpolation unit can be controlled by a first control signal, each first switch (switches B0 - BN-1) in the second phase interpolation unit can be controlled by a second control signal, and the second control signal is the inverted signal of the first control signal. In some embodiments, the first control signal and the second control signal are respectively N-bit thermometer codes, each bit in the N-bit thermometer code is used to control a first switch, and these two N-bit thermometer codes are complementary codes.

[0041] The second switches in the first auxiliary interpolation unit and the second auxiliary interpolation unit are both controlled by a third control signal, that is, the first auxiliary interpolation unit and the second auxiliary unit are connected or disconnected simultaneously. Taking the control signal input to the digital phase interpolator as a binary code as an example to illustrate the determination of the first control signal, the second control signal, and the third control signal. The digital phase interpolator may include a decoding unit. The decoding unit receives the binary code input to the digital phase interpolator and translates the binary code into two N-bit thermometer codes pe and po, where pe = po + 1. Then the decoding unit selects one thermometer code from the thermometer codes pe and po as the first control signal according to the least significant bit (LSB) of the binary code, and takes the inverted code of the selected thermometer code as the second control signal. For example, when the LSB of the binary code = 0, the thermometer code po is selected as the first control signal, and the inverted code of the thermometer code po is taken as the second control signal; when the LSB = 1, the thermometer code pe is selected as the first control signal, and the inverted code of the thermometer code pe is taken as the second control signal. The third control signal can be determined by the least significant bit of the binary code. For example, the third control signal is the least significant bit of the binary code. In some embodiments, the binary code can be an (n + 1)-bit binary code, where N = 2 n , n is an integer greater than or equal to 1.

[0042] In some embodiments, the buffer unit includes a third inverter.

[0043] It should be noted that in each embodiment of the application, the buffer unit can be composed of an inverter or a NAND gate. As long as the buffer unit can provide driving ability, its specific structural composition is not limited here.

[0044] Figure 4 is a circuit schematic diagram showing a 16-bit digital phase interpolator. As Figure 4As shown, the first input signal In_a is input to the first phase interpolation unit, and the second input signal In_b is input to the second phase interpolation unit. The first auxiliary interpolation unit is connected in parallel between the input end and the output end of the first phase interpolation unit, and the second auxiliary interpolation unit is connected in parallel between the input end and the output end of the second phase interpolation unit. The output ends of the first and second phase interpolation units are connected to the buffer unit, and the interpolation result is output via the buffer unit.

[0045] The first phase interpolation unit includes 8 basic interpolation units connected in parallel, and the second phase interpolation unit includes 8 basic interpolation units connected in parallel. Each basic interpolation unit includes a first inverter and a first switch connected in series with the first inverter. Both the first and second auxiliary interpolation units include a second inverter and a second switch connected in series with the second inverter. The switches A0 - A7 and switches B0 - B7 in the first and second phase interpolation units can be controlled by thermometer codes. The weights of both the first auxiliary interpolation unit and the second auxiliary interpolation unit are 1 / 2 of the weight of the basic interpolation unit. For example, when the weight of the basic interpolation unit is 1, the weights of the first and second auxiliary interpolation units are 0.5.

[0046] It should be noted that in the embodiments of the present application, such as Figure 1 , 3 and as shown in 4, the circuit side where the first phase interpolation unit and the first auxiliary interpolation unit are located is one of the above-mentioned "two sides", and the circuit side where the second phase interpolation unit and the second auxiliary interpolation unit are located is the other of the above-mentioned "two sides".

[0047] Assume that the control signal input to the Figure 4 shown digital phase interpolator is a 4-bit binary code. Then, the 4-bit binary code needs to be translated into two 8-bit thermometer codes pe and po first, and then one of the thermometer codes is selected from pe and po according to the least significant bit of the 4-bit binary code to control the switches A0 - A7, and the inverse code of the selected thermometer code is used to control the switches B0 - B7. At the same time, the least significant bit of the 4-bit binary code is used to control the switches C and D in the 2 auxiliary interpolation units.

[0048] Next, take the Figure 4 shown encoding method of a 16-bit digital phase interpolator as an example for illustration.

[0049] For example, when the input control signal is the 4-bit binary code "0000", the 4-bit binary code "0000" can be translated first to obtain two 8-bit thermometer codes pe and po. Then, according to the least significant bit of the binary code "0000", one of the thermometer codes is selected from pe and po as the first control signal. Here, the least significant bit is 0, so po can be selected as the first control signal, and the complement of po is selected as the second control signal. The specific translation method has been described above and will not be elaborated here. After translation processing, the 8-bit first control signal for controlling the 8 switches A0 - A7 of the first phase interpolation unit is "11111111", and the 8-bit second control signal for controlling the 8 switches B0 - B7 of the second phase interpolation unit is "00000000". Since the least significant bit of the 4-bit binary code "0000" is 0, the control codes for the switch C of the first auxiliary interpolation unit and the switch D of the second auxiliary interpolation unit are both "0". Obviously, "1" and "0" in the control signal or control code are two opposite control commands. For example, when "1" represents "closing" the corresponding switch, "0" represents "opening" the corresponding switch.

[0050] When the input control signal is the 4-bit binary code "0001", the first control signal is "11111110", and the second control signal is "00000001". Since the least significant bit of the 4-bit binary code "0001" is 1, the control codes for the switch C of the first auxiliary interpolation unit and the switch D of the second auxiliary interpolation unit are both "1".

[0051] When the input control signal is the 4-bit binary code "0010", the first control signal is "11111110", and the second control signal is "00000001". Since the least significant bit of the 4-bit binary code "0010" is 0, the control codes for the switch C of the first auxiliary interpolation unit and the switch D of the second auxiliary interpolation unit are both "0".

[0052] When the input control signal is the 4-bit binary code "0011", the first control signal is "11111100", and the second control signal is "00000011". Since the least significant bit of the 4-bit binary code "0011" is 1, the control codes for the switch C of the first auxiliary interpolation unit and the switch D of the second auxiliary interpolation unit are both "1".

[0053] And so on until all 4-bit binary codes are traversed.

[0054] Table 1 is Figure 4 the corresponding switch control codes for the interpolation results output by the 16-bit digital phase interpolator shown and the binary codes of the control signals input to the digital phase interpolator

[0055]

[0056] Through the above control signal encoding method, Figure 4 the 16-bit digital phase interpolator shown can achieve the same interpolation effect as Figure 2 the same. Moreover, compared with the traditional 16-bit digital phase interpolator that requires 32 basic interpolation units in parallel, the solution of this application only requires 16 basic interpolation units and 2 auxiliary interpolation units to achieve the interpolation effect of the 16-bit digital phase interpolator, which greatly reduces the power consumption and area.

[0057] It should be noted that each circuit component mentioned in the embodiments of this application is a logic module. Physically, a logic module can be a physical module, a part of a physical module, or can be implemented by a combination of multiple physical modules. The physical implementation manner of these logic modules themselves is not the most important. The combination of the functions implemented by these logic modules is the key to solving the technical problems proposed in this application. In addition, in order to highlight the innovative part of this application, the above device embodiments of this application do not introduce modules that are not closely related to solving the technical problems proposed in this application, which does not mean that there are no other modules in the above device embodiments.

[0058] It should be noted that in the claims and the specification of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one" does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0059] Although this application has been illustrated and described by referring to some preferred embodiments of this application, those of ordinary skill in the art should understand that various changes can be made in form and detail without departing from the spirit and scope of this application.

Claims

1. A digital phase interpolator, characterized in that, it includes: a first phase interpolation unit, a second phase interpolation unit, a first auxiliary interpolation unit, a second auxiliary interpolation unit, and a buffer unit; The first auxiliary interpolation unit is connected in parallel with the first phase interpolation unit between a first input signal and an input end of the buffer unit; The second auxiliary interpolation unit is connected in parallel with the second phase interpolation unit between a second input signal and an input end of the buffer unit, and there is a preset phase difference between the first input signal and the second input signal; An output end of the buffer unit is an output end of the digital phase interpolator; Wherein, both the first phase interpolation unit and the second phase interpolation unit include N basic interpolation units connected in parallel, and the weights of both the first auxiliary interpolation unit and the second auxiliary interpolation unit are 1 / 2 of the weights of the basic interpolation units, where N is an integer greater than 1.

2. The digital phase interpolator according to claim 1, characterized in that, The first auxiliary interpolation unit and the second auxiliary interpolation unit are controlled by the same control signal so that the first auxiliary interpolation unit and the second auxiliary interpolation unit are turned on or off simultaneously.

3. The digital phase interpolator according to claim 1, characterized in that, The basic interpolation unit includes a first inverter.

4. The digital phase interpolator according to claim 3, characterized in that, The basic interpolation unit further includes a first switch, and the first inverter is connected in series with the first switch.

5. The digital phase interpolator according to claim 3, characterized in that, Both the first auxiliary interpolation unit and the second auxiliary interpolation unit include a second inverter.

6. The digital phase interpolator according to claim 5, characterized in that, Both the first auxiliary interpolation unit and the second auxiliary interpolation unit further include a second switch, and the second inverter is connected in series with the second switch.

7. The digital phase interpolator according to claim 1, characterized in that, The buffer unit includes a third inverter.

8. The digital phase interpolator according to claim 1, characterized in that, The first phase interpolation unit is controlled by a first control signal, the second phase interpolation unit is controlled by a second control signal, and the second control signal is an inverted signal of the first control signal.

9. The digital phase interpolator according to claim 8, characterized in that, Both the first control signal and the second control signal are N-bit thermometer codes.

10. The digital phase interpolator according to claim 9, characterized in that, The first control signal and the second control signal are translated by a decoding unit according to a binary code input to the digital phase interpolator.

11. The digital phase interpolator according to claim 10, characterized in that, The decoding unit translates the binary code into two N-bit thermometer codes pe and po, selects one of the two N-bit thermometer codes pe and po as the first control signal according to the least significant bit of the binary code, and uses the complement code of the selected thermometer code as the second control signal; where pe = po + 1.

12. The digital phase interpolator according to claim 10, characterized in that, both the first auxiliary interpolation unit and the second auxiliary interpolation unit are controlled by the least significant bit of the binary code.

Images