Self-adaptive decision feedback sequence estimator insensitive to line pair exchange

Abstract

The invention provides a self-adaptive decision feedback sequence estimator insensitive to line pair switching. The self-adaptive decision feedback sequence estimator comprises a decision feedback module, a subset remapping module, a four-dimensional branch measurement module, an addition, comparison and selection module and a surviving path storage module, the decision feedback module comprises first to fourth decision feedback components; the first to fourth decision feedback components have the same structure, and each of the first to fourth decision feedback components comprises a line pair input channel, a hard decision unit, an advanced decision feedback unit, a one-dimensional branch measurement unit, an adaptive unit and a decision feedback equalization unit. According to the self-adaptive decision feedback sequence estimation module, a line pair exchange error correction function, a self-adaptive decision feedback equalization function and a viterbi decoding function are realized, and meanwhile, the self-adaptive decision feedback equalization function and the viterbi decoding function are not influenced when the line pair exchange error correction function is performed, so that the whole self-adaptive decision feedback sequence estimation module is insensitive to exchange of line pairs, and the reliability of the self-adaptive decision feedback sequence estimation module is improved. And the time sequence of the high-order adaptive decision feedback equalizer is optimized.

Description

Technical Field

[0001] The invention relates to the field of digital signals of circuits and systems, and in particular to an adaptive decision feedback sequence estimator which is insensitive to line pair switching. Background Art

[0002] With the advancement of chip design technology, digital integrated circuit design is facilitated, and many digital algorithms can achieve better timing and power consumption under the new technology.

[0003] For 1000BASE-T physical layer chips, the key technologies include decoders and adaptive decision feedback equalizers. The current design in this area lacks module coupling, resulting in poor performance, and does not consider the impact of line pair switching on Viterbi decoding. Therefore, an adaptive decision feedback sequence estimator that is insensitive to line pair switching is designed, merging these structures into one structure with higher robustness. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide an adaptive decision feedback sequence estimator which is insensitive to line pair switching in view of the defects involved in the background technology.

[0005] The present invention adopts the following technical solutions to solve the above technical problems:

[0006] An adaptive decision feedback sequence estimator insensitive to line pair switching includes a decision feedback module, a subset remapping module, a four-dimensional branch metric module, an addition, comparison and selection module and a survivor path storage module;

[0007] The decision feedback module includes first to fourth decision feedback components;

[0008] The first to fourth decision feedback components have the same structure, and all include a line pair input channel, a hard decision unit, an advance decision feedback unit, a one-dimensional branch metric unit, an adaptive unit, and a decision feedback equalization unit;

[0009] The line pair input channel is used to receive an external input signal, store the input signal for one cycle, and then output it as a signal pair_in to the hard decision unit;

[0010] On one hand, the hard decision unit adds pair_in to the post inter-symbol interference signal Post_canc output by the decision feedback equalization unit to obtain the signal woPost without post inter-symbol interference. Then, it passes woPost through a five-symbol decision maker {±2, ±1, 0} to generate a hard decision signal hard_dec. Next, it subtracts the hard decision signal from the signal woPost without post inter-symbol interference to generate a residual error signal error and outputs it to the adaptive unit. On the other hand, the hard decision unit adds pair_in to the signal L2Post_canc output by the decision feedback equalization unit, which contains the signal from the second post inter-symbol interference onwards, to generate a signal w2Post_in with only the first two inter-symbol interferences remaining and transmits it to the look-ahead decision feedback unit;

[0011] The adaptive unit receives the residual error signal error from the hard decision unit and the final decision data V from the survivor path storage module 0D to perform LMS operations to generate tap coefficients W at different times tap and transmits them to the decision feedback equalization unit;

[0012] The decision feedback equalization unit convolves the tentative decision data V from the survivor path storage module 0D with the tap coefficients W at different times from the adaptive unit tap This convolution operation is implemented using an FIR filter structure and outputs all post inter-symbol interference cancellation values Post_canc and the remaining last two post inter-symbol interference cancellation values L2Post_canc to the hard decision unit for post inter-symbol interference cancellation of the received signal;

[0013] The look-ahead decision feedback unit receives the signal w2Post_in output by the hard decision unit, which contains only the first two inter-symbol interferences. By receiving the path decision values V 0 i 、V 1 i at the first two moments from the survivor path metric module, where i = 0, 1,..., 7, it performs look-ahead feedback operations to obtain a signal viterbi_input without post inter-symbol interference i and outputs it to the one-dimensional branch metric unit. The look-ahead feedback operation first multiplies all possible symbol combinations transmitted in the first two periods by the first two tap coefficients respectively, adds the 25 results to the input signal through an adder, and then selects the corresponding data according to the path decision values V 0 i 、V 1 i to achieve look-ahead cancellation of the inter-symbol interference from the first two moments on the current time line;

[0014] The one-dimensional branch metric unit receives the data viterbi_input that eliminates all inter-symbol interference from the advanced decision feedback unit i ; passes viterbi_input i through the symbol decision devices of the symbol subsets {-2, 0, 2} and {-1, 1} respectively to obtain the one-dimensional symbol decision values 1D_X i and 1D_Y i ; then subtracts viterbi_input i from the one-dimensional symbol decision values 1D_X i and 1D_Y i respectively, squares the results to obtain the one-dimensional decision squared error values 1D_XBM i and 1D_YBM i ; sends 1D_X i , 1D_Y i , 1D_XBM i , and 1D_YBM i to the subset remapping module;

[0015] The subset remapping module receives the one-dimensional symbol decision values and one-dimensional decision squared error values from all one-dimensional branch metric units; the subset remapping module combines the one-dimensional decision values and one-dimensional decision squared error values of the four line pairs according to the line pair error correction selection signal pair_switch i . Since it is a four-dimensional eight-state viterbi decoder, the 8 states S i are divided into 8 state subsets D0,...., D7, each state subset contains two sub-subsets, the D0 subset contains the two sub-subsets XXXX and YYYY, the D1 subset contains the two sub-subsets XXXY and YYYX, the D2 subset contains the two sub-subsets XXY and YYXX, the D3 subset contains the two sub-subsets XXYX and YYXY, the D4 subset contains the two sub-subsets XYYX and YXXY, the D5 subset contains the two sub-subsets XYYY and YXXX, the D6 subset contains the two sub-subsets XYXY and YXYX, and the D7 subset contains the two sub-subsets XYXX and YXYY; the combination of subsets is to select the corresponding combination method according to the line pair error correction selection signal pair_switch i of each state; combines the decision squared error values into the four-dimensional branch metrics 4D_XBM ij and 4D_YBM ij , i = 0, 1,..., 7, j = 0, 1, 2, 3, combines the symbol decision values into the four-dimensional decision symbols 4D_X ij and 4D_Y ij ; sends the four-dimensional branch metrics 4D_XBM ij and 4D_YBMij and the four-dimensional decision symbol 4D_X ij and 4D_Y ij Send to the four-dimensional branch metric module;

[0016] The four-dimensional branch metric module receives the four-dimensional branch metric 4D_XBM from the subset remapping module ij 、4D_YBM ij and four-dimensional decision symbol 4D_XBM ij 、4D_YBM ij , select the smaller value of the four-dimensional branch metric 4D_BM in the two sub-subsets X and Y ij And output to the addition, comparison and selection module, select the four-dimensional decision symbol 4D_XY corresponding to the smaller sub-set of the four-dimensional branch metric ij Output to the surviving path storage module;

[0017] The add, compare and select module is used to convert the state S i The branch metric 4D_BM output by the four-dimensional branch metric module ij The path metric path_metric accumulated with the four-dimensional branch metric at the previous moment i n-1 Add them together to get the new path metric value path_metric i n , then select the path with the smallest path metric value from the current state transition path as the surviving path, which is represented by path_metric i n =min i (path_metric i n-1 +4DBM ij ), where path_metric i n Indicates the current state S i The path with the smallest corresponding path metric value will be selected, and the position signal path_select of the smallest path will be selected i Output to the surviving path storage module; then the minimum path value path_metric in 8 states i n Select the minimum value path_metric_best, select the signal final_select as the location information of the surviving path and output it to the surviving path storage module;

[0018] The surviving path storage module includes 8 path storage units M i , and 1 path survivor unit; path storage unit M i Receive and Status S iThe minimum path position signal path_select of the corresponding Gabi selection module i and the four-dimensional decision symbol data 4D_XY of the subset remapping module ij ; Path storage unit M i Records the subset of the minimum path branches from each state to the next state at different times, and selects which four-dimensional decision symbol data 4D_XY to store through the minimum path position signal path_select i to the path storage unit, and stores the decision symbols at each time of the path storage unit M ij as V i t is the path storage depth, t = 0,...12, and V t i and V 0 i and V 1 i The 12-bit data stored are output to the look-ahead decision feedback unit in the first to fourth decision feedback components in groups of every 3 bits; The path survivor unit receives the survivor path position information final_select from the Gabi selection module, selects the survivor paths from the 8 stored paths V t i stored in the path storage unit at different times, and obtains the best four-dimensional decision symbol data V tD at different times, and sends the best four-dimensional decision symbol V 0D at the first time to the adaptive unit and the decision feedback unit in the decision feedback component.

[0019] As a further optimization scheme of the adaptive decision feedback sequence estimator insensitive to line pair swapping in the present invention, the look-ahead decision feedback unit includes an adder, a selector, and a saturation quantizer; The look-ahead decision feedback unit uses the PAM5 signals at two times, and there are 25 possible permutations and combinations. The 8-state Viterbi inputs of each line pair need to depend on the output values V 0 i and V 1 i generated by the survivor path storage module for 8 states at two times, i = 0, 1,..., 7, where w2Post_in is the signal of pair_in that eliminates all inter-symbol interference except the inter-symbol interference between the last two orders. There are 4 * 25 = 100 operation results for the four line pairs, and a total of 4 convolution units are calculated 100 adders, 100 6-bit flip-flops, 32 25-to-1 selectors, and 100 saturation quantization units; The V 0 i and V1 i After selection, the remaining 4 * 8 = 32 results are sent to the one-dimensional branch metric unit.

[0020] As a further optimization scheme of the line pair exchange-insensitive adaptive decision feedback sequence estimator of the present invention, the decision feedback equalization unit adopts a FIR filter structure that combines direct form and transposed form, and borrows the output multiplexing flip-flop delay of the survivor path unit module; the first three orders of the decision feedback equalizer use the transposed form structure, including three multiplication units, three adders, and three groups of flip-flops to compensate for the delay brought by Viterbi decoding; when the storage depth is w, the total order of the decision feedback is N and the direct form is in groups of L orders, the remaining orders of the decision feedback equalizer include N - 3 multiplier units, N - 1 adders, N / L transposed flip-flops, and N - w - N / L data flip-flops; when N is not an integer multiple of L, the remaining orders of the equalizer form a group of direct form FIR structures alone.

[0021] As a further optimization scheme of the line pair exchange-insensitive adaptive decision feedback sequence estimator of the present invention, the adaptive equalization unit adopts the LMS algorithm. When in groups of L orders in direct form, L > 3 and the total order N is an integer multiple of L, it includes N / L - 1 error flip-flops, and the bit width of the flip-flops is determined according to the bit width of the input residual error signal error; and N adaptive units, including N multipliers and N accumulators.

[0022] As a further optimization scheme of the line pair exchange-insensitive adaptive decision feedback sequence estimator of the present invention, the one-dimensional branch metric unit includes a decision symbol lookup table and a squared difference lookup table; the Viterbi input data viterbi_input of the 8 states of the current line pair i Performs symbol decision and error calculation. The symbols are divided into two subsets X / Y, X = {+1, -1}, Y = {+2, 0, -2}; the input viterbi_input i After being judged with the two subsets X and Y, the decision symbol data 1D_X and 1D_Y are obtained, and then the data is used to calculate the error with viterbi_input i And then perform a square operation to calculate the branch metric values 1D_XBM i And 1D_YBM i ; The formula used is 1DBranch_error i =(sign X,Y (viterbi_input i ) - viterbi_input i ) 2, obtain the branch metric values 1D_XBM for the X subset and 1D_YBM for the Y subset with 8 states in one dimension i and 1D_YBM i and the decision symbol values 1D_X i and 1D_Y i ; The above operations can be implemented by a lookup table, which includes 32 X sub - subset decision units, 32 X sub - subset squared error lookup tables, 32 Y sub - subset decision units, and 32 Y sub - subset squared error lookup tables.

[0023] As a further optimization scheme of the adaptive decision feedback sequence estimator insensitive to line - pair swapping in the present invention, the subset remapping module includes 336 2 - to - 1 selection units for swapping the sub - subset branch metrics of line pairs 2, 3, and 4, and 336 2 - to - 1 selection units for swapping the sub - subset decision symbols; This swapping can achieve subset remapping, so that the swapping of line pairs during IDLE data transmission does not affect the Viterbi output value, and the Viterbi can be correctly decoded, making the module insensitive to line - pair swapping.

[0024] As a further optimization scheme of the adaptive decision feedback sequence estimator insensitive to line - pair swapping in the present invention, the four - dimensional branch metric module includes an adder unit, a minimum selection unit, and a minimum value output unit; Compare and output the branch metric of the smallest four - dimensional sub - subset while selecting the corresponding sub - subset D i,X or D i,Y ; It includes 128 adders to merge the one - dimensional branch metrics of the four line pairs in each state according to sub - subsets. In addition, it also includes 64 minimum value output units for outputting the smallest four - dimensional sub - subset branch metric and the smallest sub - subset under one subset after merging, and uses 64 2 - to - 1 selectors to output this smallest sub - subset.

[0025] As a further optimization scheme of the adaptive decision feedback sequence estimator insensitive to line - pair swapping in the present invention, the add - compare - select module includes an adder unit, a minimum value selection unit, a minimum value output unit, an accumulation unit. The operation includes 9 minimum value output units, 32 adders, and 8 10 - bit flip - flops. In addition to the above operations, to prevent overflow, the add - compare - select module also includes 8 subtractors and 1 10 - bit flip - flop for subtracting the smallest path metric value.

[0026] As a further optimization scheme of the adaptive decision feedback sequence estimator insensitive to line - pair swapping in the present invention, the surviving path storage module includes 8 path storage units and 1 path surviving unit, with a storage depth of w1. When w1>6, the path storage unit includes 8*w1 4 - to - 1 selectors and 8*w1 12 - bit flip - flops, and the path surviving unit includes w2 8 - to - 1 selectors and w2 12 - bit flip - flops.

[0027] Compared with the prior art by adopting the above technical solution, the present invention has the following technical effects:

[0028] Using subset remapping to solve the influence of wire pair swapping on Viterbi decoding, combining an adaptive decision feedback equalizer with Viterbi decoding to reduce circuit complexity, and optimizing the timing by using a combined direct and transposed FIR structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a schematic diagram of the overall architecture of the adaptive decision feedback sequence estimator of the present invention that is insensitive to wire pair swapping;

[0030] Figure 2 It is a schematic diagram of the overall architecture of the present invention based on a look-ahead decision feedback unit;

[0031] Figure 3 It is a schematic diagram of the internal and connection relationships of the one-dimensional branch metric module, subset remapping module, and four-dimensional branch metric module of the present invention;

[0032] Figure 4 It is a schematic diagram of the internal relationship of the survivor path storage module of the present invention;

[0033] Figure 5 It is a schematic diagram of the internal and connection relationships of the adaptive equalization module, decision feedback equalizer, and look-ahead decision feedback unit of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings:

[0035] The present invention can be implemented in many different forms and should not be considered limited to the embodiments described herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, components are enlarged for clarity.

[0036] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, and / or parts, these elements, components, and / or parts are not limited by these terms. These terms are only used to distinguish one element, component, and / or part from another. Thus, the first element, component, and / or part discussed below may become the second element, component, or part without departing from the teachings of the present invention.

[0037] Such as Figure 1As shown, the present invention discloses an adaptive decision feedback sequence estimator which is insensitive to line pair exchange, including a line pair input channel, a hard decision unit, an advance decision feedback unit, a one-dimensional branch metric module, a four-dimensional branch metric module, an addition, comparison and selection module, a surviving path storage module, a subset remapping module, a decision feedback equalization module, and an adaptive equalization module.

[0038] like Figure 2 As shown, the line pair input channel, the hard decision unit, and the advanced decision feedback unit are used to process the external input signal received by the line pair input channel to eliminate the influence of the post-intersymbol crosstalk generated by the data of the first two moments. The line pair input channel is used to receive the external input signal, store the input signal for one cycle, and output it as a signal pair_in to the hard decision unit. On the one hand, the hard decision unit adds pair_in to the post-inter-code crosstalk signal Post_canc output by the decision feedback equalization unit to obtain the signal woPost with the post-inter-code crosstalk eliminated, and then passes it through the five-symbol decision device {±2, ±1,0} to generate a hard decision signal hard_dec, and then subtracts the hard decision signal from the signal woPost with the post-inter-code crosstalk eliminated to generate a residual error signal error, which is output to the adaptive unit; on the other hand, pair_in is added to the signal L2Post_canc output by the decision feedback equalization unit containing the signal after the second post-inter-code crosstalk to generate a signal w2Post_in with only the first two inter-code crosstalks remaining and transmit it to the advance decision feedback unit; the advance decision feedback unit uses an advance calculation structure to receive the signal w2Post_in containing only the first two inter-code crosstalks output by the hard decision unit, and uses the PAM5 signals at the first two moments, with 25 possible permutations and combinations, and receives the path decision value V at the first two moments from the surviving path metric module 0 i 、V 1 i , i = 0, 1, ..., 7, and perform advance feedback operation to obtain the signal viterbi_input that eliminates the inter-symbol interference. i . The advance decision feedback unit includes an adder, a selector, and a saturation quantizer; the four line pairs have a total of 4*25=100 operation results, which contain a total of 4 convolution units. And 100 adders, 100 6-bit flip-flops, 32 25-to-1 selectors, and 100 saturation quantization units. The V generated by the survivor path storage module 0 i and V 1 i After the selection, 4*8=32 results remain, which are sent to the one-dimensional branch metric unit.

[0039] As shown Figure 3 in the figure, the one-dimensional branch metric module passes viterbi_input i through the symbol decision devices of the symbol subsets {-2, 0, 2} and {-1, 1} respectively, and obtains the one-dimensional symbol decision values 1D_X i and 1D_Y i ; then viterbi_input i is subtracted from the one-dimensional symbol decision values 1D_X i and 1D_Y i respectively, and then squared to obtain the one-dimensional decision squared error values 1D_XBM i and 1D_YBM i ; This module includes 32 X sub-subset decision units, 32 X sub-subset squared error lookup tables, 32 Y sub-subset decision units, and 32 Y sub-subset squared error lookup tables.

[0040] As shown Figure 3 in the figure, the subset remapping module combines the one-dimensional decision values and one-dimensional decision squared error values of four line pairs according to the line pair error correction selection signal pair_switch i . According to the subset combination method, the decision squared error values are combined into the four-dimensional branch metric 4D_XBM ij and 4D_YBM ij , where i = 0, 1,..., 7, j = 0, 1, 2, 3, and the combined symbol decision values are combined into the four-dimensional decision symbol 4D_X ij and 4D_Y ij ; This exchange can achieve subset remapping. For example, XXXY of the D1 subset is composed of the X of line pair 1, the X of line pair 2, the X of line pair 3, and the Y of line pair 4. However, after swapping line pairs 3 and 4, XXXY of the D1 subset becomes XXYX of the D3 subset, so that the swapping of line pairs during IDLE data transmission does not affect the Viterbi output value, and Viterbi can be correctly decoded, making the module insensitive to line pair swapping. This module includes 336 1-of-2 selectors for swapping the sub-subset branch metrics of line pairs 2, 3, and 4, and 336 1-of-2 selectors for swapping the sub-subset decision symbols.

[0041] As shown Figure 3 in the figure, the four-dimensional branch metric module combines the branch metric values and decision symbol values of the one-dimensional branch metric modules of 4 line pairs according to the state transition and transition subset of trellis-coded modulation. Each subset contains two sub-subsets. For example, the D0 subset contains two sub-subsets of XXXX and YYYY. The four-dimensional branch metric module receives the four-dimensional branch metrics 4D_XBM ij and 4D_YBM ij from the subset remapping moduleand the four-dimensional decision symbol 4D_XBM ij , 4D_YBM ij , select the smaller four-dimensional branch metric 4D_BM of the four-dimensional subsets in the two sub-sets of X and Y ij and output it to the add-compare-select module, and select the four-dimensional decision symbol 4D_XY corresponding to the sub-set with the smaller four-dimensional branch metric ij and output it to the survivor path storage module. The four-dimensional branch metric module includes an addition unit, a minimum selection unit, and a minimum value output unit; compare and output the branch metric of the smallest four-dimensional sub-set and simultaneously select the corresponding sub-set D i,X or D i,Y . This module includes 128 adders to merge the one-dimensional branch metrics of the four line pairs in each state according to the sub-sets. In addition, it includes 64 minimum value output units to output the smallest four-dimensional branch metric and the smallest sub-set of the merged sub-set, and simultaneously uses 64 1-of-2 selectors to output this smallest sub-set

[0042] The add-compare-select module is used to add the branch metric 4D_BM output by the four-dimensional branch metric module for state S i to the path metric path_metric obtained by accumulating the four-dimensional branch metric at the previous moment ij to obtain a new path metric value path_metric i n-1 , and then select the path with the smallest path metric value in the path of the current state transition as the survivor path to be retained, which is expressed as path_metric i n = min i n (path_metric i i n-1 + 4DBM ij i ), where path_metric n i represents the path with the smallest path metric value corresponding to state S i at the current moment, and output the position signal path_select i for selecting this minimum path to the survivor path storage module; then, among the minimum path values path_metric i nThe minimum value path_metric_best is selected from them, and the signal final_select is selected as the position information of the surviving path and output to the surviving path storage module; the add-compare-select module includes an addition unit, a minimum value selection unit, a minimum value output unit, and an accumulation unit. The operation includes 9 minimum value output units, 32 adders, and 8 10-bit flip-flops. In addition to the above operations, to prevent overflow, the add-compare-select module also includes 8 subtractors and 1 10-bit flip-flop for subtracting the minimum path metric value.

[0043] As Figure 4 shown, the surviving path storage module is divided into 8 path storage units and 1 path surviving unit, which are the path storage unit and the path surviving unit in state 0 in the figure. The path storage unit M i receives the minimum path position signal path_select i from the add-compare-select module corresponding to the state S i and the four-dimensional decision symbol data 4D_XY ij of the subset remapping module; the path storage unit M i records the subset of the minimum path branches from each state to the next state at different times, and selects which four-dimensional decision symbol data 4D_XY i to store through the minimum path position signal path_select ij to the path storage unit, and stores the decision symbols of each moment of the path storage unit M i as V t i , where t is the path storage depth, t = 0,... 12, and outputs the 12-bit data stored in V 0 i and V 1 i to the look-ahead decision feedback unit in the first to fourth decision feedback components in groups of 3 bits each; the path surviving unit receives the surviving path position information final_select from the add-compare-select module, selects the surviving path from the 8 stored paths V t i stored in the path storage unit at different times, obtains the best four-dimensional decision symbol data V tD at different times, and sends the best four-dimensional decision symbol V 0D at the first moment to the adaptive unit and the decision feedback unit in the decision feedback component. The storage depth of this module is w. When w > 6, the path storage unit includes 8*w 4-to-1 selectors and 8*w 12-bit flip-flops, and the path surviving unit includes w 8-to-1 selectors and w 12-bit flip-flops.

[0044] As Figure 5As shown in the figure, the decision feedback equalization module is used to achieve post-inter-symbol interference cancellation. It adopts a hybrid FIR filter structure of direct form and transposed form, and borrows the output of the surviving path unit module to multiplex the trigger delay. The first three stages of the decision feedback equalizer use the transposed form to compensate for the delay caused by Viterbi decoding. It includes three multiplication units, three adders, and three groups of flip-flops, and the flip-flops are determined according to the bit width of the operation result. When the storage depth is w, the total order of the decision feedback is N and the direct form is in groups of L orders, the remaining orders of the decision feedback equalizer include N - 3 multiplier units, N - 1 adders, N / L transposed flip-flops, and N - w - N / L data flip-flops; when N is not an integer multiple of L, the remaining orders of the equalizer form a separate group of direct form FIR structures.

[0045] As Figure 5 shown in the figure, the adaptive equalization module adopts the LMS algorithm. When the direct form is in groups of L orders, L > 3 and the total order N is an integer multiple of L, it includes N / L - 1 error flip-flops, and the bit width of the flip-flops is determined according to the bit width of the input residual error signal error; and N adaptive units, including N multipliers and N accumulators.

[0046] In summary, an adaptive decision feedback sequence estimator insensitive to line pair swapping proposed by the present invention can perform Viterbi decoding, is not affected by line pair swapping at the same time, realizes an adaptive decision feedback equalizer, and optimizes the timing.

[0047] The above-described specific embodiments have detailed the purpose and technical solutions of the present invention. It should be noted that without departing from the principle of the present invention, several substitutions and improvements can be made, and these substitutions and improvements should also be regarded as the protection scope of the present invention.

Claims

1. An adaptive decision feedback sequence estimator insensitive to line pair switching, characterized in that: It includes a decision feedback module, a subset remapping module, a four-dimensional branch metric module, an addition, comparison and selection module and a surviving path storage module; The decision feedback module includes first to fourth decision feedback components; The first to fourth decision feedback components have the same structure, and all include a line pair input channel, a hard decision unit, an advance decision feedback unit, a one-dimensional branch metric unit, an adaptive unit, and a decision feedback equalization unit; The line pair input channel is used to receive an external input signal, store the input signal for one cycle, and then output it as a signal pair_in to the hard decision unit; On the one hand, the hard decision unit performs an addition operation on pair_in and the post-inter-symbol crosstalk signal Post_canc output by the decision feedback equalization unit to obtain a signal woPost with the post-inter-symbol crosstalk eliminated, and then passes it through a five-symbol decision device {±2, ±1,0} to generate a hard decision signal hard_dec, and then performs a subtraction operation on the hard decision signal and the signal woPost with the post-inter-symbol crosstalk eliminated to generate a residual error signal error, which is output to the adaptive unit; On the other hand, pair_in is added to the signal L2Post_canc outputted from the decision feedback equalization unit and contains the signal after the second post-intersymbol interference, so as to generate a signal w2Post_in with only the first two intersymbol interferences remaining and transmit it to the advance decision feedback unit; The adaptive unit receives the residual error signal error from the hard decision unit and the final decision data V of the surviving path storage module. 0D Perform LMS operation to generate tap coefficients W at different times tap and transmit it to the decision feedback equalization unit; The decision feedback equalization unit converts the tentative decision data V from the surviving path storage module into 0D The tap coefficients W at different times from the adaptive unit tap Perform a convolution operation, which is implemented using an FIR filter structure, and output all post-inter-code crosstalk elimination values ​​Post_canc and the remaining two post-inter-code crosstalk elimination values ​​L2Post_canc to a hard decision unit to perform post-inter-code crosstalk elimination of a received signal; The advance decision feedback unit receives the signal w2Post_in containing only the first two inter-symbol interferences outputted by the hard decision unit, and receives the path decision value V0 at the first two moments from the surviving path metric module. i 、V1 i , i = 0, 1, ..., 7, and perform advance feedback operation to obtain the signal viterbi_input that eliminates the inter-symbol interference. i And output it to the one-dimensional branch metric unit; the advance feedback operation is to first multiply all possible symbol combinations transmitted in the first two cycles by the first two tap coefficients respectively, add the total 25 results to the input signal through the adder, and then calculate the path decision value V0 according to the surviving path storage module i 、V1 i Select the corresponding data to achieve the advanced elimination of the inter-code interference of the current time line affected by the previous two time points; The one-dimensional branch metric unit receives data viterbi_input from the advance decision feedback unit to eliminate all inter-symbol interference i ; viterbi_input i After passing through the symbol decision device of the symbol subset {-2,0,2} and the symbol subset {-1,1} respectively, the one-dimensional symbol decision value 1D_X is obtained. i , 1D_Y i ; Then viterbi_input i and the one-dimensional symbol decision value 1D_X i , 1D_Y i Subtract and square to get the one-dimensional decision square error value 1D_XBM i , 1D_YBM i ; 1D_X i , 1D_Y i , 1D_XBM i , 1D_YBM i Send to the subset remapping module; The subset remapping module receives one-dimensional symbol decision values ​​and one-dimensional decision square error values ​​from all one-dimensional branch metric units; The subset remapping module selects the signal pair_switch based on the line pair error correction i , the one-dimensional decision value and the one-dimensional decision square error value of the four line pairs are combined; because it is a four-dimensional eight-state Viterbi decoder, the eight states S i Divide into 8 state subsets D0, ...., D7, each state subset contains two sub-subsets, D0 subset contains XXXX and YYYY sub-subsets, D1 subset contains XXXY and YYYX sub-subsets, D2 subset contains XXY and YYXX sub-subsets, D3 subset contains XXYX and YYXY sub-subsets, D4 subset contains XYYX and YXXY sub-subsets, D5 subset contains XYYY and YXXX sub-subsets, D6 subset contains XYXY and YXYX sub-subsets, D7 subset contains XYXX and YXYY sub-subsets; the combination of subsets is based on the line pair error correction selection signal pair_switch of each state i Select the corresponding combination method; combine the decision square error value into a four-dimensional branch metric 4D_XBM according to the subset combination method ij 、4D_YBM ij , i = 0, 1, ..., 7, j = 0, 1, 2, 3, the combined symbol decision value is a four-dimensional decision symbol 4D_X ij and 4D_Y ij ; The four-dimensional branch metric 4D_XBM ij 、4D_YBM ij and the four-dimensional decision symbol 4D_X ij and 4D_Y ij Send to the four-dimensional branch metric module; The four-dimensional branch metric module receives the four-dimensional branch metric 4D_XBM from the subset remapping module ij 、4D_YBM ij and four-dimensional decision symbol 4D_XBM ij 、4D_YBM ij , select the smaller value of the four-dimensional branch metric 4D_BM in the two sub-subsets X and Y ij And output to the addition, comparison and selection module, select the four-dimensional decision symbol 4D_XY corresponding to the sub-subset of the smaller four-dimensional branch metric ij Output to the surviving path storage module; The add, compare and select module is used to convert the state S i The branch metric 4D_BM output by the four-dimensional branch metric module ij The path metric path_metric accumulated with the four-dimensional branch metric at the previous moment i n-1 Add them together to get the new path metric value path_metric i n , then select the path with the smallest path metric value from the current state transition path as the surviving path, which is represented by path_metric i n =min i (path_metric i n-1 +4DBM ij ), where path_metric i n Indicates the current state S i The path with the smallest corresponding path metric value will be selected, and the position signal path_select of the smallest path will be selected i Output to the surviving path storage module; then the minimum path value path_metric in 8 states i n Select the minimum value path_metric_best, select the signal final_select as the location information of the surviving path and output it to the surviving path storage module; The surviving path storage module includes 8 path storage units M i , and 1 path survivor unit; path storage unit M i Receive and Status S i The corresponding minimum path position signal path_select of the addition, comparison and selection module i The four-dimensional decision symbol data 4D_XY of the subset remapping module ij ; Path storage unit M i Record the minimum path branch subset from each state to the next state at different times, through the minimum path position signal path_select i To select which four-dimensional decision symbol data 4D_XY to store ij To the path storage unit, the path storage unit M i The decision symbol at each moment is stored as V t i , t is the path storage depth, t = 0, ... 12, and V0 i and V1 i The stored 12-bit data is output to the advance decision feedback unit in the first to fourth decision feedback components in groups of 3 bits each; the path survivor unit receives the survivor path position information final_select from the addition, comparison and selection module, and performs a comparison on the 8 storage paths V stored in the path storage unit at different times. t i Select the surviving path and obtain the best four-dimensional decision symbol data V at different times tD , and the symbol V for the best four-dimensional decision at the first moment 0D Sent to the adaptive unit and decision feedback unit in the decision feedback component.

2. The line pair switching insensitive adaptive decision feedback sequence estimator according to claim 1, characterized in that: The advance decision feedback unit includes an adder, a selector and a saturation quantizer; the advance decision feedback unit uses the PAM5 signal at two times, and there are 25 possible combinations. The 8-state Viterbi input of each line pair needs to rely on the surviving path storage module to generate the output value V0 of the 8 states at two times. i and V1 i , i=0,1,...,7, Among them, w2Post_in is the signal of pair_in that eliminates all post-inter-code crosstalk except the post-two-order inter-code crosstalk. There are 4*25=100 calculation results for the four line pairs, which contains 4 convolution units for calculation. 100 adders, 100 6-bit flip-flops, 32 25-to-1 selectors, and 100 saturation quantization units; V0 of the current line pair generated by the survivor path storage module i and V1 i After the selection, 4*8=32 results remain, which are sent to the one-dimensional branch metric unit.

3. The line pair switching insensitive adaptive decision feedback sequence estimator according to claim 2, characterized in that: The decision feedback equalizer unit adopts a direct and transposed mixed FIR filter structure, and borrows the output multiplexing trigger delay of the survivor path unit module; the first three orders of the decision feedback equalizer use a transposed structure, including three multiplication units, three adders, and three groups of triggers to compensate for the delay caused by Viterbi decoding; when the storage depth is w, the total number of decision feedback orders is N and L orders form a group of direct types, the remaining orders of the decision feedback equalizer include N-3 multiplier units, N-1 adders, N / L transposed triggers, and NwN / L data triggers; when N is not an integer multiple of L, the remaining orders of the equalizer separately constitute a group of direct FIR structures.

4. The line pair switching insensitive adaptive decision feedback sequence estimator according to claim 3, characterized in that: The adaptive equalization unit adopts the LMS algorithm. When L orders form a group of direct types, L>3 and the total order N is an integer multiple of L, it includes N / L-1 error triggers, and the trigger bit width is determined according to the input residual error signal error bit width; and N adaptive units, including N multipliers and N accumulators.

5. The line pair switching insensitive adaptive decision feedback sequence estimator according to claim 4, characterized in that: The one-dimensional branch metric unit includes a decision symbol lookup table and a square difference lookup table; the Viterbi input data viterbi_input of the 8 states of the current line pair i Perform symbol decision and error calculation. The symbols are divided into two sub-sets X / Y, X = {+1, -1}, Y = {+2, 0, -2}; input viterbi_input i After the judgment is made with the two sub-sets X and Y, the judgment symbol data 1D_X and 1D_Y are obtained, and then the data is used with viterbi_input i After calculating the error, perform a square operation to calculate the branch metric 1D_XBM i and 1D_YBM i ; The formula used is 1DBranch_error i =(sign X,Y (viterbi_input i )-viterbi_input i ) 2 , and the one-dimensional 8-state discrimination is the branch metric value 1D_XBM of the X subset and the Y subset i and 1D_YBM i And the judgment symbol value 1D_X i and 1D_Y i The above operation can be implemented by a lookup table, which includes 32 X sub-subset decision units, 32 X sub-subset square error lookup tables, 32 Y sub-subset decision units, and 32 Y sub-subset square error lookup tables.

6. The line pair switching insensitive adaptive decision feedback sequence estimator according to claim 5, characterized in that: The subset remapping module includes 336 2-to-1 selection units for exchanging sub-subset branch metrics of line pairs 2, 3, and 4, and 336 2-to-1 selection units for exchanging sub-subset decision symbols; this exchange can realize subset remapping, so that the exchange of line pairs during IDLE data transmission does not affect the Viterbi output value, and the Viterbi can be correctly decoded, making the module insensitive to line pair exchange.

7. The line pair switching insensitive adaptive decision feedback sequence estimator according to claim 6, characterized in that: The four-dimensional branch metric module comprises an addition unit, a minimum selection unit and a minimum value output unit; the branch metric of the four-dimensional sub-subset with the minimum value is output by comparing and outputting. At the same time, select the corresponding sub-subset D i,X or D i,Y ; It contains 128 adders to merge the one-dimensional branch metrics of the four line pairs in each state according to sub-subsets. In addition, it also contains 64 minimum output units for outputting the minimum sub-subset four-dimensional branch metric and the minimum sub-subset in a subset after merging, and uses 64 2-to-1 selectors to output this minimum sub-subset.

8. The pair-switching-insensitive adaptive decision feedback sequence estimator according to claim 7, characterized in that: The addition, comparison and selection module includes an addition unit, a minimum value selection unit, a minimum value output unit, and an accumulation unit. The operation includes 9 minimum value output units, 32 adders and 8 10-bit triggers. In addition to the above operations, in order to prevent overflow, the addition, comparison and selection module also includes 8 subtractors and 1 10-bit trigger, which are used to subtract the minimum path metric value.

9. The line pair switching insensitive adaptive decision feedback sequence estimator according to claim 8, characterized in that: The surviving path storage module includes 8 path storage units and 1 path surviving unit, and the storage depth is w. When w>6, the path storage unit includes 8*w 4-to-1 selectors and 8*w 12-bit triggers, and the path surviving unit includes w 8-to-1 selectors and w 12-bit triggers.

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