Pixel-level non-uniformity calibration front-end circuit based on back gate modulation and electronic equipment

Abstract

The invention provides a pixel-level non-uniformity calibration front-end circuit based on back gate modulation and electronic equipment, and relates to the field of integrated circuits. One end of the source end modulation unit receives a first group of bias voltages, and the other end is connected with a first common end of the single-ended amplifier; one end of the back gate modulation unit receives a second group of bias voltages, and the other end is connected with a second common end of the single-ended amplifier; the input end of the single-ended amplifier is connected with the source end of the injection tube; and the output end of the single-ended amplifier is connected with the grid end of the injection tube to form a negative feedback system. According to the pixel-level non-uniformity calibration analog front end based on back gate modulation, the current of the analog front end is calibrated and adjusted step by step, and non-uniformity calibration is achieved. And for n-bit calibration, the n-bit calibration can be realized only by using 2m + 2l wires, so that direct-current voltage wires required by calibration are reduced, and the problem of wiring tension is relieved. The whole circuit has the advantages of small area, low power consumption, low direct-current voltage required by calibration, low noise and the like.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a pixel-level non-uniformity calibration front-end circuit and an electronic device based on back-gate modulation. Background Art

[0002] With the development of semiconductor technology, the pixel area of imaging chips is getting smaller and smaller, and the problem of fixed pattern noise is becoming more and more serious. Therefore, non-uniformity calibration is necessary. These voltages for calibration are generally connected to each pixel in the array in a row or column manner. However, as the pixel pitch also becomes smaller, it becomes more and more difficult to perform multi-bit non-uniformity calibration within the pixel.

[0003] Because as the requirement for non-uniformity calibration accuracy becomes higher and higher, more calibration voltages are needed. However, the smaller the pixel pitch, the tighter the trace pitch left within the pixel. If n-bit calibration is required, the traditional calibration method requires 2 n calibration voltages, corresponding to 2 n voltage lines. This undoubtedly requires a large number of voltage lines and trace pitches, occupying a large area, which obviously does not meet the development requirement of smaller and smaller pixel areas. Summary of the Invention

[0004] In view of the above problems, the present invention is proposed to provide a pixel-level non-uniformity calibration front-end circuit and an electronic device based on back-gate modulation to solve or partially solve the above problems.

[0005] In a first aspect of an embodiment of the present invention, a pixel-level non-uniformity calibration front-end circuit based on back-gate modulation is provided. The pixel-level non-uniformity calibration front-end circuit includes: a source-end modulation unit, a back-gate modulation unit, and a single-ended amplifier;

[0006] One end of the source-end modulation unit receives a first set of bias voltages, and the other end is connected to a first common terminal of the single-ended amplifier;

[0007] One end of the back-gate modulation unit receives a second set of bias voltages, and the other end is connected to a second common terminal of the single-ended amplifier;

[0008] The input end of the single-ended amplifier is connected to the source end of the injection tube;

[0009] The output end of the single-ended amplifier is connected to the gate end of the injection tube.

[0010] Optionally, the source-end modulation unit includes: a first selector;

[0011] The input end of the first selector receives the first set of bias voltages;

[0012] The output end of the first selector is connected to the first common terminal of the single-ended amplifier.

[0013] Optionally, the back gate modulation unit includes: a second selector;

[0014] The input end of the second selector receives the second set of bias voltages;

[0015] The output end of the second selector is connected to the second common end of the single-ended amplifier.

[0016] Optionally, the single-ended amplifier includes: a common-source transistor and a current source;

[0017] The source end of the common-source transistor serves as the first common end of the single-ended amplifier and is connected to the source end modulation unit;

[0018] The body end of the common-source transistor serves as the second common end of the single-ended amplifier and is connected to the back gate modulation unit;

[0019] The gate end of the common-source transistor serves as the input end of the single-ended amplifier and is connected to the source end of the injection transistor;

[0020] The drain end of the common-source transistor serves as the output end of the single-ended amplifier, is connected to the gate end of the injection transistor, and is grounded through the current source.

[0021] Optionally, the voltages of the first set of bias voltages and the second set of bias voltages are each provided by a digital-to-analog conversion unit;

[0022] The first set of bias voltages includes: 2 m DC bias voltages;

[0023] The second set of bias voltages includes: 2 l DC bias voltages;

[0024] The 2 m DC bias voltages and the 2 l DC bias voltages altogether correspond to 2 m +2 l DC voltage lines, where m + l = n.

[0025] Optionally, the source end modulation unit is controlled by a first code value;

[0026] The back gate modulation unit is controlled by a second code value;

[0027] The source end modulation unit is configured to select a corresponding DC voltage from the first bias voltages and output it to the first common end of the single-ended amplifier based on the first code value;

[0028] The back-gate modulation unit is configured to select a corresponding DC voltage from the second bias voltages and output it to the second common terminal of the single-ended amplifier based on the second code value;

[0029] Wherein, the first code value is m bits, and the second code value is l bits.

[0030] Optionally, when the voltage at the first common terminal of the single-ended amplifier in the feedback system changes arbitrarily by ΔV S , the voltage at its input terminal changes by ΔV G , and the first adjustment ratio is defined as ΔV G / ΔV S ; when the voltage at the second common terminal of the single-ended amplifier changes arbitrarily by ΔV B , the voltage at its input terminal changes by ΔV G , and the second adjustment ratio is defined as ΔV G / ΔV B .

[0031] Optionally, by changing the magnitude of the target difference voltage, the ratio of the first adjustment ratio ΔV G / ΔV S to the second adjustment ratio ΔV G / ΔV B is changed;

[0032] Wherein, the expression of the target difference voltage V SB is:

[0033] V SB = V S - V B

[0034] In the above formula, V S represents the voltage at the source terminal of the common-source transistor, V B represents the voltage at the body terminal of the common-source transistor, and V G represents the voltage at the gate terminal of the common-source transistor.

[0035] Optionally, the expression of the current I 0 in the branch where the common-source transistor is located is:

[0036]

[0037] In the above formula, μ represents the mobility, C 0X represents the capacitance per unit area of the gate oxide layer of the common-source transistor, W represents the channel width of the common-source transistor, L represents the channel length of the common-source transistor, V OV represents the overdrive voltage, V GS represents the gate-source voltage of the common-source transistor, and V TH represents the threshold voltage of the common-source transistor;

[0038] The voltage V at the gate terminal of the common-source transistor G has the following expression:

[0039] |V G - V S - V TH | = V OV

[0040]

[0041] In the above formula, V TH0 represents the threshold voltage when the target difference voltage V SB = 0, γ represents the body effect coefficient, and φ F represents the Fermi potential;

[0042] The expression of the first adjustment ratio is:

[0043]

[0044] The expression of the second adjustment ratio is:

[0045]

[0046] Among them, the expression of the second adjustment ratio characterizes that the noise voltage at the body terminal of the common-source transistor is reduced to times the original and then transmitted to the source terminal of the injection transistor.

[0047] In the second aspect of the embodiments of the present invention, an electronic device is provided, and the electronic device includes: the pixel-level non-uniformity calibration front-end circuit according to any one of the first aspects.

[0048] The pixel-level non-uniformity calibration front-end circuit provided by the present invention includes: a source-end modulation unit, a back-gate modulation unit, and a single-ended amplifier. One end of the source-end modulation unit receives a first set of bias voltages, and the other end is connected to the first common terminal of the single-ended amplifier; one end of the back-gate modulation unit receives a second set of bias voltages, and the other end is connected to the second common terminal of the single-ended amplifier; the input terminal of the single-ended amplifier is connected to the source terminal of the injection transistor; the output terminal of the single-ended amplifier is connected to the gate terminal of the injection transistor, forming a negative feedback system.

[0049] The pixel-level non-uniformity calibration front-end circuit based on back-gate modulation proposed by the present invention creatively proposes a brand-new overall architecture. By using the advantages of the common-source single-ended amplifier structure, such as simple structure and relatively low power consumption, a pixel-level non-uniformity calibration analog front-end based on back-gate modulation is designed, and the injection current of the detector is calibrated and adjusted step by step, thereby realizing non-uniformity calibration. Among them, the number of MOS transistors contributing noise becomes smaller, and the required current and area are reduced by half. Through step-by-step calibration, for n-bit calibration, only 2m +2 l (m + l = n) wires can achieve n-bit calibration, reducing the DC voltage wires required for calibration and alleviating the problem of tight routing. The entire circuit has the advantages of small area, low power consumption, less DC voltage required for calibration, and low noise, and has high practicality. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] By reading the following detailed description of the preferred embodiments, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. Moreover, throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0051] Figure 1 is a schematic structural diagram of a traditional buffer injection type analog front end;

[0052] Figure 2 is an architecture diagram of a pixel-level non-uniformity calibration front-end circuit based on back-gate modulation according to an embodiment of the present invention;

[0053] Figure 3 is a structural diagram of a preferred pixel-level non-uniformity calibration front-end circuit based on back-gate modulation according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0054] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, and are only a part of the embodiments of the present invention, rather than all of the embodiments, and are not used to limit the present invention.

[0055] In the pixel circuit, the weak voltage or current signal converted by the detector is sent into the integrator through the analog front-end circuit to complete integration and amplification, and then the digital code value is obtained through analog-to-digital conversion. The analog front-end here is an important component for obtaining the detector signal.

[0056] In the focal plane array analog-digital mixed signal circuit, affected by factors such as process processing, environmental temperature, self-heating effect, and power supply voltage, the gain of each pixel in the array will deviate, resulting in fixed pattern noise during array imaging. To reduce this fixed pattern noise, some focal plane array circuits will introduce non-uniformity calibration circuits to adjust the pixel-level front-end for certain drifts to make the pixels in the array as uniform as possible. Common analog front-end structures include direct injection type and buffer injection type, etc.

[0057] The inventors found that although the direct injection (DI) analog front end has a simple structure and can achieve non-uniformity calibration by adjusting the gate voltage of the injection tube, as the detector current decreases, the input impedance of the injection tube increases and the injection efficiency decreases. Therefore, this structure is not suitable for the cases where the detector internal resistance is small and the injection current is small. In addition, as the area of the injection tube becomes smaller, the threshold voltage V of the injection tube TH is greatly affected by the process, which affects the reverse bias voltage on the photodiode, thus bringing fixed pattern noise to the pixel array.

[0058] The buffered injection (BDI) analog front end is to connect an operational amplifier across the gate and source of the injection tube to form a negative feedback structure, as Figure 1 shown in the schematic diagram of the structure of a traditional buffered injection analog front end. For a simple BDI structure, the operational amplifier generally selects a five-transistor operational transconductance amplifier (five-transistor OTA). It is connected across the source and gate of the injection tube M 0 . The current I generated by the detector in is simultaneously transmitted to the source end of the injection tube M 0 and the inverting end of the amplifier, and its non-inverting end receives the adjustment voltage V BDI . The current I in is integrated on the integration capacitor C 0 after passing through the injection tube M INT . The input impedance of the injection tube M 0 is reduced to 1 / (1 + A) of the original by using the negative feedback structure (where A is the gain of the amplifier) in this way, thus improving the injection efficiency.

[0059] The BDI structure composed of a five-transistor operational transconductance amplifier utilizes the characteristic of virtual short at the input terminals of the two differential pairs in the negative feedback structure to control the voltage at the non-inverting end of the differential pair to adjust the source end of the injection tube M 0 . And the introduced operational amplifier can make the source end of the injection tube at the sensitive node and V BDI virtually short, so that the source end voltage of the injection tube M 0 is stabilized at a fixed voltage level. Especially for a photoconductive detector, if precise regulation of the bias voltage across the detector is required, pixel-level detector current trimming can be achieved by adjusting V BDI , thus achieving the effect of non-uniformity calibration.

[0060] However, the inventors further found through research that with the development of technology, the imaging system has higher and higher requirements for the accuracy of non-uniformity calibration, and high-precision multi-bit calibration has become a current hotspot. However, for a general operational amplifier type BDI front end, only the V at the input end of the operational amplifier can be adjusted BDI, which results in a large number of DC bias voltages being connected to the pixels in high-bit calibration. Naturally, a large number of DC voltage lines are required to transmit the DC bias voltages. As the pixel area continues to decrease, this approach is no longer feasible. Moreover, the area and power consumption within the pixel are getting smaller and smaller, and the requirements for the operational amplifier are getting higher and higher. In the face of these problems, it is urgent to propose a brand-new structure to improve the traditional buffer injection type analog front-end structure.

[0061] In view of the above problems, through a large amount of research, the inventor creatively proposes a pixel-level non-uniformity calibration front-end circuit and an electronic device based on back-gate modulation according to the present invention, which makes full use of the common terminal of the single-ended amplifier and performs two-dimensional adjustment in the feedback system, greatly reducing the cost of in-pixel calibration. The technical solutions proposed by the present invention will be explained and described below.

[0062] The pixel-level non-uniformity calibration front-end circuit based on back-gate modulation according to the present invention includes: a source-end modulation unit, a back-gate modulation unit, and a single-ended amplifier, as shown in Figure 2 shown.

[0063] One end of the source-end modulation unit receives the first set of bias voltages, and the other end is connected to the first common terminal of the single-ended amplifier; one end of the back-gate modulation unit receives the second set of bias voltages, and the other end is connected to the second common terminal of the single-ended amplifier; the input end of the single-ended amplifier is connected to the source end of the injection transistor; the output end of the single-ended amplifier is connected to the gate end of the injection transistor, and the single-ended amplifier and the injection transistor form a negative feedback system.

[0064] In a preferred embodiment of the present invention, the source-end modulation unit includes: a first selector; the back-gate modulation unit includes: a second selector;

[0065] The input end of the first selector receives the first set of bias voltages; the output end of the first selector is connected to the first common terminal of the single-ended amplifier. The input end of the second selector receives the second set of bias voltages; the output end of the second selector is connected to the second common terminal of the single-ended amplifier.

[0066] For the first set of bias voltages and the second set of bias voltages, their respective voltages can be provided by the digital-to-analog conversion unit; of course, they can also be provided by other means, for example: two sets of bias voltages are generated externally and provided for the pixel-level non-uniformity calibration front-end circuit to use.

[0067] The first set of bias voltages includes: 2 m DC bias voltages; the second set of bias voltages includes: 2 l DC bias voltages.

[0068] A preferred structure of a single - ended amplifier includes: a common - source transistor and a current source. The common - source transistor can be a PMOS transistor or an NMOS transistor. The single - ended amplifier can be a common - source amplifier based on a PMOS transistor. Taking the PMOS transistor as an example: the source terminal of the PMOS transistor serves as the first common terminal of the single - ended amplifier and is connected to the source - end modulation unit; the body terminal of the PMOS transistor (i.e., the substrate of the PMOS transistor, also known as the back - gate terminal) serves as the second common terminal of the single - ended amplifier and is connected to the back - gate modulation unit; the gate terminal of the PMOS transistor serves as the input terminal of the single - ended amplifier and is connected to the source terminal of the injection transistor; the drain terminal of the PMOS transistor serves as the output terminal of the single - ended amplifier, is connected to the gate terminal of the injection transistor, and is grounded through the current source.

[0069] It can be understood that due to the respective characteristics of PMOS transistors and NMOS transistors, those skilled in the art can easily obtain the corresponding circuit structure of the single - ended amplifier with an NMOS transistor. The specific structure will not be elaborated one by one.

[0070] Since there are 2 m DC bias voltages and 2 l DC bias voltages, so in total there are 2 m +2 l DC voltage lines, where m + l=n. Compared with the traditional calibration method that requires 2 n voltage lines, the number of DC voltage lines required for calibration is reduced, which well alleviates the problem of tight routing.

[0071] In addition, for the two modulation units, their essence is to select the required DC bias voltage from multiple DC bias voltages to calibrate the detector bias voltage. Therefore, other selection circuits or components with selector functions can be used. The selector is only taken as a preferred structure as the two modulation units.

[0072] For the two modulation units, the source - end modulation unit is controlled by the first code value; the back - gate modulation unit is controlled by the second code value. The source - end modulation unit is configured to select the corresponding DC voltage in the first bias voltage based on the first code value and output it to the first common terminal of the single - ended amplifier; the back - gate modulation unit is configured to select the corresponding DC voltage in the second bias voltage based on the second code value and output it to the second common terminal of the single - ended amplifier. Herein, the first code value is m - bit and the second code value is l - bit.

[0073] Based on the above structure, in the feedback system, when the voltage at the first common terminal of the single - ended amplifier changes arbitrarily by ΔV S , the voltage at its input terminal changes by ΔV G , then the first adjustment ratio is ΔV G / ΔV S ; when the voltage at the second common terminal of the single - ended amplifier changes arbitrarily by ΔV BWhen the input terminal voltage changes by ΔV G , the second adjustment ratio is ΔV G / ΔV B . That is: for the structure with a PMOS transistor as a single-ended amplifier, when the voltage at its source terminal changes arbitrarily, the first adjustment ratio of its gate terminal voltage is ΔV G / ΔV S , when the voltage at the body terminal of the PMOS transistor changes arbitrarily, the second adjustment ratio of its gate terminal voltage is ΔV G / ΔV B .

[0074] In addition, preferably, the ratio of the first adjustment ratio ΔV SB / ΔV G / ΔV S and the second adjustment ratio ΔV G / ΔV B can be changed by changing the magnitude of the target difference voltage V SB . Among them, the expression of V SB is:

[0075] V SB =V S -V B

[0076] In the above formula, V S represents the voltage at the source terminal of the PMOS transistor, V B represents the voltage at the body terminal of the PMOS transistor, and V G represents the voltage at the gate terminal of the PMOS transistor.

[0077] The expression of the first adjustment ratio is:

[0078]

[0079] The expression of the second adjustment ratio is:

[0080]

[0081] To better understand the above pixel-level non-uniformity calibration front-end circuit, refer to the structural diagram of a preferred pixel-level non-uniformity calibration front-end circuit based on back-gate modulation shown in Figure 3 . To better understand the principle and function of the calibration front-end circuit structure and distinguish it from the traditional circuit structure, Figure 3 shows an example of the combination of the calibration front-end circuit and a part of the traditional circuit structure, shown in the form of specific components. It includes: a source terminal modulation unit MUX1, a back-gate modulation unit MUX2, a current source I 0 , a common-source transistor M 1, the single - ended amplifier part is framed by a virtual box Z, and its structure is based on a pixel - level non - uniform calibration front - end circuit with back - gate modulation. The gate terminal of the common - source transistor M 1 is connected to the source terminal of the injection transistor M 0 ; at the same time, the current I in generated by the detector T flows into the source terminal of the injection transistor M 0 . The gate terminal of the injection transistor M 0 is respectively connected to the drain terminal of the common - source transistor M 1 and the current source I 0 . The first set of bias voltages is represented by , and the second set of bias voltages is represented by . DH<m:1>represents the first code value, and DL<l:1>represents the second code value. The rest of the structure is referred to Figure 1 for description and will not be elaborated one by one.

[0082] It can be known from the Figure 3 structure that: the single - ended amplifier has a simple structure, so the number of MOS transistors contributing to noise becomes smaller, and the required current and area are halved. When the size of the common - source transistor M 1 is determined and the current in the branch where it is located is determined, the overdrive voltage V OV of the common - source transistor M 1 is a determined value. This can also be obtained from the following three equations: The current I 0 in the branch where M 1 is located has the following expression:

[0083]

[0084] In the above formula, μ represents the mobility, C 0X represents the capacitance per unit area of the gate oxide layer of the common - source transistor M 1 , W represents the channel width of the common - source transistor M 1 , L represents the channel length of the common - source transistor M 1 , V GS represents the gate - source voltage of the common - source transistor M 1 , and V TH represents the threshold voltage of the common - source transistor M 1 ;

[0085] And the voltage V G at the gate terminal of the common - source transistor M 1 has the following expression:

[0086] |V G -V S -V TH |=V OV

[0087]

[0088] In the above formula, V TH0Indicates the target differential voltage V SB is the threshold voltage when = 0, γ represents the body effect coefficient, and φ F represents the Fermi potential.

[0089] By using two selectors MUX1 and MUX2 in combination with the first code value and the second code value, two DC bias voltages can be respectively selected from the two bias voltages, so as to achieve the adjustment of V S and V B The goal is to further realize the adjustment of V G in the feedback system, so as to realize the trimming of the output current I in of the detector T, and finally realize non-uniformity calibration.

[0090] By setting the magnitude of V SB the first adjustment ratio ΔV G / ΔV S and the second adjustment ratio ΔV G / ΔV B The different ratios can be realized to achieve step-by-step calibration. And it can be seen from the above formula that the expression of the second adjustment ratio characterizes that the noise voltage at the body end of the common-source transistor is reduced to times and then transmitted to the source end of the injection transistor M 0 . This is less noisy than directly adjusting at the gate end of the input pair transistor in the traditional structure. At the same time, V S is adjusted by m bits, and V B is adjusted by l bits. Through step-by-step calibration, using 2 m +2 l (m + l = n) wires achieve n-bit calibration, reducing the DC voltage wires required for calibration and better alleviating the problem of tight routing.

[0091] Based on the above pixel-level non-uniformity calibration front-end circuit, an embodiment of the present invention further provides an electronic device, and the electronic device includes: the pixel-level non-uniformity calibration front-end circuit as described above.

[0092] Through the above embodiments, the pixel-level column-level hybrid readout circuit provided by the present invention includes: a source-end modulation unit, a back-gate modulation unit, and a single-ended amplifier. One end of the source-end modulation unit receives the first set of bias voltages, and the other end is connected to the first common end of the single-ended amplifier; one end of the back-gate modulation unit receives the second set of bias voltages, and the other end is connected to the second common end of the single-ended amplifier; the input end of the single-ended amplifier is connected to the source end of the injection transistor; the output end of the single-ended amplifier is connected to the gate end of the injection transistor.

[0093] The front-end circuit for pixel-level non-uniformity calibration based on back-gate modulation proposed by the present invention creatively presents a brand-new overall architecture. Utilizing the advantages of a simple common-source single-ended amplifier structure and relatively low power consumption, an analog front-end for pixel-level non-uniformity calibration based on back-gate modulation is designed. The injection current of the detector is calibrated and adjusted step by step, thereby achieving non-uniformity calibration. Among them, the number of MOS transistors contributing to noise decreases, and the required current and area are halved. Through step-by-step calibration, for n-bit calibration, only 2 m +2 l (m + l = n) wires are required to achieve n-bit calibration, reducing the DC voltage lines required for calibration and alleviating the problem of tight routing. The entire circuit has the advantages of small area, low power consumption, few DC voltages required for calibration, and low noise, and has high practicality.

[0094] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or terminal device comprising the element.

[0095] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms without departing from the purpose of the present invention and the scope protected by the claims. All of these are within the protection scope of the present invention.

Claims

1. A pixel-level non-uniformity calibration front-end circuit based on back-gate modulation, characterized in that: The pixel-level non-uniformity calibration front-end circuit comprises: a source modulation unit, a back-gate modulation unit and a single-ended amplifier; One end of the source-end modulation unit receives a first group of bias voltages, and the other end is connected to the first common end of the single-ended amplifier; One end of the back gate modulation unit receives a second group of bias voltages, and the other end is connected to the second common end of the single-ended amplifier; The input end of the single-ended amplifier is connected to the source end of the injection tube; The output end of the single-ended amplifier is connected to the gate end of the injection tube.

2. The pixel-level non-uniformity calibration front-end circuit according to claim 1, characterized in that: The source-end modulation unit comprises: a first selector; An input terminal of the first selector receives the first group of bias voltages; An output terminal of the first selector is connected to a first common terminal of the single-ended amplifier.

3. The pixel-level non-uniformity calibration front-end circuit according to claim 1, characterized in that: The back gate modulation unit comprises: a second selector; An input terminal of the second selector receives the second group of bias voltages; An output terminal of the second selector is connected to a second common terminal of the single-ended amplifier.

4. The pixel-level non-uniformity calibration front-end circuit according to claim 1, characterized in that: The single-ended amplifier comprises: a common source tube and a current source; The source end of the common source tube serves as the first common end of the single-ended amplifier and is connected to the source-end modulation unit; The body end of the common source tube serves as the second common end of the single-ended amplifier and is connected to the back-gate modulation unit; The gate end of the common source tube serves as the input end of the single-ended amplifier and is connected to the source end of the injection tube; The drain end of the common source tube serves as the output end of the single-ended amplifier, is connected to the gate end of the injection tube, and is grounded through the current source.

5. The pixel-level non-uniformity calibration front-end circuit according to claim 1, characterized in that: The voltages of the first group of bias voltages and the second group of bias voltages are each provided by a digital-to-analog conversion unit; The first set of bias voltages includes: m A DC bias voltage; The second group of bias voltages includes: l A DC bias voltage; 2 m A DC bias voltage and the 2 l DC bias voltage, corresponding to a total of 2 m +2 l DC voltage lines, where m+l=n.

6. The pixel-level non-uniformity calibration front-end circuit according to any one of claims 1 to 3, characterized in that: The source modulation unit is controlled by a first code value; The back gate modulation unit is controlled by a second code value; The source-end modulation unit is configured to select a corresponding DC voltage in the first bias voltage based on the first code value and output it to the first common terminal of the single-ended amplifier; The back gate modulation unit is configured to select a corresponding DC voltage in the second bias voltage based on the second code value and output it to the second common terminal of the single-ended amplifier; The first code value is m bits, and the second code value is 1 bit.

7. The pixel-level non-uniformity calibration front-end circuit according to claim 1, characterized in that: In the feedback system, the voltage at the first common terminal of the single-ended amplifier changes arbitrarily ΔV S When the input voltage changes ΔV G , define the first adjustment ratio as ΔV G / ΔV S The voltage at the second common terminal of the single-ended amplifier changes arbitrarily ΔV B When the input voltage changes ΔV G , define the second adjustment ratio as ΔV G / ΔV B .

8. The pixel-level non-uniformity calibration front-end circuit according to claim 4, characterized in that: By changing the size of the target difference voltage, the first adjustment ratio ΔV is changed. G / ΔV S and the second adjustment ratio ΔV G / ΔV B The ratio of Wherein, the target difference voltage V SB The expression is: V SB =V S -V B In the above formula, V S Represents the voltage at the source end of the common source tube, V B Represents the voltage of the body terminal of the common source tube, V G Represents the voltage at the gate terminal of the common source tube.

9. The pixel-level non-uniformity calibration front-end circuit according to claim 8, characterized in that: The expression of the current I0 of the branch where the common source tube is located is: In the above formula, μ represents mobility, C 0X represents the capacitance per unit area of ​​the gate oxide layer of the common source tube, W represents the channel width of the common source tube, L represents the channel length of the common source tube, V OV Represents the overdrive voltage, V GS Represents the gate-source voltage of the common source tube, V TH represents the threshold voltage of the common source transistor; The gate voltage V G The expression is: |V G -V S -V TH |=V OV In the above formula, V TH0 represents the target difference voltage V SB =0 when the threshold voltage, γ represents the body effect coefficient, φ F represents the Fermi potential; The expression of the first adjustment ratio is: The expression of the second adjustment ratio is: The expression of the second adjustment ratio indicates that the noise voltage at the body end of the common source tube is reduced to the original After being multiplied, it is transmitted to the source end of the injection pipe.

10. An electronic device, characterized in that: The electronic device comprises: a pixel-level non-uniformity calibration front-end circuit as described in any one of claims 1-9.

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