Wafer-level thin film transistor based on ultra-wide-band-gap semiconductor GeO2 and preparation method of wafer-level thin film transistor

Abstract

The wafer-level thin film transistor based on the ultra wide band gap semiconductor GeO2 comprises a substrate, a gate dielectric layer and a channel layer, the gate dielectric layer is arranged above the substrate, the channel layer is arranged above the gate dielectric layer, the substrate is made of a wafer formed by a P-type heavily doped Si material, and the substrate is made of a P-type heavily doped Si material. The gate dielectric layer is made of a high-k gate dielectric, and the channel layer is made of Sn-doped GeO2. According to the thin film transistor provided by the embodiment of the invention, through combination of the high-k gate dielectric and the ultra-wide-band-gap semiconductor GeO2, the thermal stability and reliability of the device can be enhanced, and an FET device array of Sn doped GeO2 can be prepared on the wafer-level silicon-based substrate, so that the application prospect of the ultra-wide-band-gap semiconductor GeO2 device is expanded. The embodiment of the invention further provides a preparation method of the wafer-level thin film transistor.

Description

Technical Field

[0001] This application belongs to the technical field of semiconductor materials, and particularly relates to a wafer-level thin film transistor based on ultra-wide bandgap semiconductor GeO 2 and a preparation method thereof. Background Art

[0002] With the rapid development of emerging technologies such as renewable energy conversion technologies, power grids, and electric vehicles, the demand for power devices is increasing day by day. These applications require materials to have the ability to withstand higher voltages, faster switching speeds, and more efficient thermal management. Therefore, ultra-wide bandgap (UWBG) semiconductor materials have become the focus of research. The dielectric breakdown field (E C ) of semiconductor materials in power devices is positively correlated with the bandgap of the materials. The larger the bandgap, the stronger the high-voltage resistance ability of the materials.

[0003] Currently, GeO 2 (germanium oxide) as an ultra-wide bandgap semiconductor material has gradually attracted attention. Its theoretical bandgap can reach 4.7 eV, and the dielectric breakdown field strength is as high as 7 MV / cm, making it have good application prospects in high-power and high-frequency devices. Although GeO 2 has the above excellent properties in theory, its practical application in power electronics has not been fully explored. Summary of the Invention

[0004] In view of the problems existing in the above related technologies, the present invention provides a thin film transistor based on the combination of a high-k gate dielectric and an ultra-wide bandgap semiconductor GeO 2 and a preparation method thereof. By combining the high-k gate dielectric with the ultra-wide bandgap semiconductor GeO 2 , the thermal stability and reliability of the device can be enhanced, and an FET device array of Sn-doped GeO 2 can be prepared on a wafer-level silicon-based substrate, thereby expanding the application prospects of ultra-wide bandgap semiconductor GeO 2 devices.

[0005] In a first aspect, an embodiment of the present application provides a wafer-level thin film transistor based on an ultra-wide bandgap semiconductor GeO 2 , including a substrate, a gate dielectric layer, and a channel layer. The gate dielectric layer is disposed above the substrate, and the channel layer is disposed above the gate dielectric layer. The substrate is made of a wafer formed by P-type heavily doped Si material. The gate dielectric layer is made of a high-k gate dielectric, and the channel layer is made of Sn-doped GeO 2 .

[0006] Further, the gate dielectric layer is made of HfLaO.

[0007] Further, it further includes a gate electrode layer, the gate electrode layer is disposed below the gate dielectric layer, and the gate electrode layer is made of P-type heavily doped Si.

[0008] Further, it further includes a source electrode and a drain electrode, and the source electrode and the drain electrode are disposed above the channel layer.

[0009] Further, both the source electrode and the drain electrode are made of a layer of Ti with a thickness of 10 nm and a layer of Au with a thickness of 50 nm.

[0010] In a second aspect, an embodiment of the present application further provides a method for fabricating a wafer-level thin film transistor based on ultra-wide bandgap semiconductor GeO 2 for fabricating the wafer-level thin film transistor as described in any one of the above, characterized by including the following steps:

[0011] Using a wafer made of P-type heavily doped Si material as a substrate;

[0012] Simultaneously sputtering and depositing an HfLaO thin film on the surface of the substrate using a La target and an Hf target to form a high-k gate dielectric layer; and

[0013] Simultaneously sputtering and depositing a Sn-doped GeO 2 thin film on the surface of the HfLaO thin film to form a channel layer.

[0014] Further, the simultaneously sputtering and depositing an HfLaO thin film on the surface of the substrate using a La target and an Hf target to form a high-k gate dielectric layer includes:

[0015] Using a magnetron sputtering method to simultaneously sputter and deposit the HfLaO thin film on the surface of the substrate using a La target and an Hf target to form the high-k gate dielectric layer.

[0016] Further, after using the wafer made of P-type heavily doped Si material as a substrate, it further includes:

[0017] Placing the substrate in an ultrasonic cleaner and ultrasonically cleaning it with acetone, absolute ethanol, and deionized water in sequence for at least 15 min.

[0018] Further, after simultaneously sputtering and depositing an HfLaO thin film on the surface of the substrate using a La target and an Hf target to form a high-k gate dielectric layer, it includes:

[0019] Performing oxygen plasma treatment on the surface of the substrate after depositing the HfLaO thin film.

[0020] Further, when simultaneously sputtering and depositing a Sn-doped GeO on the surface of the HfLaO thin film 2After forming the channel layer, the thin film further includes:

[0021] Form an electrode pattern on the channel layer by photolithography, then deposit a layer of Ti thin film by electron beam evaporation, and then deposit a layer of Au thin film on the Ti thin film by electron beam evaporation to form the source electrode and the drain electrode.

[0022] The thin film transistor provided by the embodiment of the present application uses a high-k material as the gate dielectric layer, which can significantly improve the gate capacitance, reduce the leakage current, enhance the thermal stability and reliability of the device, and through the combination of the high-k gate dielectric and the ultra-wide bandgap semiconductor GeO 2 Combined, they complement each other, passivate oxide defects, can more effectively control the charge of the channel layer, significantly improve the electrical performance, can significantly reduce the power consumption at the same time, and can fabricate an FET device array of Sn-doped GeO 2 on a wafer-level silicon-based substrate, thereby expanding the application prospects of ultra-wide bandgap semiconductor GeO 2 devices. Description of the Drawings

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the structures shown in these drawings.

[0024] Figure 1 It is a schematic structural diagram of a wafer-level thin film transistor based on the ultra-wide bandgap semiconductor GeO provided by the embodiment of the present application; 2

[0025] Figure 2 It is a schematic flow diagram of a preparation method of a wafer-level thin film transistor based on the ultra-wide bandgap semiconductor GeO provided by the embodiment of the present application; 2

[0026] Figure 3 It is a schematic diagram of actual thin film preparation of a preparation method of a wafer-level thin film transistor based on the ultra-wide bandgap semiconductor GeO provided by the embodiment of the present application; 2

[0027] Figure 4 It is a schematic diagram of the breakdown voltage characteristics involved in a wafer-level thin film transistor device based on the ultra-wide bandgap semiconductor GeO provided by the embodiment of the present application; 2

[0028] Figure 5 It is a schematic diagram of a wafer-level thin film transistor based on the ultra-wide bandgap semiconductor GeO provided by the embodiment of the present application; 2Schematic diagram of the characteristics of the thermal conductivity varying with temperature of the wafer-level thin-film transistor device deposited on a silicon carbide substrate;

[0029] Figure 6 For the wafer-level thin-film transistor device provided by an embodiment of the present application based on the ultra-wide bandgap semiconductor GeO 2 Schematic diagram of the surface morphology of the high-k gate dielectric of the wafer-level thin-film transistor device under different atmosphere treatments;

[0030] Figure 7 For the wafer-level thin-film transistor device provided by an embodiment of the present application based on the ultra-wide bandgap semiconductor GeO 2 Schematic diagram of the device transfer characteristics of the high-k gate dielectric of the wafer-level thin-film transistor device under different atmosphere treatments;

[0031] Figure 8 For the wafer-level thin-film transistor device provided by an embodiment of the present application based on the ultra-wide bandgap semiconductor GeO 2 Transfer characteristic curve of the 4-inch wafer-level GeO device array of the wafer-level thin-film transistor device; 2

[0032] Figure 9 For the wafer-level thin-film transistor device provided by an embodiment of the present application based on the ultra-wide bandgap semiconductor GeO 2 Statistical chart of the output characteristic curves of 25 randomly selected devices on the wafer-level thin-film transistor device array;

[0033] The realization, functional features and advantages of the purpose of the present application will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0034] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0035] It should be understood that when used in this specification and the appended claims, the terms "comprises" and "comprising" indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations.

[0036] ​It should also be understood that the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. As used in the specification of this application and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application according to specific circumstances.

[0037] Referring to Figure 1 , an embodiment of this application provides a wafer-level thin film transistor based on ultra-wide bandgap semiconductor GeO 2 . The wafer-level thin film transistor includes a substrate, a gate dielectric layer, and a channel layer. The gate dielectric layer is disposed above the substrate, and the channel layer is disposed above the gate dielectric layer. The substrate is made of a wafer formed of P-type heavily doped Si material. The gate dielectric layer is made of a high-k gate dielectric, and the channel layer is made of Sn-doped GeO 2 (Sn-doped GeO 2 ).

[0038] Specifically, as Figure 1 shown, the gate dielectric layer is made of a high-k gate dielectric. High-k materials refer to materials with a dielectric constant greater than that of silicon dioxide (SiO 2 ), such as hafnium-based oxides (such as HfO 2 ), aluminum-based oxides (Al 2 O 3 ), and zirconium-based oxides (ZrO 2 ), etc. The characteristics of high-k materials include a relatively high dielectric constant, good thermal stability, and a wide bandgap, which enable them to perform excellently in semiconductor devices. The channel layer is made of Sn-doped GeO 2 (Sn-doped GeO 2 ). Through appropriate doping (Sn doping) and appropriate doping power, the transformation of GeO 2 from an insulator to a semiconductor is successfully achieved. The thin film transistor provided by the embodiment of this application uses a high-k material as the gate dielectric layer, which can significantly increase the gate capacitance, reduce the leakage current, enhance the thermal stability and reliability of the device. Moreover, by combining the high-k gate dielectric with the ultra-wide bandgap semiconductor GeO 2 , they complement each other, passivate oxide defects, can more effectively control the charge in the channel layer, significantly improve the electrical performance, and at the same time can significantly reduce the power consumption. In addition, an FET device array of Sn-doped GeO 2 can be fabricated on a wafer-level silicon-based substrate, thereby expanding the application prospects of ultra-wide bandgap semiconductor GeO 2 devices.

[0039] Further, referring again to Figure 1 , in some embodiments of the present application, the gate dielectric layer is made of HfLaO (hafnium lanthanum oxide).

[0040] As described above, high-k materials refer to materials with a dielectric constant greater than that of silicon dioxide (SiO 2 ), such as hafnium-based oxides (e.g., HfO 2 ), aluminum-based oxides (Al 2 O 3 ) and zirconium-based oxides (ZrO 2 ), etc. The characteristics of high-k materials include a relatively high dielectric constant, good thermal stability, and a wide bandgap, which enable them to perform well in semiconductor devices.

[0041] Further, the wafer-level thin-film transistor based on the ultra-wide bandgap semiconductor GeO 2 of the embodiments of the present application further includes a gate electrode layer ( Figure 1 not shown), the gate electrode layer is disposed below the gate dielectric layer, and the gate electrode layer is made of P-type heavily doped Si.

[0042] Specifically, the gate electrode layer controls the current between the drain and the source by changing the gate voltage. When the gate voltage is zero or a negative voltage, the channel is in the off state, and the current between the drain and the source is almost zero. When the gate voltage increases to a certain value, the channel opens and allows current to pass through. The gate electrode layer of the thin-film transistor provided by the embodiments of the present application is made of P-type heavily doped Si.

[0043] Further, the wafer-level thin-film transistor based on the ultra-wide bandgap semiconductor GeO 2 of the embodiments of the present application further includes a source electrode and a drain electrode, and the source electrode and the drain electrode are disposed above the channel layer.

[0044] Specifically, the source electrode is the output terminal of the current, and carriers (electrons) enter from the source electrode. The drain electrode is the input terminal of the current, and carriers are discharged from the drain electrode. The source electrode and the drain electrode are disposed above the channel layer.

[0045] Further, both the source electrode and the drain electrode are made of a 10-nm-thick Ti layer and a 50-nm-thick Au layer.

[0046] Specifically, an electrode pattern is formed on the channel layer by photolithography, and then a Ti thin film is deposited by electron beam evaporation, and then an Au thin film is deposited on the Ti thin film by electron beam evaporation to form the source-drain electrodes. Among them, the shape of the source-drain electrodes is rectangular, with a length of 300 μm and a width of 100 μm, and the channel length of the finally fabricated thin-film transistor is 5 μm.

[0047] In addition, referring to Figure 2 and Figure 3 , an embodiment of the present application also provides a method for fabricating a wafer-level thin-film transistor based on a wide-bandgap semiconductor GeO 2 , for fabricating the wafer-level thin-film transistor as described in any one of the above, characterized by including the following steps:

[0048] S101: Using a wafer made of P-type heavily doped Si material as the substrate;

[0049] S102: Simultaneously sputtering and depositing an HfLaO thin film on the surface of the substrate using a La target and an Hf target to form a high-k gate dielectric layer; and

[0050] S103: Simultaneously sputtering and depositing an Sn-doped GeO 2 thin film on the surface of the HfLaO thin film to form a channel layer.

[0051] The method for fabricating a wafer-level thin-film transistor provided by the embodiment of the present application does not require complex and difficult-to-control processes, and realizes the implementation of a novel wide-bandgap semiconductor GeO 2 as a device combined with a channel layer and a high-k gate dielectric. Furthermore, it can be effectively applied to the field of power semiconductor devices and is suitable for popularization and application.

[0052] Referring to Figure 4 , Figure 4 is a schematic diagram of the breakdown voltage characteristics of a wafer-level thin-film transistor device based on a wide-bandgap semiconductor GeO 2 provided by an embodiment of the present application. In the test process, a voltage is applied across the source electrode and the drain electrode. As the voltage between the source and the drain gradually increases, the device breaks down at 410V. Therefore, the wide-bandgap semiconductor GeO 2 device provided by the embodiment of the present application exhibits a large breakdown voltage, although the thickness of its channel layer is only 6nm, which proves that the wide-bandgap semiconductor GeO 2 device provided by the embodiment of the present invention has good voltage withstand characteristics.

[0053] Referring to Figure 5 , Figure 5 is a schematic diagram of the characteristics of the thermal conductivity varying with temperature of a wafer-level thin-film transistor device based on a wide-bandgap semiconductor GeO 2 deposited on a silicon carbide substrate provided by an embodiment of the present application. The thermal conductivity characteristics of a 6nm-thick Sn-doped GeO 2 thin film deposited on a silicon carbide substrate varying with temperature are tested by the transient plane heat source method. As the temperature rises, its thermal conductivity increases and does not decrease significantly with the increase in temperature, demonstrating good high-temperature resistance characteristics of the device fabricated on a high-thermal-conductivity substrate.

[0054] Referring to Figure 6 , Figure 6 which is a schematic diagram of the surface morphology of the high-k gate dielectric involved in the wafer-level thin-film transistor device based on the ultra-wide bandgap semiconductor GeO 2 under different atmosphere treatments. Compared with the high-k gate dielectric HfLaO without argon plasma treatment, the HfLaO treated with surface oxygen plasma has the smoothest and most uniform surface, which can improve the interface layer quality between the high-k gate dielectric HfLaO and the channel layer Sn-doped GeO 2 , thus improving the overall performance of the device.

[0055] Referring to Figure 7 , Figure 7 which is a schematic diagram of the device transfer characteristics of the high-k gate dielectric involved in the wafer-level thin-film transistor device based on the ultra-wide bandgap semiconductor GeO 2 under different atmosphere treatments. The device with the high-k gate dielectric HfLaO after oxygen plasma treatment has the best electrical performance, with a subthreshold swing of 0.59 V / dec, a threshold voltage of 2.58 V, and a switching ratio reaching 10 5 , and a mobility exceeding 15 cm 2 V -1 s -1 .

[0056] Referring to Figure 8 , Figure 8 which is the transfer characteristic curve of the 4-inch wafer-level GeO 2 device array involved in the wafer-level thin-film transistor device based on the ultra-wide bandgap semiconductor GeO 2 . An FET device array of Sn-doped GeO 2 was fabricated on a 4-inch wafer-level silicon-based substrate and the transfer characteristics of 130 devices were tested. The devices exhibited good electrical characteristics and uniformity, with an average on-state current density of 100 mA / mm and an average threshold voltage of 2.7 V.

[0057] Referring to Figure 9 , Figure 9 which is a statistical chart of the output characteristic curves of 25 randomly selected devices on the wafer-level thin-film transistor device array based on the ultra-wide bandgap semiconductor GeO 2 . By randomly selecting 25 devices on the fabricated 4-inch wafer-level device array to test the output characteristics, all devices showed good field effects, thus demonstrating that the wafer-level thin-film transistor device array based on the ultra-wide bandgap semiconductor GeO 2 has good uniformity.

[0058] The above test results show that the wafer-level thin-film transistors provided by the embodiments of the present application based on the ultra-wide bandgap semiconductor GeO 2 and the devices prepared therefrom have good electrical properties, such as having advantages of low threshold voltage, low subthreshold swing, high on-state current, high switching ratio, high mobility, etc. At the same time, the prepared 4-inch wafer-level GeO 2 transistor array has good uniformity.

[0059] The devices prepared by the preparation method provided by the embodiments of the present application have good electrical characteristics. High-quality thin films can be prepared by physical vapor deposition at room temperature, realizing a novel ultra-wide bandgap semiconductor GeO through a simple process method 2 as a device combining a channel layer and a high-k gate dielectric, and thus can be effectively applied to the field of power semiconductor devices and is suitable for popularization and application.

[0060] Further, the simultaneous sputtering deposition of the HfLaO thin film using a La target and an Hf target on the surface of the substrate to form a high-k gate dielectric layer includes:

[0061] The HfLaO thin film is simultaneously sputtered and deposited on the surface of the substrate using a La target and an Hf target by means of magnetron sputtering to form the high-k gate dielectric layer.

[0062] Specifically, in the above steps, the vacuum degree of the cavity for growing the HfLaO thin film is less than 10 -4 Pa, the working pressure is 1 Pa, the sputtering power of the La target is 45 W, the sputtering power of the Hf target is 8 W, the sputtering gas introduced is Ar, the flow rate is 24 sccm, the sputtering gas introduced is N 2 , the flow rate is 1 sccm, the reaction gas introduced is O 2 , the flow rate is 6 sccm, and the sputtering time is 6000 s, so as to ensure the stable formation of the high-k gate dielectric layer.

[0063] In addition, the preparation method of the wafer-level thin-film transistor provided by the embodiments of the present application uses the method of magnetron sputtering to simultaneously deposit the Sn-doped GeO 2 thin film on the surface of the HfLaO thin film located above the substrate to form a channel layer. When sputtering, the vacuum degree of the cavity for growing the thin film is less than 10 -4 Pa, the working pressure is 1 Pa, the sputtering power of the Sn target is 9 W, the sputtering power of the Ge target is 30 W, the sputtering gas Ar is introduced, the flow rate is 20 sccm, and the reaction gas O 2, the flow rate is 4 sccm, the time is 500 s, and the targets are Sn target and Ge target. Among them, the sputtering power parameters of the Sn target and Ge target are the optimal parameters. If the sputtering power of the Sn target is low, the conductivity is very poor and it behaves as an insulator. If the sputtering power of the Sn target is too high, the conductivity is too strong and it behaves as a conductor, both without normal semiconductor characteristics. If the sputtering power of the Ge target is less than 30 W, it cannot start up normally. Increasing the sputtering power of the Ge target will reduce the conductivity of the thin film. Therefore, the sputtering power of the Ge target is fixed, and the semiconductor characteristics are regulated by adjusting the sputtering power of the Sn target. The Sn-doped GeO with a deposition time of 500 s 2 The device with the channel layer thickness has the optimal electrical characteristics.

[0064] Further, after using the wafer formed of P-type heavily doped Si material as the substrate, it further includes:

[0065] Placing the substrate in an ultrasonic cleaner and ultrasonically cleaning it with acetone, absolute ethanol, and deionized water in sequence for at least 15 min.

[0066] Specifically, in semiconductor processes, substrate cleaning is a crucial step. The purpose of cleaning is to remove contaminants on the substrate surface, which may include dust, grease, metal ions, organic substances, etc. These contaminants will affect the quality of subsequent process steps, such as lithography, etching, ion implantation, etc., thus affecting the performance and reliability of the final device.

[0067] The cleaning step usually includes multiple sub-steps, such as chemical cleaning (using acidic or alkaline solutions to remove organic substances and metal ions), physical cleaning (using ultrasonic waves or sandblasting to remove solid particles), deionized water rinsing (removing residual chemicals and ions), etc. The specific cleaning methods and steps depend on the type of substrate material, the type and concentration of contaminants, and the requirements of subsequent processes.

[0068] In the method for preparing a wafer-level thin film transistor provided in the embodiment of the present application, the substrate needs to be placed in an ultrasonic cleaner and ultrasonically cleaned with acetone, absolute ethanol, and deionized water in sequence for at least 15 min, which can ensure the thorough cleaning of the substrate surface. This step is crucial in semiconductor processes because it directly affects the quality of subsequent process steps and the performance of the final device.

[0069] Further, after simultaneously sputtering and depositing the HfLaO thin film on the substrate surface using the La target and Hf target to form a high-k gate dielectric layer, it includes:

[0070] Performing oxygen plasma treatment on the substrate surface after depositing the HfLaO thin film.

[0071] Specifically, the substrate after depositing the high-k gate dielectric HfLaO film is placed in a plasma cleaner for treatment, and the plasma treatment is carried out in an oxygen atmosphere. The applied RF power is 50 W, and the plasma cleaning time is 1 min. Among them, when setting plasma treatment under different atmosphere conditions, it is found that the gate dielectric after plasma treatment in the oxygen atmosphere has the lowest surface roughness and defect density, and the fabricated device has the optimal electrical characteristics; the RF power and cleaning time are fixed.

[0072] Further, after simultaneously sputtering and depositing Sn-doped GeO on the surface of the HfLaO film using an Sn target and a Ge target 2 to form a channel layer, it further includes:

[0073] An electrode pattern is formed on the channel layer by photolithography, then a Ti film is deposited by electron beam evaporation, and then an Au film is deposited on the Ti film by electron beam evaporation to form the source electrode and the drain electrode.

[0074] As described above, an electrode pattern is formed on the channel layer by photolithography, then a Ti film is deposited by electron beam evaporation, and then an Au film is deposited on the Ti film by electron beam evaporation to form the source and drain electrodes. Among them, the source and drain electrodes are rectangular in shape, with a length of 300 μm and a width of 100 μm, and the channel length of the finally fabricated thin film transistor is 5 μm.

[0075] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A wafer-level thin-film transistor based on an ultra-wide bandgap semiconductor GeO2, characterized in that: It includes a substrate, a gate dielectric layer and a channel layer, wherein the gate dielectric layer is arranged above the substrate, and the channel layer is arranged above the gate dielectric layer. The substrate is made of a wafer formed of a P-type heavily doped Si material, the gate dielectric layer is made of a high-k gate dielectric, and the channel layer is made of Sn-doped GeO2.

2. The wafer-level thin film transistor according to claim 1, wherein: The gate dielectric layer is made of HfLaO.

3. The wafer-level thin film transistor according to claim 2, wherein: It also includes a gate electrode layer, which is arranged below the gate dielectric layer and is made of P-type heavily doped Si.

4. The wafer-level thin film transistor according to claim 2, wherein: Also included is a source electrode and a drain electrode, wherein the source electrode and the drain electrode are disposed above the channel layer.

5. The wafer-level thin film transistor according to claim 2, characterized in that: The source electrode and the drain electrode are both made of a layer of Ti with a thickness of 10 nm and a layer of Au with a thickness of 50 nm.

6. A method for preparing a wafer-level thin film transistor based on an ultra-wide bandgap semiconductor GeO2, used for preparing the wafer-level thin film transistor as claimed in any one of claims 1 to 5, characterized in that: The following steps are involved: A wafer formed of a P-type heavily doped Si material is used as a substrate; Sputtering and depositing a HfLaO film on the surface of the substrate using a La target and a Hf target simultaneously to form a high-k gate dielectric layer; and A Sn-doped GeO2 film is simultaneously sputtered and deposited on the surface of the HfLaO film using a Sn target and a Ge target to form a channel layer.

7. The method according to claim 6, characterized in that The method of simultaneously sputtering and depositing a HfLaO film on the surface of a substrate using a La target and a Hf target to form a high-k gate dielectric layer comprises: The HfLaO film is deposited on the surface of the substrate by sputtering simultaneously using a La target and a Hf target by magnetron sputtering to form the high-k gate dielectric layer.

8. The method according to claim 6, characterized in that After the wafer formed of P-type heavily doped Si material is used as the substrate, the method further includes: The substrate was placed in an ultrasonic instrument and ultrasonically cleaned with acetone, anhydrous ethanol and deionized water for at least 15 minutes respectively.

9. The method according to claim 6, characterized in that After simultaneously sputtering and depositing a HfLaO film on the surface of the substrate using a La target and a Hf target to form a high-k gate dielectric layer, the method comprises: The surface of the substrate after the HfLaO film is deposited is treated with oxygen plasma.

10. The method according to claim 6, characterized in that After the Sn-doped GeO2 film is simultaneously sputtered and deposited on the surface of the HfLaO film by using a Sn target and a Ge target to form a channel layer, the method further includes: An electrode pattern is formed on the channel layer by photolithography, and then a Ti film is deposited by electron beam evaporation. Then, an Au film is deposited on the Ti film by electron beam evaporation to form the source electrode and the drain electrode.

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