Preparation method of stacked transistor, stacked transistor, device and equipment

Abstract

The invention provides a preparation method of a stacked transistor, the stacked transistor, a device and equipment, and the method comprises the steps: forming a first semiconductor structure, a first sacrificial layer and a second semiconductor structure which are sequentially stacked on a substrate, and enabling the first semiconductor structure and the second semiconductor structure to comprise a first material layer and a second material layer which are sequentially stacked; depositing a semiconductor material in the gate region to form a pseudo gate structure; removing the first sacrificial layer to form a first groove; transversely etching the first material layer in the first semiconductor structure, the first material layer in the second semiconductor structure and the pseudo gate structure to form a second groove; depositing a dielectric material in the first groove and the second groove to respectively form an isolation layer, a first inner side wall, a second inner side wall and a side wall; and forming a first gate-all-around transistor and a second gate-all-around transistor based on the second semiconductor structure and the first semiconductor structure respectively. According to the invention, the process steps and complexity in the forming process of the stacked transistor can be reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated semiconductors, and particularly to a method for manufacturing a stacked transistor, a transistor, a device, and an apparatus. Background Art

[0002] At present, with the continuous deepening of Moore's Law, continuously promoting the miniaturization of transistor size is a hot issue in the current industry research and development. By integrating two or more layers of transistors in the vertical space, the stacked transistor realizes further improvement of the transistor integration density, and becomes one of the important technologies for continuing the miniaturization of integrated circuit size.

[0003] In related technologies, the process for manufacturing stacked transistors adopts a monolithic scheme or a sequential scheme, both of which have the problems of high manufacturing process difficulty and high complexity. Therefore, in order to simplify the process flow and reduce the manufacturing difficulty, the manufacturing process of stacked transistors still needs to be improved. Summary of the Invention

[0004] The present application provides a method for manufacturing a stacked transistor, a stacked transistor, a device, and an apparatus, which can reduce the process steps and complexity in the formation process of the stacked transistor.

[0005] In a first aspect, an embodiment of the present application provides a method for manufacturing a stacked transistor, the method including: forming a semiconductor structure on a substrate, the semiconductor structure including a first semiconductor structure, a first sacrificial layer, and a second semiconductor structure stacked in sequence along a first direction, the first semiconductor structure including a first material layer and a second material layer stacked in sequence along the first direction, and the second semiconductor structure including a first material layer and a second material layer stacked in sequence along the first direction; depositing a semiconductor material in a gate region to form a pseudo-gate structure, the pseudo-gate structure surrounding the second semiconductor structure, the first sacrificial layer, and the first semiconductor structure, and the height of the pseudo-gate structure being higher than the height of the semiconductor structure; removing the first sacrificial layer to form a first groove; etching the first material layer in the first semiconductor structure, the first material layer in the second semiconductor structure, and the portion of the pseudo-gate structure higher than the semiconductor structure along a second direction to form a second groove, the second direction being a direction perpendicular to the first direction; depositing a dielectric material in the first groove and the second groove to respectively form an isolation layer at the position where the first sacrificial layer is removed, a first inner sidewall at the position where the first material layer in the second semiconductor structure is etched, a second inner sidewall at the position where the first material layer in the first semiconductor is etched, and a sidewall at the position where the portion of the pseudo-gate structure higher than the semiconductor structure is etched; forming a first surrounding-gate transistor on one side of the isolation layer having the first inner sidewall and the sidewall, based on the second semiconductor structure; and forming a second surrounding-gate transistor on one side of the isolation layer having the second inner sidewall, based on the first semiconductor structure.

[0006] In a possible implementation, a dielectric material is deposited in the first groove and the second groove to form an isolation layer at the position where the first sacrificial layer is removed, a first inner sidewall at the position where the first material layer in the second semiconductor structure is etched, a second inner sidewall at the position where the first material layer in the first semiconductor is etched, and a sidewall at the position where the portion of the pseudo-gate structure above the semiconductor structure is etched, including: depositing a dielectric material on the substrate to cover the pseudo-gate structure; anisotropically etching the dielectric material in the source-drain regions to form the isolation layer, the first inner sidewall, the second inner sidewall, and the sidewall respectively.

[0007] In a possible implementation, based on the second semiconductor structure, a first surrounding-gate transistor is formed, including: removing the semiconductor structure in the source-drain regions and filling an insulating material in the first source-drain regions corresponding to the first semiconductor structure to form a filling structure; epitaxially growing a first source-drain structure at the second source-drain regions corresponding to the second semiconductor structure; forming a first interlayer dielectric layer on the first source-drain structure; etching the portion of the pseudo-gate structure surrounding the second semiconductor structure to form a first gate structure; etching the first interlayer dielectric layer to expose the first source-drain structure; depositing a metal material on the first source-drain structure to form a first source-drain metal; and performing back-end interconnection on the first source-drain metal to form a first metal interconnection layer.

[0008] In a possible implementation, the method further includes: forming a source-drain isolation dielectric layer on the filling structure, the height of the source-drain isolation dielectric layer being the same as the height of the isolation layer; and forming a first source-drain structure on the source-drain isolation dielectric layer.

[0009] In a possible implementation, etching the portion of the pseudo-gate structure surrounding the second semiconductor structure to form a first gate structure includes: etching the portion of the pseudo-gate structure surrounding the second semiconductor structure; forming a gate isolation dielectric layer on the remaining pseudo-gate structure; etching the first material layer in the second semiconductor structure on the gate isolation dielectric layer to form a first active structure; and forming a first gate structure based on the first active structure.

[0010] In a possible implementation, the semiconductor structure further includes a second sacrificial layer, the second sacrificial layer being located between the substrate and the first semiconductor structure, with isolation structures on both sides of the second sacrificial layer, the height of the isolation structures being the same as the height of the second sacrificial layer; after forming the first surrounding-gate transistor based on the second semiconductor structure, the method further includes: flipping the first surrounding-gate transistor and removing the substrate; removing the isolation structures to form a third groove; filling the third groove with a semiconductor material to make the upper surface of the formed pseudo-gate structure flush with the upper surface of the second sacrificial layer; and forming a second surrounding-gate transistor based on the first semiconductor structure.

[0011] In a possible implementation manner, after forming the first gate structure, the method further includes: forming gate cut-off structures on both sides of the first gate structure, where the gate cut-off structures are used to isolate the gate regions of stacked transistors from the gate regions of adjacent stacked transistors.

[0012] In a second aspect, an embodiment of the present application provides a stacked transistor, which is fabricated by using the fabrication method described in the first aspect and any of its implementation manners above, and includes: a first surrounding gate transistor; a second surrounding gate transistor, where the first surrounding gate transistor and the second surrounding gate transistor are stacked, and the first surrounding gate transistor and the second surrounding gate transistor are self-aligned.

[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: the stacked transistor described in the second aspect above.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes: a circuit board and the semiconductor device described in the third aspect above, and the semiconductor device is disposed on the circuit board.

[0015] In an embodiment of the present application, a first semiconductor structure, a first sacrificial layer, and a second semiconductor structure are sequentially stacked on a substrate. Semiconductor material is deposited in the gate region to form a pseudo-gate structure, and then the first sacrificial layer is removed to form a first groove. The first material layer in the first semiconductor structure, the first material layer in the second semiconductor structure, and the part of the pseudo-gate structure that is higher than the first semiconductor structure, the first sacrificial layer, and the second semiconductor structure are etched along a first direction to form a second groove. Then, a dielectric material is deposited in the first groove and the second groove to respectively form an isolation layer at the position where the first sacrificial layer is removed, a first inner sidewall at the position where the first material layer in the second semiconductor structure is etched, a second inner sidewall at the position where the first material layer in the first semiconductor is etched, and a sidewall at the position where the part of the pseudo-gate structure that is higher than the first semiconductor structure, the first sacrificial layer, and the second semiconductor structure is etched. Then, on one side of the isolation layer having the first inner sidewall and the sidewall, a first surrounding gate transistor is formed based on the second semiconductor structure; on the side of the isolation layer having the second inner sidewall, a second surrounding gate transistor is formed based on the first semiconductor structure. Therefore, in the embodiment of the present application, the isolation layer, the inner sidewalls, and the sidewall are formed simultaneously by using the same dielectric material, which can reduce redundant process steps and process complexity.

[0016] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. Description of the Drawings

[0017] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0018] Figure 1 It is a schematic flow chart of an implementation process for a method of fabricating stacked transistors in an embodiment of the present application;

[0019] Figure 2 It is a top view schematic diagram of stacked transistors in an embodiment of the present application;

[0020] Figures 3A to 3L It is a schematic structural diagram of stacked transistors during the fabrication process in an embodiment of the present application;

[0021] Figure 4 It is a schematic structural diagram of stacked transistors in an embodiment of the present application.

[0022] The above figures:

[0023] 10. Stacked transistors; 11. First surrounding-gate transistor (front transistor); 111. First nanosheet structure; 112. First source / drain structure; 113. First interlayer dielectric layer; 114. First gate structure; 1141. First gate dielectric layer; 1142. First gate electrode layer; 115. First source / drain contact metal; 116. First metal interconnect layer; 12. Second surrounding-gate transistor (back transistor); 121. Second nanosheet structure; 122. Second source / drain structure; 123. Second interlayer dielectric layer; 124. Second gate structure; 1241. Second gate dielectric layer; 1242. Second gate electrode layer; 125. Second source / drain contact metal; 126. Second metal interconnect layer; 13. Insulating layer; 14. Carrier wafer; 20. Substrate; 21. Fourth sacrificial layer; 22. Stacking layer; 23. Third sacrificial layer; 24. Semiconductor structure; 241. First semiconductor structure; 242. Second semiconductor structure; 243. First sacrificial layer; 244. Second sacrificial layer; 25. Isolation structure; 26. Oxide layer; 27. Pseudo-gate structure; 28. Protective layer; 281. First groove; 282. Second groove; 29. MDI layer; 30. First inner sidewall; 31. Second inner sidewall; 32. Sidewall; 33. Filling structure; 34. Source / drain isolation dielectric layer; 35. Gate isolation dielectric layer; 36. First gate cut-off structure; 37. First dielectric layer; 371. Third groove; 38. Second gate cut-off structure; 39. Second dielectric layer. Detailed implementation manners

[0024] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application.

[0025] At present, with the continuous deepening of Moore's Law, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. By three-dimensional transistor stacking, stacked transistors can achieve the integration of two or more layers of transistors in the vertical space, which helps to further improve the transistor integration density and circuit performance, and is considered to be one of the important technologies to continue the miniaturization of integrated circuit size.

[0026] In one embodiment, there are two schemes for the manufacturing process of stacked transistors. The first is the monolithic scheme, and the second is the sequential scheme.

[0027] In the first scheme, N field effect transistors (NFETs) and P field effect transistors (PFETs) are fabricated on the same substrate without using substrate bonding technology. This determines that the transistors in the same layer must be of the same type, that is, NFETs or PFETs. Moreover, the upper and lower layer transistors must be strictly in the same planar space without alignment deviation. The advantage of this scheme is better integration density. The disadvantages of this scheme include the following two points: (1) The process is complex and requires a large amount of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and a basic complementary metal-oxide-semiconductor (CMOS) circuit must rely on two layers of transistors, resulting in poor design flexibility.

[0028] In the second scheme, it is based on substrate bonding and processed layer by layer. Specifically, the upper layer transistor is fabricated by bonding a substrate on the top of the fabricated lower layer transistor to vertically stack the two transistors. However, the temperature needs to be strictly controlled during the thermal process of fabricating the upper layer transistor to avoid affecting the lower layer transistor and the interconnecting wires. The advantage of this scheme is that due to substrate bonding, the device structures, channel crystal orientations, and even channel materials used for the upper and lower layer transistors can be optimized accordingly to obtain better and more matched device performance. The current technical challenges of this scheme are as follows: (1) The preparation of a high-quality upper layer transistor active layer; (2) The thinning and defect control of the upper layer bonding substrate; (3) There is an alignment error between the upper and lower layer transistors, which requires extremely high lithography accuracy.

[0029] In terms of commonalities, the technical difficulties existing in the above two solutions are as follows: (1) The thermal stability of the bottom transistor when fabricating the top transistor; (2) The performance of the top transistor under a low thermal budget; (3) The metal interconnection of transistors between layers.

[0030] To solve the above technical problems, an embodiment of the present application provides a method for fabricating stacked transistors, which can reduce the process steps and complexity during the formation of stacked transistors.

[0031] In an embodiment of the present application, the above stacked transistors can be applied to semiconductor devices such as memories and processors.

[0032] In some embodiments, the stacked transistors may include at least two transistors. Taking the first gate-all-around transistor and the second gate-all-around transistor as examples, the first gate-all-around transistor and the second gate-all-around transistor are stacked, the second semiconductor structure of the first gate-all-around transistor is self-aligned with the first semiconductor structure of the second gate-all-around transistor, and the first source / drain structure of the first gate-all-around transistor is self-aligned with the second source / drain structure of the second gate-all-around transistor in the vertical direction. Therefore, the first gate-all-around transistor and the second gate-all-around transistor are completely self-aligned.

[0033] In some embodiments, the first gate-all-around transistor and the second gate-all-around transistor in the stacked transistors are of the same type, and the gate-all-around transistor can be referred to as a gate-all-around field effect transistor (GAAFET).

[0034] Figure 1 As a schematic flowchart of an implementation process of the method for fabricating stacked transistors in an embodiment of the present application, as Figure 1 shown, the method for fabricating stacked transistors in an embodiment of the present application includes the following steps.

[0035] Step S101: Form a semiconductor structure on a substrate.

[0036] In some embodiments, the semiconductor structure includes a first semiconductor structure, a first sacrificial layer, and a second semiconductor structure stacked in sequence along a first direction. The first semiconductor structure includes a first material layer and a second material layer stacked in sequence along the first direction, and the second semiconductor structure includes a first material layer and a second material layer stacked in sequence along the first direction.

[0037] In some embodiments, the implementation process of step S101 may be as follows: Provide a substrate; sequentially stack a first material layer and a second material layer on the substrate, form a third sacrificial layer on the stacked material layers, and sequentially stack a first material layer and a second material layer on the third sacrificial layer; etch the second material layer, the first material layer, and the third sacrificial layer to form a semiconductor structure. The etched third sacrificial layer serves as the first sacrificial layer, the etched first material layer and second material layer close to the substrate serve as the first semiconductor structure, and the etched first material layer and second material layer far from the substrate serve as the second semiconductor structure. That is, the first sacrificial layer serves as an isolation structure between the first semiconductor structure and the second semiconductor structure. The first direction is the stacking direction of the stacked transistors.

[0038] Exemplarily, the substrate may be any semiconductor substrate such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, a silicon-on-insulator (SOI) substrate, etc.

[0039] In some embodiments, the material forming the first material layer is different from the material forming the second material layer, and the material forming the first sacrificial layer is also different from the materials forming the first material layer and the second material layer, so as to remove the first sacrificial layer through material selectivity in the subsequent process. The function of the first sacrificial layer will be described later. The etching process may exemplarily be at least one of dry etching, wet etching, reactive ion etching, etc.

[0040] In one example, the material forming the first material layer may be silicon germanium, the material forming the second material layer may be silicon, and the material forming the first sacrificial layer may be silicon germanium. Among them, the germanium content in the silicon germanium material forming the first sacrificial layer is different from the germanium content in the silicon germanium material forming the first material layer. Exemplarily, SiGe 1 may be used to form the first sacrificial layer, and SiGe 2 may be used to form the first material layer.

[0041] In one example, when the stacked transistor is a GAAFET, the material forming the substrate may be silicon, the material forming the first material layer may be silicon germanium, and the material forming the second material layer may be silicon. Thus, the materials forming the first semiconductor structure and the second semiconductor structure may be alternately deposited with silicon germanium and silicon. Subsequently, the first material layer (i.e., the silicon germanium material) in the first semiconductor structure and the second semiconductor structure may be removed to form the first active structure and the second active structure.

[0042] In some embodiments, the semiconductor structure further includes a second sacrificial layer. The second sacrificial layer is located between the substrate and the first semiconductor structure. Both sides of the second sacrificial layer are isolation structures, and the height of the isolation structure is the same as the height of the second sacrificial layer.

[0043] It can be understood that in the embodiments of the present application, a fourth sacrificial layer may also be formed on the substrate, and then a first material layer and a second material layer are sequentially stacked on the fourth sacrificial layer. A third sacrificial layer is formed on the stacked material layers, and a first material layer and a second material layer are sequentially stacked on the third sacrificial layer. Thereafter, the stacked layers, the third sacrificial layer, and the fourth sacrificial layer may be etched to form a semiconductor structure, and the etched fourth sacrificial layer serves as the second sacrificial layer.

[0044] In some embodiments, the material for forming the second sacrificial layer may be a silicon-germanium material. The germanium content in the silicon-germanium material for forming the first sacrificial layer is different from the germanium content in the silicon-germanium materials for forming the first material layer and the second sacrificial layer. Exemplarily, SiGe 3 may be used to form the second sacrificial layer.

[0045] In some embodiments, after forming the semiconductor structure, an insulating material may be deposited on the substrate to form an isolation structure.

[0046] It can be understood that after forming the semiconductor structure, an insulating material may be deposited on the substrate and thinned so that the upper surface of the formed isolation structure is flush with the upper surface of the second sacrificial layer to expose the first semiconductor structure.

[0047] In one example, the isolation structure may adopt the method of shallow trench isolation (STI). Exemplarily, the insulating material for forming the isolation structure may be any one of the following: silicon nitride (SiN, Si 3 N 4 ), silicon dioxide (SiO 2 ), or silicon carbon oxide (SiCO), etc. The thinning process may be a process such as chemical-mechanical planarization (CMP).

[0048] In some embodiments, after forming the isolation structure, an oxide material may be deposited on the isolation structure to form an oxide layer, and the oxide layer covers the semiconductor structure. When depositing an oxide to form an oxide layer, a very thin film may be deposited on the surface of the substrate by atomic layer deposition (ALD).

[0049] Step S102: Deposit a semiconductor material in the gate region to form a dummy gate structure.

[0050] In some embodiments, the dummy gate structure surrounds the second semiconductor structure, the first sacrificial layer, and the first semiconductor structure, and the height of the dummy gate structure is higher than the height of the semiconductor structure.

[0051] Exemplarily, the semiconductor material may be materials such as polysilicon (poly Si) and amorphous silicon.

[0052] It can be understood that after forming the semiconductor structure and the isolation structure, the gate region can be opened by photolithography, and a semiconductor material such as polysilicon is deposited in the gate region as a dummy gate structure shared by the front transistor and the back transistor. That is, in the embodiments of the present application, the gate regions of the front transistor and the back transistor in the stacked transistor are defined by the dummy gate structure, so that self-alignment of the upper and lower transistors in the stacked transistor in the gate region can be achieved. Among them, the height of the dummy gate structure is greater than the height of the semiconductor structure.

[0053] In some embodiments, in the case of forming an oxide layer, a dummy gate structure can be formed on the oxide layer.

[0054] In some embodiments, after forming the dummy gate structure, an insulating material can be deposited on the dummy gate structure to form a protective layer. Exemplarily, the insulating material may be SiN.

[0055] In some embodiments, after forming the protective layer, the oxide layer on the semiconductor structure in the source-drain region can be removed to facilitate subsequent removal of the semiconductor structure in the source-drain region.

[0056] Step S103: Remove the first sacrificial layer to form a first groove.

[0057] It can be understood that the first sacrificial layer located between the first semiconductor structure and the second semiconductor structure can be etched isotropically to form a groove, so as to form an isolation structure between the front and back transistors based on this groove subsequently.

[0058] Step S104: Etch the first material layer in the first semiconductor structure, the first material layer in the second semiconductor structure, and the part of the dummy gate structure higher than the semiconductor structure along the second direction to form a second groove.

[0059] It can be understood that the second direction is the vertical direction of the first direction.

[0060] In some embodiments, when the material of the first material layer is SiGe 2, a part of SiGe2 in the first semiconductor structure and the second semiconductor structure can be etched laterally to leave space for the inner spacer. Moreover, a part of the dummy gate structure higher than the semiconductor structure can be etched laterally to leave space for the gate spacer, so that a second groove can be formed.

[0061] It can be understood that the positions of the inner spacer and the side wall are on the same side of the semiconductor structure.

[0062] Step S105: Deposit a dielectric material in the first groove and the second groove to form an isolation layer at the position where the first sacrificial layer is removed, form a first inner sidewall at the position where the first material layer in the second semiconductor structure is etched, form a second inner sidewall at the position where the first material layer in the first semiconductor is etched, and form a sidewall at the position where the portion of the pseudo-gate structure higher than the semiconductor structure is etched.

[0063] In some embodiments, the implementation process of step S105 may be: deposit a dielectric material on the substrate to cover the pseudo-gate structure; anisotropically etch the dielectric material in the source-drain regions to form an isolation layer, a first inner sidewall, a second inner sidewall, and a sidewall respectively.

[0064] In some embodiments, when there is an isolation structure on the substrate and a protective layer on the pseudo-gate structure, a dielectric material may be deposited on the isolation structure to make the upper surface of the dielectric material flush with the upper surface of the protective layer, and then the dielectric material in the source-drain regions is etched. In this way, the dielectric material deposited at the removed first sacrificial layer can form an isolation layer, the dielectric material deposited at the etched first material layer of the second semiconductor structure can form a first inner sidewall, the dielectric material deposited at the etched first material layer of the first semiconductor structure can form a second inner sidewall, and the dielectric material deposited at the etched pseudo-gate structure can form a sidewall. Among them, the isolation layer can also be called a middle dielectric isolation (MDI) layer, and the MDI layer serves as an isolation structure between the front transistors and the back transistors.

[0065] It can be understood that the sidewalls are located on both sides of the pseudo-gate structure, the first inner sidewalls are located on both sides of the first material layer of the second semiconductor structure, that is, the first inner sidewalls are the sidewalls of the gate structure of the first ring-gate transistor, and the second inner sidewalls are located on both sides of the first material layer of the first semiconductor structure, that is, the second inner sidewalls are the sidewalls of the gate structure of the second ring-gate transistor. Exemplarily, the sidewalls may have a single-layer structure and are made of the same material as a whole, such as porous carbon silicon oxyhydride (SICOH), etc.

[0066] In the embodiments of the present application, the originally separate MDI process, inner spacer process, and gate spacer process are integrated, and the MDI layer and the inner spacer are formed simultaneously during the formation of the gate spacer, so that redundant process steps and process complexity can be reduced.

[0067] In some embodiments, after forming the gate spacer, MDI layer, and inner spacer, the protective layer on the pseudo-gate structure may be removed.

[0068] Step S106: On one side of the isolation layer having the first inner wall and the side wall, form a first gate-all-around transistor based on the second semiconductor structure.

[0069] It can be understood that since the isolation layer is located in the middle of the first semiconductor structure and the second semiconductor structure, a front transistor can be fabricated on one side of the isolation layer, and a back transistor can be fabricated on the other side of the isolation layer. The first inner wall is located on both sides of the first material layer of the second semiconductor structure, the second inner wall is located on both sides of the first material layer of the first semiconductor structure, and the side wall is located above the first inner wall. Therefore, taking the isolation layer as the boundary, one side of the isolation layer has the first inner wall, the side wall and the second semiconductor structure, and the other side of the isolation layer has the second inner wall and the first semiconductor structure. In this way, first, on the side of the isolation layer having the first inner wall and the side wall, a first gate-all-around transistor can be formed based on the second semiconductor structure.

[0070] In some embodiments, the implementation process of forming the first gate-all-around transistor based on the second semiconductor structure can be as follows: Remove the semiconductor structure in the source / drain region, and fill the insulating material in the corresponding first source / drain region of the first semiconductor structure to form a filling structure; epitaxially grow a first source / drain structure at the corresponding second source / drain region of the second semiconductor structure; form a first interlayer dielectric layer on the first source / drain structure; etch the part of the dummy gate structure surrounding the second semiconductor structure to form a first gate structure; etch the first interlayer dielectric layer to expose the first source / drain structure; deposit a metal material on the first source / drain structure to form a first source / drain metal; perform back-end interconnect on the first source / drain metal to form a first metal interconnect layer.

[0071] It can be understood that by etching the semiconductor structure in the source / drain region, both the first semiconductor structure and the second semiconductor structure in the source / drain region can be removed. After the source / drain region is exposed, an insulating material can be filled in the corresponding first source / drain region of the first semiconductor to form a filling structure. In this way, the source / drain region of the back transistor can be defined by the filling structure to achieve self-alignment of the upper and lower transistors in the source / drain region of the flip-chip stacked transistor. Exemplarily, the insulating material can be silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxynitride (SiON), etc.

[0072] In some embodiments, after removing the oxide layer in the source / drain region in step S102, the first semiconductor structure, the first sacrificial layer and the second semiconductor structure in the source / drain region can be removed. Then, etch the first sacrificial layer, laterally etch the first material layer in the first semiconductor structure, the first material layer in the second semiconductor structure and the dummy gate structure to form a gate spacer, an MDI layer and an inner spacer respectively.

[0073] In some embodiments, in the presence of a second sacrificial layer and an isolation structure, after forming the gate spacer, the MDI layer, and the inner spacer, the second sacrificial layer and the isolation structure within the source / drain regions may be removed to fully expose the entire source / drain regions.

[0074] In some embodiments, in the presence of an MDI layer, when forming the filling structure, the filling structure may cover a portion of the MDI layer.

[0075] It can be understood that after etching the semiconductor structure within the source / drain regions, a source / drain groove is formed. Thus, source / drain epitaxial growth may be performed at the source / drain groove to form a first source / drain structure. After forming the first source / drain structure, an interlayer dielectric may be deposited on the first source / drain structure and thinned to the upper surface of the first source / drain structure to form a first interlayer dielectric layer.

[0076] Exemplarily, strained materials such as silicon germanium or silicon carbide may be formed by selective epitaxial growth in the source / drain groove to fill the source / drain grooves of the front transistors (first gate-all-around transistors), and then a first source / drain structure may be formed on the strained materials through a heavy doping process. Exemplarily, the interlayer dielectric may be SiO 2 。

[0077] For ease of description, the first source / drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. In addition, the first source / drain metal, the second source / drain structure, the second source / drain metal, etc. mentioned subsequently are similar to the first source / drain structure, where "source / drain" is an abbreviation for "source and / or drain".

[0078] After forming the first interlayer dielectric layer, the portion of the dummy gate structure surrounding the second semiconductor structure may be removed to form the first gate structure of the first gate-all-around transistor.

[0079] It can be understood that the dummy gate structure of the first gate-all-around transistor formed above is removed through an etching process to obtain a first gate groove. An insulating material is deposited at the first gate groove to form a first gate dielectric layer, and a metal material is deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate dielectric layer and the first gate electrode layer together constitute the first gate structure.

[0080] Exemplarily, the first gate dielectric layer may be composed of a silicon oxide layer and a high-K hafnium oxide layer, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor. The first gate electrode layer may be composed of multiple layers of electrode materials, and each layer of electrode material includes, but is not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0081] In some embodiments, the portion of the dummy gate structure surrounding the second semiconductor structure may also be etched; a gate isolation dielectric layer is formed on the remaining dummy gate structure; on the gate isolation dielectric layer, the first material layer in the second semiconductor structure is etched to form a first active structure; based on the first active structure, a first gate structure is formed.

[0082] It can be understood that after etching the dummy gate structure of the first gate-all-around transistor, an insulating material may be deposited on the remaining dummy gate structure of the second gate-all-around transistor, and then the insulating material is anisotropically etched to the bottom of the second semiconductor structure, and then the insulating material is isotropically etched to form a gate isolation dielectric layer. Then, a first gate dielectric layer and a first gate electrode layer are sequentially formed on the gate isolation dielectric layer to form a first gate structure.

[0083] In some embodiments, since the second semiconductor structure includes a first material layer and a second material layer stacked in sequence, when removing the portion of the dummy gate structure surrounding the second semiconductor structure, the oxide layer surrounding the second semiconductor structure and the first material layer in the second semiconductor structure may be removed together to form the first active structure of the first gate-all-around transistor. Then, an insulating material is deposited on the surface of the first active structure to form a first gate dielectric layer, and a metal material is deposited on the first gate dielectric layer to form a first gate electrode layer. The first active structure may also be referred to as a first nanosheet structure.

[0084] In some embodiments, the portion of the dummy gate structure surrounding the second semiconductor structure may be removed by high-temperature oxidation first, and then the oxide layer surrounding the second semiconductor structure and the first material layer in the second semiconductor structure are removed. In this way, when the portion of the dummy gate structure surrounding the second semiconductor structure is removed by high-temperature oxidation, the oxide layer can protect the channel from the influence of high temperature.

[0085] It can be understood that after forming the gate structure, a portion of the first interlayer dielectric layer may be etched to expose the first source / drain structure, and then a metal material is deposited on the first source / drain structure to form a first source / drain contact metal. After forming the first source / drain contact metal, back-end processes may be performed to form a first metal interconnection layer.

[0086] It can be understood that the back-end processes may exemplarily be processes such as inter-metal dielectric deposition, metal line formation, and lead pad formation.

[0087] It should be noted that the first source / drain structure, the first interlayer dielectric layer, the first gate structure, the first source / drain metal, and the first metal interconnection layer can all be formed by standard steps of semiconductor manufacturing processes, and the embodiments of the present application do not make specific limitations thereto.

[0088] In some embodiments, a source / drain isolation dielectric layer may be formed on the filling structure, and the height of the source / drain isolation dielectric layer is the same as that of the isolation layer; on the source / drain isolation dielectric layer, a first source / drain structure is formed.

[0089] It can be understood that after the filling structure is formed, an insulating material may be deposited on the filling structure and thinned so that the upper surface of the formed source / drain isolation structure is flush with the upper surface of the MDI layer. Then, a first gate-all-around transistor is fabricated on the source / drain isolation dielectric layer.

[0090] In some embodiments, after the first gate structure of the first gate-all-around transistor is formed, a first gate cut-off structure may be formed on both sides of the first gate structure, and the first gate cut-off structure is used to isolate the gate region of the stacked transistor from the gate region of the adjacent stacked transistor.

[0091] It can be understood that after the first gate structure is formed, gate cutting may be performed on the first gate structure to form a first gate cut-off groove; an insulating material is filled in the first gate cut-off groove to form a first gate cut-off structure.

[0092] Exemplarily, a photoresist may be coated on the upper surface of the first gate structure. After the photoresist is exposed and developed (i.e., a photoresist layer is formed), a notch is formed at a preset position, where the notch corresponds to the gate cut-off region of the first gate-all-around transistor. Then, using the photoresist layer as a mask, a part of the first gate structure is etched to form a first gate cut-off groove. After the first gate cut-off groove is formed, the first gate cut-off groove may be filled with an insulating material to form a first gate cut-off structure on both sides of the first gate structure.

[0093] It should be noted that the width of the first gate cut-off groove (i.e., the size of the notch of the photoresist layer) can be designed according to actual situations, but the second semiconductor structure cannot be etched. The embodiments of the present application do not limit this.

[0094] In some embodiments, before the first source / drain metal is formed, a first dielectric layer may be formed on the first gate structure and the first interlayer dielectric layer.

[0095] It can be understood that an insulating material can be deposited on the first gate structure and the first interlayer dielectric layer to form a first dielectric layer, which can also be referred to as a pre-metal dielectric (PMD) layer. The PMD layer has the following two functions: (1) Electrical isolation. The PMD layer electrically isolates the transistor device and the metal interconnect layer, preventing current from flowing in unwanted paths and ensuring the normal operation of the circuit. (2) Physical protection. The PMD layer can block impurity sources such as mobile particles (e.g., sodium ions), prevent the impurity sources from affecting the performance of the transistor device, and protect the device from the external environment. Among them, the insulating material for forming the PMD layer can be, for example, SiO 2 , SiN and other materials.

[0096] In some embodiments, after forming the first gate-all-around transistor based on the second semiconductor structure, the first gate-all-around transistor can be flipped and the substrate can be removed to expose the first semiconductor structure; based on the first semiconductor structure, a second gate-all-around transistor can be formed.

[0097] It can be understood that after forming the first gate-all-around transistor, the first gate-all-around transistor can be bonded to a carrier wafer, and then the first gate-all-around transistor can be flipped for subsequent preparation of a backside transistor.

[0098] In some embodiments, an insulating material (such as silicon oxide) can be deposited on the first metal interconnect layer to form a first insulating layer, and the first insulating layer can be bonded to a carrier wafer, and then the first gate-all-around transistor can be flipped.

[0099] In some embodiments, after flipping the first gate-all-around transistor, the substrate can be removed; the isolation structure can be removed to form a third groove; a semiconductor material can be filled in the third groove so that the upper surface of the formed dummy gate structure is flush with the upper surface of the second sacrificial layer; based on the first semiconductor structure, a second gate-all-around transistor can be formed.

[0100] It can be understood that since there is still a second sacrificial layer and the isolation structures on both sides of the second sacrificial layer in the gate region of the backside transistor, after removing the substrate, the isolation structures in the gate region can be removed to expose the second sacrificial layer. Then, materials such as polysilicon can be deposited on both sides of the exposed second sacrificial layer so that the formed dummy gate structure can completely define the gate region of the backside transistor.

[0101] In some embodiments, after filling a semiconductor material in the third groove so that the upper surface of the formed dummy gate structure is flush with the upper surface of the second sacrificial layer, the second sacrificial layer can be selectively removed.

[0102] Step S107: On one side of the isolation layer having the second inner sidewall, a second gate-all-around transistor is formed based on the first semiconductor structure.

[0103] In some embodiments, after removing the substrate, the filling structure may be etched selectively by material to expose the first source / drain region of the back-side transistor.

[0104] It can be understood that since the filling structure covers the first source / drain region of the back-side transistor, when fabricating the back-side transistor, the filling structure may be etched selectively by material to expose the first source / drain region. Since the filling structure is used to locate the source / drain region where the back-side transistor is located, subsequently when fabricating the back-side transistor, there is no need to select a region through photolithography, and the source / drain region can be directly opened by material selectivity to fabricate a back-side transistor that is completely self-aligned with the front-side transistor.

[0105] In some embodiments, the implementation process of forming the second surrounding-gate transistor based on the first semiconductor structure may be as follows: epitaxially grow a second source / drain structure at the first source / drain region; form a second interlayer dielectric layer on the second source / drain structure; etch the part of the dummy gate structure surrounding the first semiconductor structure to form a second gate structure; etch the second interlayer dielectric layer to expose the second source / drain structure; deposit a metal material on the second source / drain structure to form a second source / drain metal; perform back-end interconnect on the second source / drain metal to form a second metal interconnect layer.

[0106] It can be understood that after etching the filling structure in the first source / drain region, a source / drain groove will be formed. Therefore, source / drain epitaxial growth may be performed at the source / drain groove to form a second source / drain structure. After forming the second source / drain structure, an interlayer dielectric may be deposited on the second source / drain structure and thinned to the upper surface of the second source / drain structure to form a second interlayer dielectric layer. Then, the dummy gate structure of the second surrounding-gate transistor formed above may be removed, an insulating material may be deposited on the exposed surface of the second semiconductor structure to form a second gate dielectric layer, and a metal material may be deposited on the second gate dielectric layer to form a second gate electrode layer. The second gate dielectric layer and the second gate electrode layer together constitute the second gate structure.

[0107] In some embodiments, since the first semiconductor structure includes a first material layer and a second material layer stacked in sequence, when removing the part of the dummy gate structure surrounding the first semiconductor structure, the oxide layer surrounding the first semiconductor structure and the first material layer in the first semiconductor structure may be removed together to form the second active structure of the second surrounding-gate transistor. Then, an insulating material is deposited on the surface of the second active structure to form a second gate dielectric layer, and a metal material is deposited on the second gate dielectric layer to form a second gate electrode layer.

[0108] After forming the second gate structure, a portion of the second interlayer dielectric layer may be etched to expose the second source / drain structure, and then a metal material is deposited on the second source / drain structure to form the second source / drain metal. After forming the second source / drain metal, back-end processes may be performed to form the second metal interconnect layer.

[0109] In some embodiments, after forming the second gate structure of the second surrounding gate transistor, second gate cut-off structures may be formed on both sides of the second gate structure.

[0110] In some embodiments, before forming the second source / drain metal, a second dielectric layer may be formed on the second gate structure and the second interlayer dielectric layer.

[0111] It should be noted that the preparation methods of the second source / drain structure, the second interlayer dielectric layer, the second gate structure, the second source / drain metal, the second metal interconnect layer, the second gate cut-off structure, and the second dielectric layer of the second surrounding gate transistor are the same as those of the first source / drain structure, the first interlayer dielectric layer, the first gate structure, the first source / drain metal, the first metal interconnect layer, the first gate cut-off structure, and the first dielectric layer in the first surrounding gate transistor, and will not be elaborated here.

[0112] In the embodiments of the present application, a first semiconductor structure, a first sacrificial layer, and a second semiconductor structure are sequentially stacked on a substrate. A semiconductor material is deposited in the gate region to form a dummy gate structure, and then the first sacrificial layer is removed to form a first groove. The first material layer in the first semiconductor structure, the first material layer in the second semiconductor structure, and the portion of the dummy gate structure that is higher than the first semiconductor structure, the first sacrificial layer, and the second semiconductor structure are etched along a first direction to form a second groove. Then, a dielectric material is deposited in the first groove and the second groove to form an isolation layer at the position where the first sacrificial layer is removed, a first inner sidewall at the position where the first material layer in the second semiconductor structure is etched, a second inner sidewall at the position where the first material layer in the first semiconductor is etched, and sidewalls at the position where the portion of the dummy gate structure that is higher than the first semiconductor structure, the first sacrificial layer, and the second semiconductor structure is etched. On one side of the isolation layer having the first inner sidewall and the sidewalls, a first surrounding gate transistor is formed based on the second semiconductor structure; on the side of the isolation layer having the second inner sidewall, a second surrounding gate transistor is formed based on the first semiconductor structure. Therefore, in the embodiments of the present application, the same dielectric material is used to simultaneously form the isolation layer, the inner sidewalls, and the sidewalls, which can reduce redundant process steps and process complexity.

[0113] Taking the active structure in the stacked transistor as a nanosheet structure as an example, the preparation method of the stacked transistor provided in the embodiments of the present application will be described below. Figure 2It is a top view schematic diagram of the stacked transistor in the embodiment of the present application. It should be noted that for ease of understanding, only the nanosheet structure, gate structure, and source-drain structure are shown in the top view. Among them, the A-A' direction is the cross-section direction of the stacked transistor along the gate structure; the B-B' direction is the cross-section direction of the stacked transistor along the source-drain structure; the C-C' direction is the cross-section direction of the stacked transistor along the nanosheet structure.

[0114] Next, the preparation process of the stacked transistor provided by the embodiment of the present application will be introduced. Figures 3A to 3L It is a schematic structural diagram of the stacked transistor in the preparation process of the embodiment of the present application. Figure 4 It is a schematic structural diagram of the stacked transistor in the embodiment of the present application.

[0115] The first step: form a fourth sacrificial layer 21 on the original substrate 20, form a stacked layer 22 on the fourth sacrificial layer 21, form a third sacrificial layer 23 on the stacked layer 22, and then form a stacked layer 22 on the third sacrificial layer 23 (see (a) in Figure 3A .

[0116] Exemplarily, a Si layer can be provided, deposit SiGe 3 material on the Si layer to form the fourth sacrificial layer, and then alternately deposit SiGe2 material and Si material on the fourth sacrificial layer to form a stacked layer with a preset thickness. Then deposit SiGe 1 material on the stacked layer to form the third sacrificial layer, and alternately deposit SiGe2 material and Si material on the third sacrificial layer to form a stacked layer with a preset thickness. It should be noted that the SiGe1 material, SiGe2 material, and SiGe3 material here are only an exemplary description, and actually other materials can also be used.

[0117] The second step: etch the stacked layer 22, the third sacrificial layer 23, and the fourth sacrificial layer 21 in sequence until the substrate 20 to form a semiconductor structure 24 (see (b) in Figure 3A .

[0118] It can be understood that through etching, a second sacrificial layer 244, a first semiconductor structure 241 close to the substrate, a second semiconductor structure 242 far from the substrate, and a first sacrificial layer 243 can be formed.

[0119] The third step: deposit an insulating material on the substrate 20 to form an isolation structure 25, and perform CMP and selective etching until the upper surface of the isolation structure is flush with the upper surface of the second sacrificial layer 244 (see (c) in Figure 3A .

[0120] The fourth step: form an oxide layer 26 on the substrate 20 (see (a) in Figure 3B .

[0121] It is understandable that the oxide layer 26 is a thin film deposited on the surface of the semiconductor structure 24.

[0122] Step 5: Deposit materials such as polysilicon on the oxide layer 26 to form a dummy gate structure 27 shared by the front and back sides, and form a protective layer 28 on the dummy gate structure 27 (see (b) in Figure 3B .

[0123] It is understandable that by defining the gate regions of the front and back transistors in the stacked transistor through the dummy gate structure, self-alignment of the upper and lower transistors in the stacked transistor in the gate region can be achieved.

[0124] Step 6: Etch and remove the oxide layer 26 on the semiconductor structure in the source-drain region (see (c) in Figure 3B .

[0125] Step 7: Etch and remove the first semiconductor structure 241, the second semiconductor structure 242, and the first sacrificial layer 243 in the source-drain region (see (a) in Figure 3C .

[0126] Step 8: Isotropically etch the first sacrificial layer 243 to form a first groove 281 (see (b) in Figure 3C .

[0127] Step 9: Laterally etch the SiGe 2 material in the first semiconductor structure and the second semiconductor structure to form a second groove 282 to reserve space for the inner spacer (see (c) in Figure 3C .

[0128] Step 10: Laterally etch the dummy gate structure to form a second groove 282 to reserve space for the gate spacer (see (a) in Figure 3D .

[0129] Step 11: Isotropically deposit a dielectric material (see (b) in Figure 3D .

[0130] Step 12: Anisotropically etch the dielectric material in the source-drain region to form an MDI layer 29, a first inner sidewall 30, a second inner sidewall 31, and a sidewall 32 (see (c) in Figure 3D .

[0131] It should be noted that the thickness of the MDI layer 29 does not exceed twice the thickness of the sidewall 32, otherwise voids are likely to occur inside the MDI layer during isotropic deposition.

[0132] Step 13: Etch the protective layer 28 (see (a) in Figure 3E .

[0133] Step 14: Anisotropically etch the second sacrificial layer 244 and the isolation structure 25 in the source / drain regions (see (b) in Figure 3E ).

[0134] Step 15: Fill the source / drain regions with an insulating material to form a filling structure 33 that covers the source / drain regions of the back transistors (see (c) in Figure 3E ).

[0135] Step 16: Form a source / drain isolation dielectric layer 34 on the filling structure 33 (see (a) in Figure 3F ).

[0136] Step 17: Form the first source / drain structure 112 of the front transistors (see (b) in Figure 3F ).

[0137] Step 18: Deposit an interlayer dielectric in the source / drain regions and etch back to form the first interlayer dielectric layer 113 (see (c) in Figure 3F ).

[0138] Step 19: Etch the part of the dummy gate structure 27 that surrounds the second semiconductor structure (see (a) in Figure 3G ).

[0139] Step 20: Form a gate isolation dielectric layer 35 on the remaining dummy gate structure (see (b) in Figure 3G ).

[0140] It can be understood that the dummy gate structure can be oxidized at a high temperature, and the channel will not be affected due to the protection of the oxide layer 26.

[0141] Step 21: Remove the oxide layer surrounding the second semiconductor structure and the SiGe 2 material in the second semiconductor structure to form the first nanosheet structure 111, and form the first gate structure 114 of the front transistors based on the first nanosheet structure 111 (see (c) in Figure 3G ).

[0142] It can be understood that an insulating material is deposited on the surface of the first nanosheet structure 111 to form the first gate dielectric layer 1141, and a metal material is deposited on the first gate dielectric layer 1141 in the gate region to form the first gate electrode layer 1142. The first gate dielectric layer 1141 and the first gate electrode layer 1142 constitute the first gate structure 114.

[0143] Step 22: Form first gate cutoff structures 36 on both sides of the first gate structure (see (a) in Figure 3H ).

[0144] Step 23: Form a first dielectric layer 37 on the first gate structure 114 and the first interlayer dielectric layer 113, and form a first source / drain metal 115 on the first source / drain structure 112 (see (b) in Figure 3H ).

[0145] Step 24: Form a first metal interconnect layer 116 (see (c) in Figure 3H ).

[0146] Step 25: Deposit an insulating material on the first metal interconnect layer 116 to form an insulating layer 13. After bonding the carrier wafer 14 to the insulating layer 13, flip the first gate-all-around transistor (see (a) in Figure 3I ).

[0147] Step 26: Thin and CMP to remove the substrate 20 (see (b) in Figure 3I ).

[0148] Step 27: Selectively etch the isolation structure 25 in the gate region to form a third groove 371 (see (c) in Figure 3I ).

[0149] Step 28: Fill the third groove 371 with materials such as polysilicon to supplement the previously formed dummy gate structure (see (a) in Figure 3J ).

[0150] Step 29: Remove the filling structure 33 (see (b) in Figure 3J ).

[0151] Step 30: Form a second source / drain structure 122 and a second interlayer dielectric layer 123 of the backside transistor (see (c) in Figure 3J ).

[0152] Step 31: Etch to remove the dummy gate structure of the backside transistor (see (a) in Figure 3K ).

[0153] Step 32: Fill the etched area with an insulating material to supplement the previously formed gate isolation dielectric layer (see (b) in Figure 3K ).

[0154] It can be understood that by oxidizing the exposed dummy gate structure, an oxide can be formed, so that the oxide serves as the isolation between the front and back gate structures, and the oxide layer 26 protects the channel during this thermal process.

[0155] Step 33: Remove the second sacrificial layer 244, the oxide layer surrounding the first semiconductor structure, and the SiGe 2 material in the first semiconductor structure to form the second nanosheet structure 121, and form the second gate structure 124 of the back transistor based on the second nanosheet structure 121 (see Figure 3K in (c)).

[0156] It can be understood that an insulating material is deposited on the surface of the second nanosheet structure 121 to form the second gate dielectric layer 1241, and a metal material is deposited on the second gate dielectric layer 1241 to form the second gate electrode layer 1242. The second gate dielectric layer 1241 and the second gate electrode layer 1242 constitute the second gate structure 124.

[0157] Step 34: Form second gate cut-off structures 38 on both sides of the second gate structure 124 (see Figure 3L in (a)).

[0158] Step 35: Form a second dielectric layer 39 on the second gate structure 124 and the second interlayer dielectric layer 123, and form a second source / drain metal 125 on the second source / drain structure 122 (see Figure 3L in (b)).

[0159] Step 36: Form a second metal interconnect layer 126 (see Figure 4 ).

[0160] In the embodiments of the present application, the originally separate inner spacer process, MDI process, and gate spacer process are integrated. After performing gate spacer, inner spacer void etching and MDI sacrificial layer removal, an isotropic deposition of a dielectric material is performed and anisotropic etching is carried out to fill the void between the channels of the front transistor and the back transistor to form the MDI layer, and fill the lateral etching voids to form the gate spacer and the inner spacer. The same dielectric material is used to simultaneously form the gate spacer, inner spacer, and MDI layer, reducing redundant process steps and lowering the process complexity; at the same time, it avoids the problem that the dielectric material in the MDI process and the inner spacer process is not easy to etch back. The method of the embodiments of the present application is beneficial to improving the process success rate and the electrical performance of the transistor.

[0161] Furthermore, the stacked transistors provided by the embodiments of the present application can be detected using detection and analysis instruments, such as: scanning electron microscope (SEM), transmission electron microscope (TEM), scanning transmission electron microscopy (STEM), etc. Taking TEM as an example, the embodiments of the present application can adopt the method of TEM sectioning to detect the structure of the above-mentioned stacked transistors.

[0162] The embodiments of the present application provide a semiconductor device, including: the stacked transistors as described in the above embodiments.

[0163] The embodiments of the present application provide an electronic device, including: a circuit board and the semiconductor device as described in the above embodiments. The semiconductor device is disposed on the circuit board, and the semiconductor device includes the above-mentioned stacked transistors.

[0164] In the description of the embodiments of the present application, the descriptions with reference to terms such as "one embodiment", "an embodiment", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic expressions of the above terms are not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine the different embodiments or examples described in the present application and the features of the different embodiments or examples.

[0165] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a stacked transistor, characterized in that: The method comprises: A semiconductor structure is formed on a substrate, wherein the semiconductor structure includes a first semiconductor structure, a first sacrificial layer, and a second semiconductor structure sequentially stacked along a first direction, the first semiconductor structure includes a first material layer and a second material layer sequentially stacked along the first direction, and the second semiconductor structure includes a first material layer and a second material layer sequentially stacked along the first direction; Depositing a semiconductor material in the gate region to form a dummy gate structure, wherein the dummy gate structure surrounds the second semiconductor structure, the first sacrificial layer, and the first semiconductor structure, and the height of the dummy gate structure is higher than the height of the semiconductor structure; removing the first sacrificial layer to form a first groove; Etching the first material layer in the first semiconductor structure, the first material layer in the second semiconductor structure, and a portion of the dummy gate structure higher than the semiconductor structure along a second direction to form a second groove, wherein the second direction is a direction perpendicular to the first direction; Depositing dielectric material in the first groove and the second groove to respectively form an isolation layer at a position where the first sacrificial layer is removed, a first inner sidewall at a position where the first material layer in the second semiconductor structure is etched, a second inner sidewall at a position where the first material layer in the first semiconductor is etched, and a sidewall at a position where a portion of the dummy gate structure higher than the semiconductor structure is etched; On one side of the isolation layer having the first inner sidewall and the sidewall, a first gate-all-around transistor is formed based on the second semiconductor structure; A second all-around gate transistor is formed on a side of the isolation layer having the second inner sidewall based on the first semiconductor structure.

2. The method according to claim 1, characterized in that The step of depositing dielectric material in the first groove and the second groove to respectively form an isolation layer at a position where the first sacrificial layer is removed, a first inner sidewall at a position where the first material layer in the second semiconductor structure is etched, a second inner sidewall at a position where the first material layer in the first semiconductor is etched, and a sidewall at a position where a portion of the dummy gate structure higher than the semiconductor structure is etched, comprises: Depositing a dielectric material on the substrate so that the dielectric material covers the dummy gate structure; The dielectric material in the source and drain regions is anisotropically etched to form the isolation layer, the first inner sidewall, the second inner sidewall and the sidewall, respectively.

3. The method according to claim 1, characterized in that: The step of forming a first gate-all-around transistor based on the second semiconductor structure comprises: Removing the semiconductor structure in the source-drain region, and filling the first source-drain region corresponding to the first semiconductor structure with an insulating material to form a filling structure; epitaxially growing a first source-drain structure at a second source-drain region corresponding to the second semiconductor structure; forming a first interlayer dielectric layer on the first source-drain structure; Etching a portion of the dummy gate structure surrounding the second semiconductor structure to form a first gate structure; Etching the first interlayer dielectric layer to expose the first source-drain structure; Depositing a metal material on the first source-drain structure to form a first source-drain metal; Back-end interconnection is performed on the first source-drain metal to form a first metal interconnection layer.

4. The method according to claim 3, characterized in that The method further comprises: forming a source-drain isolation dielectric layer on the filling structure, wherein the height of the source-drain isolation dielectric layer is the same as the height of the isolation layer; The first source-drain structure is formed on the source-drain isolation dielectric layer.

5. The method according to claim 3, characterized in that: The etching of a portion of the dummy gate structure surrounding the second semiconductor structure to form a first gate structure includes: Etching a portion of the dummy gate structure surrounding the second semiconductor structure; forming a gate isolation dielectric layer on the retained dummy gate structure; On the gate isolation dielectric layer, etching the first material layer in the second semiconductor structure to form a first active structure; Based on the first active structure, the first gate structure is formed.

6. The method according to claim 1, characterized in that The semiconductor structure further includes a second sacrificial layer, the second sacrificial layer is located between the substrate and the first semiconductor structure, two sides of the second sacrificial layer are isolation structures, and the height of the isolation structure is the same as the height of the second sacrificial layer; After forming a first gate-all-around transistor based on the second semiconductor structure, the method further includes: Flipping the first gate-all-around transistor, and removing the substrate; removing the isolation structure to form a third groove; Filling the third groove with semiconductor material so that the upper surface of the formed dummy gate structure is flush with the upper surface of the second sacrificial layer; The second gate-all-around transistor is formed based on the first semiconductor structure.

7. The method according to claim 3, characterized in that After forming the first gate structure, the method further includes: A gate cut-off structure is formed on both sides of the first gate structure, and the gate cut-off structure is used to isolate the gate region of the stacked transistor from the gate region of the adjacent stacked transistor.

8. A stacked transistor, prepared using the preparation method according to any one of claims 1 to 7, characterized in that: include: a first gate-all-around transistor; The second all-round gate transistor is stacked with the first all-round gate transistor and the second all-round gate transistor, and the first all-round gate transistor and the second all-round gate transistor are self-aligned.

9. A semiconductor device, characterized in that: include: The stacked transistor as claimed in claim 8.

10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.

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