Method for preparing semiconductor device

Abstract

The present application provides a method for preparing a semiconductor device, belonging to the field of semiconductor technology. The method comprises forming a first gate structure and a second gate structure on a first device region and a second device region of a substrate; forming a first stress buffer layer on the substrate, the first gate structure, and the second gate structure; forming a first patterned photoresist layer on the first stress buffer layer in the second device region, and performing ion implantation on the substrate on both sides of the first gate structure; removing the first patterned photoresist layer; forming a second patterned photoresist layer on the first stress buffer layer in the first device region, and performing ion implantation on the substrate on both sides of the second gate structure; and removing the second patterned photoresist layer. The first stress buffer layer can isolate basic groups on the surfaces of the first and second gate structures, thereby preventing footing and undercutting problems in the first and second patterned photoresist layers, without increasing the complexity of the process.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor device. Background Art

[0002] Currently, the source / drain doping process is performed after the gate sidewalls are formed. Prior to this, a photolithography process is performed to expose the source / drain regions. During the photolithography process, changes in the substrate's surface acidity and alkalinity directly affect the photoresist profile. However, since the gate sidewall material is typically nitride, which contains a strong alkalinity, this neutralizes the photoacid generated during the photolithography exposure process, resulting in incomplete development on both sides of the photoresist bottom, causing PR footing. Figure 1 Schematic diagram of generating footings on both sides of the bottom of the photoresist, from Figure 1 It can be seen that there are obvious photoresist residues on both sides of the bottom of the photoresist, which will have a great impact on the source and drain doping process.

[0003] In theory, to prevent the formation of footing on the bottom and sides of the photoresist, the substrate surface can be treated with an acidic gas (such as nitrous oxide) before spin coating to consume the basic groups on the substrate surface and increase the pH of the substrate surface. However, in actual manufacturing processes, the acidic gas will instantly consume a large number of basic groups, resulting in excessive photoacid during the photolithography process, causing overexposure on the bottom and sides of the photoresist, resulting in undercut (PR undercut). Figure 2 Schematic diagram of the undercut on both sides of the bottom of the photoresist. Figure 2 As can be seen in the figure, there are obvious defects on both sides of the bottom of the photoresist, which will also have a great impact on the source and drain doping process. Summary of the Invention

[0004] In view of this, the embodiments of the present application are directed to providing a method for preparing a semiconductor device to solve the problem in the prior art that the photoresist layer is prone to footing and undercutting.

[0005] In one aspect, the present application provides a method for preparing a semiconductor device, comprising:

[0006] Providing a substrate having a first device region and a second device region;

[0007] forming a first gate structure and a second gate structure on the substrate, wherein the first gate structure and the second gate structure are respectively located in the first device region and the second device region;

[0008] forming a first stress buffer layer on the substrate, the first gate structure, and the second gate structure;

[0009] forming a first patterned photoresist layer on the first stress buffer layer in the second device region, and performing ion implantation on the substrate on both sides of the first gate structure;

[0010] removing the first patterned photoresist layer;

[0011] forming a second patterned photoresist layer on the first stress buffer layer in the first device region, and performing ion implantation on the substrate at both sides of the second gate structure; and

[0012] The second patterned photoresist layer is removed.

[0013] In some embodiments, the material of the first stress buffer layer is oxide.

[0014] In some embodiments, the thickness of the first stress buffer layer is less than or equal to 100 nm.

[0015] In some embodiments, the first gate structure and the second gate structure both include a gate oxide layer, a gate conductive layer, a gate shielding layer and a gate sidewall, the gate oxide layer, the gate conductive layer and the gate shielding layer are stacked on the substrate from bottom to top, the gate sidewall at least covers the sidewalls of the gate oxide layer, the gate conductive layer and the gate shielding layer, and the outermost layer of the gate sidewall is made of nitride.

[0016] In some embodiments, the gate sidewall includes at least a first sidewall structure and a second sidewall structure, the first sidewall structure covers the sidewalls of the gate oxide layer, the gate conductive layer and the gate shielding layer, the second sidewall structure includes an oxide layer and a nitride layer, the oxide layer conformally covers the substrate, the sidewalls of the first sidewall structure and the top surface of the gate shielding layer, the nitride layer is located on the portion of the sidewall covered by the oxide layer, and when ion implantation is performed on the substrate on both sides of the first gate structure and ion implantation is performed on the substrate on both sides of the second gate structure, the portion of the oxide layer covering the substrate serves as an injection barrier layer.

[0017] In some embodiments, after removing the second patterned photoresist layer, the preparation method further includes:

[0018] forming a stress-introducing layer on the first stress buffer layer and performing an annealing process; and,

[0019] The stress-introducing layer and the first stress buffer layer are removed.

[0020] In some embodiments, after removing the second patterned photoresist layer, the preparation method further includes:

[0021] removing the first stress buffer layer;

[0022] forming a second stress buffer layer on the substrate, the first gate structure, and the second gate structure, wherein the thickness of the second stress buffer layer is greater than the thickness of the first stress buffer layer;

[0023] forming a stress-introducing layer on the second stress buffer layer and performing an annealing process; and,

[0024] The stress-introducing layer and the second stress buffering layer are removed.

[0025] In some embodiments, after removing the second patterned photoresist layer, the preparation method further includes:

[0026] forming a third stress buffer layer on the first stress buffer layer;

[0027] forming a stress-introducing layer on the third stress buffer layer and performing an annealing process; and,

[0028] The stress-introducing layer, the third stress buffer layer, and the first stress buffer layer are removed.

[0029] In some embodiments, one of the first device region and the second device region is an NMOS device region, and the other is a PMOS device region.

[0030] In some embodiments, the NMOS device region includes an NMOS device core unit region and an NMOS device peripheral region, the PMOS device region includes a PMOS device core unit region and a PMOS device peripheral region, and the substrates of the NMOS device core unit region, the NMOS device peripheral region, the PMOS device core unit region, and the PMOS device peripheral region all have the first gate structure or the second gate structure.

[0031] In some embodiments, an embedded epitaxial layer is provided in the substrate of the PMOS device region, and the ion implantation into the substrate of the PMOS device region includes ion implantation into the embedded epitaxial layer.

[0032] The present application provides a method for preparing a semiconductor device, comprising providing a substrate having a first device region and a second device region; forming a first gate structure and a second gate structure on the substrate, the first gate structure and the second gate structure being located in the first device region and the second device region, respectively; forming a first stress buffer layer on the substrate, the first gate structure, and the second gate structure; forming a first patterned photoresist layer on the first stress buffer layer in the second device region, and performing ion implantation on the substrate on both sides of the first gate structure; removing the first patterned photoresist layer; forming a second patterned photoresist layer on the first stress buffer layer in the first device region, and performing ion implantation on the substrate on both sides of the second gate structure; and removing the second patterned photoresist layer. The unexpected effect of the present application is that a first stress buffer layer is directly formed after the first gate structure and the second gate structure are formed. The first stress buffer layer can isolate the basic groups on the surfaces of the first gate structure and the second gate structure, and the surface of the first stress buffer layer is relatively stable without broken bonds, which can avoid the consumption of photoacid during exposure, thereby avoiding the problems of footing and undercutting of the first patterned photoresist layer and the second patterned photoresist layer, and improving the morphology of the first patterned photoresist layer and the second patterned photoresist layer; moreover, the first stress buffer layer does not need to be removed after the ion implantation process, and can play a stress buffer role in the subsequent stress memory process without increasing the complexity of the process. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of creating footings for the bottom sides of the photoresist.

[0034] Figure 2 Schematic diagram of creating undercuts on both sides of the bottom of the photoresist.

[0035] Figure 3 A flowchart of a method for preparing a semiconductor device provided in accordance with an embodiment of the present invention.

[0036] Figure 4 A schematic structural diagram of forming a first gate structure and a second gate structure on a substrate is provided for one embodiment of the application.

[0037] Figure 5 A schematic structural diagram of forming a first stress buffer layer on a substrate, a first gate structure, and a second gate structure according to an embodiment of the present invention is provided.

[0038] Figure 6 A schematic structural diagram of forming a first patterned photoresist layer on a first stress buffer layer in a second device region according to an embodiment of the present invention.

[0039] Figure 7A schematic structural diagram of ion implantation into the substrate on both sides of the first gate structure according to an embodiment of the present invention.

[0040] Figure 8 A schematic diagram of the structure after removing the first patterned photoresist layer according to an embodiment of the application.

[0041] Figure 9 A schematic structural diagram of forming a second patterned photoresist layer on a first stress buffer layer in a first device region according to an embodiment of the present invention.

[0042] Figure 10 A schematic structural diagram of ion implantation into the substrate on both sides of the second gate structure is provided in accordance with an embodiment of the present invention.

[0043] Figure 11 A schematic diagram of the structure after removing the second patterned photoresist layer according to an embodiment of the application.

[0044] Figure 12 A schematic structural diagram of forming a stress-introducing layer on a first stress buffer layer according to an embodiment of the present invention.

[0045] Figure 13 A schematic diagram of the structure after removing the stress-introducing layer and the first stress buffer layer according to an embodiment of the application.

[0046] Figure 14 A schematic diagram of the structure after removing the portion of the oxide layer covering the substrate and the top surface of the gate shielding layer in the second sidewall structure provided in an embodiment of the application.

[0047] Figure 15 A schematic structural diagram of removing the first stress buffer layer and forming the second stress buffer layer and the stress introduction layer according to an embodiment of the application.

[0048] Figure 16 A schematic structural diagram of forming a third stress buffer layer and a stress introduction layer on a first stress buffer layer according to an embodiment of the present invention.

[0049] Wherein, the accompanying drawings are marked as follows:

[0050] 100-substrate; 110a-NMOS device core unit region; 110b-NMOS device peripheral region; 120a-PMOS device core unit region; 120b-PMOS device peripheral region; 101-trench isolation structure; 102-embedded epitaxial layer; 103-source and drain regions; 200a-first gate structure; 200b-second gate structure; 201-gate oxide layer; 202-gate conductive layer; 203-gate shielding layer; 204-gate sidewall; 300-first stress buffer layer; 401-first patterned photoresist layer; 402-second patterned photoresist layer; 500-stress introduction layer; 600-second stress buffer layer; 700-third stress buffer layer. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0052] An embodiment of the present application provides a method for manufacturing a semiconductor device. Figure 3 A flowchart of a method for preparing a semiconductor device according to an embodiment of the present invention is provided. Figure 3 As shown, the method for preparing a semiconductor device includes:

[0053] Step S100: providing a substrate having a first device region and a second device region;

[0054] Step S200: forming a first gate structure and a second gate structure on a substrate, wherein the first gate structure and the second gate structure are respectively located in a first device region and a second device region;

[0055] Step S300: forming a first stress buffer layer on the substrate, the first gate structure and the second gate structure;

[0056] Step S400: forming a first patterned photoresist layer on the first stress buffer layer in the second device region, and performing ion implantation on the substrate on both sides of the first gate structure;

[0057] Step S500: removing the first patterned photoresist layer;

[0058] Step S600: forming a second patterned photoresist layer on the first stress buffer layer in the first device region, and performing ion implantation on the substrate on both sides of the second gate structure; and

[0059] Step S700: removing the second patterned photoresist layer.

[0060] Figures 4 to 16 The following is a schematic diagram of the structure corresponding to the corresponding steps of the method for preparing the semiconductor device provided in this embodiment. Figures 4 to 16 The method for manufacturing the semiconductor device provided in this embodiment is described in detail.

[0061] like Figure 4 As shown, step S100 is performed to provide a substrate 100. The material of the substrate 100 can be selected from silicon, silicon-on-insulator, germanium, germanium-on-insulator, silicon-germanium, gallium arsenide, or silicon carbide. A trench isolation structure 101 is formed in the substrate 100. The trench isolation structure 101 extends from the substrate 100 into the substrate 100 and is used to define an active area in the substrate 100. Two adjacent active areas are isolated by the trench isolation structure 101.

[0062] The substrate 100 further has a first device region and a second device region. In some embodiments, the first device region may be an NMOS device region, which is used to form an NMOS device. The first device region includes an NMOS device core unit region 110a (also known as an N core region) and an NMOS device peripheral region 110b (also known as an N IO region). The NMOS device core unit region 110a is used to form an NMOS core device, and the NMOS device peripheral region 110b is used to form an NMOS peripheral device. The second device region may be a PMOS device region, which is used to form a PMOS device. The second device region includes a PMOS device core unit region 120a (also known as a P core region) and a PMOS device peripheral region 120b (also known as a P IO region). The PMOS device core unit region 120a is used to form a PMOS core device, and the PMOS device peripheral region 120b is used to form a PMOS peripheral device. The PMOS device core cell region 120 a , the PMOS device peripheral region 120 b , the NMOS device core cell region 110 a , and the NMOS device peripheral region 110 b are isolated from each other by the trench isolation structure 101 .

[0063] It should be noted that Figure 4 The substrate 100 is only schematically shown to have a PMOS device core cell region 120a, a PMOS device peripheral region 120b, an NMOS device core cell region 110a, and an NMOS device peripheral region 110b. The relative positions of the PMOS device core cell region 120a, the PMOS device peripheral region 120b, the NMOS device core cell region 110a, and the NMOS device peripheral region 110b on the substrate 100 are not limited thereto.

[0064] The top of the trench isolation structure 101 can be higher than the surface of the substrate 100 or flush with the surface of the substrate 100. The material of the trench isolation structure 101 is silicon oxide, but it should not be limited to this. In other embodiments, the trench isolation structure 101 can also be other dielectric materials, such as high-K (dielectric constant) dielectrics such as metal oxides.

[0065] In some embodiments, an embedded epitaxial layer 102 is provided in the substrate 100 of the PMOS device core cell region 120a and the PMOS device peripheral region 120b. The embedded epitaxial layer 102 is located in the substrate 100 on both sides of the second gate structure 200b. A silicon cap layer may be provided on the embedded epitaxial layer 102. The embedded epitaxial layer 102 may have a sigma shape, a U shape, or other possible shapes.

[0066] Please continue reading Figure 4 , performing step S200 to form a first gate structure 200a and a second gate structure 200b on the substrate 100. The first gate structure 200a is located in the first device region, and the first gate structure 200a is present on the substrate 100 in both the NMOS device core cell region 110a and the NMOS device peripheral region 110b. The second gate structure 200b is located in the second device region, and the second gate structure 200b is present on the substrate 100 in both the PMOS device core cell region 120a and the PMOS device peripheral region 120b. The first gate structure 200a and the second gate structure 200b have the same structure and can be fabricated simultaneously.

[0067] Furthermore, the first gate structure 200a and the second gate structure 200b each include a gate oxide layer 201, a gate conductive layer 202, a gate shielding layer 203, and a gate spacer 204. The gate oxide layer 201, the gate conductive layer 202, and the gate shielding layer 203 are stacked sequentially from bottom to top on the substrate 100. The gate spacer 204 covers at least the sidewalls of the gate oxide layer 201, the gate conductive layer 202, and the gate shielding layer 203, and the outermost layer of the gate spacer 204 is made of nitride. Specifically, the gate oxide layer 201, the gate conductive layer 202, and the gate shielding layer 203 are all patterned film layers, and the gate spacer 204 can be a single-layer structure or a multi-layer structure.

[0068] In some embodiments, the gate spacer 204 has an ONON (oxide-nitride-oxide-nitride) structure and includes a first spacer structure and a second spacer structure. Both the first and second spacer structures have an ON (oxide-nitride) structure, that is, each comprises an oxide layer and a nitride layer stacked in sequence. The first spacer structure covers the sidewalls of the gate oxide layer 201, the gate conductive layer 202, and the gate shielding layer 203, while the oxide layer in the second spacer structure conformally covers the substrate 100, the sidewalls of the first spacer structure, and the top surface of the gate shielding layer 203. The nitride layer in the second spacer structure is located on the portion of the second spacer structure where the oxide layer covers the first spacer structure. As a result, the outermost layer of the gate spacer 204 is made of nitride (the nitride layer in the second spacer structure), resulting in a surface with a high number of basic groups.

[0069] The steps of forming the first gate structure 200a and the second gate structure 200b may be: depositing a gate oxide material layer, a gate conductive material layer and a gate shielding material layer on the substrate 100 ( Figure 4 (not shown), the gate shielding material layer, the gate conductive material layer, and the gate oxide material layer are then etched until the substrate 100 is exposed. The remaining gate oxide material layer, gate conductive material layer, and gate shielding material layer constitute the gate oxide layer 201, the gate conductive layer 202, and the gate shielding layer 203, respectively. Thereafter, a first spacer material layer (comprising an oxide layer and a nitride layer stacked in sequence) is deposited all over the substrate 100. The first spacer material layer on the substrate 100 and on top of the gate shielding layer 203 is removed, leaving the first spacer material layer on the sidewalls of the gate oxide layer 201, the gate conductive layer 202, and the gate shielding layer 203 to form a first spacer structure. Afterwards, a second spacer material layer (including an oxide layer and a nitride layer stacked in sequence) is deposited all over the substrate 100, and the second spacer material layer conformally covers the substrate 100, the sidewall of the first spacer structure and the top surface of the gate shielding layer 203. Then, the portion of the nitride layer in the second spacer material layer located on the top surface of the substrate 100 and the top surface of the gate shielding layer 203 is removed, and the portion of the nitride layer in the second spacer material layer located on the sidewall of the first spacer structure is retained. The oxide layer in the second spacer material layer and the remaining nitride layer in the second spacer material layer constitute the second spacer structure.

[0070] In this embodiment, the material of the gate oxide layer 201 can be a dielectric material such as silicon oxynitride or silicon oxide, and the material of the gate conductive layer 202 can generally be a conductive material such as polysilicon or metal; the material of the oxide layer in the gate sidewall 204 can generally be a dielectric material such as silicon oxide, and the material of the nitride layer in the gate sidewall 204 can generally be a dielectric material such as silicon nitride.

[0071] like Figure 5As shown, step S300 is performed to form a first stress buffer layer 300 on the substrate 100, the first gate structure 200a and the second gate structure 200b. The first stress buffer layer 300 is entirely located on the substrate 100, the first gate structure 200a and the second gate structure 200b. Figure 5 As can be seen in FIG, the first stress buffer layer 300 conformally covers the oxide layer and the nitride layer of the second spacer structure.

[0072] In some embodiments, the material of the first stress buffer layer 300 is oxide, for example, a dielectric material such as TEOS (tetraethyl orthosilicate) or silicon oxide.

[0073] In some embodiments, the thickness of the first stress buffer layer 300 may be relatively small, for example, less than or equal to 100 nm, so as to prevent the first stress buffer layer 300 from affecting the subsequent ion implantation process.

[0074] like Figure 6 As shown, step S400 is performed to form a first patterned photoresist layer 401 on the first stress buffer layer 300 in the second device region (including the PMOS device core unit region 120a and the PMOS device peripheral region 120b). The first patterned photoresist layer 401 completely covers the first stress buffer layer 300 in the second device region. Forming the first patterned photoresist layer 401 includes steps such as spin coating of photoresist, curing, and exposure and development, which will not be described in detail here. It can be understood that since the first patterned photoresist layer 401 is formed on the first stress buffer layer 300, when the first patterned photoresist layer 401 is exposed, the first stress buffer layer 300 can isolate the basic groups on the surface of the gate sidewall 204 of the first gate structure 200a and the second gate structure 200b, and the surface of the first stress buffer layer 300 is relatively stable without broken bonds, which can avoid the first patterned photoresist layer 401 from consuming photoacid during exposure, thereby avoiding the first patterned photoresist layer 401 from having footing and undercutting problems, improving the morphology of the first patterned photoresist layer 401, and facilitating the subsequent ion implantation process on the substrate 100 on both sides of the first gate structure 200a.

[0075] like Figure 7 As shown, using the first patterned photoresist layer 401 as a mask, ion implantation is performed on the substrate 100 on both sides of the first gate structure 200a, thereby forming source and drain regions 103 in the substrate 100 on both sides of the first gate structure 200a. The first gate structure 200a and the source and drain regions 103 on both sides thereof can constitute an NMOS device.

[0076] It should be noted that when ion implantation is performed on the substrate 100 on both sides of the first gate structure 200a, the portion of the oxide layer in the second sidewall structure covering the substrate 100 can serve as an injection barrier layer; however, it should be understood that since the substrate 100 also has a first stress buffer layer 300, the oxide layer in the second sidewall structure can also only cover the sidewalls of the first sidewall structure (not covering the top surface of the substrate 100 and the gate shielding layer 203). At this time, the portion of the first stress buffer layer 300 covering the substrate 100 can serve as an injection barrier layer.

[0077] like Figure 8 As shown, step S500 is performed to remove the first patterned photoresist layer 401 by using a process such as ashing.

[0078] like Figure 9 As shown, step S600 is performed to form a second patterned photoresist layer 402 on the first stress buffer layer 300 in the first device region (including the NMOS device core unit region 110a and the NMOS device peripheral region 110b). The second patterned photoresist layer 402 completely covers the first stress buffer layer 300 in the first device region. Forming the second patterned photoresist layer 402 includes steps such as spin coating of photoresist, curing, and exposure and development, which will not be described in detail here. It can be understood that since the second patterned photoresist layer 402 is formed on the first stress buffer layer 300, when the second patterned photoresist layer 402 is exposed and developed, the first stress buffer layer 300 can isolate the basic groups on the surface of the gate sidewall 204 of the first gate structure 200a and the second gate structure 200b, and the surface of the first stress buffer layer 300 is relatively stable without broken bonds, which can prevent the second patterned photoresist layer 402 from consuming photoacid during exposure, thereby avoiding the second patterned photoresist layer 402 from having footing and undercutting problems, improving the morphology of the second patterned photoresist layer 402, and facilitating the subsequent ion implantation process on the substrate 100 on both sides of the second gate structure 200b.

[0079] like Figure 10 As shown, ion implantation is performed on the substrate 100 on both sides of the second gate structure 200b using the second patterned photoresist layer 402 as a mask. It should be noted that, since the substrate 100 on both sides of the second gate structure 200b has an embedded epitaxial layer 102, implantation of ion into the substrate 100 on both sides of the second gate structure 200b is actually implantation of ion into the embedded epitaxial layer 102 on both sides of the second gate structure 200b, thereby completing source and drain doping of the embedded epitaxial layer 102. The second gate structure 200b and the embedded epitaxial layers 102 on both sides thereof can thus constitute a PMOS device.

[0080] It should be noted that the embedded epitaxial layer 102 may not be provided in the substrate 100 on both sides of the second gate structure 200b. In this case, ion implantation may be performed directly on the substrate 100 on both sides of the second gate structure 200b, thereby forming source and drain regions in the substrate 100 on both sides of the second gate structure 200b. The second gate structure 200b and the source and drain regions on both sides thereof may also constitute a PMOS device.

[0081] It should be noted that, when ion implantation is performed on the substrate 100 on both sides of the second gate structure 200b, the portion of the oxide layer in the second spacer structure covering the substrate 100 can serve as an injection barrier layer; however, it should be understood that, since the substrate 100 also has a first stress buffer layer 300, the oxide layer in the second spacer structure can also only cover the sidewalls of the first spacer structure (not covering the substrate 100). In this case, the portion of the first stress buffer layer 300 covering the substrate 100 can also serve as an injection barrier layer.

[0082] like Figure 11 As shown, step S700 is performed to remove the second patterned photoresist layer 402 by using a process such as ashing.

[0083] It should be noted that in one embodiment of the present application, the first device region is an NMOS device region, and the second device region is a PMOS device region. Thus, ion implantation is performed on the substrate 100 of the NMOS device region first, followed by ion implantation on the substrate 100 of the PMOS device region. However, this should not be limiting. In another embodiment of the present application, the first device region may be a PMOS device region, and the second device region may be an NMOS device region. In this case, ion implantation is performed on the substrate 100 of the PMOS device region first, followed by ion implantation on the substrate 100 of the NMOS device region. In other words, the order of ion implantation does not affect the implementation of the present application.

[0084] Next, if Figure 12 As shown, a stress-introducing layer 500 is formed on the first stress buffer layer 300, and the stress-introducing layer 500 conformally covers the first stress buffer layer 300. The stress-introducing layer 500 and the first stress buffer layer 300 together constitute a stress memory layer. The first stress buffer layer 300 can serve as an etch stop layer during the subsequent etching of the stress-introducing layer 500, and can also play a stress buffering role, preventing the stress-introducing layer 500 from causing unnecessary damage to the first gate structure 200a and the second gate structure 200b. The stress-introducing layer 500 can be used to induce corresponding stress in the channel region of the substrate 100.

[0085] In some embodiments, the stress-introducing layer 500 may be made of a dielectric material such as silicon nitride.

[0086] Furthermore, for an NMOS device, the stress-introducing layer 500 may have a tensile stress, which will increase the electron mobility in the channel region of the NMOS device. For a PMOS device, the stress-introducing layer 500 may have a compressive stress, which will increase the hole mobility in the channel region of the PMOS device. It should be understood that the stress-introducing layer 500 having the desired stress type can be obtained by adjusting process parameters.

[0087] In some embodiments, after forming the stress-introducing layer 500 , the stress-introducing layer 500 may be etched to remove the stress-introducing layer 500 in the first device region or the second device region.

[0088] Please continue reading Figure 12 , an annealing process is performed on the stress memory layer. The annealing process may include a spike annealing process and a laser annealing process performed sequentially. The spike annealing process is used to activate the source and drain regions in the substrate 100, while the laser annealing process is used for stress memory. Specifically, the spike annealing process is first performed to activate the doped ions in the source and drain regions, making the ions uniformly distributed and repairing the lattice damage to the substrate 100 caused by ion implantation. Then, the laser annealing process is performed to transfer the stress in the stress introduction layer 500 into the channel region of the substrate 100, thereby improving the stress in the channel region, thereby increasing carrier mobility and improving device performance.

[0089] In some embodiments, the temperature of the spike annealing process can be 900°C to 1100°C, the annealing time can be 1 minute to 5 minutes, and the annealing can be completed in an inert gas atmosphere; the temperature of the laser annealing process can be 1100°C to 1300°C, the annealing time can be less than or equal to 1 second, and the laser annealing can use a laser with a wavelength of 2000nm to 20000nm.

[0090] like Figure 13 As shown, the stress-introducing layer 500 and the first stress buffer layer 300 are removed. Specifically, a wet etching process can be used to remove the stress-introducing layer 500. In this case, the wet etching solution can be a phosphoric acid solution. The phosphoric acid solution can etch the stress-introducing layer 500 but does not corrode the first stress buffer layer 300, so the stress-introducing layer 500 can be effectively removed.

[0091] Next, a wet etching process may be used to remove the first stress buffer layer 300 . In this case, the wet etching solution may be a hydrofluoric acid solution.

[0092] like Figure 14 As shown, etching is performed to remove the portion of the oxide layer in the second spacer structure covering the substrate 100 and the top surface of the gate shielding layer 203 .

[0093] It is understood that the first stress buffer layer 300 in the present application does not need to be removed after the two ion implantation processes, and can serve as a stress buffer during the stress memory process without increasing the complexity of the process. In other words, the present application advances the formation of the first stress buffer layer 300, which would originally be formed after the two ion implantation processes, to before the two ion implantation processes. Simply by reversing the order of the two ion implantation processes and the formation of the first stress buffer layer 300, the morphology of the first patterned photoresist layer 401 and the second patterned photoresist layer 402 can be simultaneously improved, thereby achieving device performance improvement with minimal process changes.

[0094] Of course, in order to avoid affecting the ion implantation process, the thickness of the first stress buffer layer 300 is relatively small, and may not have a good stress buffering effect. Therefore, in some embodiments, such as Figure 15 As shown, after removing the second patterned photoresist layer 402, the first stress buffer layer 300 can be removed, and then a second stress buffer layer 600 can be formed on the substrate 100, the first gate structure 200a, and the second gate structure 200b. The material of the second stress buffer layer 600 can be the same as that of the first stress buffer layer 300, but the thickness of the second stress buffer layer 600 can be greater than that of the first stress buffer layer 300, so that the second stress buffer layer 600 has a better stress buffering effect.

[0095] Afterwards, a stress-introducing layer 500 may be formed on the second stress buffer layer 600, conformally covering the second stress buffer layer 600. A normal stress memorization process may then be performed. After the stress memorization process, the stress-introducing layer 500 and the second stress buffer layer 600 may be removed.

[0096] Furthermore, in some embodiments, Figure 16 As shown, after removing the second patterned photoresist layer 402, a third stress buffer layer 700 can be formed on the first stress buffer layer 300. The third stress buffer layer 700 conformally covers the first stress buffer layer 300. The material of the third stress buffer layer 700 can be the same as that of the first stress buffer layer 300. In the subsequent stress memory process, the first stress buffer layer 300 and the third stress buffer layer 700 jointly play a stress buffering role, thereby achieving a better stress buffering effect.

[0097] Afterwards, a stress-introducing layer 500 may be formed on the third stress buffer layer 700, conformally covering the third stress buffer layer 700. A normal stress-memorizing process may then be performed. After the stress-memorizing process, the stress-introducing layer 500, the third stress buffer layer 700, and the first stress buffer layer 300 may be removed.

[0098] In summary, this embodiment provides a method for preparing a semiconductor device, including providing a substrate 100, the substrate 100 having a first device region and a second device region; forming a first gate structure 200a and a second gate structure 200b on the substrate 100, the first gate structure 200a and the second gate structure 200b being located in the first device region and the second device region, respectively; forming a first stress buffer layer 300 on the substrate 100, the first gate structure 200a and the second gate structure 200b; forming a first patterned photoresist layer 401 on the first stress buffer layer 300 in the second device region, and performing ion implantation on the substrate 100 on both sides of the first gate structure 200a; removing the first patterned photoresist layer 401; forming a second patterned photoresist layer 402 on the first stress buffer layer 300 in the first device region, and performing ion implantation on the substrate 100 on both sides of the second gate structure 200b; and removing the second patterned photoresist layer 402. The unexpected effect of the present application is that the first stress buffer layer 300 is directly formed after the first gate structure 200a and the second gate structure 200b are formed. The first stress buffer layer 300 can isolate the basic groups on the surfaces of the first gate structure 200a and the second gate structure 200b, and the surface of the first stress buffer layer 300 is relatively stable without broken bonds, which can avoid the consumption of photoacid during exposure, thereby avoiding the first patterned photoresist layer 401 and the second patterned photoresist layer 402 from having footing and undercutting problems, and improving the morphology of the first patterned photoresist layer 401 and the second patterned photoresist layer 402; moreover, the first stress buffer layer 300 does not need to be removed after the ion implantation process, and can play a stress buffer role in the subsequent stress memory process without increasing the complexity of the process.

[0099] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. The systems disclosed in the embodiments are described briefly because they correspond to the methods disclosed in the embodiments. For relevant details, refer to the method description.

[0100] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0101] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0102] It should also be recognized that the terms described herein are used only to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" herein include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices and may include secondary steps as well as secondary devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. In addition, the implementation of the methods and / or devices in the embodiments of the present invention may include performing the selected tasks manually, automatically, or in combination.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate having a first device region and a second device region; forming a first gate structure and a second gate structure on the substrate, wherein the first gate structure and the second gate structure are respectively located in the first device region and the second device region, and each of the first gate structure and the second gate structure includes a gate spacer, wherein the outermost layer of the gate spacer is made of nitride; forming a first stress buffer layer on the substrate, the first gate structure, and the second gate structure; forming a first patterned photoresist layer on the first stress buffer layer in the second device region, and performing ion implantation on the substrate on both sides of the first gate structure; removing the first patterned photoresist layer; forming a second patterned photoresist layer on the first stress buffer layer in the first device region, and performing ion implantation on the substrate on both sides of the second gate structure, wherein when the second patterned photoresist layer is exposed and developed, the surface of the first stress buffer layer is stable and has no broken bonds; and The second patterned photoresist layer is removed.

2. The method for preparing a semiconductor device according to claim 1, wherein: The material of the first stress buffer layer is oxide.

3. The method for preparing a semiconductor device according to claim 1, wherein: The thickness of the first stress buffer layer is less than or equal to 100 nm.

4. The method for preparing a semiconductor device according to claim 1, wherein: The first gate structure and the second gate structure also include a gate oxide layer, a gate conductive layer and a gate shielding layer. The gate oxide layer, the gate conductive layer and the gate shielding layer are stacked on the substrate from bottom to top, and the gate sidewall at least covers the side walls of the gate oxide layer, the gate conductive layer and the gate shielding layer.

5. The method for preparing a semiconductor device according to claim 4, wherein: The gate sidewall includes at least a first sidewall structure and a second sidewall structure, the first sidewall structure covers the sidewalls of the gate oxide layer, the gate conductive layer and the gate shielding layer, the second sidewall structure includes an oxide layer and a nitride layer, the oxide layer conformally covers the substrate, the sidewalls of the first sidewall structure and the top surface of the gate shielding layer, the nitride layer is located on the portion of the oxide layer covering the first sidewall structure, and when ion implantation is performed on the substrate on both sides of the first gate structure and ion implantation is performed on the substrate on both sides of the second gate structure, the portion of the oxide layer covering the substrate serves as an injection barrier layer.

6. The method for preparing a semiconductor device according to claim 1, wherein: After removing the second patterned photoresist layer, the preparation method further includes: forming a stress-introducing layer on the first stress buffer layer and performing an annealing process; and, The stress-introducing layer and the first stress buffer layer are removed.

7. The method for preparing a semiconductor device according to claim 1, wherein: After removing the second patterned photoresist layer, the preparation method further includes: removing the first stress buffer layer; forming a second stress buffer layer on the substrate, the first gate structure, and the second gate structure, wherein the thickness of the second stress buffer layer is greater than that of the first stress buffer layer; forming a stress-introducing layer on the second stress buffer layer and performing an annealing process; and, The stress-introducing layer and the second stress buffering layer are removed.

8. The method for preparing a semiconductor device according to claim 1, wherein: After removing the second patterned photoresist layer, the preparation method further includes: forming a third stress buffer layer on the first stress buffer layer; forming a stress-introducing layer on the third stress buffer layer and performing an annealing process; and, The stress-introducing layer, the third stress buffer layer, and the first stress buffer layer are removed.

9. The method for preparing a semiconductor device according to any one of claims 1 to 8, wherein: One of the first device region and the second device region is an NMOS device region, and the other is a PMOS device region.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The NMOS device area includes an NMOS device core unit area and an NMOS device peripheral area, and the PMOS device area includes a PMOS device core unit area and a PMOS device peripheral area. The substrates of the NMOS device core unit area, the NMOS device peripheral area, the PMOS device core unit area, and the PMOS device peripheral area all have the first gate structure or the second gate structure.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: An embedded epitaxial layer is provided in the substrate of the PMOS device region, and ion implantation into the substrate of the PMOS device region includes ion implantation into the embedded epitaxial layer.

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