Hybrid image sensor with multiple modes of operation

Abstract

Hybrid image sensors with multiple modes of operation are disclosed herein. In one embodiment, a pixel arrangement includes a first photosensor, a first floating diffusion region, a second photosensor, a second floating diffusion region, and a mode switch. The mode switch can include: (a) a first switch selectively coupling a second floating diffusion region to a first floating diffusion region; and (b) a second switch configured to selectively couple the second floating diffusion to event vision sensor (EVS) readout circuitry. The mode switch is operable to transition the pixel arrangement between: (i) a first mode in which the pixel arrangement is controllable to output intensity information corresponding to first light incident on the first photosensor and / or second light incident on the second photosensor; and (ii) a second mode in which the pixel arrangement is controllable to output contrast information corresponding to the first light and / or the second light.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 608,150, filed on Dec. 8, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to image sensors. For example, some embodiments of the present technology relate to hybrid image sensors having multiple operating modes, such as complementary metal oxide semiconductor (CMOS) image sensor (CIS) operating mode, event-based vision sensor (EVS), and hybrid CIS and EVS operating modes. Background Art

[0004] Image sensors have become ubiquitous and are now widely used in digital cameras, mobile phones, cameras, and medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, there is a desire to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range, etc.) through both device architecture design and image acquisition processing.

[0005] Typical image sensors operate in response to image light from an external scene incident on the image sensor. The image sensor includes a pixel array having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge after absorbing the image light. The image charge generated by the pixels can be measured as an analog output image signal on column bitlines, which varies according to the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, and the image light is read out as an analog image signal from the column bitlines and converted into a digital value to provide information representing the external scene. Summary of the Invention

[0006] According to one aspect of the present disclosure, a pixel arrangement is provided. The pixel arrangement includes: a first photoelectric sensor configured to photogenerate a first charge based at least in part on first light incident on the first photoelectric sensor; a first floating diffusion region configured to receive the first charge from the first photoelectric sensor; a second photoelectric sensor different from the first photoelectric sensor and configured to photogenerate a second charge based at least in part on second light incident on the second photoelectric sensor; a second floating diffusion region configured to receive the second charge from the second photoelectric sensor; and a mode switch including: a first switch selectively coupling the second floating diffusion region to the first floating diffusion region, and a second switch different from the first switch and configured to selectively couple the second floating diffusion region to an event vision sensor (EVS) readout circuitry, wherein the mode switch is operative to transition the pixel arrangement between: (i) a first mode in which the pixel arrangement can be controlled to produce a first output corresponding to the intensity information of the first light, the second light, or both the first light and the second light; and (ii) a second mode in which the pixel arrangement can be controlled to produce a second output corresponding to the contrast information of the first light, the second light, or both the first light and the second light.

[0007] According to another aspect of the present disclosure, a system is provided. The system includes: a first die including: at least one pixel having: a first photoelectric sensor; a first floating diffusion region configured to receive a first charge photogenerated by the first photoelectric sensor; a first transfer transistor configured to selectively couple the first photoelectric sensor to the first floating diffusion region; a second photoelectric sensor different from the first photoelectric sensor; a second floating diffusion region configured to receive a second charge photogenerated by the second photoelectric sensor; and a second transfer transistor configured to selectively couple the second photoelectric sensor to the second floating diffusion region, and a mode switch including: a first switch selectively coupling the second floating diffusion region to the first floating diffusion region, and a second switch coupled to the first switch via the second floating diffusion region; and a second die different from the first die and including an event vision sensor (EVS) readout circuitry, wherein the second switch is configured to selectively couple the second floating diffusion region to the EVS readout circuitry.

[0008] According to another aspect of the present disclosure, a pixel is provided. The pixel includes: a photoelectric sensor selectively coupled to a first floating diffusion region through a transfer gate; and a mode switch configured to transition the pixel between: (i) a first mode in which the pixel can be controlled to output complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) information corresponding to light incident on the photoelectric sensor; and (ii) a second mode in which the pixel can be controlled to output non-CIS information corresponding to light incident on the photoelectric sensor, wherein the mode switch includes: a first switch selectively (a) coupling a second floating diffusion region to the first floating diffusion region and (b) coupling the first floating diffusion region and the second floating diffusion region to a CIS readout circuit system, and a second switch (a) coupled to the first switch via the second floating diffusion region and (b) selectively coupling the second floating diffusion region to an event vision sensor (EVS) readout circuit system. Description of the Drawings

[0009] Non-limiting and non-exhaustive embodiments of the present technology are described below with reference to the following figures, in which like or similar reference numerals are used throughout to refer to like or similar components unless otherwise specified.

[0010] Figure 1 is a partial schematic diagram of a stacked hybrid complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) and an event-based vision sensor (EVS) system configured according to various embodiments of the present technology.

[0011] Figure 2 is a partial schematic circuit diagram of a pixel arrangement of two pixels configured according to various embodiments of the present technology.

[0012] Figures 3A to 3C is corresponding to according to various embodiments of the present technology Figure 2 a timing diagram of various operating modes of the pixel arrangement.

[0013] Figure 4A is a partial schematic circuit diagram of a pixel arrangement of four pixels configured according to various embodiments of the present technology.

[0014] Figures 4B to 4Q is corresponding to Figure 4A a partial schematic diagram of a pixel array of the pixel arrangement and configured according to various embodiments of the present technology.

[0015] Figure 5A is a partial schematic circuit diagram of another pixel arrangement of two pixels configured according to various embodiments of the present technology.

[0016] Figures 5B to 5D is a partial schematic diagram of a pixel array corresponding to Figure 5A and configured according to various embodiments of the present technology.

[0017] Figures 6 to 9 is a partial schematic diagram of other pixel arrangements configured according to various embodiments of the present technology.

[0018] Figure 10 is a partial schematic circuit diagram of another pixel arrangement of two pixels, the pixel arrangement being configured according to various embodiments of the present technology.

[0019] Figure 11 is incorporated Figure 10 and is a partial schematic circuit diagram of pixel arrangements including multiple examples and configured according to various embodiments of the present technology.

[0020] Figure 12A is a partial schematic circuit diagram of another pixel arrangement configured according to various embodiments of the present technology.

[0021] Figures 12B to 12D is corresponding to Figure 12A and is a partial schematic diagram of a pixel array configured according to various embodiments of the present technology.

[0022] Figure 13 is a partial schematic circuit diagram of another pixel arrangement configured according to various embodiments of the present technology.

[0023] Those skilled in the art will understand that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be enlarged relative to other elements to assist in the understanding of various aspects of the present technology. Additionally, common but well-known elements or methods that are useful or required in commercially viable embodiments are typically not depicted in the figures or described in detail below, so as not to unnecessarily obscure the description of various aspects of the present technology. Detailed Description

[0024] The present disclosure relates to image sensors and associated systems, devices, and methods having multiple operating modes. For example, several embodiments of the present technology relate to image sensors that can operate in a CIS operating mode, an EVS operating mode, or a hybrid (CIS and EVS) operating mode. Such image sensors may include a plurality of pixels, where one or more of the pixels include at least one mode switch for facilitating switching between various operating modes of the image sensor. In the following description, specific details are set forth to provide a thorough understanding of aspects of the present technology. However, those skilled in the relevant art will recognize that the systems, devices, and techniques described herein may be practiced without one or more of the specific details set forth herein or with other methods, components, materials, etc.

[0025] Reference to "example" or "embodiment" throughout this specification means that a particular feature, structure, or characteristic described in connection with the example or embodiment is included in at least one example or embodiment of the present technology. Thus, the use of the phrases "for example", "as an example", or "embodiment" herein are not necessarily all referring to the same example or embodiment and are not necessarily limited to the particular example or embodiment being discussed. Additionally, the features, structures, or characteristics of the present technology described herein may be combined in any suitable manner to provide additional examples or embodiments of the present technology.

[0026] For ease of description, spatial relative terms (e.g., "below", "beneath", "above", "below", "over", "on", "top", "bottom", "left", "right", "center", "middle", and the like) are used herein to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. It should be understood that, in addition to the orientation depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device or system during use or operation. For example, if the device or system illustrated in the figures is rotated, pivoted, or flipped about a horizontal axis, then an element or feature described as "below" or "beneath" or "under" one or more other elements or features may be oriented "above" one or more other elements or features. Thus, the exemplary terms "below" or "beneath" are non-limiting and may cover both above and below orientations. The device or system may be otherwise oriented (e.g., rotated 90 degrees about a vertical axis or in other orientations) in addition to or instead of the orientation illustrated in the figures, and the spatial relative descriptors used herein are interpreted accordingly. Additionally, it should also be understood that when an element is referred to as being "between" two other elements, it may be the only element between the two other elements or there may be one or more intervening elements.

[0027] Temporal relative terms (e.g., "simultaneously", "substantially simultaneously", or "at the same time") are used herein to describe events or operations occurring concurrently in a near-instantaneous manner taking into account the necessary delays in signal transmission and / or processing (e.g., circuit system processing time, signal propagation time, computation time, or the like associated with circuit components). Thus, unless otherwise specified, as used herein, "simultaneously", "substantially simultaneously", or "at the same time" may refer to events or operations that occur at exactly the same time or within one second or less of each other after taking into account signal transmission and / or processing.

[0028] It should be understood that although the terms first, second, third, etc. may be used in this disclosure and the claims to describe various elements, these elements should not be limited by these terms and should not be used to determine the process sequence or formation order of the associated elements. Unless otherwise indicated, these terms are only used to distinguish one element from another. Thus, the first element discussed below may be referred to as the second element without departing from the teachings of the disclosed embodiments.

[0029] It should be understood that the term "semiconductor material" as recited throughout this disclosure may correspond to a part or the whole of a semiconductor wafer (e.g., a silicon wafer). In some embodiments, the semiconductor material may comprise or otherwise be formed of: silicon, silicon germanium alloy, germanium, silicon carbide alloy, indium gallium arsenide alloy, any other alloy formed of III-V compounds, combinations thereof, one or more epitaxial layers of the foregoing materials, or a bulk substrate thereof. More specifically, the semiconductor material may correspond to any semiconductor material or combination of materials that can be doped or otherwise configured to facilitate the formation of an integrated circuit (e.g., to form individual circuit system components such as source / drain regions of transistors, memory elements, photodiodes, or the like). It should be understood that the term "photodiode" may correspond to a doped region disposed within a semiconductor material and configured to generate image charges (e.g., one or more electrons or holes) in response to incident light. For example, a photodiode may correspond to an n-doped region disposed within a p-type semiconductor material or an n-doped region surrounded by a p-type well disposed within the semiconductor material.

[0030] Throughout this specification, several terms of the art are used. These terms have their ordinary meaning in the art, unless specifically defined herein or the context in which they are used otherwise clearly indicates. It should be noted that element names and symbols may be used interchangeably throughout this document (e.g., Si and silicon); however, both have the same meaning.

[0031] A. Overview

[0032] Disclosed are hybrid image sensors (and associated systems, devices, and methods) having multiple operating modes. For example, some embodiments of the present technology relate to various imaging systems having pixel circuits that provide hybrid functionality (e.g., simultaneous image / video capture and event-driven sensing capabilities). Although normal image / video sensors provide good image and / or video capture capabilities, one of the limitations of normal image / video sensors is that normal image sensors do not provide ultra-high frame rate and ultra-high speed capture capabilities, which may be useful in various applications such as machine vision, gaming, and artificial intelligence sensing fields. Attempts to provide such ultra-high frame rate and ultra-high speed capabilities to typical image / video sensors have resulted in compromised solutions that provide poorer quality image capture compared to their normal image sensor counterparts.

[0033] It should be understood that the circuit designs according to the teachings of the present disclosure solve at least some of the problems discussed above. For example, the image sensors or pixel arrangements disclosed herein may operate in a hybrid mode, where for various event-driven (or other) applications, the image sensor / pixel arrangement simultaneously uses a first set of pixels to provide good image and video capture capabilities and uses a second set of pixels to sense events at an ultra-high frame rate and at an ultra-high speed. Continuing with this example, the image sensor / pixel arrangement may also operate in the following modes: (i) only the CIS mode, where the first set of pixels and the second set of pixels are used to provide image and video capture capabilities; and / or (ii) only the EVS mode, where the first set of pixels and the second set of pixels are used to sense events at an ultra-high frame rate and at an ultra-high speed. The image sensor / pixel arrangement may transition between the hybrid mode, only the CIS mode, and / or only the EVS mode using a mode switch, such as a mode switch located on the same die as the first set of pixels and the second set of pixels.

[0034] Accordingly, as will be shown and described in the various examples below, an example pixel arrangement includes: a first photosensor configured to photogenerate a first charge (e.g., one or more electrons or holes) based at least in part on first light incident on the first photosensor; a first floating diffusion region coupled to a CIS readout circuit system and configured to receive the first charge from the first photosensor; a second photosensor different from the first photosensor and configured to photogenerate a second charge (e.g., one or more electrons or holes) based at least in part on second light incident on the second photosensor; a second floating diffusion region configured to receive the second charge from the second photosensor; and a mode switch. The mode switch may include: a first switch selectively coupling the second floating diffusion region to the first floating diffusion region; and a second switch different from the first switch and configured to selectively couple the second floating diffusion region to an event vision sensor (EVS) readout circuit system. The mode switch can be used to transition the pixel arrangement between: (i) a first mode (e.g., a CIS-only mode) in which the pixel arrangement can be controlled to produce a first output corresponding to the intensity information of the first light and the second light; (ii) a second mode (e.g., a hybrid mode) in which the pixel arrangement can be controlled to (e.g., simultaneously) produce (a) a second output corresponding to the contrast information (or other non-CIS information) of the second light and (b) a third output corresponding to the intensity information of the first light; and / or (iii) a third mode (e.g., an EVS-only mode) in which the pixel arrangement can be controlled to produce a fourth output corresponding to the contrast information (or other non-CIS information) of the first light and the second light. The present technology thus facilitates the use of (e.g., pixel connections and timing control of the mode switch) to transition the pixel arrangement between the first mode, the second mode, and / or the third mode.

[0035] In some embodiments, the mode switch may be located on the same die as the first photosensor and the second photosensor. Locating the mode switch on the same die as the first photosensor and the second photosensor may reduce the amount of transistors and / or other circuit systems required to locate all or a portion of the mode switch circuit on a different die (e.g., a second die including the EVS readout circuit system). Additionally or alternatively, locating the mode switch on the same die as the first photosensor and the second photosensor may avoid routing power supply signals to different dies.

[0036] In addition, the present technology provides several other advantages. For example, the present technology facilitates the capture of CIS information using a conventional CIS readout process. As another example, the present technology can be implemented with a small pixel size. As a specific example, the first and second photoelectric sensors described above (a) can be the first and second photoelectric sensors of a split photoelectric sensor (e.g., split photodiodes) pixel, respectively, (b) can be positioned under the same microlens and / or (c) can have different full well capacities or different sensitivities. In an embodiment where the first and second photoelectric sensors are positioned under the same microlens, the first light and the second light can be guided by the same microlens onto the first and second photoelectric sensors. As another specific example, the first and second photoelectric sensors described above (a) can be the first and second photoelectric sensors of a multi-photoelectric sensor (e.g., multi-photodiodes) pixel, respectively, (b) can be of different sizes or include different sensitivities and / or (c) can be configured to achieve different imaging functionalities (e.g., the first photoelectric sensor can be configured as an imaging pixel, and the second pixel can be configured as a phase detection pixel or a depth sensing pixel).

[0037] Additionally or alternatively, the present technology can be implemented as various pixel architectures (e.g., pixel arrays of 1x1, 1x2, 2x1, 2x2 or other sizes; phase detection autofocus; high dynamic range; dual conversion gain; pixels, sub-pixels, transfer transistors, control gates and / or floating diffusion regions having any number of photoelectric sensors; pixels having a floating diffusion region shared by any number of photoelectric sensors). As a specific example, the first and second photoelectric sensors described above can be parts of the first pixel and the second pixel, respectively. In some embodiments, the first pixel and the second pixel can be vertically aligned with each other or can be horizontally aligned with each other. In these and other embodiments, the first pixel and the second pixel can (a) be coupled to the same bit line, (b) be coupled to the same CIS readout circuitry and / or (c) be coupled to the same EVS readout circuitry (e.g., via the same hybrid bonding that couples (i) the first pixel and the second pixel positioned on the first die to (ii) the event detection circuitry on the second die).

[0038] B. Selected Embodiments of a Hybrid Imaging Sensor with Multiple Operating Modes and Associated Systems, Devices, and Methods

[0039] Figure 1Partial schematic diagram of a stacked complementary metal oxide semiconductor (CMOS) image sensor (CIS) having an event-based vision sensor (EVS) system 100 (“stacked system 100”) configured according to various embodiments of the present technology. As shown, the stacked system 100 includes a first die 102, a second die 104, and a third die 106 stacked and coupled together in a stacked chip scheme. In some embodiments, the first die 102, the second die 104, and the third die 106 are semiconductor dies including a suitable semiconductor material (e.g., silicon). In the illustrated embodiment, the first die 102 (also referred to herein as the “top die”) includes a pixel array 108. The third die 106 (also referred to herein as the “bottom die”) includes an image readout circuit 116 (also referred to herein as the “image readout mixed-signal circuitry”). The image readout circuit 116 can be coupled to the pixel array 108 of the top die 102 through column-level connections 110 for normal image readout. In some embodiments, the column-level connections 110 for normal image readout are implemented from the column bit lines of the pixel array 108 using through-silicon vias (TSVs) extending between the top die 102 and the bottom die 106 and routed through the second die 104.

[0040] In some embodiments, the pixel array 108 is a two-dimensional (2D) array including a plurality of pixel units (also referred to as “pixels”), each pixel unit including at least one photosensor (e.g., at least one photodiode) exposed to incident light. As shown in the illustrated embodiment, the pixels are arranged in rows and columns. As further discussed herein, the pixels of the pixel array 108 can operate at least in part as CIS pixels and / or at least in part as EVS pixels. When operating as CIS pixels, the pixels can be used to acquire image data of a person, location, object, etc., and the image data can then be used to reproduce an image and / or video of the person, location, object, etc. For example, each CIS pixel is configured to photogenerate an image charge in response to incident light. After each CIS pixel has acquired its image charge, the corresponding analog image charge data can be read out by the image readout circuit 116 in the bottom die 106 through the column bit lines. In some embodiments, the image charge from each row of the pixel array 108 can be read out in parallel by the image readout circuit 116 through the column bit lines.

[0041] The image readout circuit 116 in the bottom die 106 may include amplifiers, analog-to-digital converter (ADC) circuitry, associated analog support circuitry, associated digital support circuitry, etc. for normal image readout and processing. In some embodiments, the image readout circuit 116 may also include event-driven readout circuitry, as will be described in more detail below. In operation, the optically generated analog image charge signal is read out from the pixel cells of the pixel array 108, amplified and converted to a digital value in the image readout circuit 116. In some embodiments, the image readout circuit 116 may read out one row of image data at a time. In other instances, the image readout circuit 116 may use various other techniques (not shown), such as serial readout or all pixels simultaneously full parallel readout, to read out the image data. The image data may be stored or even manipulated by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, etc.).

[0042] In the illustrated embodiment, the second die 104 (also referred to herein as the "intermediate die") includes an event-driven sensing array 112 coupled to the pixel array 108 in the top die 102. In some embodiments, the event-driven sensing array 112 is coupled to the pixels of the pixel array 108 through a hybrid bond between the top die 102 and the intermediate die 104. The event-driven sensing array 112 may include an event-driven circuit array. In some embodiments, in accordance with the teachings of the present disclosure, each of the event-driven circuits in the event-driven sensing array 112 is coupled to at least one of the plurality of pixels of the pixel array 108 through a hybrid bond between the top die 102 and the intermediate die 104 to asynchronously detect events occurring in the light incident on the pixel array 108.

[0043] In some embodiments, corresponding event detection signals are generated by the event-driven circuits in the event-driven sensing array 112. The event detection signals may be received and processed by the event-driven peripheral circuitry 114, which in some embodiments is disposed around the periphery of the event-driven sensing array 112 in the intermediate die 104, as Figure 1 shown. Figure 1 The illustrated embodiment also illustrates column-level connections 110 for normal image readout routing through the intermediate die 104 between the top die 102 and the bottom die 106.

[0044] Figure 2 is a partial schematic circuit diagram of a pixel arrangement 220 configured according to various embodiments of the present technology. The pixel arrangement 220 includes two pixels: a first pixel 229 and a second pixel 239. The first pixel 229 and / or the second pixel 239 may be Figure 1An example of one of the pixels in the pixel array 108 or another pixel configured according to various embodiments of the present technology. In the illustrated embodiment, the first pixel 229 (also referred to herein as an "RGB pixel") includes a photosensor 221 (e.g., a photodiode), a floating diffusion region 227, and a transfer transistor 222 that selectively couples the photosensor 221 to the floating diffusion region 227 based at least in part on a transfer control signal TX_CIS. The photosensor 221 is configured to photogenerate image charge in response to incident light, and the floating diffusion region 227 is configured to receive the image charge from the photosensor 221 at least when the transfer transistor 222 is selectively activated using the transfer control signal TX_CIS.

[0045] The first pixel 229 further includes a reset transistor 223, a source follower transistor 224, and a row selection transistor 225. The reset transistor 223 can selectively couple the floating diffusion region 227 to a voltage source (e.g., for a reset operation) based at least in part on a reset signal RST. The source follower transistor 224 includes a gate terminal coupled to the floating diffusion region 227. The source follower transistor 224 is also coupled between (i) a voltage source (e.g., the same voltage source or a different voltage source as the voltage source coupled to the reset transistor 223) and (ii) the row selection transistor 225. The row selection transistor 225: (a) is coupled between the source follower transistor 224 and a bit line 230; and (b) is selectively activated based at least in part on a row selection signal RS. The source follower transistor 224 and the row selection transistor 225 are also collectively referred to herein as the "readout circuitry" of the first pixel 229.

[0046] Now referring to Figure 2 the second pixel 239, the second pixel 239 (also referred to herein as a "hybrid EVS pixel") includes a photosensor 231 (e.g., a photodiode), a floating diffusion region 237, and a transfer transistor 232 that selectively couples the photosensor 231 to the floating diffusion region 237 based at least in part on a transfer control signal TX_EVS. The photosensor 231 is configured to photogenerate image charge in response to incident light, and the floating diffusion region 237 is configured to receive the image charge from the photosensor 231 at least when the transfer transistor 232 is selectively activated using the transfer control signal TX_EVS.

[0047] Figure 2 The first pixel 229 and the second pixel 239 are each illustrated with a single photosensor 221 and 231, respectively. As described in more detail below, in other embodiments of the present technology, either or both of the first pixel 229 and the second pixel 239 may include a different number of photosensors (e.g., two, three, four, or more photosensors). For example, referring below to Figures 4A to 5D, the pixels described in greater detail in 10 and 11 each include four photoelectric sensors. As a specific example, either or both of the first pixel 229 and the second pixel 239 can be a split photodiode pixel (e.g., can be used for high dynamic range (HDR) applications).

[0048] Figure 2 The first pixel 229 and the second pixel 239 of are also each described as having a single control gate (transfer transistors 222 and 232, respectively). In other embodiments, either or both of the first pixel 229 and the second pixel 239 can include a different number of control gates (e.g., two, three, four, or more transfer transistors). For example, the first pixel 229 and / or the second pixel 239 can include one or more transfer transistors for each of its photoelectric sensors. As another example, the first pixel 229 and / or the second pixel 239 can include fewer transfer transistors than photoelectric sensors (e.g., one transfer transistor for two or more photoelectric sensors).

[0049] In addition, Figure 2 the first pixel 229 of is described as having a floating diffusion region (floating diffusion region 227), and Figure 2 the second pixel 239 of is described as having a floating diffusion region (floating diffusion region 237). For example, the first pixel 229 and the second pixel 239 are each described with a 1x1 architecture, where the single floating diffusion regions 227 and 237 are respectively coupled to (or selectively coupled to) the single photoelectric sensors 221 and 231, respectively. In other embodiments, the first pixel 229 and / or the second pixel 239 can include more than one floating diffusion region and / or a different number of photoelectric sensors coupled to each floating diffusion region. For example, the floating diffusion region can be shared by one or more photoelectric sensors (e.g., coupled or selectively coupled to one or more photoelectric sensors), such as one photoelectric sensor, two photoelectric sensors, three photoelectric sensors, four photoelectric sensors, etc. As another example, multiple floating diffusion regions can share (e.g., be coupled to or selectively coupled to) the same photodiode. Thus, the first pixel 229 and / or the second pixel 239 can be configured with any pixel architecture, such as 1x2, 2x1, 1x3, 3x1, 2x2, 3x3, 4x4, and others.

[0050] In addition, Figure 2The pixel arrangement 220 is described as a 1x2 pixel arrangement. In other embodiments, the first pixel 229 and the second pixel 239 may be configured in a different pixel arrangement, such as a 2x1 pixel arrangement. In these and other embodiments, the first pixel 229 and the second pixel 239 may be part of a larger pixel arrangement. For example, the first pixel 229 and / or the second pixel 239 may be configured / arranged as a 1x3 pixel arrangement, a 3x1 pixel arrangement, a 2x2 pixel arrangement, a 3x3 pixel arrangement, a 4x4 pixel arrangement, or another suitable pixel arrangement.

[0051] In Figure 2 the embodiment described, the pixel arrangement 220 further includes a mode switch circuit 235 (also referred to herein as a "mode switch"). As shown, the mode switch circuit 235 includes a first switch 236 (also referred to herein as a "CIS switch", "CIS mode switch", "first mode switch", and the like) and a second switch 238 (also referred to herein as an "EVS switch", "EVS mode switch", "second mode switch", and the like). The first switch 236 (e.g., a transistor, a standard switch, etc.) is configured to selectively couple the second pixel 239 to the first pixel 229. For example, the first switch 236 is configured to selectively couple the floating diffusion region 237 of the second pixel 239 to the floating diffusion region 227 of the first pixel 229 at least in part based on the first switch control signal CIS_MODE_SW. As a specific example, the first switch 236 may be electrically positioned between the floating diffusion region 237 of the second pixel 239 and the floating diffusion region 227 of the first pixel 229. Thus, when the first switch 236 is activated (e.g., turned on), the charge accumulated on the floating diffusion region 237 can be applied to the gate of the source follower transistor 224, such that the corresponding analog signal can be read out onto the bit line 230 (e.g., when the row select transistor 225 is activated at least in part based on the row select signal RS and / or when the reset transistor 223 is deactivated at least in part based on the reset signal RST). In other words, the activation of the first switch 236 (e.g., when the second switch 238 is off or deactivated) can facilitate the readout of the second pixel 239 via the readout circuitry of the first pixel 229. In other words, the activation of the first switch 236 (e.g., when the second switch 238 is not activated) can facilitate the readout of intensity information (e.g., a CIS image signal) onto the bit line 230 from either or both of the first pixel 229 and the second pixel 239.

[0052] The second switch 238 of the mode switch circuit 235 (e.g., a transistor, a standard switch, etc.) is configured to selectively couple the second pixel 239 to the EVS readout circuitry at least in part based on the second switch control signal EVS_MODE_SW (e.g., Figure 1(one of the event-driven circuits included in the event-driven sensing array 112 shown in). For example, the second switch 238 may be electrically positioned between the floating diffusion region 237 of the second pixel 239 and an EVS readout circuit system (e.g., on Figure 1 the second die 104 of), e.g., between the floating diffusion region 237 and a hybrid bond that couples the second pixel 239 (e.g., on Figure 1 the first die 102 of) to the corresponding event-driven circuit of the event-driven sensing array (e.g., on the second die 104). As another example, the second switch 238 may be electrically positioned (i) such that the floating diffusion region 237 is electrically positioned between the second switch 238 and the first switch 236, and / or (ii) such that the second switch 238 is coupled to the first switch 236 via the floating diffusion region 237.

[0053] When the second switch 238 of the mode switch circuit 235 is activated, the charge accumulated on the floating diffusion region 237 may be transferred to the EVS readout circuit system corresponding to the second pixel 239. Additionally, when both the first switch 236 and the second switch 238 are activated together, the charge accumulated on the floating diffusion region 227 of the first pixel 229 may also be transferred to the EVS readout circuit system corresponding to the second pixel 239 (e.g., when the row selection transistor 225 and / or the reset transistor 223 are also not activated). In other words, the activation of the second switch 238 (e.g., when (a) the first switch 236 is not activated and / or (b) the first switch 236 is activated, the reset transistor 223 is not activated, and / or the row selection transistor 225 is not activated) may facilitate the generation of a contrast change (e.g., an event signal) corresponding to either or both of the first pixel 229 and the second pixel 239.

[0054] The mode switch circuit 235 thus facilitates operation of the pixel arrangement 220 in any of three modes: a CIS-only mode (also referred to herein as the “first mode”), in which both the first pixel 229 and the second pixel 239 of the pixel arrangement 220 can be used to obtain CIS information (e.g., a CIS image signal); a hybrid CIS and EVS mode (also referred to herein as the “hybrid mode” or the “second mode”), in which the pixel arrangement 220 can be used (e.g., simultaneously) to provide CIS information (e.g., from the first pixel 229) and non-CIS information (e.g., from the second pixel 239); and an EVS-only mode (also referred to herein as the “third mode”), in which both the first pixel 229 and the second pixel 239 can be used to obtain non-CIS information (e.g., an event signal corresponding to a luminance change, event detection, phase detection autofocus, etc.). In other words, the mode switch can be used to transition the pixel arrangement 220 between: (a) one or more first modes (e.g., the CIS-only mode and / or the hybrid CIS and EVS mode), in which the pixel arrangement can be controlled to produce an output corresponding to intensity information, luminance information, or CIS information (e.g., color information) of light incident on the first pixel 229 and / or the second pixel 239; and (b) one or more second modes (e.g., the hybrid CIS and EVS mode and / or the EVS-only mode), in which the pixel arrangement can be controlled to produce an output corresponding to the contrast or other non-CIS information of light incident on the first pixel 229 and / or the second pixel 239).

[0055] For example, by activating the first switch 236 of the mode switch circuit 235 while deactivating the second switch 238, charges accumulated on both the floating diffusion region 227 of the first pixel 229 and the floating diffusion region 237 of the second pixel 239 can be read out onto the bit line 230 via the readout circuitry of the first pixel 229 when the row selection transistor 225 is activated using the row selection signal RS. Thus, activation of the first switch 236 while the second switch 238 is deactivated can correspond to the CIS-only mode of the pixel arrangement 220.

[0056] Figure 3A is a timing diagram 340 corresponding to the readout of the pixel arrangement 220 when the pixel arrangement 220 is operating in the CIS-only mode. Referring together to Figure 2 and Figure 2 and 3A , at time t0, the first switch control signal CIS_MODE_SW is asserted with, for example, a positive voltage signal (such that the first switch 236 of the mode switch circuit 235 is activated), while the second switch control signal EVS_MODE_SW is de-asserted or applied with, for example, a ground reference voltage level or a negative voltage level (such that the second switch 238 of the mode switch circuit 235 is deactivated). As Figure 3AAs shown, during the remainder of the time shown in timing diagram 340, the first switch 236 may remain activated and the second switch 238 may remain deactivated. When the first switch 236 is activated, the floating diffusion region 237 of the second pixel 239 is coupled to the floating diffusion region 227 of the first pixel 229.

[0057] It should be understood that the definition of a signal being in an asserted state means that the signal has a voltage level (e.g., a positive voltage) sufficient to turn on the corresponding transistor. The definition of a signal being in a de-asserted state means that the signal has a voltage level (e.g., ground or a negative voltage) sufficient to turn off the corresponding transistor (or cut off the conduction path of the corresponding transistor).

[0058] In addition, at time t0, the reset signal RST is in an asserted state such that the reset transistor 223 is activated, and the row select signal RS is in a de-asserted state such that the row select transistor 225 is deactivated. Additionally, both the transfer control signal TX_CIS and the transfer control signal TX_EVS are de-asserted, such that the transfer transistor 222 and the transfer transistor 232 are deactivated, respectively. Thus, the floating diffusion region 227 and the floating diffusion region 237 are reset via the reset transistor 223 at time t0.

[0059] At time t1, the reset signal RST is de-asserted, and the row select signal RS is asserted. Thus, the reset transistor 223 is deactivated, and the row select transistor 225 is activated. In some embodiments, a first reset level signal (corresponding to the charge on the floating diffusion regions 227 and 237 after resetting the floating diffusion regions 227 and 237) may be sampled and read out onto the bit line 230 between time t1 and time t2 (e.g., for correlated double sampling).

[0060] At time t2, the transfer control signal TX_CIS is asserted, thereby activating the transfer transistor 222 of the first pixel 229. Activation of the transfer transistor 222 couples the photosensor 221 of the first pixel 229 to (i) the floating diffusion region 227 of the first pixel 229 and (ii) the floating diffusion region 237 of the second pixel 239. Activation of the transfer transistor 222 also allows the charge photogenerated by the photosensor 221 in response to incident light to (a) be transferred to the floating diffusion regions 227 and 237 and (b) be applied to the gate of the source follower transistor 224. Since the row select signal RS remains asserted between time t1 and time t4, the first signal level signal (corresponding to the image charge (i) photogenerated by the photosensor 221 and (ii) applied to the gate of the source follower transistor 224 between time t2 and time t3) is sampled and read out to the bit line 230 between time t3 and time t4 from the first pixel 229. At time t3, the transfer control signal TX_CIS is de-asserted, thereby deactivating the transfer transistor 222 and decoupling the photosensor 221 from the floating diffusion regions 227 and 237. The interval between time t2 and time t3 may represent the charge transfer period. In some embodiments, an integration or exposure period (not shown) associated with the photosensor 221 may occur prior to time t2. In these and other embodiments, a precharge or reset period (during which the photosensor 221, photosensor 231, floating diffusion region 227, and / or floating diffusion region 237 may be reset) may occur prior to the integration or exposure period.

[0061] At time t4, the reset signal RST is asserted again to activate the reset transistor 223, and the row select signal RS is de-asserted to deactivate the row select transistor 225. Subsequently, the floating diffusion regions 227 and 237 are reset via the reset transistor 223 between time t4 and time t5.

[0062] At time t5, the reset signal RST is de-asserted, and the row select signal RS is asserted. Accordingly, the reset transistor 223 is deactivated, and the row select transistor 225 is activated. In some embodiments, a second reset level signal (corresponding to the charge on the floating diffusion regions 227 and 237 after resetting the floating diffusion regions 227 and 237) may be sampled and read out to the bit line 230 between time t5 and time t6 (e.g., for correlated double sampling). In these and other embodiments, an integration or exposure period (not illustrated) associated with the photosensor 231 may occur prior to time t6.

[0063] At time t6, the transfer control signal TX_EVS is asserted, thereby activating the transfer transistor 232 of the second pixel 239. Activation of the transfer transistor 232 couples the photosensor 231 of the second pixel 239 to (i) the floating diffusion region 237 of the second pixel 239 and (ii) the floating diffusion region 227 of the first pixel 229. Activation of the transfer transistor 232 also allows the charge photogenerated by the photosensor 231 in response to incident light to (a) be transferred to the floating diffusion region 237 and the floating diffusion region 227 and (b) be applied to the gate of the source follower transistor 224. Since the row select signal RS remains asserted between time t5 and time t8, the second signal level signal (corresponding to the image charge that is (i) photogenerated by the photosensor 231 and (ii) applied to the gate of the source follower transistor 224 between time t6 and time t7) is sampled and read out to the bit line 230 between time t7 and time t8. At time t7, the transfer control signal TX_EVS is de-asserted, thereby deactivating the transfer transistor 232 and decoupling the photosensor 231 from the floating diffusion region 237 and the floating diffusion region 227.

[0064] At time t8, the reset signal RST is asserted again to activate the reset transistor 223, and the row select signal RS is de-asserted to deactivate the row select transistor 225 (e.g., to reset the charge on the floating diffusion regions 227 and 237).

[0065] Although shown as being activated for the entire duration between time t0 and time t8 of the timing diagram 340 shown in Figure 3A In other embodiments, the first switch control signal CIS_MODE_SW may be asserted to selectively activate the first switch 236 of the mode switch circuit 235 only during the time corresponding to acquiring the CIS image signal of the second pixel 239 between time t0 and t8. For example, the first switch control signal CIS_MODE_SW may be activated from time t0 to time t1 (e.g., for resetting the floating diffusion region 237), deactivated from time t1 to time t4, and then activated from time t4 to time t8. As another example, the first switch control signal CIS_MODE_SW may be deactivated from time t0 to time t4 and then activated from time t4 to time t8.

[0066] Additionally or alternatively, although the first pixel 229 is shown as being read out before the second pixel 239 in Figure 3A In other embodiments, the second pixel 239 may be read out before the first pixel 229. As a specific example, the transfer control signal TX_EVS may be at Figure 3Apulsed between time t2 and time t3 (instead of between time t6 and time t7), and the transfer control signal TX_CIS can be pulsed between time t6 and time t7 (instead of between time t2 and time t3).

[0067] Referring again to Figure 2 , when the first switch 236 of the mode switch circuit 235 is deactivated while the second switch 238 of the mode switch circuit 235 is activated, the first pixel 229 can be operated to obtain a CIS image signal, while the second pixel 239 can be operated to detect an event occurring in the external scene monitored by the second pixel 239. For example, an analog signal corresponding to the charge accumulated on the floating diffusion region 227 of the first pixel 229 can be read out onto the bit line 230 when the row selection signal RS is asserted to activate the row selection transistor 225, and the charge accumulated on the floating diffusion region 237 of the second pixel 239 can be transferred to the EVS readout circuitry corresponding to the second pixel 239. Thus, activation of the second switch 238 when the first switch 236 is not activated can correspond to the hybrid CIS and EVS modes of the pixel arrangement 220.

[0068] Figure 3B is a timing diagram 350 of the readout of the pixel arrangement 220 corresponding to when the pixel arrangement 220 is operating in the hybrid CIS and EVS modes. Referring together to Figure 2 and Figure 2 and 3B , at time t0, the first switch control signal CIS_MODE_SW is de-asserted (such that the first switch 236 of the mode switch circuit 235 is deactivated), while the second switch control signal EVS_MODE_SW is asserted (such that the second switch 238 of the mode switch circuit 235 is activated). Additionally, the transfer control signal TX_EVS is asserted such that (i) the transfer transistor 232 is activated and (ii) the photosensor 231 is coupled to the floating diffusion region 237. Thus, the photosensor 231 and the floating diffusion region 237 of the second pixel 239 can be coupled to the EVS readout circuitry corresponding to the second pixel 239. Consequently, the image charge generated photoelectrically by the photosensor 231 can be transferred to the EVS readout circuitry to generate a contrast change (e.g., an event signal). A contrast change above a threshold (e.g., a change in the intensity of light incident on the photosensor 231 from darker to brighter and greater than the threshold, a change in the intensity of light incident on the photosensor 231 from brighter to darker and greater than the threshold) can indicate that an event (e.g., motion) has occurred within the external scene monitored by the second pixel 239, and can trigger the EVS readout circuitry to trigger an event detection signal indicating that the second pixel 239 has detected an event in the scene. As Figure 3BAs shown, throughout the entire duration shown in timing diagram 350, the first switch control signal CIS_MODE_SW can remain de-asserted (meaning that the first switch 236 can remain de-activated), the second switch control signal EVS_MODE_SW can remain asserted (meaning that the second switch 238 can remain activated), and the transfer control signal TX_EVS can remain activated (meaning that the transfer transistor 232 can remain activated). Thus, throughout the entire duration shown in Figure 3B the photoelectric sensor 231 and the floating diffusion region 237 of the second pixel 239 can be coupled to the EVS readout circuitry corresponding to the second pixel 239. In other words, throughout the entire duration between time t0 and time t8 in the timing diagram 350 of Figure 3B , the second pixel 239 can operate as an event vision pixel.

[0069] In addition, at time t0 of the timing diagram 350, the reset signal RST is in the asserted state such that the reset transistor 223 is activated, and the row selection signal RS is in the de-asserted state such that the row selection transistor 225 is de-activated. Additionally, the transfer control signal TX_CIS is de-asserted such that the transfer transistor 222 of the first pixel 229 is de-activated. Thus, the floating diffusion region 227 of the first pixel 229 is reset via the reset transistor 223 at time t0.

[0070] At time t1, the reset signal RST is de-asserted, and the row selection signal RS is asserted. Thus, the reset transistor 223 is de-activated, and the row selection transistor 225 is activated. In some embodiments, a first reset level signal (corresponding to the charge on the floating diffusion region 227 after resetting the floating diffusion region 227) can be sampled and read out onto the bit line 230 between time t1 and time t2 (e.g., for correlated double sampling).

[0071] At time t2, the transfer control signal TX_CIS is asserted (e.g., via a pulse high signal), thereby activating the transfer transistor 222 of the first pixel 229. Activation of the transfer transistor 222 (i) couples the photosensor 221 of the first pixel 229 to the floating diffusion region 227 of the first pixel 229, and (ii) allows the charge photo-generated by the photosensor 221 in response to incident light to (a) be transferred to the floating diffusion region 227 and (b) be applied to the gate of the source follower transistor 224. Because the row select signal RS remains asserted between time t1 and time t4, the first signal level signal (corresponding to the image charge (i) photo-generated by the photosensor 221 and (ii) applied to the gate of the source follower transistor 224 between time t2 and time t3) is sampled and read out onto the bit line 230 between time t3 and time t4. At time t3, the transfer control signal TX_CIS is de-asserted, thereby deactivating the transfer transistor 222 and decoupling the photosensor 221 from the floating diffusion region 227 and the floating diffusion region 237. As shown, the transfer control signal may remain de-asserted for the remaining duration shown in the timing diagram 350.

[0072] At time t4, the reset signal RST is asserted again to activate the reset transistor 223, and the row select signal RS is de-asserted to deactivate the row select transistor 225. Subsequently, the floating diffusion region 227 of the first pixel 229 is reset via the reset transistor 223. As shown, the reset signal RST may remain asserted and the row select signal RS may remain de-asserted for the remaining duration shown in the timing diagram 350.

[0073] Referring again to Figure 2 , when the first switch 236 and the second switch 238 of the mode switch circuit 235 are activated (e.g., when the row select transistor 225 and / or the reset transistor 223 are not activated), the charge accumulated on the floating diffusion region 227 of the first pixel 229 and the floating diffusion region 237 of the second pixel 239 can be transferred to the EVS readout circuitry corresponding to the second pixel 239. Thus, activation of the first switch 236 and the second switch 238 (e.g., when the row select transistor 225 and / or the reset transistor 223 are not activated) can correspond to the EVS-only mode of the pixel arrangement 220.

[0074] Figure 3C is the timing diagram 360 corresponding to the readout of the pixel arrangement 220 when the pixel arrangement 220 is operating in the EVS-only mode. Referring together to Figure 2 and Figure 2 and 3C, at time t0, the first switch control signal CIS_MODE_SW is asserted to activate the first switch 236 of the mode switch circuit 235; the second switch control signal EVS_MODE_SW is asserted to activate the second switch 238 of the mode switch circuit 235; the transfer control signal TX_CIS is asserted to activate the transfer transistor 222; and the transfer control signal TX_EVS is asserted to activate the transfer transistor 232. Thus, the photosensor 221 and the floating diffusion region 227 of the first pixel 229 are each coupled to the EVS readout circuitry via the first switch 236 and the second switch 238 of the mode switch circuit 235. Additionally, the photosensor 231 and the floating diffusion region 237 of the second pixel 239 are each coupled to the EVS readout circuitry via the second switch 238 of the mode switch circuit 235. As Figure 3C shown, during the remaining time shown in the timing diagram 360, the states of the first switch control signal CIS_MODE_SW, the second switch control signal EVS_MODE_SW, the transfer control signal TX_CIS, and the transfer control signal TX_EVS remain unchanged. Thus, during the remainder of the time shown in the timing diagram 360, the first switch 236, the second switch 238, the transfer transistor 222, and the transfer transistor 232 remain activated, respectively. Also as Figure 3C shown, the reset signal RST and the row select signal RS are de-asserted at time t0 and remain de-asserted during the remainder of the time shown in the timing diagram 360. Thus, the reset transistor 223 and the row select transistor 225 are de-activated at time t0 and remain de-activated during the remainder of the time shown in the timing diagram 360.

[0075] When the photosensors 221, the floating diffusion regions 227, the photosensors 231, and the floating diffusion regions 237 are coupled to the EVS readout circuitry, the image charge generated by the photosensor 221 and / or the photosensor 231 is transferred to the EVS readout circuitry to produce a contrast change (e.g., an event signal). A contrast change above a threshold (e.g., a change in the intensity of light incident on the photosensor 221 and / or the photosensor 231 from darker to brighter and greater than the threshold, a change in the intensity of light incident on the photosensor 211 and / or the photosensor 231 from brighter to darker and greater than the threshold) may indicate that an event (e.g., motion) has occurred in the external scene monitored by the first pixel 229 and / or the second pixel 239, and may trigger the EVS readout circuitry to trigger an event detection signal indicating that the first pixel 229 and / or the second pixel 239 has detected an event in the scene.

[0076] Referring again to Figure 2, all or a portion of the mode switch circuit 235 may be located on the same die as the first pixel 229 and / or the second pixel 239 (e.g., Figure 1 the first die 102). In some embodiments, locating the mode switch circuit 235 on the same die as the first pixel 229 and / or the second pixel 239 may reduce the amount of transistors and / or other circuitry required to locate all or a portion of the mode switch circuit on a die different from the die on which the first pixel 229 and / or the second pixel 239 are located (e.g., the first die 102) (e.g., Figure 1 the second die 104). Additionally or alternatively, locating the mode switch circuit 235 on the same die as the first pixel 229 and / or the second pixel 239 may avoid routing power supply signals (e.g., VDDAPIX, AVDD, etc.) to different dies. In other embodiments of the present technology, all or a portion of the mode switch circuit 235 (e.g., the first switch 236 and / or the second switch 238) may be located on a die different from the die on which the first pixel 229 and / or the second pixel 239 are located.

[0077] The principles of the present technology discussed above with reference to Figures 1 to 3C may be adapted to a variety of other image sensors, pixel arrangements, and / or pixel architectures. For example, Figure 4A is a partial schematic circuit diagram of a pixel arrangement 420 configured according to various embodiments of the present technology. As shown, the pixel arrangement 420 includes four pixels: a first pixel 429a, a second pixel 439a, a third pixel 429b, and a fourth pixel 439b. The first pixel 429a, the second pixel 439a, the third pixel 429b, and / or the fourth pixel 439b may be Figure 1 one of the pixels in the pixel array 108 of Figure 2 the first pixel 229 of Figure 2 or an example of another pixel configured according to various embodiments of the present technology. As shown, Figure 4A the architecture / arrangement of the first pixel 429a and the second pixel 439a and the architecture / arrangement of the third pixel 429b and the fourth pixel 439b are each generally similar to Figure 2 the architecture / arrangement of the first pixel 229 and the second pixel 239 of the pixel arrangement 220. Thus, like reference numerals are used in Figure 2 and 4A to denote the same or at least generally similar components, and in view of the detailed discussion of the pixel arrangement 220 provided above, the detailed discussion of the pixel arrangement 420 is substantially omitted here for the sake of brevity.

[0078] Compared with the first pixel 229 of the pixel arrangement 220 of Figure 2 , Figure 4AThe first pixel 429a and the third pixel 429b of the pixel arrangement 420 each include four photoelectric sensors (individually identified as the first to fourth photoelectric sensors 421a to 421d) and four transfer transistors (individually identified as the first to fourth transfer transistors 422a to 422d). Each of the photoelectric sensors 421a to 421d of the first pixel 429a is configured to generate image charges (e.g., one or more electrons or holes) in response to light incident thereon. Each of the photoelectric sensors 421a to 421d of the first pixel 429a is selectively coupled to the floating diffusion region 427a of the first pixel 429a via a corresponding one of the transfer transistors 422a to 422d of the first pixel 429a. The first and second transfer transistors 422a and 422b of the first pixel 429a are selectively activated using a first transfer control signal, and the third and fourth transfer transistors 422c and 422d of the first pixel 429a are selectively activated using a second transfer control signal. The first transfer control signal may be the same signal as or a different signal from the second transfer control signal. In other embodiments, each of the transfer transistors 422a to 422d of the first pixel 429a may be selectively activated via a transfer control signal different from the transfer control signals used to selectively activate the other ones of the transfer transistors 422a to 422d of the first pixel 429a. Each of the photoelectric sensors 421a to 421d of the first pixel 429a (alone or in combination with the corresponding ones of the transfer transistors 422a to 422d) is also referred to herein as a "sub-pixel" of the first pixel 429a.

[0079] Similarly, each of the photoelectric sensors 421a to 421d of the third pixel 429b is selectively coupled to the floating diffusion region 427b of the third pixel 429b via a corresponding one of the transfer transistors 422a to 422d of the third pixel 429b. Each of the photoelectric sensors 421a to 421d of the third pixel 429b is configured to generate image charges (e.g., one or more electrons or holes) in response to light incident thereon. The first and second transfer transistors 422a and 422b of the third pixel 429b are selectively activated using a third transfer control signal, and the third and fourth transfer transistors 422c and 422d of the third pixel 429b are selectively activated using a fourth transfer control signal. The third transfer control signal may be the same signal as or a different signal from the fourth transfer control signal. Additionally or alternatively, the third transfer control signal and / or the fourth transfer control signal may be the same signal (or a different signal) as the first transfer control signal and / or the second transfer control signal discussed above with reference to the first pixel 429a. In other embodiments, each of the transfer transistors 422a to 422d of the third pixel 429b may be selectively activated via a transfer control signal different from the transfer control signals used to selectively activate the other ones of the transfer transistors 422a to 422d of the third pixel 429b. Each of the photoelectric sensors 421a to 421d of the third pixel 429b (alone or in combination with the corresponding ones of the transfer transistors 422a to 422d) is also referred to herein as a "sub-pixel" of the third pixel 429b.

[0080] In addition, compared with the second pixel 239 of the pixel arrangement 220 of Figure 2 Figure 4AThe second pixel 439a and the fourth pixel 439b of the pixel arrangement 420 each include four photoelectric sensors (individually identified as the first to fourth photoelectric sensors 431a to 431d) and four transfer transistors (individually identified as the first to fourth transfer transistors 432a to 432d). Each of the photoelectric sensors 431a to 431d in the second pixel 439a is selectively coupled to the floating diffusion region 437a of the second pixel 439a via a corresponding one of the transfer transistors 432a to 432d in the second pixel 439a. Each of the photoelectric sensors 431a to 431d in the second pixel 439a is configured to generate photoimage charges (e.g., one or more electrons or holes) in response to light incident thereon. The first and second transfer transistors 432a and 432b of the second pixel 439a are selectively activated using a fifth transfer control signal, and the third and fourth transfer transistors 432c and 432d of the second pixel 439a are selectively activated using a sixth transfer control signal. The fifth transfer control signal may be the same signal or a different signal from the sixth transfer control signal. Additionally or alternatively, the fifth transfer control signal and / or the sixth transfer control signal may be the same signal (or a different signal) as the first transfer control signal, the second transfer control signal, the third transfer control signal, and / or the fourth transfer control signal discussed above with reference to the first pixel 429a and / or the third pixel 429b. In other embodiments, each of the transfer transistors 432a to 432d in the second pixel 439a may be selectively activated via a transfer control signal different from the transfer control signals used to selectively activate the other ones of the transfer transistors 432a to 432d in the second pixel 439a. Each of the photoelectric sensors 431a to 431d in the second pixel 439a (alone or in combination with the corresponding ones of the transfer transistors 432a to 432d) is also referred to herein as a "sub-pixel" of the second pixel 439a.

[0081] Similarly, each of the photoelectric sensors 431a to 431d of the fourth pixel 439b is selectively coupled to the floating diffusion region 437b of the fourth pixel 439b via a corresponding one of the transfer transistors 432a to 432d of the fourth pixel 439b. Each of the photoelectric sensors 431a to 431d of the fourth pixel 439b is configured to photogenerate image charges (e.g., one or more electrons or holes) in response to light incident thereon. The first and second transfer transistors 432a and 432b of the fourth pixel 439b are selectively activated using a seventh transfer control signal, and the third and fourth transfer transistors 432c and 432d of the fourth pixel 439b are selectively activated using an eighth transfer control signal. The seventh transfer control signal may be the same signal as or a different signal from the eighth transfer control signal. Additionally or alternatively, the seventh transfer control signal and / or the eighth transfer control signal may be the same signal (or a different signal) as the first transfer control signal, the second transfer control signal, the third transfer control signal, the fourth transfer control signal, the fifth transfer control signal, and / or the sixth transfer control signal discussed above with reference to the first pixel 429a, the third pixel 429b, and / or the second pixel 439a. In other embodiments, each of the transfer transistors 432a to 432d of the fourth pixel 439b may be selectively activated via a transfer control signal different from the transfer control signals used to selectively activate the other ones of the transfer transistors 432a to 432d of the fourth pixel 439b. Each of the photoelectric sensors 431a to 431d of the fourth pixel 439b (alone or in combination with the corresponding ones of the transfer transistors 432a to 432d) is also referred to herein as a "sub-pixel" of the fourth pixel 439b.

[0082] Similar to Figure 2 the pixel arrangement 220, Figure 4A the pixel arrangement 420 may include a mode switch that facilitates operation of the pixel arrangement 420 in any one of three different modes: a CIS-only mode, a hybrid CIS and EVS mode, and an EVS-only mode. For example, in the illustrated embodiment, the mode switch includes a first switch 436a, a second switch 438a, a third switch 436b, and a fourth switch 438b. The first switch 436a and the second switch 438a are arranged with respect to the first pixel 429a and the second pixel 439a in a manner generally similar to Figure 2 the first switch 236 and the second switch 238 of the mode switch circuit 235 with respect to Figure 2 the first pixel 229 and the second pixel 239 of Figure 2 the first switch 236 and the second switch 238 of the mode switch circuit 235 with respect to Figure 2The first pixel 229 and the second pixel 239 are arranged in a manner that is arranged with respect to the third pixel 429b and the fourth pixel 439b. Thus, in view of the detailed discussion of the first switch 236 and the second switch 238 of the mode switch circuit 235 provided above, the detailed discussion of the first switch 436a, the second switch 438a, the third switch 436b, and the fourth switch 438b is substantially omitted here for the sake of brevity.

[0083] As Figure 4A shown, the first switch 436a and the third switch 436b are configured to receive a first switch control signal SW1. Thus, the first switch 436a and the third switch 436b are configured to be selectively activated at least in part based on the first switch control signal SW1. Additionally or alternatively, the second switch 438a and the fourth switch 438b are configured to receive a second switch control signal SW2. Accordingly, the second switch 438a and the fourth switch 438b are configured to be selectively activated at least in part based on the second switch control signal SW2.

[0084] Figures 4B to 4D is corresponding to Figure 4A a partial schematic view of a 2x2 pixel array 470 of the pixel arrangement 420. Specifically, Figures 4B to 4D each of the pixel arrays 470 in Figure 4B illustrates one of the operating modes of the pixel arrangement 420. For example, Figure 4A the pixel array 470 shown in Figure 4B illustrates only the CIS mode of the pixel arrangement 420, in which the first pixel 429a, the second pixel 439a, the third pixel 429b, and the fourth pixel 439b can each be used to capture CIS information (e.g., a CIS image signal) without loss of image quality, for example, compared to a conventional only-CIS pixel array. In some embodiments, the first pixel 429a, the second pixel 439a, the third pixel 429b, and the fourth pixel 439b can be the same color (e.g., arranged under a color filter having the same spectral response). In these and other embodiments, to place Figure 2 the pixel arrangement 420 of 3A in the only-CIS mode illustrated by the array 470 shown in Figure 2 the first switch control signal SW1 can be asserted (thereby activating the first switch 436a and the third switch 436b of the mode switch of the pixel arrangement 420), while the second switch control signal SW2 is not asserted (thereby deactivating the second switch 438a and the fourth switch 438b of the mode switch). The operation of the pixel arrangement 420 in the only-CIS mode can be generally similar to the operation of the Figure 2 pixel arrangement 220 in the only-CIS mode described in detail above with reference to Figure 2 and 3A . Thus, the detailed discussion of the only-CIS mode of the pixel arrangement 420 is omitted here for the sake of brevity.

[0085] Figure 4C The pixel array 470 shown in Figure 4A illustrates a hybrid CIS and EVS mode of the pixel arrangement 420, where the first pixel 429a and the third pixel 429b are used to capture CIS information (e.g., a CIS image signal), and the second pixel 439a and the fourth pixel 439b are used to capture non-CIS information (e.g., an event signal, event detection, phase detection autofocus, etc.). Thus, when the pixel arrangement 420 operates in the hybrid CIS and EVS mode, the pixel array 470 can provide both CIS information (e.g., from the first pixel 429a and the third pixel 429b) and non-CIS information (e.g., from the second pixel 439a and the fourth pixel 439b) simultaneously. In some embodiments, in order to Figure 4A place the pixel arrangement 420 of Figure 4C in the hybrid CIS and EVS mode illustrated by the array 470 shown in Figure 2 and 3B described in detail above, the second switch control signal SW2 can be asserted (thereby activating the second switch 438a and the fourth switch 438b of the mode switch of the pixel arrangement 420), while the first switch control signal SW1 is not asserted (thereby deactivating the first switch 436a and the third switch 436b of the mode switch). The operation of the pixel arrangement 420 in the hybrid CIS and EVS mode can be generally similar to that of the Figure 2 pixel arrangement 220 described in detail above with reference to

[0086] Figure 4D The pixel array 470 shown in Figure 4A illustrates the only EVS mode of the pixel arrangement 420, where the first pixel 429a, the second pixel 439a, the third pixel 429b, and the fourth pixel 439b are each used to capture non-CIS information (e.g., an event signal, event detection, phase detection autofocus, etc.). In some embodiments, in order to Figure 4A place the pixel arrangement 420 of Figure 4D in the only EVS mode illustrated by the array 470 shown in Figure 2 and 3C described in detail above, both the first switch control signal SW1 and the second switch control signal SW2 can be asserted, thereby activating respectively (a) the first switch 436a and the third switch 436b and (b) the second switch 438a and the fourth switch 438b of the mode switch of the pixel arrangement 420. The operation of the pixel arrangement 420 in the only EVS mode can be generally similar to that of the Figure 2The operation of the pixel arrangement 220 in only the EVS mode. Therefore, a detailed discussion of the only EVS mode of the pixel arrangement 420 is omitted here for the sake of brevity.

[0087] Referring again to Figure 4A , the first switch signal SW1 is shown as being used to control both the first switch 436a and the third switch 436b, and the second switch signal SW2 is shown as being used to control both the second switch 438a and the fourth switch 438b. In other embodiments, the first switch 436a may be configured to receive a different switch control signal than the third switch 436b. In these and other embodiments, the second switch 438a may be configured to receive a different switch control signal than the fourth switch 438b. Using different switch control signals can facilitate the independent activation of the first switch 436a, the second switch 438a, the third switch 436b, and / or the fourth switch 438b, which can allow for operation in the hybrid CIS and EVS modes Figure 4A of the pixel arrangement 420 with even more possibilities. Some of these other possibilities are shown in Figures 4E to 4J , which is a partial schematic diagram of a 2x2 pixel array 470 corresponding to the pixel arrangement 420 of Figure 4A .

[0088] For example, Figure 4E the pixel array 470 shown in Figure 4A illustrates one possibility of the hybrid CIS and EVS modes of the pixel arrangement 420 of Figure 4A , where the first pixel 429a, the third pixel 429b, and the fourth pixel 439b are used to capture CIS image signals, and the second pixel 439a is used to capture event signals. In some embodiments, in order to place the pixel arrangement 420 of Figure 4E in the hybrid CIS and EVS modes illustrated by the array 470 shown in

[0089] Figure 4F , the second switch 438a and the third switch 436b of the mode switch of the pixel arrangement 420 may be activated, while the first switch 436a and the fourth switch 438b of the mode switch are deactivated, such that both CIS and non-CIS information (e.g., intensity changes or event information) can be obtained without sacrificing too much color pixel information for EVS functionality in accordance with the teachings of the present disclosure.

[0089] Figure 4F The pixel array 470 shown in Figure 4A illustrates another possibility of the hybrid CIS and EVS modes of the pixel arrangement 420 of Figure 4A , where the first pixel 429a, the second pixel 439a, and the third pixel 429b are used to capture CIS image signals, and the fourth pixel 439b is used to capture event signals. In some embodiments, in order to place the pixel arrangement 420 of Figure 4FThe hybrid CIS and EVS mode illustrated in the array 470, the first switch 436a and the fourth switch 438b of the mode switch of the pixel arrangement 420 can be activated, while the second switch 438a and the third switch 436b of the mode switch are deactivated, so that both CIS and non-CIS information (e.g., intensity changes or event information) can be obtained without degrading the image quality (e.g., not sacrificing all color pixels for EVS functionality).

[0090] Figure 4G Another possibility of the hybrid CIS and EVS mode of the pixel arrangement 420 illustrated in Figure 4A where the third pixel 429b and the fourth pixel 439b are used to capture the CIS image signal, and the first pixel 429a and the second pixel 439a are used to capture the event signal. In some embodiments, in order to place the Figure 4A pixel arrangement 420 of in the hybrid CIS and EVS mode illustrated by the array 470 shown in Figure 4G the first switch 436a, the second switch 438a and the third switch 436b of the mode switch of the pixel arrangement 420 can be activated, while the fourth switch 438b of the mode switch is deactivated, so that both CIS and non-CIS information (e.g., intensity changes or event information) can be obtained without sacrificing too much color pixel information for EVS functionality according to the teachings of the present disclosure.

[0091] Figure 4H Another possibility of the hybrid CIS and EVS mode of the pixel arrangement 420 illustrated in the pixel array 470 shown in Figure 4A where the first pixel 429a and the second pixel 439a are used to capture the CIS image signal, and the third pixel 429b and the fourth pixel 439b are used to capture the event signal. In some embodiments, in order to place the Figure 4A pixel arrangement 420 of in the hybrid CIS and EVS mode illustrated by the array 470 shown in Figure 4H the first switch 436a, the third switch 436b and the fourth switch 438b of the mode switch of the pixel arrangement 420 can be activated, while the second switch 438a of the mode switch is deactivated, so that both CIS and non-CIS information (e.g., intensity changes or event information) can be obtained without sacrificing too much color pixel information for EVS functionality according to the teachings of the present disclosure.

[0092] Figure 4I Another possibility of the hybrid CIS and EVS mode of the pixel arrangement 420 illustrated in the pixel array 470 shown in Figure 4AAnother possibility for the hybrid CIS and EVS mode of the pixel arrangement 420, where the first pixel 429a, the second pixel 439a, and the fourth pixel 439b are used to capture the CIS image signal, and the third pixel 429b is used to capture the event signal. In some embodiments, in order to Figure 4A place the pixel arrangement 420 of Figure 4I in the hybrid CIS and EVS mode illustrated by the array 470 shown in

[0093] Figure 4J the first switch 436a, the second switch 438a, and the fourth switch 438b of the mode switch of the pixel arrangement 420 can be activated, while the third switch 436b of the mode switch is deactivated, so that both CIS and non-CIS information (e.g., intensity changes or event information) can be obtained without sacrificing too much color pixel information in exchange for the EVS functionality according to the teachings of the present disclosure. Figure 4A Another possibility for the hybrid CIS and EVS mode of the pixel arrangement 420 illustrated by the pixel array 470 shown in Figure 4A where the second pixel 439a, the third pixel 429b, and the fourth pixel 439b are used to capture the CIS image signal, and the first pixel 429a is used to capture the event signal. In some embodiments, in order to Figure 4J place the pixel arrangement 420 of

[0094] in the hybrid CIS and EVS mode illustrated by the array 470 shown in Figure 4A the second switch 438a, the third switch 436b, and the fourth switch 438b of the mode switch of the pixel arrangement 420 can be activated, while the first switch 436a of the mode switch is deactivated, so that both CIS and non-CIS information (e.g., intensity changes or event information) can be obtained without sacrificing too much color pixel information in exchange for the EVS functionality according to the teachings of the present disclosure. Figures 4K to 4Q In some embodiments, the transfer transistors 422a to 422d of the first pixel 429a, the transfer transistors 432a to 432d of the second pixel 439a, the transfer transistors 422a to 422d of the third pixel 429b, and / or the transfer transistors 432a to 432d of the fourth pixel 439b can be utilized to achieve Figure 4A even more possibilities for the hybrid CIS and EVS mode of the pixel arrangement 420, some of which are shown in Figures 4K to 4Q For example, Figure 4K the pixel array 470 shown in Figure 4A illustrates the possibility of the hybrid CIS and EVS mode of the pixel arrangement 420, where the second pixel 439a, the third pixel 429b, and the fourth pixel 439b are used to capture the CIS image signal, and the first pixel 429a is used to capture the event signal. In some embodiments, in order to Figure 4A place the pixel arrangement 420 ofFigure 4K The hybrid CIS and EVS modes illustrated by the array 470 shown in can be such that the first switch 436a, the second switch 438a, and the third switch 436b of the mode switch of the pixel arrangement 420 are activated, while (i) the fourth switch 438b is deactivated and (ii) the transfer transistors 432a to 432d of the second pixel 439a are deactivated. When an image signal corresponding to the image charges generated by the photosensors 431a to 431d of the second pixel 439a is to be read out onto the bit line 430, the first switch 436a of the mode switch and the transfer transistors 432a to 432d of the second pixel 439a can be activated, while the transfer transistors 422a to 422d of the first pixel 429a and the second switch 438a of the mode switch are deactivated.

[0095] Figure 4L The pixel array 470 shown in illustrates Figure 4A Another possibility of the hybrid CIS and EVS modes of the pixel arrangement 420, where the first pixel 429a, the second pixel 439a, and the fourth pixel 439b are used to capture CIS image signals, and the third pixel 429b is used to capture event signals. In some embodiments, in order to place Figure 4A the pixel arrangement 420 of into the hybrid CIS and EVS modes illustrated by the array 470 shown in Figure 4L The first switch 436a, the third switch 436b, and the fourth switch 438b of the mode switch of the pixel arrangement 420 can be activated, while (i) the second switch 438a is deactivated and (ii) the transfer transistors 432a to 432d of the fourth pixel 439b are deactivated. When an image signal corresponding to the image charges generated by the photosensors 431a to 431d of the fourth pixel 439b is to be read out onto the bit line 430, the third switch 436b of the mode switch and the transfer transistors 432a to 432d of the fourth pixel 439b can be activated, while the transfer transistors 422a to 422d of the third pixel 429b and the fourth switch 438b of the mode switch are deactivated.

[0096] Figure 4M The pixel array 470 shown in illustrates Figure 4A Another possibility of the hybrid CIS and EVS modes of the pixel arrangement 420, where the second pixel 439a and the third pixel 429b are used to capture CIS image signals, and the first pixel 429a and the fourth pixel 439b are used to capture event signals. In some embodiments, in order to place Figure 4A the pixel arrangement 420 of into the hybrid CIS and EVS modes illustrated by Figure 4MThe hybrid CIS and EVS modes illustrated in the array 470 show that the first switch 436a, the second switch 438a, and the fourth switch 438b of the mode switch of the pixel arrangement 420 can be activated, while (i) the third switch 436b is deactivated and (ii) the transfer transistors 432a to 432d of the second pixel 439a are deactivated. When an image signal corresponding to the image charge generated by the photosensors 431a to 431d of the second pixel 439a is to be read out onto the bit line 430, the first switch 436a of the mode switch and the transfer transistors 432a to 432d of the second pixel 439a can be activated, while the transfer transistors 422a to 422d of the first pixel 429a and the second switch 438a of the mode switch are deactivated.

[0097] Figure 4N Another possibility of the hybrid CIS and EVS modes of the pixel arrangement 420 illustrated in Figure 4A where the first pixel 429a and the fourth pixel 439b are used to capture CIS image signals, and the second pixel 439a and the third pixel 429b are used to capture event signals. In some embodiments, to place Figure 4A the pixel arrangement 420 of Figure 4N The hybrid CIS and EVS modes illustrated in the array 470 show that the second switch 438a, the third switch 436b, and the fourth switch 438b of the mode switch of the pixel arrangement 420 can be activated, while (i) the first switch 436a is deactivated and (ii) the transfer transistors 432a to 432d of the fourth pixel 439b are deactivated. When an image signal corresponding to the image charge generated by the photosensors 431a to 431d of the fourth pixel 439b is to be read out onto the bit line 430, the third switch 436b of the mode switch and the transfer transistors 432a to 432d of the fourth pixel 439b can be activated, while the transfer transistors 422a to 422d of the third pixel 429b and the fourth switch 438b of the mode switch are deactivated.

[0098] Figure 4O Another possibility of the hybrid CIS and EVS modes of the pixel arrangement 420 illustrated in Figure 4A where the second pixel 439a and the fourth pixel 439b are used to capture CIS image signals, and the first pixel 429a and the third pixel 429b are used to capture event signals. In some embodiments, to place Figure 4A the pixel arrangement 420 of Figure 4OThe hybrid CIS and EVS modes illustrated by the array 470 shown can be activated for the first switch 436a, the second switch 438a, the third switch 436b, and the fourth switch 438b of the mode switch of the pixel arrangement 420, while (i) the transfer transistors 432a to 432d of the second pixel 439a and (ii) the transfer transistors 432a to 432d of the fourth pixel 439b are deactivated. When an image signal corresponding to the image charge generated by the photosensors 431a to 431d of the second pixel 439a is to be read out onto the bit line 430, the first switch 436a of the mode switch and the transfer transistors 432a to 432d of the second pixel 439a can be activated, while the transfer transistors 422a to 422d of the first pixel 429a and the second switch 438a of the mode switch are deactivated. Similarly, when an image signal corresponding to the image charge generated by the photosensors 431a to 431d of the fourth pixel 439b is to be read out onto the bit line 430, the third switch 436b of the mode switch and the transfer transistors 432a to 432d of the fourth pixel 439b can be activated, while the transfer transistors 422a to 422d of the third pixel 429b and the fourth switch 438b of the mode switch are deactivated.

[0099] Figure 4P Another possibility of the hybrid CIS and EVS modes of the pixel arrangement 420 shown in Figure 4A where the second pixel 439a is used to capture a CIS image signal, and the first pixel 429a, the third pixel 429b, and the fourth pixel 439b are used to capture event signals. In some embodiments, in order to place Figure 4A the pixel arrangement 420 of Figure 4P The hybrid CIS and EVS modes illustrated by the array 470 shown can be activated for the first switch 436a, the second switch 438a, the third switch 436b, and the fourth switch 438b of the mode switch of the pixel arrangement 420, while (i) the transfer transistors 432a to 432d of the second pixel 439a are deactivated. When an image signal corresponding to the image charge generated by the photosensors 431a to 431d of the second pixel 439a is to be read out onto the bit line 430, the first switch 436a of the mode switch and the transfer transistors 432a to 432d of the second pixel 439a can be activated, while the transfer transistors 422a to 422d of the first pixel 429a and the second switch 438a of the mode switch are deactivated.

[0100] Figure 4Q Another possibility of the hybrid CIS and EVS modes of the pixel arrangement 420 shown in Figure 4AAnother possibility for the hybrid CIS and EVS mode of the pixel arrangement 420, where the fourth pixel 439b is used to capture the CIS image signal, and the first pixel 429a, the second pixel 439a, and the third pixel 429b are used to capture event signals. In some embodiments, in order to place the Figure 4A pixel arrangement 420 into the hybrid CIS and EVS mode illustrated by the array 470 shown in Figure 4Q , the first switch 436a, the second switch 438a, the third switch 436b, and the fourth switch 438b of the mode switch of the pixel arrangement 420 can be activated, while (i) the transfer transistors 432a to 432d of the fourth pixel 439b are deactivated. When the image signal corresponding to the image charge generated by the photosensors 431a to 431d of the fourth pixel 439b is to be read out onto the bit line 430, the third switch 436b of the mode switch and the transfer transistors 432a to 432d of the fourth pixel 439b can be activated, while the transfer transistors 422a to 422d of the third pixel 429b and the fourth switch 438b of the mode switch are deactivated.

[0101] Referring again to Figure 4B , the first pixel 429a, the second pixel 439a, the third pixel 429b, and the fourth pixel 439b of the pixel array 470 can each include corresponding microlenses 485a to 485d positioned above their respective photosensors 421a to 421d and 431a to 431d. In other embodiments, microlenses can be shared between two or more of the first pixel 429a, the second pixel 439a, the third pixel 429b, and / or the fourth pixel 439b. Additionally or alternatively, the first pixel 429a, the second pixel 439a, the third pixel 429b, and / or the fourth pixel 439b can each include color filters above their respective photosensors 421a to 421d and 431a to 431d. In other embodiments, color filters can be shared between two or more of the first pixel 429a, the second pixel 439a, the third pixel 429b, and / or the fourth pixel 439b. Some of the color filters can be configured to transmit light corresponding to a specific color or a specific range of light wavelengths (e.g., red, green, blue, or non-RGB colors) to the photosensors 421a to 421d and / or 431a to 431d positioned below the color filters. Additionally or alternatively, some of the color filters can be transparent such that all light incident on the color filter can be transmitted through the color filter and illuminate the photosensors 421a to 421d and / or 431a to 431d positioned below the color filter.

[0102] Figure 5Ais a partial schematic circuit diagram of another pixel arrangement 520 configured according to various embodiments of the present technology. As shown, the pixel arrangement 520 includes two pixels: a first pixel 529 and a second pixel 539. The first pixel 529 and / or the second pixel 539 may be an example of: Figure 1 one of the pixels in the pixel array 108 of Figure 2 the first pixel 229 of Figure 2 the second pixel 239 of Figure 4A one or more of the pixels 429a, 429b, 439a and / or 439b of Figure 4A ; or another pixel configured according to various embodiments of the present technology. As shown, the architecture / arrangement of the first pixel 529 and the second pixel 539 are each generally similar to Figure 4A and 5A the architecture / arrangement of the first pixel 429a and the second pixel 439a of the pixel arrangement 420, except that the first pixel 529 and the second pixel 539 of the pixel arrangement 520 are horizontally arranged with respect to each other instead of vertically arranged with respect to each other. Thus, like reference numerals are used in and

[0103] to denote the same or at least generally similar components, and in view of the detailed discussion of the pixel arrangement 420 provided above, the detailed discussion of the pixel arrangement 520 is substantially omitted here for the sake of brevity. Figure 4A Figure 5A Similar to Figure 4A the pixel arrangement 420 of Figure 4A the pixel arrangement 520 of

[0104] As Figure 5AAs shown, the first switch 536 is configured to receive a first switch control signal SW1. Thus, the first switch 536 is configured to be selectively activated at least in part based on the first switch control signal SW1. Additionally or alternatively, the second switch 538 is configured to receive a second switch control signal SW2. Accordingly, the second switch 538 is configured to be selectively activated at least in part based on the second switch control signal SW2.

[0105] Figures 5B to 5D corresponds to Figure 5A partial schematic view of a 1x2 pixel array 570 of the pixel arrangement 520. Specifically, Figures 5B to 5D each of the pixel arrays 570 in Figure 5B illustrates one of the operating modes of the pixel arrangement 520. For example, Figure 5A the pixel array 570 shown in Figure 5B illustrates only the CIS mode of the pixel arrangement 520, where the first pixel 529 and the second pixel 539 can each be used to capture a CIS image signal. In some embodiments, in order to place Figure 2 the pixel arrangement 520 of 3A into the only CIS mode illustrated by the array 570 shown in Figure 2 the first switch control signal SW1 can be asserted (thereby activating the first switch 536 of the mode switch of the pixel arrangement 520), while the second switch control signal SW2 is not asserted (thereby deactivating the second switch 538 of the mode switch). The operation of the pixel arrangement 520 in the only CIS mode can be generally similar to that of the

[0106] Figure 5C the pixel array 570 shown in Figure 5A illustrates the hybrid CIS and EVS mode of the pixel arrangement 520 of Figure 5A where the first pixel 529 is used to capture a CIS image signal and the second pixel 539 is used to capture an event signal. In some embodiments, in order to place Figure 5C the pixel arrangement 520 of Figure 2 into the hybrid CIS and EVS mode illustrated by the array 570 shown in 3B the second switch control signal SW2 can be asserted (thereby activating the second switch 538 of the mode switch of the pixel arrangement 520), while the first switch control signal SW1 is not asserted (thereby deactivating the first switch 536 of the mode switch). The operation of the pixel arrangement 520 in the hybrid CIS and EVS mode can be generally similar to that of the Figure 2The operation of the pixel arrangement 220 in the hybrid CIS and EVS modes. Thus, a detailed discussion of the hybrid CIS and EVS modes of the pixel arrangement 520 is omitted here for the sake of brevity.

[0107] Figure 5D The pixel array 570 shown in Figure 5A illustrates the only EVS mode of the pixel arrangement 520, where the first pixel 529 and the second pixel 539 are each used to capture event signals. In some embodiments, to place the Figure 5A pixel arrangement 520 in the only EVS mode illustrated by the array 570 shown in Figure 5D , both the first switch control signal SW1 and the second switch control signal SW2 can be asserted, thereby activating the first switch 536 and the second switch 538, respectively, of the mode switch of the pixel arrangement 520. The operation of the pixel arrangement 520 in the only EVS mode can be generally similar to that of the Figure 2 and 3C detailedly described Figure 2 pixel arrangement 220 in the only EVS mode. Thus, a detailed discussion of the only EVS mode of the pixel arrangement 520 is omitted here for the sake of brevity.

[0108] Referring again to Figure 5B, the first pixel 529 may include a first microlens 585a over two of its photosensors (e.g., the first photosensor 521a and the third photosensor 521c) and a second microlens 585b over two other of its photosensors (e.g., the second photosensor 521b and the fourth photosensor 521d). Similarly, the second pixel 539 may include a third microlens 585c over two of its photosensors (e.g., the first photosensor 531a and the third photosensor 531c) and a fourth microlens 585d over two other of its photosensors (e.g., the second photosensor 531b and the fourth photosensor 531d). Each of the photosensors 521a to 521d of the first pixel 529 is configured to generate an image charge (e.g., one or more electrons or holes) in response to light guided thereto by a corresponding microlens (e.g., the first microlens 585a or the second microlens 585b). Each of the photosensors 531a to 531d of the second pixel 539 is configured to generate an image charge (e.g., one or more electrons or holes) in response to light guided thereto by a corresponding microlens (e.g., the third microlens 585c or the fourth microlens 585d). Additionally or alternatively, the first pixel 529 and / or the second pixel 539 may each include one or more color filters positioned over their respective photosensors 521a to 521d and / or 531a to 531d, respectively. In other embodiments, color filters may be shared between the first pixel 529 and the second pixel 539. Some of the color filters may be configured to transmit light corresponding to a particular color (e.g., red, green, blue, or a non-RGB color) to the photosensors 521a to 521d and / or 531a to 531d positioned below the color filter. Additionally or alternatively, some of the color filters may be transparent such that all light incident on the color filter may pass through the color filter and illuminate the photosensors 521a to 521d and / or 531a to 531d positioned below the color filter.

[0109] discussed above Figure 2 and 5A respectively relate to the horizontal pixel arrangements 220 and 520 of two pixels, where the first pixel is positioned to the left of the second pixel. In other pixel arrangements of the present technology, the first pixel may be positioned to the right of the second pixel. Additionally, Figure 4A relates to the pixel arrangement 420 of four pixels, where similar pixels (e.g., the first pixel 429a and the third pixel 429b, and the second pixel 439a and the fourth pixel 439b) are arranged diagonally to each other. Other pixel arrangements of any number of pixels are of course possible and within the scope of the present technology. Figures 6 to 9 is a partial schematic diagram illustrating various examples of these other pixel arrangements. For example, Figure 6is a partial schematic view of a pixel arrangement 670 configured according to various embodiments of the present technology. As shown, the pixel arrangement 670 includes four pixels: a first pixel 629a, a second pixel 639a, a third pixel 629b, and a fourth pixel 639b. In the pixel arrangement 670, similar pixels (e.g., the first pixel 629a and the third pixel 629b, and the second pixel 639a and the fourth pixel 639b) are vertically aligned with each other.

[0110] As another example, Figure 7 is a partial schematic view of a pixel arrangement 770 configured according to various embodiments of the present technology. As shown, the pixel arrangement 770 includes four pixels: a first pixel 729a, a second pixel 739a, a third pixel 729b, and a fourth pixel 739b. In the pixel arrangement 770, similar pixels (e.g., the first pixel 729a and the third pixel 729b, and the second pixel 739a and the fourth pixel 739b) are horizontally aligned with each other.

[0111] As yet another example, Figure 8 is a partial schematic view of a pixel arrangement 870 configured according to various embodiments of the present technology. As shown, the pixel arrangement 870 includes four pixels: a first pixel 829a, a second pixel 839a, a third pixel 829b, and a fourth pixel 839b. In the pixel arrangement 870, similar pixels (e.g., the first pixel 829a and the third pixel 829b, and the second pixel 839a and the fourth pixel 839b) are diagonally arranged with each other in a direction opposite to that of Figure 4A the pixel arrangement 420.

[0112] As yet another example, Figure 9 is a partial schematic view of a pixel arrangement 970 configured according to various embodiments of the present technology. As shown, the pixel arrangement 970 includes two pixels: a first pixel 929 and a second pixel 939. In the pixel arrangement 970, the first pixel 929 and the second pixel 939 are vertically aligned with each other, with the second pixel 939 positioned above the first pixel 929. In other embodiments, the first pixel 929 and the second pixel 939 may be vertically aligned with each other, with the first pixel 929 positioned above the second pixel 939.

[0113] Figure 10 is a partial schematic circuit diagram of another pixel arrangement 1020 configured according to various embodiments of the present technology. As shown, the pixel arrangement 1020 includes a first pixel 1029 and a second pixel 1039. The first pixel 1029 and / or the second pixel 1039 may be an example of Figure 1 one of the pixels in the pixel array 108 of Figure 2 the first pixel 229 of Figure 2 the second pixel 239 of Figure 4Aone or more of pixels 429a, 429b, 439a, and / or 439b; or another pixel configured according to various embodiments of the present technology. As shown, the architecture / arrangement of the first pixel 1029 and the second pixel 1039 are each generally similar to Figure 4A the architecture / arrangement of the first pixel 429a and the second pixel 439a of the pixel arrangement 420 of Figure 4A and 10 respectively, except that the first pixel 1029 further includes a dual floating diffusion region (DFD) switch 1026 (e.g., a transistor, a standard switch, etc.) that selectively couples the floating diffusion region 1027 of the first pixel 1029 to a MOS capacitor 1028 coupled to ground (e.g., for dual conversion gain (DCG) operation and / or other high dynamic range (HDR) imaging applications). Thus, like reference numerals are used in

[0114] to denote the same or at least generally similar components, and in view of the detailed discussion of the pixel arrangement 420 provided above, the detailed discussion of the pixel arrangement 1020 is substantially omitted here for the sake of brevity.

[0114] Similar to Figure 4A the pixel arrangement 420 of Figure 10 the pixel arrangement 1020 of Figure 4A may include a mode switch 1035 that facilitates operating the pixel arrangement 1020 in any of three different modes: a CIS-only mode, a hybrid CIS and EVS mode, and an EVS-only mode. For example, in the illustrated embodiment, the mode switch 1035 includes a first switch 1036 and a second switch 1038. The first switch 1036 and the second switch 1038 are arranged with respect to the first pixel 1029 and the second pixel 1039 in a manner generally similar to Figure 4A the first switch 436a and the second switch 438a of the mode switch circuit of the pixel arrangement 420 of Figure 4A with respect to the first pixel 429a and the second pixel 439a arrangement of Figure 4A Thus, in view of the detailed discussion of the first switch 436a and the second switch 438a of the mode switch circuit of the pixel arrangement 420 provided above, the detailed discussion of the first switch 1036 and the second switch 1038 is substantially omitted here for the sake of brevity.

[0115] Figure 11 is incorporated into Figure 10Partial schematic circuit diagram of the pixel arrangement 1120 of multiple examples of the pixel arrangement 1020. Specifically, the pixel arrangement 1120 is a 2x2 pixel array that includes a first example of the pixel arrangement 1020 (referred to herein as the first pixel arrangement 1020a) and a second example of the pixel arrangement 1020 (referred to herein as the second pixel arrangement 1020b). The first pixel arrangement 1020a and the second pixel arrangement 1020b are positioned as the pixel arrangement 1120 such that similar pixels (e.g., the first pixel 1029a of the first pixel arrangement 1020a and the first pixel 1029b of the second pixel arrangement 1020b, and the second pixel 1039a of the first pixel arrangement 1020a and the second pixel 1039b of the second pixel arrangement 1020b) are diagonally positioned as the 2x2 pixel array of the pixel arrangement 1120. The first pixel 1029a, the first pixel 1029b, the second pixel 1039a, and the second pixel 1039b may be examples of: Figure 1 one of the pixels of the pixel array 108; Figure 2 the first pixel 229; Figure 2 the second pixel 239; Figure 4A one or more of the pixels 429a, 429b, 439a, and / or 439b; or another pixel configured according to various embodiments of the present technology. As shown, the architecture / arrangement of the pixel arrangement 1120 is generally similar to Figure 4A the architecture / arrangement of the pixel arrangement 420. Therefore, in view of the detailed discussion of the pixel arrangement 420 provided above, the detailed discussion of the pixel arrangement 1120 is substantially omitted here for the sake of brevity.

[0116] The first pixel arrangement 1020a and / or the second pixel arrangement 1020b may include mode switches. In the illustrated embodiment, the first pixel arrangement 1020a includes a mode switch 1035a, and the second pixel arrangement 1020b includes a mode switch 1035b. Each of the mode switches 1035a and 1035b includes a first switch 1036 and a second switch 1038, which facilitate operating the pixel arrangement 1120 in any one of the following three modes: only the CIS mode, the hybrid CIS and EVS mode, and only the EVS mode. As shown, the first switch 1036 of the mode switch 1035a and the first switch 1036 of the mode switch 1035b are each configured to receive a first switch control signal CIS_SW, and the second switch 1038 of the mode switch 1035a and the second switch 1038 of the mode switch 1035b are each configured to receive a second switch control signal EVS_SW. As referred to above Figure 4AIn other embodiments of the present technology, the first switch 1036 of the mode switch 1035a can be configured to receive a different switch control signal than the first switch 1036 of the mode switch 1035b, and / or the second switch 1038 of the mode switch 1035a can be configured to receive a different switch control signal than the second switch 1038 of the mode switch 1035b. The separate control signals can facilitate greater control over which pixels of the pixel arrangement 1120 are operated to capture CIS information and which pixels of the pixel arrangement 1120 are operated to capture non-CIS information when the pixel arrangement 1120 is operating in the hybrid CIS and EVS modes.

[0117] Also as Figure 11 described, the transfer transistors of the first pixel 1029a and the first pixel 1029b are controlled using the same signals TXL_CIS and TXR_CIS; the transfer transistors of the second pixel 1039a and the second pixel 1039b are controlled using the same signals TXL_EVS and TXR_EVS; and the row selection transistors of the first pixel 1029a and the first pixel 1029b are controlled using the same signal RS. In addition, the row selection transistors of the first pixel 1029a and the first pixel 1029b are coupled to the same bit line 1030 or bit line group. Thus, when the pixel arrangement 1120 is operating in the CIS-only mode or in the hybrid CIS and EVS modes, CIS information is simultaneously read out from the first pixel arrangement 1020a onto the same bit line 1030 (or bit line group) as the CIS information read out from the second pixel arrangement 1020b. In addition, both the second switch 1038 of the mode switch 1035a of the first pixel arrangement 1020a and the second switch 1038 of the mode switch 1035b of the second pixel arrangement 1020b are coupled to the EVS readout circuitry (e.g., Figure 1 one or more of the event-driven circuits included in the event-driven sensor array 112 shown in

[0118] In other embodiments, the transfer transistors of the first pixel 1029a and the transfer transistors of the first pixel 1029b may be controlled using different control signals; the transfer transistors of the second pixel 1039a and the transfer transistors of the second pixel 1039b may be controlled using different control signals; the row selection transistors of the first pixel 1029a and the row selection transistors of the first pixel 1029b may be controlled using different control signals; the reset transistors of the first pixel 1029a and the reset transistors of the first pixel 1029b may be controlled using different control signals; and / or the DFD switches of the first pixel 1029a and the DFD switches of the first pixel 1029b may be controlled using different control signals. Using different control signals may facilitate independent control of the various components of the first pixel arrangement 1020a and / or the second pixel arrangement 1020b. In these and other embodiments, the row selection transistors of the first pixel 1029a may be coupled to different bit lines and / or different groups of bit lines than the row selection transistors of the first pixel 1029b, and / or the second switch 1038 of the mode switch 1035a of the first pixel arrangement 1020a and the second switch 1038 of the mode switch 1035b of the second pixel arrangement 1020b may be coupled to different hybrid junctions, different groups of hybrid junctions, and / or different EVS readout circuitry (e.g., different event-driven circuits or different groups of event-driven circuits).

[0119] Similar to other pixel arrangements discussed herein, the first pixel 1029a, the first pixel 1029b, the second pixel 1039a, and / or the second pixel 1039b may be disposed under a color filter and / or a microlens. One or more of the color filters may have one of a variety of colors (e.g., red, green, or blue). The first pixel 1029a, the first pixel 1029b, the second pixel 1039a, and / or the second pixel 1039b may be disposed under color filters of the same color or different colors. Additionally or alternatively, the first pixel 1029a, the first pixel 1029b, the second pixel 1039a, and / or the second pixel 1039b may be disposed (a) under a color filter having a non-RGB or transparent filter or (b) under no filter.

[0120] The principles of the present technology may also be utilized in a phase detection autofocus (PDAF) pixel architecture. For example, Figure 12A is a partial schematic circuit diagram of a pixel arrangement 1220 configured according to various embodiments of the present technology. The pixel arrangement 1220 may be or include a dual-photoelectric sensor autofocus pixel circuit and is thus also referred to herein as "pixel 1220". The pixel 1220 may be Figure 1An example of one of the pixels in the pixel array 108 or another pixel configured according to various embodiments of the present technology. As shown, pixel 1220 includes a left sub-pixel 1229 and a right sub-pixel 1239. The architecture / arrangement of the left sub-pixel 1229 and the right sub-pixel 1239 of pixel 1220 is generally similar to Figure 2 the first pixel 229 and the second pixel 239 of the pixel arrangement 220 of Figure 2 and 12A . Therefore, like reference numerals are used in

[0121] and Figure 2 to denote the same or at least substantially similar components, and in view of the detailed discussion of the pixel arrangement 220 provided above, the detailed discussion of pixel 1220 is substantially omitted here for the sake of brevity. Figure 12A Compared with the first pixel 229 and the second pixel 239 of the pixel arrangement 220 of

[0122] each including the pitch of a complete pixel, the pitch of the left sub-pixel 1229 and the pitch of the right sub-pixel 1239 of the pixel 1220 of Figure 2 are each half of the pixel. Therefore, the photosensor 1221 of the left sub-pixel 1229 can be regarded as the left photosensor of the dual-photosensor autofocus pixel circuit 1220 (e.g., the left channel of pixel 1220), and the photosensor 1231 of the right sub-pixel 1239 can be regarded as the right photosensor of the dual-photosensor autofocus pixel circuit 1220 (e.g., the right channel of pixel 1220). Figure 12A Similar to the pixel arrangement 220 of Figure 2 , the pixel 1220 of Figure 2 can include a mode switch 1235 that facilitates operating the pixel 1220 in any of the following three different modes: only CIS mode, hybrid CIS and EVS mode, and only EVS mode. For example, in the illustrated embodiment, the mode switch 1235 includes a first switch 1236 and a second switch 1238. The first switch 1236 and the second switch 1238 are arranged with respect to the left sub-pixel 1229 and the right sub-pixel 1239 in a manner generally similar to the first switch 236 and the second switch 238 of the mode switch circuit 235 of the pixel arrangement 220 of Figure 2 with respect to the first pixel 229 and the second pixel 239. Therefore, in view of the detailed discussion of the first switch 236 and the second switch 238 of the mode switch circuit 235 provided above with reference to

[0123] as Figure 12A, the first switch 1236 is configured to receive the first switch control signal CIS_MODE_SW. Thus, the first switch 1236 is configured to be selectively activated based at least in part on the first switch control signal CIS_MODE_SW. Additionally or alternatively, the second switch 1238 is configured to receive the second switch control signal EVS_MODE_SW. Thus, the second switch 1238 is configured to be selectively activated based at least in part on the second switch control signal EVS_MODE_SW.

[0124] Figures 12B to 12D is corresponding to Figure 12A 1 is a partial schematic diagram of a pixel array 1270 of the pixel arrangement 1220. The pixel array 1270 is also referred to herein as a "photoelectric sensor array 1270". Figures 12B to 12D Each of describes one of the operating modes of pixel 1220. For example, Figure 12B The photosensor array 1270 shown in FIG. 1 illustrates a CIS-only mode of the pixel 1220, where the left half pixel 1229 and the right half pixel 1239 can each be used to capture a CIS image signal (e.g., to form phase information). In some embodiments, Figure 12A The pixels 1220 are placed by Figure 12B 12, the first switch control signal CIS_MODE_SW may be asserted (thereby activating the first switch 1236 of the mode switch 1235 of the pixel 1220), while the second switch control signal EVS_MODE_SW is not asserted (thereby deactivating the second switch 1238 of the mode switch 1235). The operation of the pixel 1220 in the CIS-only mode may be substantially similar to the above-referenced Figure 2 and 3A Detailed description Figure 2 Therefore, a detailed discussion of the CIS-only mode of the pixel arrangement 220 is omitted here for the sake of brevity.

[0125] Figure 12C The photoelectric sensor array 1270 shown in FIG. Figure 12A In some embodiments, in order to capture the CIS image signal, the left half pixel 1229 is used to capture the CIS image signal, and the right half pixel 1239 is used to capture the event signal. Figure 12A The pixels 1220 are placed by Figure 12CThe hybrid CIS and EVS modes illustrated by the photoelectric sensor array 1270 are described. The second switch control signal EVS_MODE_SW can be asserted (thereby activating the second switch 1238 of the mode switch 1235 of the pixel 1220), while the first switch control signal CIS_MODE_SW is not asserted (thereby deactivating the first switch 1236 of the mode switch 1235). The operation of the pixel 1220 in the hybrid CIS and EVS modes can be generally similar to that of the pixel arrangement 220 described in detail above with reference to Figure 2 and 3B described in detail Figure 2 in the hybrid CIS and EVS modes. Therefore, the detailed discussion of the hybrid CIS and EVS modes of the pixel 1220 is omitted here for the sake of brevity.

[0126] Figure 12D The photoelectric sensor array 1270 illustrated in Figure 12A the only EVS mode of the pixel 1220, where the left half pixel 1229 and the right half pixel 1239 are each used to capture event signals. In some embodiments, in order to place the Figure 12A pixel 1220 in the only EVS mode illustrated by the photoelectric sensor array 1270 in Figure 12D , both the first switch control signal CIS_MODE_SW and the second switch control signal EVS_MODE_SW can be asserted, thereby activating the first switch 1236 and the second switch 1238 of the mode switch 1235 of the pixel 1220 respectively. The operation of the pixel 1220 in the only EVS mode can be generally similar to that of the pixel arrangement 220 described in detail above with reference to Figure 2 and 3C described in detail Figure 2 in the only EVS mode. Therefore, the detailed discussion of the only EVS mode of the pixel 1220 is omitted here for the sake of brevity.

[0127] Referring again to Figure 12B, the microlens 1285 can be positioned over the photoelectric sensors 1221 and 1231 of the pixel 1220. In these and other embodiments, the microlens 1285 can be configured to direct the first light and the second light to the photoelectric sensors 1221 and 1231 of the pixel 1220 respectively. In other embodiments, different microlenses can be positioned over the photoelectric sensors 1221 and 1231. In some embodiments, different color filters can be positioned over the photoelectric sensors 1221 and 1231. In other embodiments, the color filters can be shared between the photoelectric sensors 1221 and 1231. One or more of the color filters can be configured to transmit light corresponding to a specific color (e.g., red, green, or blue or non-RGB colors) to the photoelectric sensors 1221 and / or 1231 positioned below the color filter. Additionally or alternatively, one or more of the color filters can be transparent such that all light incident on the color filter can be transmitted through the color filter and illuminate the photoelectric sensors 1221 and / or 1231 positioned below the color filter.

[0128] Figure 12A The left half-pixel 1229 and the right half-pixel 1239 of the pixel 1220 are illustrated as being horizontally aligned with each other. Thus, the photoelectric sensor 1221 can correspond to the left channel of the pixel 1220, and the photoelectric sensor 1231 can correspond to the right channel of the pixel 1220. In other embodiments, the positions of the left half-pixel 1229 and the right half-pixel 1239 can be exchanged such that the photoelectric sensor 1221 can correspond to the right channel of the pixel 1220 and the photoelectric sensor 1231 can correspond to the left channel of the pixel 1220. In still other embodiments, the left half-pixel 1229 and the right half-pixel 1239 can be vertically aligned with each other such that (a) the left half-pixel 1229 is positioned above the right half-pixel 1239 or (b) the left half-pixel 1229 is positioned below the right half-pixel 1239. In these embodiments, the photoelectric sensor 1221 can correspond to the upper channel or the lower channel of the pixel 1220 respectively, and the photoelectric sensor 1231 can correspond to the lower channel or the upper channel of the pixel 1220 respectively.

[0129] The principles of the present technology can also be utilized in a split photoelectric sensor pixel architecture. For example, Figure 13 is a partial schematic circuit diagram of a pixel arrangement 1320 configured according to various embodiments of the present technology. The pixel arrangement 1320 can be or include a split photoelectric sensor (e.g., split photodiode, multi-photodiode) pixel circuit and is thus also referred to herein as "pixel 1320". The pixel 1320 can be Figure 1An example of one of the pixels in the pixel array 108 or another pixel configured according to various embodiments of the present technology. As shown, pixel 1320 includes a first portion 1329 and a second portion 1339. The architecture / arrangement of the first portion 1329 and the second portion 1339 of pixel 1320 is generally similar to Figure 2 the first pixel 229 and the second pixel 239 of the pixel arrangement 220 of Figure 2 and 13 . Thus, like reference numerals are used in

[0130] to denote the same or at least substantially similar components, and in view of the detailed discussion of the pixel arrangement 220 provided above, the detailed discussion of pixel 1320 is substantially omitted here for the sake of brevity. The first portion 1329 of pixel 1320 includes a photoelectric sensor 1321, and the second portion 1339 of pixel 1320 includes a photoelectric sensor 1331. The photoelectric sensor 1321 can be configured to have a different sensitivity and / or full well capacity from the photoelectric sensor 1331. For example, the photoelectric sensor 1321 can be a large photoelectric sensor (e.g., a large photodiode), and the photoelectric sensor 1331 can be a small photoelectric sensor (e.g., a small photodiode).

[0130] Similar to Figure 2 the pixel arrangement 220 of Figure 13 the pixel 1320 can include a mode switch 1335 that facilitates operating the pixel 1320 in any of the following three different modes: only CIS mode, hybrid CIS and EVS mode, and only EVS mode. For example, in the illustrated embodiment, the mode switch 1335 includes a first switch 1336 and a second switch 1338. The first switch 1336 and the second switch 1338 are arranged with respect to the first portion 1329 and the second portion 1339 in a manner generally similar to Figure 2 the first switch 236 and the second switch 238 of the mode switch circuit 235 of the pixel arrangement 220 of Figure 2 with respect to the first pixel 229 and the second pixel 239. Thus, in view of the detailed discussion of the first switch 236 and the second switch 238 of the mode switch circuit 235 provided above with reference to Figure 2 , the detailed discussion of the first switch 1336 and the second switch 1338 is substantially omitted here for the sake of brevity.

[0131] As Figure 13As shown, the first switch 1336 is configured to receive a first switch control signal CIS_MODE_SW. Thus, the first switch 1336 is configured to be selectively activated at least in part based on the first switch control signal CIS_MODE_SW. Additionally or alternatively, the second switch 1338 is configured to receive a second switch control signal EVS_MODE_SW. Accordingly, the second switch 1338 is configured to be selectively activated at least in part based on the second switch control signal EVS_MODE_SW.

[0132] When the pixel 1320 operates in the CIS-only mode, the first portion 1329 and the second portion 1339 can each be used to capture a CIS image signal. In some embodiments, to place the pixel 1320 in the CIS-only mode, the first switch control signal CIS_MODE_SW can be asserted (thereby activating the first switch 1336 of the mode switch 1335), while the second switch control signal EVS_MODE_SW is not asserted (thereby deactivating the second switch 1338 of the mode switch 1335). The operation of the pixel 1320 in the CIS-only mode can be generally similar to the operation of the Figure 2 and 3A pixel arrangement 220 Figure 2 described in detail above in the CIS-only mode. Thus, a detailed discussion of the CIS-only mode of the pixel 1320 is omitted here for the sake of brevity.

[0133] When the pixel 1320 operates in the hybrid CIS and EVS mode, the first portion 1329 can be used to capture a CIS image signal, and the second portion 1339 can be used to capture an event signal. In some embodiments, to place the pixel 1320 in the hybrid CIS and EVS mode, the second switch control signal EVS_MODE_SW can be asserted (thereby activating the second switch 1338 of the mode switch 1335), while the first switch control signal CIS_MODE_SW is not asserted (thereby deactivating the first switch 1336 of the mode switch 1335). The operation of the pixel 1320 in the hybrid CIS and EVS mode can be generally similar to the operation of the Figure 2 and 3B pixel arrangement 220 Figure 2 described in detail above in the hybrid CIS and EVS mode. Thus, a detailed discussion of the hybrid CIS and EVS mode of the pixel 1320 is omitted here for the sake of brevity.

[0134] When pixel 1320 operates in the EVS-only mode, the first part 1329 and the second part 1339 can each be used to capture event signals. In some embodiments, to place pixel 1320 in the EVS-only mode, both the first switch control signal CIS_MODE_SW and the second switch control signal EVS_MODE_SW can be asserted, thereby activating the first switch 1336 and the second switch 1338 of the mode switch 1335 respectively. The operation of pixel 1320 in the EVS-only mode can be generally similar to the operation of the pixel arrangement 220 described in detail above with reference to Figure 2 and 3C described in detail Figure 2 in the EVS-only mode. Therefore, for the sake of brevity, the detailed discussion of the EVS-only mode of pixel 1320 is omitted here.

[0135] C. Conclusion

[0136] The foregoing detailed description of embodiments of the technology is not intended to be exhaustive or to limit the technology to the precise forms disclosed above. Although specific embodiments and examples of the technology are described above for illustrative purposes, those skilled in the relevant art will recognize that various equivalent modifications are possible within the scope of the technology. For example, although the steps are presented in the order given above, alternative embodiments may perform the steps in a different order. Additionally, the various embodiments described herein may also be combined to provide further embodiments.

[0137] It should be understood from the foregoing that specific embodiments of the technology have been described herein for illustrative purposes, but well-known structures and functions have not been shown or described in detail so as not to unnecessarily obscure the description of the embodiments of the technology. If any material incorporated herein by reference conflicts with the present disclosure, the present disclosure shall control. Where context permits, singular or plural terms may also respectively include plural or singular terms. Additionally, unless the term "or" is explicitly limited to mean only a single item excluding the other items of a list of two or more items, the use of "or" in this list shall be construed to include (a) any single item in the list, (b) all items in the list, or (c) any combination of the items in the list. Further, as used herein, the phrase "and / or" in, for example, "A and / or B" refers to only A, only B, and both A and B. Additionally, the terms "comprising," "including," "having," and "with" are used throughout to mean including at least the stated feature such that any greater number of the same features and / or additional types of other features are not excluded. Further, as used herein, the phrases "based on," "depending on," "due to," and "responsive to" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of the present disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on" or the phrase "at least partially upon." Moreover, the terms "connected" and "coupled" are used interchangeably herein and refer to both direct and indirect connection or coupling. For example, where context permits, element A "connected" or "coupled" to element B may mean (i) A is directly "connected" or directly "coupled" to B and / or (ii) A is indirectly "connected" or indirectly "coupled" to B.

[0138] It should also be understood from the foregoing that various modifications may be made without departing from the present disclosure or the technology. For example, those of ordinary skill in the art will understand that the various components of the technology may be further divided into sub-components, or the various components and functions of the technology may be combined and integrated. Additionally, certain aspects of the technology described in the context of specific embodiments may also be combined or eliminated in other embodiments. Further, although the advantages associated with certain embodiments of the technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments necessarily need to exhibit such advantages to fall within the scope of the technology. Accordingly, the present disclosure and the related technology may cover other embodiments not explicitly shown or described herein.

Claims

1. A pixel arrangement comprising: a first photosensor configured to photogenerate a first charge based at least in part on first light incident on the first photosensor; a first floating diffusion region configured to receive the first charge from the first photosensor; a second photosensor different from the first photosensor and configured to photogenerate a second charge based at least in part on a second light incident on the second photosensor; a second floating diffusion region configured to receive the second charge from the second photosensor; and Mode switch, which contains a first switch that selectively couples the second floating diffusion region to the first floating diffusion region, and a second switch, different from the first switch and configured to selectively couple the second floating diffusion region to event vision sensor readout circuitry, wherein the mode switch is operable to transition the pixel arrangement between: (i) a first mode, wherein the pixel arrangement is controllable to generate a first output corresponding to intensity information of the first light, the second light, or both the first light and the second light; and (ii) a second mode, wherein the pixel arrangement is controllable to generate a second output corresponding to contrast information of the first light, the second light, or both the first light and the second light. 2 . The pixel arrangement according to claim 1 , wherein the second switch is coupled to the first switch via the second floating diffusion region.

3. The pixel arrangement according to claim 1, further comprising: a first transfer transistor configured to selectively couple the first photosensor to the first floating diffusion region, wherein the first transfer transistor is distinct from the first switch; and A second transfer transistor is different from the first transfer transistor and is configured to selectively couple the second photosensor to the second floating diffusion region.

4. The pixel arrangement according to claim 1, wherein: The first output corresponds to intensity information of both the first light and the second light; and In order to generate the first output corresponding to the intensity information of the second light, the pixel arrangement can be controlled to activate the first switch of the mode switch so that: (a) the first switch and the second switch are in activated and deactivated states, respectively; (b) the second floating diffusion region is coupled to the first floating diffusion region; and (c) the second charge is transferred to the readout circuit system.

5. The pixel arrangement according to claim 1, wherein: The second output corresponds to contrast information of the second light; and To generate the second output corresponding to the contrast information of the second light, the pixel arrangement is controllable to activate the second switch of the mode switch such that the second floating diffusion region is coupled to the event vision sensor readout circuitry.

6. The pixel arrangement according to claim 5, wherein: In order to generate the second output corresponding to the contrast information of the second light, the pixel arrangement can be controlled to deactivate the first switch of the mode switch so that: (a) the first switch and the second switch are simultaneously in a deactivated state and an activated state, respectively; (b) the first floating diffusion area is decoupled from the second floating diffusion area; and (c) the second output corresponds to the contrast information of only the second light.

7. The pixel arrangement according to claim 5, wherein: When in the second mode, the pixel arrangement is further controllable to generate a third output corresponding to intensity information of the first light; and In order to generate the third output corresponding to the intensity information of the first light, the pixel arrangement can be controlled to deactivate the first switch so that: (a) the first switch and the second switch are simultaneously in a deactivated state and an activated state, respectively; (b) the first floating diffusion region is decoupled from the second floating diffusion region; and (c) the third output corresponds to the intensity information of only the first light.

8. The pixel arrangement according to claim 7, wherein: The second output corresponds to contrast information of only the second light; and When in the second mode, the pixel arrangement can be controlled to generate the second output and the third output simultaneously.

9. The pixel arrangement according to claim 5, wherein: The second output further corresponds to contrast information of the first light; and In order to generate the second output corresponding to the contrast information of the first light, the pixel arrangement can be controlled to activate the first switch of the mode switch so that: (a) the first switch and the second switch of the mode switch are in an activated state at the same time; and (b) the first floating diffusion region is coupled to the event vision sensor readout circuit system.

10. The pixel arrangement according to claim 1, wherein: The first output corresponds to intensity information of both the first light and the second light; The second output corresponds to contrast information of both the first light and the second light; and The mode switch can be used to switch the pixel arrangement between: (i) the first mode; (ii) the second mode; and (iii) a third mode, wherein the pixel arrangement can be controlled to generate a third output corresponding to (a) intensity information of the first light and (b) contrast information of the second light. 11 . The pixel arrangement of claim 1 , wherein the first switch and the second switch are positioned on a same die as the first photosensor and the second photosensor.

12. The pixel arrangement according to claim 1, wherein: The pixel arrangement comprises pixels; The pixel includes the first photosensor, the second photosensor, the first floating diffusion region, and the second floating diffusion region; The first photosensor has a first sensitivity; and The second photosensor has a second sensitivity different from that of the first photosensor.

13. The pixel arrangement according to claim 1, further comprising a split photosensor pixel, wherein the first photosensor is a first photosensor of the split photosensor pixel; and The second photosensor is a second photosensor of the split photosensor pixel. The pixel arrangement according to claim 13 , wherein the first photosensor and the second photosensor are positioned under the same microlens.

15. The pixel arrangement according to claim 1, further comprising a first pixel and a second pixel different from the first pixel, wherein The first pixel includes the first photosensor and the first floating diffusion region; and The second pixel includes the second photosensor and the second floating diffusion region.

16. The pixel arrangement according to claim 15, wherein: The first pixel further includes a third photosensor configured to photogenerate a third charge based at least in part on a third light incident on the third photosensor; The first floating diffusion region is configured to receive the third charge from the third photosensor; When in the first mode, the pixel arrangement is controllable to generate the first output such that the first output corresponds to the intensity information of the first light, the intensity information of the second light, the intensity information of the third light, or any first combination thereof; and When in the second mode, the pixel arrangement is controllable to generate the second output such that the second output corresponds to the contrast information of the first light, the contrast information of the second light, the contrast information of the third light, or any second combination thereof.

17. The pixel arrangement according to claim 16, wherein: The second pixel further includes a fourth photosensor configured to photogenerate fourth charge based at least in part on fourth light incident on the fourth photosensor; the second floating diffusion region being configured to receive the fourth charge from the fourth photosensor; When in the first mode, the pixel arrangement is controllable to generate the first output so that the first output corresponds to the intensity information of the first light, the intensity information of the second light, the intensity information of the third light, the intensity information of the fourth light, or any third combination thereof; and When in the second mode, the pixel arrangement can be controlled to produce the second output so that the second output corresponds to the contrast information of the first light, the contrast information of the second light, the contrast information of the third light, the contrast information of the fourth light, or any fifth combination thereof. 18 . The pixel arrangement according to claim 15 , wherein the first pixel and the second pixel are vertically aligned with each other.

19. The pixel arrangement of claim 15, wherein the first pixel and the second pixel are horizontally aligned with each other.

20. The pixel arrangement according to claim 15, further comprising: A third pixel, which is different from the first and second pixels and includes a third photosensor configured to photogenerate a third charge based at least in part on a third light incident on the third photosensor, and a third floating diffusion region configured to receive the third charge from the third photosensor; A fourth pixel is different from the first, second and third pixels and includes a fourth photosensor configured to photogenerate fourth charge based at least in part on fourth light incident on the fourth photosensor, and a fourth floating diffusion region configured to receive the fourth charge from the fourth photosensor; and The second mode switch includes a third switch that selectively couples the third floating diffusion region to the fourth floating diffusion region, and a fourth switch, different from the third switch and configured to selectively couple the fourth floating diffusion region to a second event vision sensor readout circuitry, wherein the second mode switch is operable to switch the pixel arrangement between: (i) a third mode, wherein the pixel arrangement is controllable to generate a third output corresponding to intensity information of the third light, the fourth light, or both the third light and the fourth light; and (ii) a fourth mode, wherein the pixel arrangement is controllable to generate a fourth output corresponding to contrast information of the third light, the fourth light, or both the third light and the fourth light.

21. The pixel arrangement according to claim 20, wherein: The first, second, third and fourth pixels are arranged in a 2x2 pixel array; The first pixel and the third pixel are diagonally offset from each other within the 2×2 pixel array; and The second pixel and the fourth pixel are diagonally offset from each other within the 2×2 pixel array.

22. The pixel arrangement of claim 20, wherein the first, second, third and fourth pixels are coupled to the same bit line.

23. A system comprising: A first die comprising At least one pixel having: a first photoelectric sensor; a first floating diffusion region configured to receive first charges photogenerated by the first photosensor; a first transfer transistor configured to selectively couple the first photosensor to the first floating diffusion region; a second photosensor, which is different from the first photosensor; a second floating diffusion region configured to receive second charges photogenerated by the second photosensor; and a second transfer transistor configured to selectively couple the second photosensor to the second floating diffusion region, and Mode switch, which includes: a first switch that selectively couples the second floating diffusion region to the first floating diffusion region, and a second switch coupled to the first switch via the second floating diffusion region; and A second die that is different from the first die and includes event vision sensor readout circuitry, wherein the second switch is configured to selectively couple the second floating diffusion region to the event vision sensor readout circuitry.

24. The system of claim 23, wherein the mode switch is operable to transition the at least one pixel between: (i) a first mode, wherein the at least one pixel is controllable to output complementary metal oxide semiconductor image sensor information corresponding to the first charge, the second charge, or both the first charge and the second charge; and (ii) a second mode, wherein the at least one pixel is controllable to output non-complementary metal oxide semiconductor image sensor information corresponding to the first charge, the second charge, or both the first charge and the second charge.

25. The system of claim 23, wherein: In the first mode, the at least one pixel is controllable to output complementary metal oxide semiconductor image sensor information corresponding to both the first charge and the second charge; and In the second mode, the at least one pixel can be controlled to simultaneously output non-complementary metal oxide semiconductor image sensor information corresponding to the second charge and complementary metal oxide semiconductor image sensor information corresponding to the first charge.

26. The system of claim 24, wherein: In the first mode, the CMOS image sensor information includes intensity and / or color information corresponding to first light incident on the first and second photosensors; and In the second mode The non-complementary metal oxide semiconductor image sensor information includes an event signal corresponding to a brightness change, an event detection, and / or phase detection autofocus information corresponding to a second light incident on the second photosensor, and The CMOS image sensor information includes intensity and / or color information corresponding to the third light incident on the first photosensor.

27. The system of claim 24, wherein: The at least one pixel further comprises a third photosensor that is different from the first and second photosensors and is configured to photogenerate a third charge based on light incident on the third photosensor, and a fourth photosensor that is different from the first, second, and third photosensors and is configured to photogenerate fourth charges based on light incident on the fourth photosensor, and The event vision sensor readout circuitry is configured to receive non-complementary metal oxide semiconductor image sensor information from the first photosensor, the second photosensor, the third photosensor, and the fourth photosensor corresponding to the first charge, the second charge, the third charge, and the fourth charge, respectively.

28. A pixel comprising: a photosensor selectively coupled to the first floating diffusion region through a transfer gate; and a mode switch configured to cause the pixel to transition between: (i) a first mode in which the pixel is controllable to output complementary metal oxide semiconductor image sensor information corresponding to light incident on the photosensor; and (ii) a second mode in which the pixel is controllable to output non-complementary metal oxide semiconductor image sensor information corresponding to light incident on the photosensor, wherein the mode switch comprises: a first switch that selectively (a) couples the second floating diffusion region to the first floating diffusion region and (b) couples the first floating diffusion region and the second floating diffusion region to complementary metal oxide semiconductor image sensor readout circuitry, and A second switch (a) is coupled to the first switch via the second floating diffusion region and (b) selectively couples the second floating diffusion region to event vision sensor readout circuitry.

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