Miniature light emitting diode and display panel

Abstract

The invention provides a miniature light-emitting diode chip. The miniature light-emitting diode chip comprises a light-emitting mesa; the top conducting layers are located on the side faces and the top face of the light-emitting table top; the passivation layer at least partially covers the side surface of the light-emitting mesa, and the passivation layer is positioned between the light-emitting mesa and the top conductive layer; the top electrode layer is located between the micro light-emitting diodes, the top electrode layer surrounds the micro light-emitting diodes, and the top electrode layer is provided with a first side wall facing the light-emitting mesa; the first side wall is only in contact with the top conductive layer at the bottom end, and the first side wall is provided with a first inclined surface.

Description

Technical Field

[0001] The present invention relates to the technical field of light-emitting diodes, and more particularly, to a micro light-emitting diode and a display panel. Background Art

[0002] Micro Light Emitting Diode technology is a high pixel density LED flat panel display technology in which micron-scale LEDs are used as pixel elements and assembled on a control backplane in a micron-scale period. The core structure of a micro light-emitting diode is a PN junction diode, which is composed of a direct bandgap semiconductor material. When a forward bias is applied to the upper and lower electrodes of the micro light-emitting diode to cause current to flow, electrons and holes recombine in the active region, and at the same time, single-color light photons are emitted.

[0003] The light emitted by a micro LED is generated by spontaneous emission and is therefore non-directional, which results in a large divergence angle. The large divergence angle causes various problems in micro LED displays. On the one hand, due to the large divergence angle, only a small part of the light emitted by the micro LED pixels can be utilized. This will greatly reduce the efficiency and brightness of the micro LED display. On the other hand, due to the large divergence angle, the light emitted by one micro LED pixel will illuminate its adjacent pixels, thereby causing light crosstalk between pixels, loss of clarity, and loss of contrast. Traditional solutions to reduce the large divergence angle may not be able to effectively handle all the light emitted by the micro LED, and only the central part of the light emitted by the micro LED can be effectively utilized, while the light emitted at a more inclined angle is not effectively utilized.

[0004] In summary, there is a need to provide a micro light-emitting diode structure that can improve the light efficiency. Summary of the Invention

[0005] In view of some or all of the problems in the prior art, the task of the present invention is to provide a micro light-emitting diode chip, including: a light-emitting mesa; a top conductive layer located on the side and top of the light-emitting mesa; a passivation layer at least partially covering the side of the light-emitting mesa and located between the light-emitting mesa and the top conductive layer; a top electrode layer located between the micro light-emitting diodes, surrounding the micro light-emitting diodes, the top electrode layer having a first sidewall facing the light-emitting mesa; the first sidewall is in contact with the top conductive layer only at the bottom end, and the first sidewall has a first inclined surface.

[0006] In some embodiments, the bottom end of the first sidewall is closer to the light-emitting mesa than the top end.

[0007] In some embodiments, the first inclined surface surrounds the light-emitting mesa and opens along the direction of light emission.

[0008] In some embodiments, the top electrode layer includes a second sidewall, the upper end of the second sidewall is connected to the lower end of the first sidewall and extends downward to the bottom of the top electrode layer; the second sidewall has a second inclined surface.

[0009] In some embodiments, the top of the second sidewall is closer to the light-emitting mesa than the bottom of the second sidewall; the second inclined surface surrounds the light-emitting mesa and opens in the direction away from the light emission.

[0010] In some embodiments, the junction of the first sidewall and the second sidewall is lower than the top of the light-emitting mesa.

[0011] In some embodiments, the light-emitting mesa has a first semiconductor epitaxial layer, a light-emitting layer, and a second semiconductor epitaxial layer.

[0012] In some embodiments, the junction is lower than the bottom of the light-emitting layer of the light-emitting mesa.

[0013] In some embodiments, the light-emitting layer includes multiple stacked semiconductor material layers.

[0014] In some embodiments, the top of the first inclined surface is higher than the top of the light-emitting layer.

[0015] In some embodiments, the top of the first inclined surface is higher than the top of the light-emitting mesa.

[0016] In some embodiments, the thickness of the top conductive layer is less than 3000 Å, and the thickness of the passivation layer is less than 3000 Å.

[0017] The thickness of the top conductive layer is in the range of 500 Å to 1500 Å, and / or

[0018] The thickness of the passivation layer is in the range of 500 Å to 1500 Å.

[0019] In some embodiments, the bottom of the first sidewall is higher than the bottom of the light-emitting mesa, and the height difference between the bottom of the first sidewall and the bottom of the light-emitting mesa is in the range of 1000 Å to 3000 Å.

[0020] In some embodiments, the included angle between the first inclined surface and the top of the light-emitting mesa is 95° - 130°.

[0021] In some embodiments, the micro light-emitting diode chip further includes:

[0022] An ohmic contact layer, the ohmic contact layer is located at the bottom of the light-emitting mesa.

[0023] In some embodiments, the electrode polarity of the ohmic contact layer is opposite to the electrode polarity of the top conductive layer.

[0024] In some embodiments, the bottoms of adjacent top electrode layers are connected, and all the top electrode layers are integrated into a whole.

[0025] In some embodiments, the longitudinal profile of adjacent top electrode layers presents a forked peak shape.

[0026] In some embodiments, the longitudinal profile shapes of adjacent top electrode layers are symmetric or asymmetric.

[0027] In some embodiments, the top electrode layer includes:

[0028] one or more main metal layers; and

[0029] a mirror surface layer covering the surface of the main metal layer, wherein the material of the one or more main metal layers is an alloy of one or more of the following metals: Ti, Ni, Au, Ag, Pt, Al, Cr, and Cu, and the mirror surface layer is Al or an Al alloy metal.

[0030] In some embodiments, the bottom of the top electrode layer is lower than the bottom of the light-emitting mesa, and all surfaces of the second sidewall are in contact with the top conductive layer.

[0031] In some embodiments, the inclination angle of the second inclined surface with respect to the light-emitting mesa is different from the inclination angle of the first inclined surface with respect to the light-emitting mesa.

[0032] In some embodiments, the inclination angle of the second sidewall is less than 90°.

[0033] In some embodiments, the top of the top electrode layer is higher than the top of the light-emitting mesa; or

[0034] the top of the top electrode layer is flush with the top of the light-emitting mesa; or

[0035] the top of the top electrode layer is lower than the top of the light-emitting mesa.

[0036] In some embodiments, the top electrode layer is a reflective cup-shaped structure, the bottom area of the reflective cup is smaller than the cup mouth area of the reflective cup, and the angle formed by the inner wall of the reflective cup and the horizontal plane in the direction of the inner light-emitting mesa is in the range of 95° - 130°.

[0037] In some embodiments, adjacent top conductive layers are connected to each other, and all the top conductive layers are integrated into a whole.

[0038] In one embodiment of the present invention, adjacent passivation layers are connected, and all the passivation layers are integrated into a whole.

[0039] In one embodiment of the present invention, the material of the passivation layer is one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0040] In one embodiment of the present invention, the bottom lateral dimension of the light-emitting mesa is larger than the top lateral dimension.

[0041] In one embodiment of the present invention, the inclination angle range of the sidewall of the light-emitting mesa is: 60° to 85°.

[0042] In one embodiment of the present invention, the bottom lateral dimension of the light-emitting mesa does not exceed 3 micrometers; and / or

[0043] The top lateral dimension of the light-emitting mesa does not exceed 1.5 micrometers.

[0044] In one embodiment of the present invention, the light-emitting mesa includes a first-type epitaxial layer, a second-type epitaxial layer, and a light-emitting layer located therebetween.

[0045] In one embodiment of the present invention, the first-type epitaxial layer is electrically connected to the ohmic contact layer;

[0046] The second-type epitaxial layer is electrically connected to the top conductive layer.

[0047] In one embodiment of the present invention, the material of the first-type epitaxial layer is a material layer of a first conductive type composed of at least two elements including Ga, N, As, Al, In, and P, and the second-type epitaxial layer is a material layer of a second conductive type composed of at least two or more elements including Ga, N, As, Al, In, and P;

[0048] The first conductive type is different from the second conductive type.

[0049] In one embodiment of the present invention, the light-emitting layer includes a multi-quantum well layer and an electron blocking layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer.

[0050] In one embodiment of the present invention, the micro light-emitting diode further includes:

[0051] A microlens, the microlens being disposed above the micro light-emitting diode.

[0052] In one embodiment of the present invention, the microlens is formed by multiple depositions. The thickness of the microlens layer deposited for the first time is in the range of 2.5 - 3.5 microns. By adjusting the lithography topography of the microlens, the lithography array topography corresponding to the position of the corresponding pixel is completed. The passivation protection layer material of the microlens is etched by ions to form a hemispherical microlens with a lens-like topography. A secondary deposition is performed on the microlens, and the thickness of the secondary deposition is in the range of 0.2 - 1 micron.

[0053] In one embodiment of the present invention, the micro light-emitting diode further includes:

[0054] A driving module, the driving module includes a driving backplane and a bonding layer, and the bonding layer is disposed at the bottom of the light-emitting mesa.

[0055] In one embodiment of the present invention, the driving backplane includes driving electrodes, and each micro light-emitting diode corresponds to one driving electrode, and the driving electrode is electrically connected to the bonding layer.

[0056] In one embodiment of the present invention, there is an isolation trench between adjacent micro light-emitting diodes, and the bottom of the isolation trench is lower than the interface between the bonding layer and the driving backplane.

[0057] In one embodiment of the present invention, a display panel is provided, which includes a micro light-emitting diode chip. The micro light-emitting diode chip includes a micro light-emitting diode array, and the micro light-emitting diode array includes a plurality of micro light-emitting diodes.

[0058] The technical solution provided by the present invention has the following beneficial effects:

[0059] 1. By providing a top electrode layer capable of reflecting light between the micro light-emitting diodes, light crosstalk between adjacent micro light-emitting diodes can be avoided. In addition, the top electrode layer can reflect the light emitted by the micro light-emitting diodes, improving the light-emitting brightness of the micro light-emitting diode chip, and thus improving the light extraction efficiency of the micro light-emitting diode.

[0060] 2. In the micro light-emitting diode structure provided by the present invention, by thinning the passivation layer and the top conductive layer, the bottom of the top electrode layer sinks 4000 Å - 6000 Å, and at the same time, the angle b formed by the inner wall of the reflection cup and the horizontal plane in the direction of the inner side light-emitting mesa is in the range of 95° - 130°, which can reflect the light within a small angle upward and improve the light extraction efficiency.

[0061] 3. The thinned passivation layer and top conductive layer can reduce the light absorption effect of the passivation layer and the top conductive layer, thereby improving the light extraction efficiency.

[0062] 4. The micro light-emitting diode structure provided by the present invention improves the microlens. By improving the profile of the microlens, the height of the lower spacer, the radius of curvature, and the lens ball height are adjusted, thereby improving the micro defects of the lens, and further effectively improving the brightness or luminous efficiency of the micro light-emitting diode chip. The specific technical effects are as follows. The advantage of increasing the height of the lower spacer lies especially in that: on the premise of determining the radius of curvature, with the light source emitting from the upper bottom of the pixel as the main radiation mode, when the radius of curvature increases, increasing the height of the lower spacer makes the radius of the emitted light increase, and the emission angle of the same point light source microlens and the air interface decreases, so that the emission angle can be increased; the smaller the radius of curvature, that is, the wider the microlens ball, is beneficial to light emission. Correspondingly, when the ball height increases, that is, the ball height of the original hemispherical microlens is changed, the escaping light can also be emitted from the microlens. By changing the curvature, the total emission angle of the microlens is increased, making it not easy to form total reflection light, which is beneficial to the light emission effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The present invention will be further described below in conjunction with the specific embodiments with reference to the drawings.

[0064] Figure 1 The top view schematic diagram of the micro light-emitting diode chip according to an embodiment of the present invention is shown.

[0065] Figure 2 The longitudinal sectional schematic diagram of the micro light-emitting diode chip according to an embodiment of the present invention is shown.

[0066] Figure 3 The top view schematic diagram of the top electrode layer of the micro light-emitting diode chip according to an embodiment of the present invention is shown.

[0067] Figure 4 The longitudinal sectional schematic diagram of the micro light-emitting diode chip according to another embodiment of the present invention is shown.

[0068] Figure 5 The longitudinal sectional schematic diagram of the micro light-emitting diode chip according to still another embodiment of the present invention is shown. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0069] It should be noted that the components in the drawings may be exaggerated for illustration purposes and are not necessarily to scale. In each drawing, the same or functionally identical components are provided with the same reference numerals.

[0070] In the present invention, unless otherwise specified, "disposed on", "disposed above", and "disposed thereon" do not exclude the presence of an intermediate object therebetween. In addition, "disposed on or above" only represents the relative positional relationship between two components, and in certain cases, such as when the product direction is reversed, it can also be converted to "disposed under or below", and vice versa.

[0071] In the present invention, each embodiment is only intended to illustrate the solution of the present invention and should not be construed as restrictive.

[0072] In the present invention, unless otherwise specified, the quantifiers "a" and "one" do not exclude the scenario of multiple elements.

[0073] In the present invention, the term "connected" can refer to both direct connection between two elements and indirect connection between two elements through an intermediate element.

[0074] In the present invention, the term "configured" means setting the shape, structure, material, and / or function of an object to achieve the desired technical effect, where "configured" includes various alternative technical means for achieving this technical effect, and these technical means become obvious under the teaching of the present invention.

[0075] It should also be noted here that in the embodiments of the present invention, for clarity and simplicity, only a part of the components or assemblies may be shown. However, those of ordinary skill in the art can understand that, under the teaching of the present invention, the required components or assemblies can be added according to the specific scenario requirements. Additionally, unless otherwise stated, the features in different embodiments of the present invention can be combined with each other. For example, a certain feature in the second embodiment can be used to replace the corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment also falls within the scope of the disclosure or the scope of the record of this application.

[0076] It should also be noted here that within the scope of the present invention, the terms "identical", "equal", "equal to", etc. do not mean that the two values are absolutely equal, but allow for a certain reasonable error. That is to say, the terms also cover "substantially identical", "substantially equal", "substantially equal to". By analogy, in the present invention, the terms indicating direction such as "perpendicular to" and "parallel to" also cover the meanings of "substantially perpendicular to" and "substantially parallel to".

[0077] In the present invention, the term "at the bottom of the light-emitting mesa" refers to the side of the light-emitting mesa facing away from the microlens, the term "at the top of the light-emitting mesa" refers to the side of the light-emitting mesa facing the microlens, and the term "side of the light-emitting mesa" refers to the two sides between the top and the bottom.

[0078] In the present invention, the term "profile of the metal layer" refers to the maximum dimension, such as length, in the plane formed by the length and width of the metal layer (or the plane perpendicular to the thickness). Similarly, the bottom profile of the light-emitting mesa refers to the maximum dimension, such as length, of the light-emitting mesa in the bottom plane (i.e., the plane perpendicular to the thickness at the bottom).

[0079] The following clearly and completely describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention.

[0080] Figure 1 The top view schematic diagram of the micro light-emitting diode chip according to an embodiment of the present invention is shown. Figure 1 It includes a micro light-emitting diode, a microlens 102, and a top electrode layer 103. Figure 2 The longitudinal cross-sectional schematic diagram of the micro light-emitting diode chip according to an embodiment of the present invention is shown. As shown in the figure, the micro light-emitting diode chip includes a driving backplane 109, a micro light-emitting diode, a top electrode layer 103, and a microlens 102. The micro light-emitting diodes are arranged on the upper surface of the driving backplane 109. The top electrode layer 103 is arranged between the micro light-emitting diodes and is arranged to surround the micro light-emitting diodes in an electrically contacting manner. The microlens 102 is arranged on the upper surface of the micro light-emitting diode, and adjacent microlenses 102 are spaced apart between the micro light-emitting diodes. In some embodiments of the present invention, the driving module includes a driving backplane 109.

[0081] The micro light-emitting diode includes: an ohmic contact layer 106, a light-emitting mesa 101, a top conductive layer 104, and a passivation layer 105. The micro light-emitting diode is arranged on the upper surface of the driving backplane 109. The driving backplane 109 is electrically connected to a bonding layer 107, and the bonding layer 107 is electrically connected to the ohmic contact layer 106, and the ohmic contact layer 106 is arranged at the bottom of the light-emitting mesa 101.

[0082] The size of each micro light-emitting diode chip does not exceed 1 cm, preferably not exceeding 5 mm. The micro light-emitting diodes are formed in an array in the micro light-emitting diode chip, and the resolution is, for example, 720*480, 640*480, 1920*1080, 1280*720, 2K, or 4K. The diameter of the micro light-emitting diode structure is at the nanometer level, for example, 20 nm to 100 nm. Each micro light-emitting diode can form at least a part of the pixel element on the micro light-emitting diode chip.

[0083] Introduction to the driving backplane 109:

[0084] For convenience, "upward" is used to indicate away from the driving backplane 109, "downward" indicates toward the driving backplane 109, and other directional terms such as top, bottom, above, below, directly below, and underneath are also interpreted accordingly. In some embodiments of the present invention, the driving backplane 109 includes a substrate (not shown in the figure), a driving circuit (not shown in the figure), and a driving electrode 108.

[0085] In some embodiments of the present invention, the substrate is a Si substrate. In some other embodiments of the present invention, the substrate is a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates. In some embodiments, the substrate is about 700 microns thick.

[0086] The driving circuit forms individual pixel drivers to control the operation of each single micro-LED pixel. The driving circuit includes, for example, complementary metal oxide semiconductor (CMOS) devices or TFT devices, etc.

[0087] Each driving electrode 108 corresponds to a micro-light emitting diode, and each driving electrode 108 is electrically connected to the bonding layer 107. In some embodiments of the present invention, the material of the driving electrode 108 is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Pt, and Au.

[0088] In some embodiments of the present invention, a light-emitting epitaxial layer structure of a micro-light emitting diode is fabricated on the surface of the epitaxial substrate. The micro-light emitting diode can be bonded to the surface of the driving backplane 109 through the bonding layer 107, and the bonding between the driving backplane 109 and the micro-light emitting diode can be achieved by high-temperature and high-pressure bonding methods such as eutectic bonding, thermocompression bonding, and transient liquid phase (TLP) bonding.

[0089] Introduction to the bonding layer 107:

[0090] In some embodiments of the present invention, the bonding layer 107 may be disposed on the driving backplane 109. In some other embodiments of the present invention, the bonding layer 107 grows on the driving backplane 109. In some embodiments of the present invention, the thickness of the bonding layer 107 is from 0.1 micrometer to 3 micrometers. In a preferred embodiment, the thickness of the bonding layer 107 is 0.6 micrometers. In some embodiments of the present invention, the bonding layer 107 includes a first metal layer (not shown in the figure) and a second metal layer (not shown in the figure). The first metal layer is in direct contact with the ohmic contact layer 106 at the bottom of the light-emitting mesa 101, and the second metal layer is located at the bottom layer of the bonding layer 107. In some embodiments of the present invention, one or more third metal layers are further disposed between the first metal layer and the second metal layer. By making the bonding layer 107 have multiple metal layers, first, the total thickness of the bonding layer 107 can be flexibly controlled by depositing multiple metal layers multiple times during the manufacturing process; second, the material selection of each metal layer is also more flexible. For example, the first metal layer in direct contact with the bottom of the ohmic contact layer 106 can select a metal material that is not easily diffused into the ohmic contact layer 106 or will not cause serious consequences even if diffused, or a metal material with a small contact resistance with the ohmic contact layer 106. The intermediate layer can select a metal material with good conductivity, and the second metal layer at the bottom layer can select a metal material with good bonding property with the driving backplane 109. In some embodiments of the present invention, the material of the first metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or the material of the second metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn; and / or the material of the third metal layer is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, and Sn. In some embodiments, the bonding layer 107 can also be used as a reflector to reflect the light emitted from the LED structure above.

[0091] In an embodiment of the present invention, after the bonding is completed, the epitaxial substrate can be removed by laser lift-off. The material of the epitaxial substrate can be sapphire or silicon. The corresponding lift-off process can be selected according to the material of the epitaxial substrate. After the epitaxial substrate is removed, the purpose of transferring the epitaxial light-emitting structure to the driving backplane 109 can be achieved. Removing the epitaxial substrate can further thin the epitaxial buffer layer structure, facilitating the subsequent PN step process of the epitaxial structure.

[0092] In one embodiment of the present invention, after bonding is completed, the light-emitting mesa 101 is etched. By adjusting the lithography topography, a micro-light-emitting diode pixel point with a regular trapezoidal structure is formed through ion etching. In one embodiment of the present invention, deep trench etching needs to be further performed on the micro-light-emitting diode partition. This process can be completed through lithography and IBE inert gas physical etching. For example, the bottom of the isolation trench between micro-light-emitting diodes is lower than the interface between the bonding layer 107 and the driving backplane 109. That is, at the isolation trench between micro-light-emitting diodes, the top of the driving backplane 109 is etched to a certain depth to ensure the isolation of micro-light-emitting diodes.

[0093] As Figure 2 shown, the driving backplane 109 includes a driving electrode 108, and the driving electrode 108 is electrically connected to the bonding layer 107. In some embodiments, the driving backplane 109 can be an integrated circuit (IC) board. The micro-light-emitting diode is electrically connected to the driving backplane 109, and the driving backplane 109 is used to control the lighting and extinguishing of the micro-light-emitting diode. In some embodiments, the integrated circuit board can be electrically connected to each micro-light-emitting diode in the micro-light-emitting diode array through separate metal interconnections. In some embodiments, each micro-light-emitting diode can be individually electrically controlled by the integrated circuit board. In some embodiments, the integrated circuit board can be electrically connected to the driving electrode 108 of the micro-light-emitting diode chip through metal interconnections. In some embodiments, a dielectric layer can be formed in the gap between micro-light-emitting diodes. In some embodiments, the dielectric layer can also be formed in the gap between interconnections.

[0094] In some embodiments, the micro-light-emitting diode chip includes a plurality of micro-light-emitting diode arrays, and each micro-light-emitting diode array includes a plurality of micro-light-emitting diodes. The driving method of the micro-light-emitting diode is, for example, passive matrix (PM) driving, where the cathodes of all micro-light-emitting diodes in each array are commonly connected to the cathode line NL, and the micro-light-emitting diodes with the same number in each array are respectively connected to the corresponding anode line PL. Thus, the on / off and light-emitting brightness of each micro-light-emitting diode can be individually controlled by controlling the signals on the corresponding cathode line and anode line.

[0095] In some embodiments, the micro-light-emitting diodes can be arranged in a regular or irregular manner on the upper surface of the driving module as the pixel points of the micro-light-emitting diode chip. The micro-light-emitting diode includes: an ohmic contact layer 106 located at the bottom of the light-emitting mesa 101, and the ohmic contact layer 106 is electrically connected to the bonding layer 107. A top conductive layer 104 is located on the side and top of the light-emitting mesa 101, and the top conductive layer 104 is electrically connected to the top electrode layer 103.

[0096] In some embodiments, the passivation layer 105 at least partially coats the side surfaces, the bottom surface, and the side surfaces of the isolation trenches of the light-emitting mesa 101, and the passivation layer 105 is located between the light-emitting mesa 101 and the top conductive layer 104. In some embodiments, the passivation layer 105 may cover a part of the top surface of the light-emitting mesa 101. In some embodiments, materials such as silicon dioxide, silicon nitride, silicon oxide, silicon oxynitride, etc. are deposited by a plasma chemical vapor deposition apparatus to form the passivation layer. Due to the limited passivation effect of the film layer, including compactness and breakdown resistance, the film layer thickness is greater than 4000 angstroms. A photolithography opening process is performed on the passivation layer 105 on the top surface of the light-emitting mesa 101 through a photolithography process, and at least a part of the surface of the top surface of the light-emitting mesa 101 is etched and exposed, and electrical contact between the light-emitting mesa 101 and the top conductive layer 104 is achieved through the opening of the passivation layer. In some embodiments of the present invention, adjacent passivation layers are connected, and all passivation layers are integrated into a whole. In some embodiments of the present invention, the material of the passivation layer is one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0097] In some embodiments, the electrode polarity of the ohmic contact layer 106 is opposite to that of the top conductive layer 104. The ohmic contact layer 106 can be, for example, a P electrode or an anode electrode, while the top conductive layer 104 is an electrode with a polarity opposite to that of the ohmic contact layer 106, such as an N electrode or a cathode electrode. In some embodiments of the present invention, the ohmic contact layer 106, the top conductive layer 104, and their connecting components can be a combination of one or more of, for example, graphene, indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), or other transparent conductive oxides (TCO).

[0098] In some embodiments of the present invention, adjacent top conductive layers 104 are connected, and all top conductive layers 104 are integrated into a whole. In some embodiments of the present invention, the top conductive layer 104 is a transparent electrode covering the entire display area. Generally, the film layer is made of indium tin oxide as a conductive material. The indium tin oxide is generally deposited by electron beam evaporation of the film layer material. Due to poor step coverage and continuity, the film thickness is generally greater than 3000 angstroms.

[0099] In some embodiments, the top conductive layer 104 can be shared by all the micro light-emitting diodes in the micro light-emitting diode array.

[0100] In some embodiments of the present invention, the light-emitting mesa 101 may be a trapezoidal platform, and the bottom lateral dimension of the light-emitting mesa 101 is greater than the top lateral dimension. In some embodiments of the present invention, the inclination angle range of the sidewall of the light-emitting mesa 101 is: 60° to 85°. In some embodiments of the present invention, the bottom lateral dimension of the light-emitting mesa 101 does not exceed 3 micrometers. In some embodiments of the present invention, the top lateral dimension of the light-emitting mesa 101 does not exceed 1.5 micrometers. In some embodiments of the present invention, the lateral dimensions of the ohmic contact layer 106 and the bonding layer 107 are greater than the bottom lateral dimension of the light-emitting mesa 101.

[0101] As Figure 2 shown, the light-emitting mesa 101 includes a first-type epitaxial layer 1011, a second-type epitaxial layer 1013, and a light-emitting layer 1012 located therebetween. The first-type epitaxial layer 1011 is electrically connected to the ohmic contact layer 106. The second-type epitaxial layer 1013 is electrically connected to the top conductive layer 104. In some embodiments, the light-emitting mesa 101 of each micro light-emitting diode in the micro light-emitting diode array may be a micro light-emitting mesa 101. In some embodiments, the micro light-emitting mesa 101 may include, from bottom to top, a first-type epitaxial layer 1011, a light-emitting layer 1012, and a second-type epitaxial layer 1013. That is to say, in the three-layer structure, the first-type epitaxial layer 1011 is closest to the driving backplane 109; the light-emitting layer 1012 is located above the first-type epitaxial layer 1011 and is farther from the driving backplane 109; the second-type epitaxial layer 1013 is located above the light-emitting layer 1012 and is the farthest from the driving backplane 109. In some embodiments, the light-emitting layer 1012 includes multiple stacked semiconductor material layers. The semiconductor material layer may be a quantum well light-emitting layer. The quantum well light-emitting layer includes stacked quantum well layers and quantum barrier layers. In some embodiments, the first-type epitaxial layer 1011 is a semiconductor material of a first conductivity type and includes multiple semiconductor layers. The main matrix material of the first-type epitaxial layer 1011 may be, but is not limited to, materials composed of Ga, N, As, P, In, or Al, etc. In addition, the first-type epitaxial layer 1011 may include, from top to bottom, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; in addition, an ohmic contact layer 106 may be formed below the window layer. In some embodiments, the second-type epitaxial layer 1013 is a semiconductor material of a second conductivity type and includes multiple semiconductor layers. The main matrix material of the second-type epitaxial layer 1013 may be, but is not limited to, materials composed of Ga, N, As, P, In, or Al, etc. In addition, the second-type epitaxial layer 1013 may include, from top to bottom, but is not limited to, a confinement layer and a waveguide layer; in addition, in some embodiments, an ohmic contact layer 106 may be formed on the confinement layer. In some embodiments of the present invention, the first conductivity type is different from the second conductivity type.

[0102] In some embodiments, the first-type epitaxial layer 1011 is an N-type GaN layer or an N-type AlGaN layer, and the second-type epitaxial layer 1013 is a P-type GaN layer or a P-type AlGaN layer. That is, the material of the second-type epitaxial layer 1013 can be a material layer of the second conductivity type composed of at least two or more elements including Ga, N, As, Al, In, and P, and the first-type epitaxial layer 1011 can be a material layer of the first conductivity type composed of at least two or more elements including Ga, N, As, Al, In, and P. In some embodiments, the light-emitting layer 1012 includes a multi-quantum well layer and an electron blocking layer. The multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer. In some embodiments, the light-emitting layer 1012 further includes an electron blocking layer, and the electron blocking layer is disposed on the first side of the light-emitting layer 1012. The first side refers to the side along which electrons migrate out of the light-emitting layer 1012. In other embodiments of the present invention, the first-type epitaxial layer 1011 can also be a P-type GaN layer or a P-type AlGaN layer, and the second-type epitaxial layer 1013 is an N-type GaN layer or an N-type AlGaN layer.

[0103] In some embodiments, the light-emitting layer 1012 includes at least one quantum well layer (not shown in the figure). The thickness of the quantum well layer is between 20 nm and 40 nm, for example, the thickness is 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x ) y In 1-y P, where the range of x is from 0.5 to 0.9, and the range of y is from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y.

[0104] In some embodiments, one of the first-type epitaxial layer 1011 and the second-type epitaxial layer 1013 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer, and the N-type cladding layer is formed on the doped N-type contact layer. The material of the N-type cladding layer is Al x In 1-x P, where the range of x is from 0.1 to 0.5, for example, x is 0.5. In addition, in these embodiments, the thickness of the N-type cladding layer is not greater than 350 nm. For example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e 17 cm -3 to 1e 18 cm -3。The material of the doped N-type contact layer is GaAs. In some embodiments, the thickness of the doped N-type contact layer is 10 nm to 30 nm. In some embodiments, the doping concentration of the doped N-type contact layer is 2e 18 cm -3 to 1e 19 cm -3 。In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where the range of x is 0.5 to 0.9 and the range of y is 0.1 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. The thickness of the N-type spacer layer is 50 nm to 75 nm, for example 65 nm.

[0105] In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light-emitting layer 1012, and the doped P-type contact layer is formed on the P-type cladding layer. In some embodiments, the material of the P-type cladding layer is Al x In 1-x P, where x is 0.3 to 0.5, for example x is 0.5. In such an embodiment, the thickness of the P-type cladding layer is not greater than 380 nm. For example, the thickness of the P-type cladding layer is 360 nm. In some embodiments, the material of the doped P-type contact layer is GaAs. The thickness of the doped P-type contact layer is 10 nm to 30 nm, for example 20 nm.

[0106] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first doped P-type transition layer formed on the P-type cladding layer, and a second doped P-type transition layer formed on the first doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where the range of x is 0.5 to 0.9 and the range of y is 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the thickness of the P-type spacer layer is 50 nm to 70 nm, for example 65 nm.

[0107] In some embodiments, the material of the first doped P-type transition layer is (Al x Ga 1-x ) y I n 1-yP, where the range of x is from 0.1 to 0.3, and the range of y is from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is that y is 1 to 5 times of x. In some embodiments, the thickness of the first doped P-type transition layer is from 20 nm to 40 nm, such as 30 nm.

[0108] In some embodiments, the material of the second doped P-type transition layer is Al x Ga 1-x As, where the range of x is from 0.5 to 0.9, such as x is 0.6. In some embodiments, the thickness of the second doped P-type transition layer is from 10 nm to 30 nm, such as 20 nm.

[0109] In some embodiments, the doping concentration of the second doped P-type transition layer is greater than the doping density of the first doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times that of the second doped P-type transition layer.

[0110] In some embodiments, the doping concentration of the doped P-type contact layer is greater than that of the second doped P-type transition layer. In addition, in some embodiments, the doping concentration of the second doped P-type transition layer is 2 to 4 times that of the first doped P-type transition layer.

[0111] For example, the doping concentration of the first doped P-type transition layer is greater than 1e 18 cm -3 , the doping density of the second doped P-type transition layer is in the range of 2e 18 cm -3 -4e 18 cm -3 , and the doping density of the doped P-type contact layer is greater than 5e 18 cm -3 .

[0112] The top electrode layer can reflect the light emitted by the micro light-emitting diode, thereby significantly increasing the total light output. At the same time, the top electrode layer can also isolate light and prevent light crosstalk between adjacent micro light-emitting diodes. By arranging the top electrode layer to surround the micro light-emitting diode in an electrical contact manner and being electrically connected to the top conductive layer, the electrical contact area between the top electrode layer and the micro light-emitting diode can be significantly increased, so that the active layer (light-emitting layer) of the micro light-emitting diode can emit light more uniformly, effectively avoiding the situation that only the electrical contact part or its vicinity emits light or the light emission brightness of the electrical contact part or its vicinity is too high.

[0113] Figure 3 Shows a top view schematic diagram of the top electrode layer of the micro light-emitting diode chip according to an embodiment of the present invention. As Figure 3As shown, the bottoms of adjacent top electrode layers 103 are connected, and all the top electrode layers are integrated into a whole. Figure 3 In [description], the top view shape (i.e., the cross-sectional shape) of the micro light-emitting diode is circular, and the top view shape of the overall top electrode layer is the grid shape remaining after removing the circle. In some embodiments of the present invention, the top view shape of the micro light-emitting diode may also be other suitable shapes, such as rectangular, square or regular polygon, etc., and the top view shape of the overall top electrode layer is correspondingly the shape remaining after removing other suitable shapes, such as the grid shape remaining after removing the rectangle, square or polygon. As Figure 2 As shown, the longitudinal section of adjacent top electrode layers presents a forked peak shape. In some embodiments of the present invention, the longitudinal section shape of adjacent top electrode layers may be symmetric or asymmetric, and the heights may be the same or different, which are not limited herein. The top electrode layer includes a first sidewall facing the light-emitting mesa, and the first sidewall contacts the top conductive layer only at the bottom end. The first sidewall is an inclined sidewall with a first inclined surface. The first inclined surface surrounds the light-emitting mesa and opens along the direction of light emission. The bottom end of the first sidewall is closer to the center of the light-emitting mesa than the top end. The inclination angle b of the first sidewall is in the range of 95° - 130°. The top electrode layer further includes a second sidewall, the upper end of the second sidewall is connected to the lower end of the first sidewall and extends downward to the bottom of the top electrode layer, and all surfaces of the second sidewall are in contact with the top conductive layer.

[0114] In some embodiments, the second sidewall has a second inclined surface, and the inclination angle of the second inclined surface relative to the light-emitting mesa is different from the inclination angle of the first inclined surface relative to the light-emitting mesa. The inclination angle of the second sidewall is less than 90°. In some embodiments, the top of the second sidewall is closer to the light-emitting mesa than the bottom of the second sidewall; the second inclined surface surrounds the light-emitting mesa and opens along the direction opposite to the light emission. The junction of the first sidewall and the second sidewall is lower than the top of the light-emitting mesa. In one embodiment, this junction is lower than the bottom of the light-emitting layer of the light-emitting mesa. The top of the first inclined surface is higher than the top of the light-emitting layer. The top of the first inclined surface is higher than the top of the light-emitting mesa.

[0115] In an embodiment of the present invention, the top electrode layer is formed at the isolation trench between the micro light-emitting diodes. The bottom of the top electrode layer contacts the top conductive layer formed in the isolation trench and protrudes upward. The bottom sidewall (second sidewall) of the top electrode layer contacts the top conductive layer covering the sidewalls of the ohmic contact layer and the bonding layer, so most of it is lower than the bottom surface of the light-emitting mesa. The upper sidewall (first sidewall) of the top electrode layer is higher than the bottom surface of the light-emitting mesa. The height difference between the bottom of the first sidewall and the bottom of the light-emitting mesa is the sum of the thicknesses of the passivation layer and the top conductive layer.

[0116] In an embodiment of the present invention, the bottom of the top electrode layer 103 is lower than the bottom of the light-emitting mesa 101.

[0117] In an embodiment of the present invention, the top of the top electrode layer 103 may be higher than the top of the light-emitting mesa 101; the top of the top electrode layer 103 may also be flush with the top of the light-emitting mesa 101; the top of the top electrode layer 103 may also be lower than the top of the light-emitting mesa 101 (for example, slightly lower than the top of the light-emitting mesa 101 by 0-1 micrometer). One, two, or three of the above situations may exist simultaneously in a chip.

[0118] Preferably, the top of the top electrode layer 103 is higher than the top of the light-emitting mesa 101. By making the height of the top of the top electrode layer 103 greater than the height of the top plane of the light-emitting mesa 101, a higher top electrode layer 103 can be obtained, further increasing the opportunity for light reflection and the light extraction efficiency.

[0119] In some embodiments of the present invention, the top electrode layer 103 has an annular cup-shaped structure, thus forming the effect of a reflective cup. The light-emitting mesa 101 is at the bottom of the reflective cup, and the bottom area of the reflective cup is smaller than the cup mouth area of the reflective cup. The angle b formed by the inner wall of the reflective cup and the horizontal plane in the direction of the inner light-emitting mesa is in the range of 95°-130°. When the micro light-emitting diode light irradiates the inner wall of the cup-shaped metal, the light path reflection improves the light extraction efficiency at small angles. The cup-shaped structure can achieve a better light-concentrating effect.

[0120] In other embodiments, the number of the top electrode layers 103 may also be 1 / 4 or 1 / 9 of the number of micro light-emitting diodes. Each top electrode layer 103 surrounds 4 micro light-emitting diodes, or 9 micro light-emitting diodes, without limitation.

[0121] The top electrode layer can increase the current spreading between adjacent micro light-emitting diodes, reduce the resistance between adjacent micro light-emitting diodes, and reduce losses. The top electrode layer can quickly and evenly spread the current to all micro light-emitting diodes.

[0122] In an embodiment of the present invention, the top electrode layer 103 may be a multi-layer structure, and the top electrode layer 103 includes one or more main metal layers. In some embodiments of the present invention, the top electrode layer 103 includes a mirror surface layer covering the surface of the main metal layer. The material of the one or more main metal layers is an alloy of one or more of the following metals: Ti, Ni, Au, Ag, Pt, Al, Cr, and Cu. The mirror surface layer may be made of AL or an AL alloy metal. The top electrode layer 103 may be formed by magnetron sputtering or evaporation, etc.

[0123] In some embodiments, the top electrode layer 103 may further include: isolation layers corresponding to each main metal layer one by one; wherein, the isolation layers and the main metal layers are arranged in an interleaved manner, and each main metal layer is located on the corresponding isolation layer.

[0124] By adopting isolation layers corresponding to each main metal layer one by one, and arranging the isolation layers and the main metal layers in an interleaved manner with each main metal layer located on the corresponding isolation layer, the influence of electromigration in the top electrode layer 103 can be effectively suppressed by setting the isolation layers. Especially when the density of micro light-emitting diodes in the micro light-emitting diode chip is relatively large, the possibility of increasing the height of the top electrode layer 103 can be obtained by setting the isolation layers, and then the light extraction efficiency can be further improved by the higher top electrode layer 103.

[0125] Furthermore, the isolation layer may include: a titanium (Ti) metal layer. It should be noted that the material of the isolation layer may also include other suitable materials, such as titanium nitride (TiN).

[0126] In some embodiments, the top electrode layer 103 may further include: an adhesion layer located at the bottommost layer of the top electrode layer 103, and the isolation layer and the main metal layer are located above the adhesion layer. The bottom stability of the top electrode layer 103 can be effectively improved through the adhesion of the adhesion layer. Especially when the density of micro light-emitting diodes is relatively large, the possibility of increasing the height of the top electrode layer 103 can be obtained by setting the adhesion layer, and then the light extraction efficiency can be further improved by the higher top electrode layer 103.

[0127] Furthermore, the adhesion layer may include: a chromium (Cr) metal layer. It should be noted that the material of the adhesion layer may also include other suitable materials, such as one or more of the following: titanium (Ti), titanium nitride (TiN), tungsten (W).

[0128] In the embodiments of the present invention, the top electrode layer 103 may further include: anti-diffusion layers corresponding to the isolation layers one by one, and each isolation layer is located on the corresponding anti-diffusion layer.

[0129] By forming anti-diffusion layers corresponding to the isolation layers one by one, and each isolation layer being located on the corresponding anti-diffusion layer, the stability of the top electrode layer 103 can be improved due to the high hardness and good anti-corrosion effect of the anti-diffusion layers. Especially when the density of micro light-emitting diodes in the micro light-emitting diode chip is relatively large, the possibility of increasing the height of the top electrode layer 103 can be obtained by setting the anti-diffusion layers, and then the light extraction efficiency can be further improved by the higher top electrode layer 103.

[0130] The anti-diffusion layer may include: a platinum (Pt) metal layer, a nickel (Ni) metal layer. It should be noted that the anti-diffusion layer may be a single-layer platinum metal layer, or a single-layer nickel metal layer, or a stack of a single-layer platinum metal layer and a single-layer nickel metal layer.

[0131] Figure 2 In [description], the lateral dimension of the bottom of the microlens 102 is greater than the lateral dimension of the light-emitting region of the micro light-emitting diode. In some embodiments, the lateral dimension of the bottom of the microlens 102 may be equal to the lateral dimension of the light-emitting region of the micro light-emitting diode.

[0132] In some embodiments, one microlens 102 may cover a plurality of lensless micro light-emitting diodes. A plurality of microlenses form a microlens array. The microlens array is disposed above the micro light-emitting diode array, wherein at least one microlens is disposed on the surface of the top conductive layer of the micro light-emitting diode, and the horizontal profile of the microlens is greater than the maximum horizontal profile of the micro light-emitting diode. The microlens is mainly used to converge and / or collimate light. For example, by adjusting parameters such as the thickness and curvature of the microlens, the focal point of the microlens can be located in the light-emitting mesa 101 of the micro light-emitting diode. The microlenses in the microlens array are usually the same. Examples of the microlens include a spherical microlens, an aspherical microlens, a Fresnal microlens, and a cylindrical microlens. As Figure 2 shown, in some embodiments of the present invention, the microlens 102 includes an upper curvature portion and a lower spacer portion. In some embodiments of the present invention, the typical shape of the lower spacer portion of each microlens 102 includes a circle, a square, a rectangle, and a hexagon. Each microlens in the microlens array of the display panel may be the same or different in terms of shape, curvature, optical power, size, base, spacer, etc.

[0133] In some embodiments of the present invention, the centers of curvature of each position on the side wall of the lower spacer portion do not coincide with the centers of curvature of each position of the upper curvature portion. The thickness of the lower spacer portion is set such that the focal point of the microlens is located in the light-emitting mesa 101 of the micro light-emitting diode. In some embodiments of the present invention, the height of the lower spacer portion of the microlens is 0.5 to 3 microns, and / or the height of the upper curvature portion of the microlens is 0.5 to 2 microns, and / or the spherical width of the microlens is 3 to 4 microns. In yet another embodiment, the microlens may be, for example, a positive hemisphere.

[0134] In some embodiments, the shape of the microlens 102 may be a curved hemispherical shape. In some embodiments, the height of the microlens 102 is no greater than 2 micrometers. In some embodiments, the height of the microlens 102 is no greater than 1 micrometer. In some embodiments, the height of the microlens 102 is no greater than 0.5 micrometers. In some embodiments, the width of the microlens 102 is no greater than 4 micrometers. In some embodiments, the width of the microlens 102 is no greater than 3 micrometers. In some embodiments, the width of the microlens 102 is no greater than 2 micrometers. In some embodiments, the width of the microlens 102 is no greater than 1 micrometer. In some embodiments, the ratio of the width to the height of the microlens 102 is greater than 1.5.

[0135] In some embodiments, microlens 102 may be made of various materials that are transparent to the wavelengths of light emitted by the micro-LED. Exemplary transparent materials for microlens 102 include polymers, dielectric materials. In some embodiments, the dielectric material includes one or more materials such as silicon oxide, silicon nitride, silicon carbide, titanium oxide, zirconium oxide, aluminum oxide, etc. In some embodiments, microlens 102 is made of photoresist.

[0136] In some embodiments, the manufacturing process of the microlens 102 is mainly based on CVD deposition of SiO 2 The film layer, because the actual thickness of the deposited film layer varies from 2.5 to 4um, the deposition procedure used is generally a high deposition rate film forming method, so deposition defects and micro cracks will occur in the deep groove area. After the deposition is completed, a photoresist with a suitable viscosity is selected, such as a positive photoresist, to coat the wafer surface, and then the light shielding area of ​​the exposure photomask is overlapped with the pixel position, and then exposed to form the microlens 102 photolithography pattern, and the photoresist morphology is fully exposed for a second time and the hard film is baked to improve, so that the photoresist shrinks due to the photosensitivity and thermal characteristics, and the cross-section forms a hemispherical morphology. At this point, the photolithography process is completed, and ICP dry etching is performed later, which is ion etching dominated by chemical etching. Then, based on the hemispherical morphology of the photolithography, according to the actual deposited SiO 2 Thickness, set a certain SiO 2 Etching time, get the remaining etching margin, then a similar Figure 1 The appearance of the microlens 102 is shown. 2 The etching rate is relatively stable and highly controllable, so the desired etching depth can be achieved by setting the etching time, wherein the position of the microlens 102 is photolithographically formed to form a hemispherical SiO 2 Morphology, the ball height here refers to the hemispherical SiO 2 The height of the ball is generally 1.5 to 1.8um. ​​Similarly, the ball width is the width of the arc-shaped hemispherical diameter. The height of the lower spacer is from the ball height to the upper bottom of the pixel point. The radius of curvature can be considered as the SiO 2For the hemispherical curve, the larger the radius of curvature, the larger the circle it represents, and the curve becomes flatter. The smaller the radius of curvature, the smaller the circle it represents, and the curve becomes more curved with a greater curvature.

[0137] However, through data simulation and multiple experimental verifications, the inventors found that the smaller the radius of curvature, that is, the wider the spherical width of the microlens 102, is beneficial to light output. Correspondingly, the increase in the spherical height, that is, changing the spherical height of the original hemispherical microlens 102, will also allow the escaping light to be emitted from the microlens 102. By changing the curvature, the total reflection angle of the microlens 102 is increased, making it difficult to form total reflection light, which is beneficial to the light output effect. In addition, in order to achieve a uniform lithography pattern, the photoresist is generally not too thick because the photoresist is also consumed as a mask layer during the etching process, and neither too much nor too little etching can obtain an ideal spherical height of the microlens 102. The effect is best when the spherical width and spherical height can form a positive semi-circular shape, that is, twice the spherical height is equal to the spherical width.

[0138] The inventors further found that the remaining amount of the lower spacer also affects the light output effect. For the same spherical height and spherical width, the lower spacer generally does not exceed the spherical height. Under the current process, there are micro-gap defects on both sides of the lower spacer of SiO 2 and light sources are prone to diffuse reflection here. If the lithography size of the microlens 102 is adjusted, this defect can be removed or reduced during the etching of the previous microlens 102, and subsequent secondary SiO 2 deposition can achieve the effect of defect repair.

[0139] In the existing process, it is inevitable that the spherical width and spherical height of the microlens 102 are not in the best conditions after etching. For example, through PECVD, the SiO 2 film layer of the microlens 102 is deposited for the first time, approximately 2.5 - 3.5 microns. Subsequently, by adjusting the lithography morphology of the microlens 102, such as the photoresist thickness, exposure energy, and hardening film temperature, the lithography array morphology at the corresponding pixel positions is completed. The passivation protection layer SIO of the microlens 102 is etched by ions 2 to form a hemispherical SIO with a lens-like morphology 2 microlens 102. After the etching of the microlens 102SIO 2 is completed, due to the lithography size and ion etching of the microlens 102, the overall radius of curvature, the height of the lower spacer, as well as the spherical height and lens spherical width of the microlens 102 are all slightly smaller. Therefore, secondary SIO 2 deposition is performed on the microlens 102 to increase the radius of curvature, the height of the lower spacer, as well as the spherical height and lens spherical width of the microlens 102. The thickness of the secondary SIO 2 deposited film needs to be based on the SiO deposited on the previous microlens 102 2The film thickness and the etched morphology of the microlens 102. The secondary deposition is generally in the range of 0.2 - 1 micron and can be performed once or multiple times. The inventor of the present invention found through research that the secondary deposition can achieve a better brightness improvement effect.

[0140] Based on this, the present invention provides a micro light-emitting diode chip and a manufacturing method thereof. The microlens 102 is formed by multiple depositions to change the height of the spacer portion, the radius of curvature, and the lens ball height under the microlens 102, improve the micro defects of the lens, and effectively improve the light efficiency of the micro light-emitting diode chip.

[0141] Figure 4 The longitudinal cross-sectional schematic diagram of the micro light-emitting diode chip according to another embodiment of the present invention is shown. Figure 4 The shown micro light-emitting diode chip and Figure 2 The difference between the shown micro light-emitting diode chips lies in the reduced thickness of the top conductive layer 104 and the passivation layer 105.

[0142] As Figure 4 shown, the passivation layer 105 can be formed by an atomic layer deposition process. Since the passivation layer 105 formed by the atomic layer deposition process has the advantages of uniform film formation, dense and hole-free, and good step coverage. The thickness of the passivation layer 105 formed thereby can be thinned to less than 3000 angstroms. In an embodiment of the present invention, the thickness of the passivation layer 105 is in the range of 500 angstroms to 1500 A, and at the same time, it can effectively reduce the chip leakage rate, meeting the chip requirements. Thinning the thickness of the passivation layer 105 can sink the annular reflective electrode (top electrode layer) and improve the light efficiency. Then, a photolithography opening process is performed on the passivation layer 105 on the top surface of the light-emitting mesa 101 through a photolithography process to etch and expose at least a part of the top surface of the light-emitting mesa 101.

[0143] As Figure 4 shown, the top conductive layer 104 can be formed on the top surface of the light-emitting mesa and the top surface of the passivation layer 105 by a sputtering process. Since the coverage and continuity of the top conductive layer 104 formed by the sputtering process are better than those of evaporation coating. The thickness of the top conductive layer 104 formed thereby can be thinned to less than 3000 angstroms. In an embodiment of the present invention, the thickness of the top conductive layer 104 is in the range of 500 angstroms to 1500 A, while ensuring that the coverage and continuity meet the chip requirements. Thinning the thickness of the top conductive layer 104 can not only reduce the light absorption effect of the top conductive layer 104, but also sink the annular reflective electrode and improve the light efficiency.

[0144] In some embodiments, by thinning the thicknesses of the passivation layer and the top conductive layer, the passivation layer and the top conductive layer can be reduced in thickness by 4,000 angstroms to 6,000 angstroms. At the same time, the height of the top electrode layer is increased by 4,000 angstroms to 6,000 angstroms. That is, with the high point of the top electrode layer remaining unchanged, the bottom of the top electrode layer sinks by 4,000 angstroms to 6,000 angstroms. At the same time, the angle b formed between the reflective inner wall of the top electrode layer and the horizontal plane of the inner light-emitting mesa direction is maintained within the range of 95° to 130°, which can reflect the light within a small angle upward and improve the light extraction efficiency. As Figure 4 shown, the light within a small angle a can be reflected upward to improve the light extraction efficiency, and the small angle a is 15° to 25°.

[0145] Figure 5 shows a longitudinal sectional schematic view of a micro light-emitting diode chip according to another embodiment of the present invention. Figure 5 The micro light-emitting diode chip shown in Figure 4 differs from the micro light-emitting diode chip shown in

[0146] in that the height of the top electrode layer is further increased such that the top of the top electrode layer is flush with, slightly lower than, or slightly higher than the top of the light-emitting mesa, thereby improving the light extraction efficiency.

[0147] Although the embodiments of the present invention have been described above, it should be understood that they are presented only as examples and not as limitations. It will be obvious to those skilled in the relevant art that various combinations, variations, and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the width and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined only by the appended claims and their equivalents.

Claims

1. A micro light emitting diode chip, comprising: Luminous countertops; A top conductive layer, the top conductive layer is located on the side and top surfaces of the light-emitting mesa; A passivation layer, the passivation layer at least partially covers the side surface of the light-emitting mesa, and the passivation layer is located between the light-emitting mesa and the top conductive layer; as well as A top electrode layer, located between the micro-LEDs, the top electrode layer surrounds the micro-LEDs, and the top electrode layer has a first side wall facing the light-emitting mesa; The first side wall contacts the top conductive layer only at a bottom end, and the first side wall has a first inclined surface.

2. The micro light emitting diode chip according to claim 1, characterized in that: The bottom end of the first side wall is closer to the light-emitting mesa than the top end.

3. The micro light emitting diode chip according to claim 2, characterized in that: The first inclined surface surrounds the light-emitting table and opens along a light-emitting direction.

4. The micro light emitting diode chip according to claim 1, characterized in that: The top electrode layer comprises a second side wall, the upper end of the second side wall is connected to the lower end of the first side wall and extends downward to the bottom of the top electrode layer; the second side wall has a second inclined surface.

5. The micro light emitting diode chip according to claim 4, characterized in that: The top of the second side wall is closer to the light-emitting table than the bottom of the second side wall; the second inclined surface surrounds the light-emitting table and opens along the direction opposite to the light-emitting direction.

6. The micro light emitting diode chip according to claim 4, characterized in that: The junction of the first side wall and the second side wall is lower than the top of the light-emitting table.

7. The micro light emitting diode chip according to claim 6, characterized in that: The light emitting mesa has a first semiconductor epitaxial layer, a light emitting layer and a second semiconductor epitaxial layer.

8. The micro light emitting diode chip according to claim 7, characterized in that: The junction is lower than the bottom of the light-emitting layer of the light-emitting mesa.

9. The micro light emitting diode chip according to claim 8, characterized in that: The light emitting layer comprises a plurality of stacked semiconductor material layers.

10. The micro light emitting diode chip according to claim 7, characterized in that: The top of the first inclined surface is higher than the top of the light-emitting layer.

11. The micro light emitting diode chip according to claim 10, characterized in that: The top of the first inclined surface is higher than the top of the light-emitting mesa.

12. The micro light emitting diode chip according to claim 1, characterized in that: The thickness of the top conductive layer is less than 3000 angstroms, and the thickness of the passivation layer is less than 3000 angstroms, the thickness of the top conductive layer is in the range of 500 angstroms to 1500 angstroms, and / or The thickness of the passivation layer is in the range of 500 angstroms to 1500 angstroms.

13. The micro light emitting diode chip according to claim 1, characterized in that: The bottom of the first side wall is higher than the bottom of the light-emitting mesa, and the height difference between the bottom of the first side wall and the bottom of the light-emitting mesa is in a range of 1000 angstroms to 3000 angstroms.

14. The micro light emitting diode chip according to claim 1, characterized in that: The included angle between the first inclined surface and the top of the light-emitting table is 95°-130°.

15. The micro light emitting diode chip according to claim 1, characterized in that: Also includes: An ohmic contact layer is located at the bottom of the light-emitting mesa.

16. The micro light emitting diode chip according to claim 15, characterized in that: The electrode polarity of the ohmic contact layer is opposite to the electrode polarity of the top conductive layer.

17. The micro light emitting diode chip according to claim 1, characterized in that: The bottoms of adjacent top electrode layers are connected, and all the top electrode layers are connected into a whole.

18. The micro light emitting diode chip according to claim 1, characterized in that: A longitudinal section of the adjacent top electrode layer presents a shape of a bifurcated peak.

19. The micro light emitting diode chip according to claim 1, characterized in that: The longitudinal cross-sections of adjacent top electrode layers are symmetrical or asymmetrical.

20. The micro light emitting diode chip according to claim 1, characterized in that: The top electrode layer comprises: one or more primary metal layers; and A reflective mirror layer covering the surface of the main metal layer, wherein the material of the one or more main metal layers is an alloy of one or more of the following metals: Ti, Ni, Au, Ag, Pt, Al, Cr and Cu, and the reflective mirror layer is AL or AL alloy metal.

21. The micro light emitting diode chip according to claim 4, characterized in that: The bottom of the top electrode layer is lower than the bottom of the light-emitting mesa, and the entire surface of the second side wall is in contact with the top conductive layer.

22. The micro light emitting diode chip according to claim 4, characterized in that: An inclination angle of the second inclined surface relative to the light-emitting mesa is different from an inclination angle of the first inclined surface relative to the light-emitting mesa.

23. The micro light emitting diode chip according to claim 22, characterized in that: The inclination angle of the second side wall is less than 90°.

24. The micro light emitting diode chip according to claim 1, characterized in that: The top of the top electrode layer is higher than the top of the light-emitting mesa; or The top of the top electrode layer is flush with the top of the light-emitting mesa; or The top of the top electrode layer is lower than the top of the light emitting mesa.

25. The micro light emitting diode chip according to claim 3, characterized in that: The top electrode layer is a reflective cup structure, the bottom area of ​​the reflective cup is smaller than the cup mouth area of ​​the reflective cup, and the angle between the inner wall of the reflective cup and the horizontal plane of the inner light-emitting table surface is in the range of 95°-130°.

26. The micro light emitting diode chip according to claim 1, characterized in that: Adjacent top conductive layers are connected to each other, and all the top conductive layers are connected into a whole.

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