Integration of field effect transistors with schottky diodes on substrate

Abstract

The application relates to integrating a field effect transistor (FET) and a Schottky barrier diode (SBD) on a substrate and forming an integrated planar semiconductor device. And forming a P-type metal oxide semiconductor (PMOS) transistor and a P-type SBD on the substrate. The P-type SBD is formed by bonding a P-type semiconductor and a first barrier metal. A doping concentration of a P-type channel of the PMOS transistor is established concurrently while forming a first portion of the P-type semiconductor of the SBD. An extended drain structure of the PMOS transistor and a second portion of the P-type semiconductor are simultaneously formed on the substrate. Different silicide contact surfaces of the extended drain structure of the PMOS transistor and the first portion and the second portion of the P-type semiconductor of the P-type SBD are concurrently formed.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 408,796, filed on September 21, 2022, entitled "Integration of Field Effect Transistors and Schottky Diodes on a Substrate", U.S. Provisional Application No. 63 / 494,362, filed on April 5, 2023, entitled "Front-End-Of-Line (FEOL) and Middle-of-Line (MOL) of Planar SCMOS Fabrication Processes", and U.S. Provisional Application No. 63 / 509,250, filed on June 20, 2023, entitled "Front-End-Of-Line (FEOL) and Middle-of-Line (MOL) of Planar SCMOS Fabrication Processes". Each of these applications is incorporated herein by reference in its entirety. Technical Field

[0003] This application generally relates to integrated circuit (IC) devices, and more particularly, to devices and methods for integrating field effect transistors (FETs) and Schottky barrier diodes (SBDs) on a semiconductor substrate. Background Art

[0004] Over the past few decades, the continuous maximum increase in integrated circuit (IC) device density has driven the development of various industries in the high-tech sector. These high-tech industries include semiconductors, electronic devices, computers, communications, and their associated software fields used to build system platforms and software applications. This increase in IC device density is mainly attributed to new lithography techniques that utilize shorter light wavelengths and / or chemical and physical manufacturing processes with desired yield, reproducibility, and quality control.

[0005] IC development has gone through multiple technology nodes corresponding to different semiconductor manufacturing processes, design rules, generations of circuits, and / or system architectures. Each technology node is achieved by reducing the size of the IC, improving the performance of metal-oxide-semiconductor field-effect transistors (MOSFETs), and increasing the levels and density of metal interconnects. As a result, each new technology node is more complex than the previous one and thus requires more expensive microfabrication technologies, facilities, and resources. At each new technology node, the tools, time, and manpower applied to implement very-large-scale integration (VLSI) circuits also become more complex and expensive. Before the 20nm technology node, MOSFETs were integrated on a substrate with a planar structure, while after the 20nm technology node, MOSFETs began to adopt a three-dimensional (3D) structure, adding height to their channel width and shortening the channel length. However, the application of technology nodes has been focused on MOSFETs and has rarely involved or not involved other active semiconductor devices (e.g., diodes). It would be beneficial to introduce different types of semiconductor devices into integrated circuits that are different from current practices. Summary of the Invention

[0006] This application relates to integrating a planar field-effect transistor (FET) and a Schottky barrier diode (SBD) on a substrate in a monolithic manner (e.g., via a planar semiconductor microfabrication process). Specifically, this application describes an overall IC manufacturing method for P-type and N-type SBDs. These SBDs are used together with P-type and N-type MOSFETs provided in existing or upcoming planar complementary metal-oxide-semiconductor (CMOS) technology nodes of large-scale industrial production, thereby implementing a Schottky-based complementary metal-oxide-semiconductor (SCMOS) IC. Each part of the SBD is formed by existing semiconductor manufacturing operations of the semiconductor microfabrication process without adding any masks and thus corresponds to the corresponding part of the FET. In some embodiments, the feature size of at least one mask (e.g., a silicide definition mask) is reduced to facilitate the simultaneous formation of the SBD and the FET in a planar semiconductor microfabrication process.

[0007] In one aspect of this application, a method of forming an integrated planar semiconductor device is implemented. The method includes forming a P-type metal-oxide-semiconductor (PMOS) transistor and a P-type SBD on a substrate. The P-type SBD is formed by bonding a P-type semiconductor and a first barrier metal (e.g., the cathode). The method further includes: simultaneously establishing the doping concentration of the P-type channel of the PMOS transistor and forming a first part of the P-type semiconductor of the P-type SBD; simultaneously forming an extended drain structure of the PMOS transistor and a second part of the P-type semiconductor on the substrate; and simultaneously forming different silicide contact surfaces of the extended drain structure of the PMOS transistor and the first and second parts of the P-type semiconductor of the P-type SBD.

[0008] In another aspect, an integrated planar semiconductor device includes a substrate, a PMOS transistor formed on the substrate, and a P-type SBD formed on the substrate and formed by bonding a P-type semiconductor and a first barrier metal. A first doping concentration of a P-type channel of the PMOS transistor is substantially the same as a first doping concentration of a first portion of the P-type semiconductor of the SBD. A doping profile of an extended drain structure of the PMOS transistor is substantially the same as a doping profile of a second portion of the P-type semiconductor. Each of the extended drain structure of the PMOS transistor and the first and second portions of the P-type semiconductor has a different silicide contact surface.

[0009] In yet another aspect of the present invention, a method of forming an integrated planar semiconductor device is implemented. The method includes forming an N-type metal oxide semiconductor (NMOS) transistor and an N-type SBD on a substrate. The N-type SBD is formed by bonding an N-type semiconductor and a first barrier metal. The method further includes: simultaneously establishing a doping concentration of an N-type channel of the NMOS transistor and forming a first portion of the N-type semiconductor of the SBD; simultaneously forming an extended drain structure of the NMOS transistor and a second portion of the N-type semiconductor on the substrate; and simultaneously forming different silicide contact surfaces of the extended drain structure of the NMOS transistor and the first and second portions of the N-type semiconductor of the N-type SBD.

[0010] In yet another aspect, an integrated planar semiconductor device includes a substrate, an N-type metal oxide semiconductor (NMOS) transistor formed on the substrate, and an N-type SBD formed on the substrate and formed by bonding an N-type semiconductor and a first barrier metal. A first doping concentration of an N-type channel of the NMOS transistor is substantially the same as a first doping concentration of a first portion of the N-type semiconductor of the SBD. A doping profile of an extended drain structure of the NMOS transistor is substantially the same as a doping profile of a second portion of the N-type semiconductor. Each of the extended drain structure of the NMOS transistor and the first and second portions of the N-type semiconductor has a different silicide contact surface.

[0011] The mention of these illustrative embodiments and implementations is not intended to limit or define the present disclosure, but rather to provide examples to assist in understanding the present disclosure. Additional embodiments are discussed in the detailed description and further description is provided in the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] To better understand the various implementations described, reference should be made to the following embodiments in conjunction with the accompanying drawings below, in which like reference numerals refer to corresponding parts throughout the figures.

[0013] Figure 1ASchematic diagram of a three-input Schottky CMOS NAND logic gate integrating a CMOS transistor and a Schottky barrier diode according to some embodiments.

[0014] Figure 1B According to some embodiments Figure 1A IC layout diagram of the three-input NAND logic gate shown in

[0015] Figure 2A and 2B Two different cross-sectional views of an exemplary integrated semiconductor device including a PMOS transistor and an N-type SBD according to some embodiments.

[0016] Figure 2C and 2D Two different cross-sectional views of an exemplary integrated semiconductor device including an NMOS transistor and a P-type SBD according to some embodiments.

[0017] Figures 3A - 3F Cross-sectional view of an integrated semiconductor device processed in the front-end-of-line (FEOL) of a planar SCMOS manufacturing process according to some embodiments.

[0018] Figure 4A and 4B Two different cross-sectional views of another exemplary integrated semiconductor device including an NMOS transistor and an N-type SBD according to some embodiments.

[0019] Figure 4C and 4D Two different cross-sectional views of another exemplary integrated semiconductor device including a PMOS transistor and a P-type SBD according to some embodiments.

[0020] Figures 5A - 5F Cross-sectional view of another exemplary integrated semiconductor device processed in the FEOL of a planar SCMOS manufacturing process according to some embodiments.

[0021] Figure 6A and 6B Two different cross-sectional views of an integrated semiconductor device including CMOS transistors and complementary SBDs and processed until before the completion of the FEOL of a planar SCMOS manufacturing process according to some embodiments.

[0022] Figure 7A and 7B Two different cross-sectional views of an integrated semiconductor device including CMOS transistors and complementary SBDs and processed to the first metal layer in the back-end-of-line (BEOL) of a planar SCMOS manufacturing process according to some embodiments.

[0023] Throughout several views of the drawings, like reference numerals refer to corresponding parts. Detailed Description

[0024] This application relates to Schottky-based complementary metal oxide semiconductor (SCMOS) technology that integrates P-type and N-type Schottky barrier diodes (SBDs) in a planar CMOS microfabrication process. Each SBD is made by bonding a barrier metal and a semiconductor structure. The barrier metal (e.g., Ni / CoEr) is doped with dopants and formed on a silicided diffusion trench (e.g., formed together with the source and drain of a CMOS transistor). Specifically, examples of the barrier metal include, but are not limited to, nickel silicide (NiSi) or cobalt silicide (CoSi 2 ). When the surface is shallowly doped with impurity atoms of a metal material (e.g., nickel, nickel silicide, cobalt, cobalt silicide, etc.) or coated with a thin layer of a metal material, another material may optionally be applied as the barrier metal. The silicided diffusion trench is formed simultaneously with the source and drain of the CMOS transistor. In some embodiments, the photomask is adjusted to block or insert certain ions implanted into the silicided diffusion trench of the SBD. In an example, the trench series resistance is reduced to increase the diode current density.

[0025] Each SBD has a conductance characteristic that is determined by the material composition of the barrier metal and the silicided diffusion trench, and more specifically, by the impurities and physical properties of the metal-silicon interface at the diode junction of the SBD. Example electronic properties of this metal-silicon interface include, but are not limited to, the barrier height associated with the on / off voltage of the SBD. In some embodiments, compared to the threshold voltage of a MOSFET integrated in SCMOS technology, the combination of the barrier metal and the silicided diffusion trench results in a relatively low value of the barrier height and on / off voltage of the Schottky barrier diode. Therefore, a Schottky barrier diode with a low on / off voltage is also referred to as a low-threshold Schottky barrier diode (LtSBD).

[0026] In various embodiments of the present application, the integration of SBD in a planar CMOS manufacturing process (e.g., at 28nm or 65nm technology nodes) is achieved by modifying a self-aligned silicidation module. A corresponding silicide definition photomask is involved in defining the SBD. The photomask has a first critical dimension that defines the feature size of the SBD. In contrast, when the silicide definition photomask is used in a planar CMOS manufacturing process that does not involve SBD, it has a second critical dimension (e.g., defining the feature size of a silicide resistor). The second critical dimension is larger than the first critical dimension associated with the SBD. Although the silicide definition photomask is not critical in a planar CMOS manufacturing process, it becomes critical in a planar SCMOS manufacturing process integrated with SBD. A computer-aided design (CAD) software tool is used to control a photomask manufacturing machine to print the features of a circuit and device layout onto the silicide definition photomask according to a logic formula. The parameters applied in the logic formula are modified to reflect the change in the critical dimension of the silicide definition photomask.

[0027] Figure 1A FIG. 100 is a schematic diagram of a three-input Schottky CMOS NAND logic gate integrating a CMOS transistor and an SBD according to some embodiments, and Figure 1B According to some embodiments Figure 1AIC layout diagram 150 of the three-input NAND logic gate shown in the figure. The three-input Schottky CMOS NAND logic gate 100 includes three P-type SBDs 102, 104, and 106, a cross-coupled latch 108, and a control transistor 110. The cross-coupled latch 108 includes two CMOS inverters 108A and 108B, and the input and output of the CMOS inverter 08A are cross-coupled to the output and input of the CMOS inverter 108B, respectively. The CMOS inverter 108A includes a PMOS transistor 112A and an NMOS transistor 114A serially coupled to the PMOS transistor 112A. The CMOS inverter 108B includes a PMOS transistor 112B and an NMOS transistor 114B serially coupled to the PMOS transistor 112B. Input A0 is coupled to the cathode of the p-type SBD 102. Input A1 is coupled to the cathode of the p-type SBD 104. Input A2 is coupled to the cathode of the p-type SBD 106. The anodes of the SBDs 102, 104, and 106 are coupled to each other. The anodes of the SBDs 102-106 are also coupled to the input of the CMOS inverter 108A (i.e., the gates of the PMOS transistor 112A and the NMOS transistor 114A) and the output of the CMOS inverter 108B (i.e., the drains of the PMOS transistor 112B and the NMOS transistor 114B). Conversely, the output Y of the NAND logic gate 100 is coupled to the output of the CMOS inverter 108A (i.e., the drains of the PMOS transistor 112A and the NMOS transistor 114A) and the input of the CMOS inverter 108B (i.e., the gates of the PMOS transistor 112B and the NMOS transistor 114B).

[0028] The CMOS inverters 108A and 108B are coupled between a high supply voltage VDD (e.g., 1.8V, 0.9V) and a low supply voltage VSS (e.g., ground, -1.8V). The source of the pull-up transistor 112A is coupled to the high supply voltage VDD, and the drain of the pull-up transistor 112B is coupled to the input of the CMOS inverter 108A and the anodes of the P-type SBDs 102-106. The control transistor 110 is controlled by the input signal PCKN. When the input signal PCKN is at the low supply voltage VSS, the input of the CMOS inverter 108A is at the high supply voltage VDD, and the output of the NAND logic gate 100 is at the low supply voltage VSS. Conversely, when the input signal PCKN is at the high supply voltage VSS, the input of the CMOS inverter 108A is determined by the combination of the inputs A0, A1, and A2, and the output of the NAND logic gate 100 is also determined by the combination of the inputs A0, A1, and A2. Therefore, the NAND logic gate 100 is dynamic logic controlled to be refreshed at a positive duty cycle of the input signal PCKN.

[0029] ReferenceFigure 1A , a Schottky-based CMOS implementation of the three-input NAND logic gate 100 uses a P-type control transistor 110 coupled to the anodes of three SBDs 102-106. Conversely, in some embodiments not shown, another Schottky CMOS implementation of the three-input NAND logic gate uses an n-type transistor 100' (instead of the PMOS control transistor 110) coupled to the anodes of three SBDs 102-106. The N-type control transistor 110' is coupled between the anodes of the three SBDs 102-106 and the low supply voltage VSS. In some embodiments not shown, the three SBDs 102-106 are implemented by N-type SBDs sharing a common anode coupled to the control transistor 110 or 110'.

[0030] In some implementations not shown, the NAND logic gate 100 has a number of inputs (e.g., 2 inputs, 8 inputs), where the number is different from three. Each input A of the NAND logic gate 100 i is coupled to the cathode of a corresponding P-type SBD, and the anode of the corresponding P-type SBD is coupled to the input of the CMOS inverter 108A. Each P-type SBD can be implemented by a PMOS or NMOS transistor in a corresponding planar CMOS manufacturing process without integrating the SBD. As the number of inputs and P-type SBDs increases, the efficiency enhancement obtained by replacing transistors with SBDs also increases. Referring Figure 1B , the inputs A0, A1, and A2 are disposed on the regions forming the P-type SBDs 102-106. Compared to transistors formed in a corresponding planar CMOS manufacturing process without integrating the SBD, the P-type SBDs 102-106 do not contain any gate, channel, source, or drain structures and require much less chip area.

[0031] In some embodiments, the P-type SBDs 102-106 are formed in an N-well. In some embodiments, at least one of the P-type SBDs 102-106 is formed in the N-well together with a subset of the PMOS transistors 110, 112A, and 112B. Additionally, in some embodiments, the anode of at least one of the P-type SBDs 102-106 overlaps the drain of a subset of the PMOS transistors 110, 112A, and 112B. Additionally, in some embodiments, one or both of the NMOS transistors 114A and 114B are formed in a P-well, which is optionally isolated from the N-well by a field oxide or a trench.

[0032] As the feature size of integrated circuits (ICs) on silicon (Si) decreases, more complex and diverse electronic functions are integrated on a single silicon die. CMOS ICs are currently used as the main semiconductor technology for forming very large scale integration (VLSI) logic and static random access memory (SRAM) ICs. The increase in the density and complexity of VLSI is mainly attributed to the continuous gradual reduction of the minimum feature size of both semiconductor functional circuits and the corresponding metal interconnects. Specifically, the continuous increase in IC density and the number of components is caused by the development of wafer fabrication plant equipment, tools, and methods, which enables the improvement of existing microfabrication technologies and transistor structures and the application of new microfabrication technologies and transistor structures. As the VLSI technology node changes from a planar CMOS manufacturing process to a vertical fin-based CMOS manufacturing process, such as from 2000 to 2010, the IC density and the number of components continue to increase.

[0033] The vertical fin-based CMOS manufacturing process is widely used in the 16 - 22 nm technology node, where CMOS transistors have been built on fins, and both the integration density and complexity have increased. The vertical fin-based CMOS manufacturing process is achieved by improving established as well as new types of semiconductor microfabrication equipment and processes. For example, self-aligned multiple patterning is applied to improve the effective resolution of lithography, and atomic layer deposition (ALD) is developed to control the thickness of various materials for nanoscale layer deposition. Plasma implantation is used to introduce semiconductor doping impurities. In some embodiments, two sets of improvements are desired for the technology node. First, one desired improvement for the technology node includes simultaneously increasing the operating speed and reducing the IC die area and power dissipation. Second, another desired improvement for the technology node includes using Schottky CMOS technology for both planar and vertical fin-based CMOS manufacturing processes.

[0034] In some embodiments, at least half of the transistors used to implement the logic circuit block are replaced by LtSBDs. The diode area of each LtSBD is optionally less than half of the minimum MOSFET size. Thus, the block area of the logic circuit block integrated with LtSBDs on the substrate is smaller. Additionally, the signal nets or interconnects of the SBD-based logic circuit block (e.g., using SBDs) are fewer than those of the transistor-based logic circuit block (e.g., using transistors without any SBDs). For example, the three-input NAND logic gate 100 has a device area of 0.84 μm × 0.73 μm. When implemented entirely based on transistors, the area of the three-input NAND logic gate is larger than the device area of 0.84 μm × 0.73 μm.

[0035] The advantages of SCMOS technology extend to digital circuits, SRAM and non-volatile memories, as well as analog circuits. SCMOS provides a low-cost solution to keep up with the progress predicted by Moore's Law. SCMOS technology does not rely on reducing the size of patterns printed on a semiconductor substrate, nor on improvements in microfabrication steps and equipment. SCMOS technology neither requires upgrading or adding microfabrication equipment, nor does it require implementing new and more complex silicon wafer processing steps. SCMOS reduces the operating expenses of IC manufacturing. In any existing technology node, the impact of adding LtSBD on existing reliability and quality assurance procedures is less than creating a new transistor structure in a new technology node. Additionally, SBD-based circuits employ a smaller number of MOSFET devices than transistor-based circuits, thereby eliminating corresponding photomasks and lithography steps in some cases. Thus, by integrating SBDs and using SBDs to modify circuits, the overall IC manufacturing cost of established technology nodes is reduced. Various embodiments of the present application relate to integrating SBDs in planar silicon resin technology nodes with little or no change to existing planar CMOS manufacturing processes.

[0036] Figure 2A and 2B are two different cross-sectional views 210 and 220 of an integrated semiconductor device 200 including a PMOS transistor 202 and an N-type SBD 204 according to some embodiments. Figure 2C and 2D are two different cross-sectional views 240 and 250 of an integrated semiconductor device 230 including an NMOS transistor 206 and a P-type SBD 208 according to some embodiments. Cross-sectional views 210 and 220 correspond to two vertical lines on the top surface of the corresponding substrate, and cross-sectional views 240 and 250 also correspond to two vertical lines on the top surface of the corresponding substrate. The integrated semiconductor device 200 integrates the PMOS transistor 202 and the N-type SBD 204 on a substrate 212, and the integrated semiconductor device 230 integrates the NMOS transistor 206 and the P-type SBD 208 on a substrate 214.

[0037] In an integrated semiconductor device 200, a PMOS transistor 202 is formed in a first N-well 216, and an N-type SBD 204 is formed in a first P-well 218. The N-type SBD 204 joins an N-type semiconductor 222 and a barrier metal 224 (i.e., the anode). The first P-well 218 and the N-well 216 are optionally connected to each other. A spacer 226 is formed between the first P-well 218 and the N-well 216 to enhance electrical isolation between the PMOS transistor 202 and the N-type SBD 204. The spacer 226A is located between the P-well 218 and the N-well 216 and includes a field oxide region or a trench. In some embodiments, each spacer 226B is used at the edge of the N-well 216 or the P-well 218. In some embodiments, each spacer 226C is used within a respective one of the N-well 216 and the P-well 218 to separate two electrical structures (e.g., the N-type SBD 204 and the well contact 228). Conversely, in an integrated semiconductor device 230, an NMOS transistor 206 is formed in a second P-well 236, and a P-type SBD 208 is formed in a second N-well 238. The P-type SBD 208 joins a P-type semiconductor 242 and a barrier metal 244 (i.e., the cathode). The second P-well 236 is different from the first P-well 218, and the second N-well 238 is different from the second N-well 216. The second P-well 236 and the N-well 238 are optionally connected to each other. A spacer 226 is formed in the connection region between the second P-well 236 and the N-well 238 to enhance electrical isolation between the NMOS transistor 206 and the P-type SBD 208.

[0038] The well contact 228 of the first P-well 218 is a combination of a first P-type portion 228A and a second P-type portion 228B, and the P-type portions 228A and 228B are formed together with a first portion 242A and a second portion 242B of the P-type semiconductor 242 of the P-type SBD 208, respectively. In other words, the P-type portions 228A and 228B are formed together with the P-type channel 202C and the extended drain structure of the PMOS transistor 202, respectively. The second portion 228B is formed in the first P-type portion 228A of the well contact 228 and has a different silicide contact surface. The well contact 248 of the second N-well 238 is a combination of a first N-type portion 248A and a second portion 248B, and the N-type portions 248A and 248B are formed together with a first portion 222A and a second portion 222B of the N-type semiconductor 222 of the N-type SBD 204, respectively. In other words, the N-type portions 248A and 248B are formed together with the N-type channel 206C and the extended drain structure 206D of the NMOS transistor 206, respectively. The second portion 248B is formed in the first N-type portion 248A of the well contact 248 and has a different silicide contact surface.

[0039] In some embodiments, substrates 212 and 214 are different portions of a silicon wafer processed by a common planar CMOS manufacturing process and separated from the silicon wafer after the planar CMOS manufacturing process is completed. Optionally, substrates 212 and 214 form a single substrate. Optionally, substrates 212 and 214 are separated from each other. The PMOS transistor 202 has a P-type channel 202C and an extended drain structure 202D. The NMOS transistor 206 has an N-type channel 206C and an extended drain structure 206D. The N-type semiconductor 222 of the N-type SBD 204 has a first portion 222A forming an N-type diffusion trench and a second portion 222B located in the N-type diffusion trench of the first portion 222A. The P-type semiconductor 242 of the P-type SBD 208 has a first portion 242A forming a P-type diffusion trench and a second portion 242B located in the P-type diffusion trench of the first portion 242A.

[0040] The first portion 242A of the P-type semiconductor 242 of the P-type SBD 208 is formed in common with the P-type channel 202C of the PMOS transistor 202 and has the same doping concentration as the P-type channel. The second portion 242B of the P-type semiconductor 242 of the P-type SBD 208 is formed in common with the extended drain structure 202D of the PMOS transistor 202. Different silicide contact surfaces of the extended drain structure 202D of the PMOS transistor 202 and the first portion 242A and the second portion 242B of the P-type semiconductor 242 of the P-type SBD 208 are formed simultaneously. Additionally, the first portion 222A of the N-type semiconductor 222 of the N-type SBD 204 is formed in common with the N-type channel 206C of the NMOS transistor 206 and has the same doping concentration as the N-type channel. The second portion 222B of the N-type semiconductor 222 of the N-type SBD 204 is formed in common with the extended drain structure 206D of the NMOS transistor 206. Different silicide contact surfaces of the extended drain structure 206D of the NMOS transistor 206 and the first portion 222A and the second portion 222B of the N-type semiconductor 222 of the N-type SBD 204 are formed simultaneously. In some embodiments, for example using a single contact photomask (also referred to as a self-aligned silicide (salicide) definition mask), the different silicide contact surfaces of the extended drain structures of the PMOS transistor 202 and the NMOS transistor 206, the first and second portions of the N-type semiconductor 222 of the N-type SBD 204, and the first and second portions of the P-type semiconductor 242 of the P-type SBD 208 are patterned and formed simultaneously.

[0041] After opening different silicide contact surfaces using a single contact photomask, a metal material layer is deposited to fill contact holes formed in different silicide contact surfaces of PMOS transistor 202, NMOS transistor 206, P-type SBD 208, and / or N-type SBD 204. The metal material layer is patterned to provide a drain path 202DA coupled to the silicide contact surface of the extended drain structure 202D of PMOS transistor 202, an anode path 242C coupled to the silicide contact surface of the second portion 242B of P-type semiconductor 242 of P-type SBD 208, and a barrier metal 244 coupled to the silicide contact surface of the first portion 242A of P-type semiconductor 242 of P-type SBD 208. The metal material layer is also patterned to provide a drain path 206DA coupled to the silicide contact surface of the extended drain structure 206D of NMOS transistor 206, a cathode path 222C coupled to the silicide contact surface of the second portion 222B of N-type semiconductor 222 of N-type SBD 204, and a barrier metal 224 coupled to the silicide contact surface of the first portion 222A of N-type semiconductor 222 of N-type SBD 204.

[0042] Each functional portion of SBD 204 or 208 corresponds to a corresponding portion in the transistor. Specifically, the first interconnect layer of the transistor corresponds to the metal layer of the SBD, and the transistor channel having threshold voltage enhanced doping corresponds to the semiconductor portion of the SBD (e.g., 222A and 242A), while the extended drain structure of the transistor is reconfigured to provide an ohmic contact with the semiconductor portion of the SBD. Although the functional portions of SBD 204 or 208 already exist in the CMOS manufacturing process, the CMOS technology node (e.g., 0.350 μm or lower) is implemented at least based on a self-aligned silicidation (SAS) photomask (i.e., a self-aligned silicide defining mask), and the SAS photomask is modified to integrate the SBD. In the CMOS manufacturing process, the SAS photomask is used to define one or more resistors and has a critical dimension that is the minimum feature size for defining one or more resistors. This critical dimension is larger than the critical dimensions of a set of other photomasks (e.g., those defining gates, metal contacts). The SAS photomask allows for relaxation of the tolerances for the feature widths and spacings to be printed on the semiconductor substrate. In an example, the critical dimension of the SAS photomask exceeds the critical line, such that the SAS photomask is labeled as non-critical. In various embodiments of the present application, to integrate the SBD in the CMOS manufacturing process, the SAS photomask is changed to a critical mask having a small critical dimension (e.g., less than a predefined critical threshold).

[0043] Each CMOS technology node has a most critical photomask, whose critical dimension is the smallest among all the photomasks used in that technology node, and the most critical photomask is the gate photomask that defines the gates of the CMOS transistors formed at that technology node. The SCMOS technology integrates LtSBD in the CMOS technology node and is applied to VLSI applications. The SCMOS technology constructs P-type and N-type LtSBDs, and each LtSBD occupies a smaller area than the corresponding diode-connected transistor. Each LtSBD is formed on the device active region (i.e., the diffusion trench), and the device active region is directly formed on the corresponding well according to the corresponding circuit function and electrical isolation requirements. Each LtSBD contains a barrier metal in contact with a lightly doped semiconductor surface with an impurity concentration of 10 15 -10 18 atoms per cubic centimeter. The lightly doped semiconductor surface is preferably doped with arsenic (As), phosphorus (P), or antimony (Sb), boron (B) according to a retrograde profile.

[0044] Examples of the barrier metals 224 and 244 include, but are not limited to, nickel silicide (NiSi), titanium silicide (TiSi), or cobalt silicide (CoSi 2 ). When the surface is lightly doped with impurity atoms of a metallic material (e.g., nickel, nickel silicide, cobalt, cobalt silicide, etc.) or coated with a thin layer of a metallic material, another material may be optionally applied as the barrier metal. Specifically, the barrier metal (e.g., Co, Ti) is combined with well doping and transistor threshold adjustment implantation, thereby forming nickel silicide (NiSi), titanium silicide (TiSi), or cobalt silicide (CoSi2). The LtSBD can be constructed with the desired electrical characteristics to operate with a set of MOSFETs in SCMOS circuit applications. Additionally, in some embodiments, each P-type or N-type SBD has a corresponding Schottky barrier height voltage within the Schottky barrier height voltage range. The corresponding Schottky barrier height voltage varies with the temperature of the corresponding SBD. In some embodiments, the SBDs are separated from adjacent SBDs or transistors by trenches. Optionally, ion implantation is applied to adjust the doping concentration of the diffusion trench or the device active region of the SBD, thereby suppressing the reverse bias current of the SBD to below the leakage current tolerance.

[0045] Figures 3A - 3FCross-sectional view of an integrated semiconductor device 200 processed in the front-end-of-line (FEOL) of a planar SCMOS manufacturing process 300, according to some embodiments. The integrated semiconductor device 200 includes at least one of a PMOS transistor 202, an NMOS transistor 206, a P-type SBD 208, and an N-type SBD 204, and is fabricated on a substrate 212 by means of a planar Schottky-based CMOS (SCMOS) manufacturing process 300. Optionally, the substrate 212 includes P-type bulk silicon (e.g., having a resistivity of 10 ohm·cm). Optionally, the substrate 212 includes silicon-on-insulator (SOI). Optionally, the substrate 212 has an epitaxial silicon layer formed on a buried oxide. The SCMOS manufacturing process 300 corresponds to a technology node (e.g., 0.250 μm, 0.180 μm, 22 nm, or 20 nm technology node). The integrated semiconductor device 200 includes VLSI logic, memory, digital circuits, analog circuits, or a combination thereof. Additionally, the SCMOS manufacturing process 300 includes silicidation of the source regions, drain regions, and gates of both the PMOS device 202 and the NMOS device 206. In some embodiments, the silicidation occurs in continuous wire segments coupled to different portions of the PMOS device 202 and the NMOS device 206. The silicidation defines a plurality of silicided regions and is achieved by means of an SAS photomask and associated lithography, patterning, or material removal steps. Such a processing module is referred to as self-aligned silicidation (SAS) or self-aligned salicidation. The SAS photomask is also referred to as a resistor protection oxide (RPO) photomask or a self-aligned silicidation barrier (SASB) photomask.

[0046] Reference Figure 3A, the substrate 212 is implanted to form a first N-well 216, a first P-well 218, a second P-well 236, and a second N-well 238. In some embodiments, two separate well photomasks are applied to define P-wells and N-wells implanted with different types of dopants at different doping concentrations, respectively. In some embodiments, the substrate 212 is P-type, and at least one of the first P-well 218 and the second P-well 236 is formed within the corresponding N-well 216 or 238. Alternatively, in some embodiments, the first P-well 218 is adjacent to the first N-well 216, and the second N-well 238 is adjacent to the second P-well 236. A plurality of spacers 226 are formed in the P-wells 218 and 236 and the N-wells 216 and 238, and each spacer 226 includes a field oxide region or a trench. Optionally, a spacer 226A is formed in the connection region between the P-well and the N-well. Optionally, a spacer 226B is used at the edge of the N-well 216 or 238 or the P-well 218 or 236. Optionally, a spacer 226C is used within one of the P-wells 218 and 236 and the N-wells 216 and 238 to separate two electrical structures formed therein. Thus, the device active region is defined by the P-wells 218 and 236, the N-wells 216 and 238, and the spacers 226.

[0047] Reference Figure 3B , a threshold adjustment ion implant is applied to the P-wells 218 and 236 and the N-wells 216 and 238. Specifically, in response to a first threshold adjustment ion implant, when the first portion 242A of the P-type semiconductor 242 of the P-type SBD 208, the doping concentration of the P-type channel 202C of the PMOS transistor 202 is simultaneously established in the first N-well 216. In some cases, the first P-well 218 or the second P-well 236 has a well contact 228 that provides a low resistance path for the P-well 218 or 236, and the well contact 228 has a first P-type portion 228A formed simultaneously with the P-type channel 202C of the PMOS transistor 202 and the first portion 242A of the P-type semiconductor 242 of the P-type SBD 208. Additionally, in some embodiments, in response to a second threshold adjustment ion implant, when the first portion 222A of the N-type semiconductor 222 of the N-type SBD 204, the doping concentration of the N-type channel 206C of the NMOS transistor 206 is simultaneously established in the second P-well 236. In some cases, the first N-well 216 or the second N-well 218 has a well contact 248 as a low resistance path, and the well contact 248 has a first N-type portion 248A formed simultaneously with the N-type channel 206C of the NMOS transistor 206 and the first portion 222A of the N-type semiconductor 222 of the N-type SBD 204.

[0048] In some embodiments, PMOS transistor 202 is a first PMOS transistor. A second PMOS transistor is configured to operate with a second P-type channel. The second P-type channel has an alternative doping concentration different from the doping concentration of P-type channel 202C of the first PMOS transistor 202, such that a first threshold voltage of the first PMOS transistor 202 is different from a second threshold voltage of the second PMOS transistor. The alternative doping concentration of the second P-type channel of the second PMOS transistor is established separately from the P-type channel 202C of the first PMOS transistor 202 and a first portion 242A of the P-type semiconductor 242 of the P-type SBD 208.

[0049] In some embodiments, NMOS transistor 206 is a first NMOS transistor. A second NMOS transistor is configured to operate with a second N-type channel. The second N-type channel has an alternative doping concentration different from the doping concentration of N-type channel 206C of the first NMOS transistor 206, such that a third threshold voltage of the first NMOS transistor 206 is different from a fourth threshold voltage of the second NMOS transistor. The alternative doping concentration of the second N-type channel of the second NMOS transistor is established separately from the N-type channel 206C of the first NMOS transistor 206 and a first portion 222A of the N-type semiconductor 222 of the N-type SBD 204.

[0050] Reference Figure 3C , clean the surface of the substrate 212 and form a gate oxide layer 308 for the P-type transistor 202 and the N-type transistor 206 on the substrate 212. In some embodiments, more than one gate oxide layer 308 is applied to define gate oxides having different thicknesses for different transistors. For example, the integrated semiconductor device 300 has two different gate oxide thicknesses, and each transistor 202 or 206 has a corresponding one of the two gate oxide thicknesses. Transistors of the core circuit have a first gate oxide thickness, and transistors of the input / output circuit have a second gate oxide thickness greater than the first gate oxide thickness. After forming the gate oxide layer 308, a gate material (e.g., metal or polysilicon) layer 310 is deposited on the gate oxide layer 308 and, optionally, patterned together with the gate oxide layer 308. Thereby, the gate layer 310 is patterned into the gate 202G of the PMOS transistor 202, the gate 206G of the NMOS transistor 206, and a plurality of spacer gates 312 formed on top of the spacer 226. In some embodiments, after depositing or patterning the gate oxide layer 308 and the gate layer 310, Figure 3Ba subset of the threshold adjustment ion implant, i.e., the subset of the threshold adjustment ion implant penetrates the gate oxide layer and the gate layer 310 to reach one or more of the following: the P-type channel 202C, the N-type channel 206C, the first part 222A of the N-type semiconductor 222, and the first part 242A of the P-type semiconductor 242.

[0051] Reference Figure 3D , a first lightly doped source and drain implant (P-type) is applied to form the lightly doped regions of the source structure 202S and the extended drain structure 202D of the PMOS transistor 202. The lightly doped region of the second part 242B of the P-type semiconductor 242 of the P-type SBD 208 is formed via the same first lightly doped source and drain implant, and the lightly doped region of the well contact 228 of the first P-well 218 is also formed via the same first lightly doped source and drain implant. A second lightly doped source and drain implant (N-type) is applied to form the lightly doped regions of the source structure 206S and the extended drain structure 206D of the NMOS transistor 206. The lightly doped region of the second part 222B of the N-type semiconductor 222 of the N-type SBD 204 is formed via the same second lightly doped source and drain implant, and the lightly doped region of the well contact 248 of the second N-well 238 is also formed via the same second lightly doped source and drain implant.

[0052] Reference Figure 3E , a first heavily doped source and drain implant (P-type) is applied to form the heavily doped regions of the source structure 202S and the extended drain structure 202D of the PMOS transistor 202. The heavily doped region of the second part 242B of the P-type semiconductor 242 of the P-type SBD 208 is formed via the same first heavily doped source and drain implant, and the heavily doped region of the well contact 228 of the first P-well 218 is also formed via the same first heavily doped source and drain implant. A second heavily doped source and drain implant (N-type) is applied to form the heavily doped regions of the source structure 206S and the extended drain structure 206D of the NMOS transistor 206. The heavily doped region of the second part 222B of the N-type semiconductor 222 of the N-type SBD 204 is formed via the same second heavily doped source and drain implant, and the heavily doped region of the well contact 248 of the second N-well 238 is also formed via the same second heavily doped source and drain implant. Each of these heavily doped regions is located within the corresponding lightly doped region of the same device structure and is integrated with the lightly doped region.

[0053] Reference Figure 3F , silicon nitride (Si 3 N 4 ) hard mask (RPO / SASB) is used to block silicidation. Via Si 3 N 4The hard mask exposes portions of the surfaces of the gate, source, and drain structures of transistors 202 and 206, and also via Si 3 N 4 The hard mask exposes portions of the surfaces of the first and second portions of SBDs 204 and 208. In Si 3 N 4 A barrier metal 224 or 244 (e.g., Pt, Ti, or Co) is deposited on the hard mask and the barrier metal is processed by heating to induce silicidation, while forming low-ohmic contacts on the exposed portions of the surfaces of the gate, source, and drain structures of transistors 202 and 206 and the first and second portions of SBDs 204 and 208. In some embodiments, via Si 3 N 4 The hard mask exposes additional resistor regions, and the resistor regions undergo self-aligned silicidation to form resistors.

[0054] In some embodiments, the silicide-defining mask has a predefined critical dimension CD. According to the silicide-defining mask, a first silicide contact surface 314 is defined on a first portion 242A of the P-type semiconductor 242 of the P-type SBD 208, and a second silicide contact surface 316 is defined on a second portion 242B of the P-type semiconductor 242. The first silicide contact surface 314 is separated from the second portion 242B of the P-type semiconductor 242 of the P-type SBD 208 by a lateral distance l 1 . The first silicide contact surface 314 is separated from the second silicide contact surface 316 by a lateral distance l 2 . The lateral distance l 1 and l 2 are greater than the predefined critical dimension CD. In some embodiments, according to the silicide-defining mask, a first silicide contact surface 318 is defined on a first portion 222A of the N-type semiconductor 222 of the N-type SBD 204, and a second silicide contact surface 320 is defined on a second portion 222B of the N-type semiconductor 222 of the N-type SBD 204. The first silicide contact surface 318 is separated from the second portion 222B of the N-type semiconductor 222 of the N-type SBD 204 by a lateral distance l 3 . The first silicide contact surface 318 is separated from the second silicide contact surface 320 by a lateral distance l 4 . The lateral distance l 3 and l 4 are greater than the predefined critical dimension CD. Additionally, in some embodiments not shown, according to the silicide-defining mask, a silicide resistor is defined on the substrate 212. The silicide resistor is different from the extended drain structure 202D of the PMOS transistor 202 and the first and second portions 242A and 242B of the P-type semiconductor 242 of the P-type SBD 208. The lateral distance l1 -l 4 It is controlled by a predefined critical dimension CD, and the silicide-defined mask is a critical mask for the planar SCMOS manufacturing process 300.

[0055] After the FEOL of the planar SCMOS manufacturing process 300, a low-dielectric SiO-based dielectric layer is deposited and planarized, for example, by chemical mechanical polishing (CMP). 2 Contacts are opened in the dielectric layer, and metal layers of the interconnects are formed to access the gates, source, and drain structures of transistors 202 and 206 and the second portions and barrier metals of SBDs 204 and 208 via the opened contacts. The metal layers of the interconnects are optionally made of aluminum (Al) or copper (Cu). In some embodiments, a dual damascene process is applied, for example, at the 0.18 μm or 0.13 μm level.

[0056] Figure 4A and 4B are two different cross-sectional views 410 and 420 of another exemplary integrated semiconductor device 200 including an NMOS transistor 206 and an N-type SBD 204 according to some embodiments. Figure 4C and 4D are two different cross-sectional views 440 and 450 of another exemplary integrated semiconductor device 230 including a PMOS transistor 202 and a P-type SBD 208 according to some embodiments. The cross-sectional views 410 and 420 correspond to two vertical lines on the top surface of the corresponding substrate 212, and the cross-sectional views 440 and 450 also correspond to two vertical lines on the top surface of the corresponding substrate. The integrated semiconductor device 200 integrates the NMOS transistor 206 and the N-type SBD 204 on the substrate 212, and the integrated semiconductor device 230 integrates the PMOS transistor 202 and the P-type SBD 208 on the substrate 214.

[0057] Refer to Figure 4A and 4B, the integrated semiconductor device 200 is planar. The N-type SBD 204 is formed on the substrate 214 and is formed by bonding an N-type semiconductor 222 and a barrier metal 224 (i.e., the anode). The first doping concentration of the N-type channel 206C of the NMOS transistor 206 is substantially the same as the first doping concentration of the first portion 222A of the N-type semiconductor 222 of the N-type SBD 204. The doping profile of the extended drain structure 206D of the NMOS transistor 206 is substantially the same as the doping profile of the second portion 222B of the N-type semiconductor 222 of the N-type SBD 204. Each of the extended drain structure 206D of the NMOS transistor 206 and the first portion 222A and the second portion 222B of the N-type semiconductor 222 has a different silicide contact surface. During the planar SCMOS manufacturing process, for example, by means of one or more ion implantation operations, the first doping concentration of the N-type channel 206C of the NMOS transistor 206 is established simultaneously with the formation of the first portion 222A of the N-type semiconductor 222 of the N-type SBD 204. For example, using the same ion implantation or diffusion operation, the extended drain structure 206D of the NMOS transistor 206 is formed simultaneously with the second portion 222B of the N-type semiconductor 222 of the N-type SBD 204. The different silicide contact surfaces of the extended drain structure 206D of the NMOS transistor 206 and the first portion 222A and the second portion 222B of the N-type semiconductor 222 are patterned and formed simultaneously. In this example, the NMOS transistor 206 and the N-type SBD 204 are integrated in the first P-well 218.

[0058] Reference Figure 4C and 4D, the integrated semiconductor device 230 is planar. The P-type SBD 208 is formed on the substrate 214 and is formed by bonding a P-type semiconductor 242 and a blocking metal 244 (i.e., the cathode). The first doping concentration of the P-type channel 202C of the PMOS transistor 202 is substantially the same as the first doping concentration of the first portion 242A of the P-type semiconductor 242 of the P-type SBD 208. The doping profile of the extended drain structure 202D of the PMOS transistor 202 is substantially the same as the doping profile of the second portion 242B of the P-type semiconductor 242 of the P-type SBD 208. Each of the extended drain structure 202D of the PMOS transistor 202 and the first portion 242A and the second portion 242B of the P-type semiconductor 242 has a different silicide contact surface. During the planar SCMOS manufacturing process, for example, by means of one or more ion implantation operations, the doping concentration of the P-type channel 202C of the PMOS transistor 202 is established simultaneously with the formation of the first portion 242A of the P-type semiconductor 242 of the P-type SBD 208. For example, using the same ion implantation or diffusion operation, the extended drain structure 202D of the PMOS transistor 202 is formed simultaneously with the second portion 242B of the P-type semiconductor 242 of the P-type SBD 208. The different silicide contact surfaces of the extended drain structure 202D of the PMOS transistor 202 and the first portion 242A and the second portion 242B of the P-type semiconductor 242 are patterned and formed simultaneously. In this example, the NMOS transistor 206 and the N-type SBD 204 are integrated in the first N-well 216.

[0059] Figures 5A - 5F FIG. 4 is a cross-sectional view of another exemplary integrated semiconductor device 200 processed in the FEOL of a planar Schottky CMOS manufacturing process 500 according to some embodiments. The integrated semiconductor device 200 includes at least one of a PMOS transistor 202, an NMOS transistor 206, a P-type SBD 208, and an N-type SBD 204, and is fabricated on a substrate 212 by means of a planar Schottky CMOS (SCMOS) manufacturing process 500. The SCMOS manufacturing process 500 includes simultaneously siliciding the contact surfaces of the source regions, drain regions, and gates of both the NMOS device 206 and the PMOS device 202, and siliciding the contact surfaces of the semiconductors of the N-type SBD 204 and the P-type SBD 208. In some embodiments, the silicidation occurs in continuous wire segments coupled to different portions of the NMOS device 206 and the PMOS device 202. The silicidation defines a plurality of silicided regions and is achieved through a SAS photomask and associated lithography, patterning, or material removal steps. Such a processing module is referred to as self-aligned silicidation (SAS) or self-aligned salicidation.

[0060] Reference Figure 5A, the substrate 212 is implanted to form an N-well 216 and a P-well 218. In some embodiments, two separate well photomasks are applied to define the P-well 218 and the N-well 216 implanted with different types of dopants at different doping concentrations, respectively. In some embodiments, the substrate 212 is P-type, and the P-well 218 is formed within the N-well 216. Alternatively, in some embodiments, the P-well 218 is separated from the N-well 216. A plurality of spacers 226 are formed between the P-well 218 and the N-well 216, within the P-well 218, and / or within the N-well 216. Each spacer 226 includes a field oxide region or a trench. Optionally, the spacer 226 is formed in the connection region between the P-well 218 and the N-well 216. Optionally, the spacer 226B is used at the edge of the N-well 216 or the P-well 218. Optionally, the spacer 226 is used within one of the N-well 216 or the P-well 218 to separate two electrical structures formed therein. Thus, the device active regions are defined by means of the N-well 216, the P-well 218, and the spacer 226.

[0061] Reference Figure 5B , a threshold adjustment ion implant is applied in the P-well 218 and the N-well 216. Specifically, in response to a first threshold adjustment ion implant, when forming a first portion 222A of the N-type semiconductor 222 of the N-type SBD 204, the doping concentration of the N-type channel 206C of the NMOS transistor 206 is simultaneously established in the P-well 218. A second portion 222B of the N-type semiconductor 222 of the N-type SBD 204 is connected to the first portion 222A and is formed simultaneously with the extended drain structure 206D of the NMOS transistor 206. Optionally, the NMOS transistor 206 further has an extended source structure 206S formed simultaneously with the extended drain structure 206D and the second portion 222B. In some embodiments, another NMOS device 406 is disposed adjacent to the N-type SBD 204, and the second portion 222B is shared with the NMOS device 406, i.e., used as the extended source or drain structure of the NMOS device 406. In an example, the NMOS device 406 is the same device as the NMOS device 206.

[0062] In some embodiments, NMOS transistor 206 is a first NMOS transistor. The integrated semiconductor device 200 includes one or more second NMOS transistors, each second NMOS transistor being configured to operate with a second N-type channel. The second N-type channel has an alternative doping concentration different from the doping concentration of the N-type channel of the first NMOS transistor 206, such that a third threshold voltage of the first NMOS transistor 206 is different from a fourth threshold voltage of the second NMOS transistor. The alternative doping concentration of the second N-type channel of the second NMOS transistor is established separately from the N-type channel 206C of the first NMOS transistor 206 and a first portion 222A of the N-type semiconductor 222 of the N-type SBD 204.

[0063] In response to a second threshold adjustment ion implant, the doping concentration of the P-type channel 202C of the PMOS transistor 202 is established in the N-well 216 simultaneously when forming a first portion 242A of the P-type semiconductor 242 of the P-type SBD 208. A second portion 242B is connected to the first portion 242A of the P-type semiconductor 242 of the P-type SBD 208 and is formed simultaneously with the extended drain structure 202D of the PMOS transistor 202. Optionally, the PMOS transistor 202 also has an extended source structure 202S formed simultaneously with the extended drain structure 202D and the second portion 242B.

[0064] In some embodiments, the PMOS device 402 is disposed adjacent to the P-type SBD 208, and the second portion 242B is shared with the PMOS device 402, i.e., serves as an extended source or drain structure of the PMOS device 402. In an example, the PMOS device 402 is the same device as the PMOS device 202. Additionally, in some embodiments, the P-type SBD 208 is applied in the NAND logic gate 100 for receiving input A i , and the PMOS device 402 corresponds to the PMOS transistor 110 or 112B. A second portion 242B of the P-type semiconductor 242 (i.e., the anode) of the P-type SBD 208 shares a physical structure with the extended source or drain structure of the PMOS transistor 110 or 112B.

[0065] In some embodiments, PMOS transistor 202 is a first PMOS transistor. Integrated semiconductor device 200 includes one or more second PMOS transistors, each second PMOS transistor being configured to operate with a second P-type channel having an alternative doping concentration different from the doping concentration of P-type channel 202C of PMOS transistor 202. The threshold voltage of PMOS transistor 202 is different from the threshold voltages of the one or more second PMOS transistors. The alternative doping concentration of the second P-type channel of the second PMOS transistor is established separately from P-type channel 202C of first PMOS transistor 202 and from a first portion 242A of P-type semiconductor 242 of P-type SBD 208.

[0066] Reference Figure 5C , the surface of clean substrate 212 is cleaned, and a gate oxide layer 508 for P-type and N-type transistors is formed on substrate 212. In some embodiments, more than one gate oxide layer 508 is applied to define gate oxides having different thicknesses for different transistors. For example, integrated semiconductor device 200 has two different gate oxide thicknesses, and each transistor 206 or 202 has a respective one selected from these two gate oxide thicknesses. The transistors of the core circuit have a first gate oxide thickness, and the transistors of the input / output circuit have a second gate oxide thickness greater than the first gate oxide thickness. After forming gate oxide layer 508, a gate material (e.g., metal or polysilicon) layer 510 is deposited on gate oxide layer 508, and optionally the gate material layer is patterned together with gate oxide layer 508. Thereby, gate layer 510 is patterned into gate 202G of PMOS transistor 202, gate 206G of NMOS transistor 206, and a plurality of spacer gates 512 formed on top of spacer 226. In some embodiments, a subset of the threshold adjustment ion implants of Figure 5B is applied after depositing or patterning gate oxide layer 508 and gate layer 510, i.e., the subset of threshold adjustment ion implants penetrates through gate oxide layer and gate layer 510 to reach one or more of the following: P-type channel 202C, N-type channel 206C, a first portion 222A of N-type semiconductor 222, and a first portion 242A of P-type semiconductor 242.

[0067] Reference Figure 5D, a first lightly doped source and drain implant (P-type) is applied to form lightly doped regions of a source structure 202S and an extended drain structure 202D of a PMOS transistor 202. A lightly doped region of a second portion 242B of a P-type semiconductor 242 of a P-type SBD 208 is formed via the same first lightly doped source and drain implant, and a lightly doped region of a well contact of a P-well 218 is also formed via the same first lightly doped source and drain implant. A second lightly doped source and drain implant (N-type) is applied to form lightly doped regions of a source structure 206S and an extended drain structure 206D of an NMOS transistor 206. A lightly doped region of a second portion 222B of an N-type semiconductor 222 of an N-type SBD 204 is formed via the same second lightly doped source and drain implant, and a lightly doped region of a well contact of an N-well 216 is also formed via the same second lightly doped source and drain implant.

[0068] Reference Figure 5E , a first heavily doped source and drain implant (P-type) is applied to form heavily doped regions of a source structure 202S and an extended drain structure 202D of a PMOS transistor 202. A heavily doped region of a second portion 242B of a P-type semiconductor 242 of a P-type SBD 208 is formed via the same first heavily doped source and drain implant, and a heavily doped region of a well contact of a P-well 218 is also formed via the same first heavily doped source and drain implant. A second heavily doped source and drain implant (N-type) is applied to form heavily doped regions of a source structure 206S and an extended drain structure 206D of an NMOS transistor 206. A heavily doped region of a second portion 222B of an N-type semiconductor 222 of an N-type SBD 204 is formed via the same second heavily doped source and drain implant, and a heavily doped region of a well contact of an N-well 216 is also formed via the same second heavily doped source and drain implant. Each of these heavily doped regions is located within a corresponding lightly doped region of the same device structure and is integrated with the lightly doped region.

[0069] Reference Figures 5A - 5E , impurity doping techniques include ion implanting ionized atoms into a target region and in-situ physically / chemically depositing a thin material layer containing impurity atoms. In some cases, annealing is performed after ion implantation or in-situ deposition, i.e., a controlled heating cycle at an elevated temperature, to drive the impurity atoms to a certain depth in the target and activate the local crystal structure. By means of these, specific electronic properties of semiconductor devices are enabled individually and in dedicated groups, such that the entire IC can be tested and the IC can be qualified as a product with reliable performance under a range of operating conditions and application environments.

[0070] Reference Figure 5F , silicon nitride (Si 3 N 4)A hard mask (RPO / SASB) is used to block silicidation. Via Si 3 N 4 The hard mask exposes portions of the surfaces of the gate, source, and drain structures of transistors 202 and 206, also via Si 3 N 4 The hard mask exposes portions of the surfaces of the first and second portions of SBDs 204 and 208. In Si 3 N 4 A barrier metal (e.g., Pt, Ti, or Co) is deposited on the hard mask and the barrier metal is heat-treated to induce silicidation, while forming low-ohmic contacts on the exposed portions of the surfaces of the gate, source, and drain structures of transistors 206 and 202 and the first and second portions of SBDs 204 and 208. In some embodiments, via Si 3 N 4 The hard mask exposes additional resistor regions, and self-aligned silicidation occurs in the resistor regions to form resistors.

[0071] In some embodiments, the silicide-defining mask has a predefined critical dimension CD. According to the silicide-defining mask, a first silicide contact surface 514 is defined on a first portion 242A of the P-type semiconductor 242 of the P-type SBD 208, and a second silicide contact surface 516 is defined on a second portion 242B of the P-type semiconductor 242. The first silicide contact surface 514 is separated from the second portion 242B of the P-type semiconductor 242 of the P-type SBD 208 by a lateral distance l 1 . The first silicide contact surface 514 is separated from the second silicide contact surface 516 by a lateral distance l 2 . The lateral distance l 1 and l 2 are greater than the predefined critical dimension CD. In some embodiments, according to the silicide-defining mask, a first silicide contact surface 518 is defined on a first portion 222A of the N-type semiconductor 222 of the N-type SBD 204, and a second silicide contact surface 520 is defined on a second portion 222B of the N-type semiconductor 222 of the N-type SBD 204. The first silicide contact surface 518 is separated from the second portion 222B of the N-type semiconductor 222 of the N-type SBD 204 by a lateral distance l 3 . The first silicide contact surface 518 is separated from the second silicide contact surface 520 by a lateral distance l 4 . The lateral distance l 3 and l 4Greater than a predefined critical dimension CD. Additionally, in some embodiments not shown, a silicide resistor is defined on the substrate 212 according to a silicide definition mask. The silicide resistor is different from the extended drain structure 202D of the PMOS transistor 202 and the first part 242A and the second part 242B of the P-type semiconductor 242 of the P-type SBD 208. The lateral distance l 1 -l 4 is controlled by the predefined critical dimension CD, and the silicide definition mask is a critical mask of the planar SCMOS manufacturing process 500.

[0072] After the FEOL of the planar Schottky CMOS manufacturing process 500, a low dielectric constant SiO 2 -based dielectric layer is deposited and planarized, for example, by chemical mechanical polishing (CMP). Contacts are opened in the dielectric layer, and a metal layer of the interconnect is formed to access the gates, source and drain structures of the transistors 202 and 206 and the second parts and barrier metals of the SBDs 204 and 208 via the opened contacts. The metal layer of the interconnect is optionally made of aluminum (Al) or copper (Cu). In some embodiments, a dual damascene process is applied, for example, at the 0.18 μm or 0.13 μm level.

[0073] Figure 6A and 6B are two different cross-sectional views 610 and 620 of the integrated semiconductor device 200 including CMOS transistors and complementary SBDs and processed until before the FEOL is completed according to some embodiments. The cross-sectional views 610 and 620 correspond to different parts of the substrate 212. In an example, the substrate 212 includes P-type bulk silicon (for example, having a resistivity of 10 ohm·cm). In another example, the substrate 212 includes SOI, including an epitaxial silicon layer formed on a buried oxide. Referring to Figure 6A , the integrated planar semiconductor device 200 includes at least an NMOS transistor 206 and an N-type SBD 204 formed on the substrate 212. The N-type SBD 204 is formed by bonding an N-type semiconductor 222 and a barrier metal 224. The first doping concentration of the first part 222A of the N-type semiconductor 222 of the N-type SBD 204 is substantially the same as the first doping concentration of the N-type channel 206C of the NMOS transistor 206. The doping profile of the extended drain structure 206D of the NMOS transistor is substantially the same as the doping profile of the second part 222B of the N-type semiconductor 222. Referring to Figure 5F, each of the extended drain structure 206D of the NMOS transistor 206 and the first portion 222A and the second portion 222B of the N-type semiconductor 222 has a different silicide contact surface 522, 518, or 520. In some embodiments, the first portion 222A of the N-type semiconductor 222 has a first silicide contact surface 518, and the second portion 222B of the N-type semiconductor has a second silicide contact surface 520 that is laterally separated from the first silicide contact surface 518 by a lateral distance l 4 ( Figure 3F and 5F ). The lateral distance l 4 is greater than a predefined critical dimension CD of the silicide definition mask.

[0074] In some embodiments not shown, a silicide resistor is formed on the substrate 212. The silicide resistor is different from the extended drain structure 206D of the NMOS transistor 206 and the first portion 222A and the second portion 222B of the N-type semiconductor 222. The size of the silicide resistor is much larger than the critical dimension CD of the silicide definition mask and is thus not limited by it. The source structure 206S and the drain structure 206D of the NMOS transistor 206 are formed via self-aligned silicidation without being limited by the critical dimension CD of the silicide definition mask. Therefore, based on the lateral distance l 3 or l 4 of the N-type SBD 204, the predefined critical dimension CD of the silicide definition mask is controlled and defined, which makes the non-critical silicide definition mask in the CMOS manufacturing process a critical mask in the SCMOS manufacturing process for integrating MOS transistors and SBDs.

[0075] In Figure 6A the example shown, both the N-type SBD 204 and the NMOS transistor 206 are formed in the P-well 218. Alternatively, in an example (e.g., in Figures 2A - 2D ), the N-type SBD 204 is located in the first P-well 218, and the NMOS transistor 206 is formed in a second P-well 236 different from the first P-well 218. Additionally, in some embodiments, the P-type SBD 208 is formed in the N-well 238 and is formed by bonding a P-type semiconductor 242 and a barrier metal 244. The N-well 238 is isolated from at least one of the first P-well 218 and the second P-well 236 by a field oxide 226A.

[0076] In some embodiments, NMOS transistor 206 includes a first NMOS transistor. Integrated semiconductor device 200 further includes a second NMOS transistor configured to operate with a second N-type channel. The second N-type channel has an alternative doping concentration different from the first doping concentration such that a first threshold voltage of the first NMOS transistor 206 is different from a second threshold voltage of the second NMOS transistor. By these means, multiple thresholds are available for forming NMOS transistors, and multiple threshold doping concentrations can be selected to form the N-type semiconductor 222 of the N-type SBD 204.

[0077] In some embodiments, a second portion 222B of the N-type semiconductor 222 includes a second region (e.g., Figure 5D a lightly doped region in Figure 5E ), in which a third region (e.g.,

[0078] a heavily doped region in Figure 2B is formed and enclosed. According to the doping profile, the second region has a second doping concentration, and the third region has a third doping concentration greater than the second doping concentration. The second doping concentration of the second portion 222B is greater than the first doping concentration of the first portion 222A.

[0079] In some embodiments, PMOS transistor 202 is formed in a first N-well 216 and is configured to operate with a P-type channel 202C. Additionally, in some embodiments, N-type SBD 204 is located in a P-well (e.g.,

[0080] Figure 2B 218 in

[0079] that has a P-well access region 228. The doping concentration of the P-type channel of PMOS transistor 202 is equal to the doping concentration of a first portion 228A of the P-well access region 228, and the doping profile of the extended drain structure of PMOS transistor 202 matches the doping profile of a second P-type portion 228B of the P-well access region 228. The second P-type portion 228B of the P-well access region 228 is formed in the first portion 228A of the P-well access region 228 and has a different silicide contact surface. The first P-type portion 228A and the second P-type portion 228B of the P-well access region 228 together provide a low-resistance path for the P-well 218.

[0080] In some embodiments, integrated semiconductor device 200 further includes a P-type SBD 208 formed in a second N-well. The P-type SBD 208 is formed by bonding a P-type semiconductor 242 and a barrier metal 244. The first N-well and the second N-well are merged into a single N-well 216. Alternatively, in some embodiments, integrated semiconductor device 200 further includes a P-type SBD 208 formed in a second N-well. The first N-well is different from the second N-well.

[0080] In some embodiments, the NMOS transistor 206 has a drain path 206DA coupled to a silicide contact surface 522 of an extended drain structure 206D of the NMOS transistor 206. The N-type SBD 204 has a cathode path 222C coupled to a silicide contact surface 520 of a second portion 222B of the N-type semiconductor 222. The drain path 206DA, the cathode path 222C, and the barrier metal 224 are formed of a first metal layer.

[0081] In some embodiments, the extended drain structure 206D of the NMOS device 206 overlaps with a second portion 222B of the N-type semiconductor 222 of the N-type SBD 204. The NMOS 206 is directly coupled to the N-type SBD 204.

[0082] From a different perspective, referring to Figure 6B , the integrated planar semiconductor device 200 includes a PMOS transistor 202 and a P-type SBD 208. The PMOS transistor 202 and the P-type SBD 208 are formed on a substrate 212. The P-type SBD 208 joins a P-type semiconductor 242 and a barrier metal 244 (e.g., a metal cathode). A first doping concentration of a P-type channel 202C of the PMOS transistor 202 is substantially the same as a first doping concentration of a first portion 242A of the P-type semiconductor 242 of the P-type SBD 208. A doping profile of an extended drain structure 202D of the PMOS transistor 202C is substantially the same as a doping profile of a second portion 242B of the P-type semiconductor 242. Each of the extended drain structure 202D of the PMOS transistor 202C and the first portion 242A and the second portion 242B of the P-type semiconductor 242 has a different silicide contact surface 524, 514, or 516.

[0083] In some embodiments, the first portion 242A of the P-type semiconductor 242 has a first silicide contact surface 514, and the second portion 242B of the P-type semiconductor 552 has a second silicide contact surface 516 separated from the first silicide contact surface 514 by a lateral distance l 2 . The lateral distance l 2 is greater than a predefined critical dimension CD of a silicide definition mask.

[0084] In some embodiments, the integrated semiconductor device 200 includes a silicide resistor that is formed on a substrate 212 and is different from the extended drain structure 202D of the PMOS transistor 202 and the first portion 242A and the second portion 242B of the P-type semiconductor 242. The size of the silicide resistor is much larger than the critical dimension CD of the silicide definition mask and is thus not limited by it. The source structure 202S and the drain structure 202D of the PMOS transistor 202 are formed via self-aligned silicidation without being limited by the critical dimension CD of the silicide definition mask. Thus, based on the lateral distance l 1 or l 2 to control and define a predefined critical dimension CD of the silicide definition mask, which makes the non-critical silicide definition mask in the CMOS manufacturing process a critical mask in the SCMOS manufacturing process for integrating MOS transistors and SBDs.

[0085] In some embodiments, the PMOS transistor 202 includes a first PMOS transistor. The integrated semiconductor device 200 includes a second PMOS transistor configured to operate with a second P-type channel. The second P-type channel has an alternative doping concentration different from the first doping concentration such that the first threshold voltage of the first PMOS transistor 202 is different from the second threshold voltage of the second PMOS transistor.

[0086] In some embodiments, the second portion 242B of the P-type semiconductor 242 includes a second region (e.g., a lightly doped region) in which a third region (e.g., a heavily doped region) is formed and enclosed. According to the doping profile, the second region has a second doping concentration, and the third region has a third doping concentration greater than the second doping concentration. The second doping concentration of the second region is greater than the first doping concentration of the first portion 242A.

[0087] In Figures 4A - 4D some embodiments shown, both the P-type SBD 208 and the PMOS transistor 202 are formed in the N-well 216. Alternatively, in Figures 2A - 2D some embodiments shown, the P-type SBD 208 is located in a first N-well 238, and the PMOS transistor 202 is formed in a second N-well 216 different from the first N-well 238. Additionally, in some embodiments, the integrated semiconductor device 200 further includes an N-type SBD 204 formed in a P-well 218 and formed by bonding an N-type semiconductor 222 and a barrier metal 224, wherein the P-well 218 is isolated from at least one of the first N-well 238 and the second N-well 216 by a field oxide 226A.

[0088] In some embodiments, NMOS transistor 206 is formed in the first P-well 218 and is configured to operate with the N-type channel 206C.

[0089] In some embodiments, referring to Figures 2A - 2D , the P-type SBD 208 is located in the N-well 238 having the N-well access region 248. The doping concentration of the N-type channel 202C of the NMOS transistor 202 is equal to the doping concentration of the first N-type portion 248A of the N-well access region 248. The doping profile of the extended drain structure 202D of the NMOS transistor 202 matches the doping profile of the second portion 248B of the N-well access region 248. The second portion 248B of the N-well access region 248 is formed in the first N-type portion 248A of the N-well access region 248 and has a different silicide contact surface. The first N-type portion 248A and the second N-type portion 248B of the N-well access region 248 together provide a low-resistance path for the N-well 238.

[0090] In some embodiments, referring to Figures 4A - 4D , the N-type SBD 204 is formed in the second P-well and is formed by bonding the N-type semiconductor 222 and the barrier metal 224. The first P-well 218 and the second P-well are merged into a single P-well 218. Alternatively, in some embodiments, referring to Figures 2A - 2D , the N-type SBD is formed in the second P-well 236 and is formed by bonding the N-type semiconductor 222 and the barrier metal 244. The first P-well 218 is different from the second P-well 236.

[0091] In some embodiments, the extended drain structure 202D of the PMOS device 202 overlaps with the second portion 242B of the P-type semiconductor 242 of the P-type SBD 208. The drain of the PMOS 202 serves as the anode of the P-type SBD 208. The PMOS 202 corresponds to one of the PMOS transistors 110 and 112B, and the P-type SBD 208 corresponds to Figure 1A one of the SBDs 102-106 in

[0092] Figure 7A and 7BTwo different cross-sectional views 710 and 720 of an integrated semiconductor device 200 according to some embodiments, including CMOS transistors 202 and 206 and complementary SBDs 204 and 208 and processed in a back-end-of-line (BEOL) process to a first metal layer. After FEOL, the surfaces of different silicide contact surfaces of the gate 202G, source structure 202S, and drain structure 202D of the PMOS transistor 202 are exposed, and the surfaces of different silicide contact surfaces of the gate 206G, source structure 206S, and drain structure 206D of the NMOS transistor 206 are also exposed. The surface of the barrier metal 244 of the P-type SBD 208 and the second portion 242B of the P-type semiconductor 242 are exposed, and the surface of the barrier metal 224 of the N-type SBD 204 and the second portion 222B of the N-type semiconductor 222 are also exposed. A first metal layer is deposited and multiple vias are provided to the exposed surfaces of different silicide contact surfaces. The first metal layer is a combination of a barrier metal layer (e.g., nickel, nickel silicide, cobalt, cobalt silicide, etc.) and a conductive metal layer (e.g., copper). The barrier metal layer provides the barrier metals 224 and 244 for the N-type SBD 204 and the P-type SBD 208, and provides contact enhancement metals on the respective different silicide contact surfaces of the PMOS transistor 202, the N-type SBD 204, the NMOS transistor 206, and the P-type SBD 208. The conductive metal layer is patterned into a first interconnect layer and provides vias to the exposed portions of the respective different silicide contact surfaces of the PMOS transistor 202, the N-type SBD 204, the NMOS transistor 206, and the P-type SBD 208.

[0093] In some embodiments, referring to Figure 7A , the NMOS transistor 206 has a drain via 206DA coupled to the silicide contact surface of the extended drain structure 206D of the NMOS transistor 206. The N-type SBD 204 has an anode via 242C coupled to the silicide contact surface of the second portion 242B of the P-type semiconductor 242. The drain via 206DA, the cathode via 222C, and the barrier metal 224 are formed by the first metal layer. In some embodiments, the source via 206SA is also formed by the first metal layer. A subset of the source via 206SA, the drain via 206DA, the cathode via 222C, and the barrier metal 224 are electrically coupled via the first metal layer. Additionally, in some embodiments, the drain structure 206D of the NMOS transistor 206 and the second portion 222B of the N-type semiconductor 222 of the N-type SBD 204 optionally overlap each other, and the drain via 206DA and the cathode via 222C also optionally overlap each other. Conversely, in some embodiments, the drain structure 206D and the second portion 222B of the N-type semiconductor 222 overlap each other and are buried under the first metal layer without any drain or cathode vias.

[0094] In some embodiments, referring to Figure 7B , the PMOS transistor 202 has a drain path 202DA coupled to the silicide contact surface of the extended drain structure 202D of the PMOS transistor 202. The p-type SBD 208 has an anode path 242C coupled to the silicide contact surface of the second portion 242B of the p-type semiconductor 242. The drain path 202DA, the anode path 242C, and the barrier metal 244 are formed of a first metal layer. In some embodiments, the source path 202SA is also formed of the first metal layer. A subset of the source path 202SA, the drain path 202DA, the anode path 242C, and the barrier metal 244 are electrically coupled via the first metal layer (e.g., via the interconnect 702). Additionally, in some embodiments, the drain structure 202D of the PMOS transistor 202 and the second portion 242B of the p-type semiconductor 242 of the p-type SBD 208 optionally overlap each other, and the drain path 202DA and the anode path 242C also optionally overlap each other. Conversely, in some embodiments, the drain structure 202D and the second portion 242B of the p-type semiconductor 242 overlap each other and are buried under the first metal layer without any drain or anode path.

[0095] In some embodiments (not shown), each of the silicide contact surfaces of the gate 206G of the NMOS transistor 206 and the gate 202G of the PMOS transistor 202 is at least partially covered by the first metal layer and accessed through a corresponding gate path. The corresponding gate path is optionally coupled, for example, via the first metal layer and / or any other interconnect layer formed above the first metal layer, to a subset of the gates, sources, and drains of the CMOS transistors and / or a subset of the barrier metals and semiconductors of the complementary SBDs formed on the substrate 212 of the integrated semiconductor device 200.

[0096] It should be understood that the specific order of operations described in each of the above figures is merely exemplary and is not intended to indicate that the described order is the only order in which the operations can be performed. Those of ordinary skill in the art will recognize various ways of forming an integrated semiconductor device having MOSFET devices and SBD devices on the same substrate as described herein. Additionally, it should be noted that the details described with respect to one of the above processes (e.g., in Figures 3A - 3F or Figures 5A - 5F ) also apply in a similar manner to any of the other processes described above. For the sake of brevity, similar details are not repeated.

[0097] It should also be understood that although the terms first, second, etc. are used herein in some cases to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various embodiments described, a first audio feature type may be referred to as a second audio feature type, and similarly, a second audio feature type may be referred to as a first audio feature type. The first audio feature type and the second audio feature type are both audio feature types, but they are not the same audio feature type.

[0098] The terms used in describing the various embodiments described herein are for the purpose of describing specific embodiments only and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are intended to include the plural forms as well. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It should be further understood that the terms "includes", "including", "comprises", and / or "comprising", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0099] As used herein, depending on the context, the term "if" may optionally be construed to mean "when", or "after", or "in response to determining", or "in response to detecting", or "in accordance with determining". Similarly, depending on the context, the phrase "if determined" or "if detected [the stated condition or event]" may optionally be construed to mean "after determining", or "in response to determining", or "after detecting [the stated condition or event]", or "in response to detecting [the stated condition or event]", or "in accordance with determining detecting [the stated condition or event]".

[0100] Although the several logical stages are shown in the drawings in a particular order, stages that are not order-dependent may be reordered, and other stages may be combined or decomposed. Although some reordering or other grouping is specifically mentioned, other reordering or grouping will be apparent to those of ordinary skill in the art, so the orderings and groupings presented herein are not an exhaustive list of alternatives. In addition, it should be recognized that the stages may be implemented in hardware, firmware, software, or any combination thereof.

[0101] For purposes of explanation, the foregoing description has been presented with reference to specific embodiments. However, the above illustrative discussion is not intended to be exhaustive or to limit the scope of the claims to the precise forms disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments were chosen and described in order to best explain the principles of the claims and their practical application, thereby enabling others skilled in the art to best utilize the embodiments and various modifications as are suited to the particular use contemplated.

Claims

1. A method of forming an integrated planar semiconductor device, comprising: forming a P-type metal-oxide semiconductor (PMOS) transistor and a P-type Schottky barrier diode (SBD) on a substrate, wherein the P-type SBD is formed by bonding a P-type semiconductor and a first barrier metal, comprising: simultaneously establishing a doping concentration of a P-type channel of the PMOS transistor and forming a first portion of the P-type semiconductor of the SBD; simultaneously forming an extended drain structure of the PMOS transistor and a second portion of the P-type semiconductor on the substrate; and simultaneously forming different silicide contact surfaces of the extended drain structure of the PMOS transistor and the first and second portions of the P-type semiconductor of the P-type SBD.

2. The method according to claim 1, further comprising performing the following according to a silicide definition mask having a predefined critical dimension: defining a first silicide contact surface of the first portion of the P-type semiconductor; defining a second silicide contact surface of the second portion of the P-type semiconductor, the second silicide contact surface being separated from the first silicide contact surface by a lateral distance greater than the predefined critical dimension.

3. The method according to claim 2, further comprising: defining a silicide resistor on the substrate according to the silicide definition mask, wherein the silicide resistor is different from the extended drain structure of the PMOS transistor and the first and second portions of the P-type semiconductor.

4. The method according to any one of the preceding claims, wherein the PMOS transistor comprises a first PMOS transistor, and the method further comprising: forming a second PMOS transistor configured to operate with a second P-type channel, wherein the second P-type channel has an alternative doping concentration different from the doping concentration of the P-type channel of the first PMOS transistor, such that a first threshold voltage of the first PMOS transistor is different from a second threshold voltage of the second PMOS transistor, comprising: separately establishing the alternative doping concentration of the second P-type channel of the second PMOS transistor from the P-type channel of the first PMOS transistor and the first portion of the P-type semiconductor of the P-type SBD.

5. The method according to any one of the preceding claims, wherein each of the second portion of the P-type semiconductor and the extended drain structure of the PMOS transistor comprises a respective second region, in which a respective third region is formed and enclosed, and simultaneously forming the extended drain structure of the PMOS transistor and the second portion of the P-type semiconductor on the substrate further comprises performing the following according to a doping profile: simultaneously using a first drain doping operation to form the second region of the second portion of the P-type semiconductor and the extended drain structure having a second doping concentration; Simultaneously using a second drain doping operation to form the third region of the second portion of the P-type semiconductor in the second region of the second portion of the P-type semiconductor and to form the third region of the extended drain structure in the second region of the extended drain structure, the third region having a third doping concentration; wherein the third doping concentration is greater than the second doping concentration, and the second doping concentration is greater than the first doping concentration of the first portion.

6. The method according to any one of the preceding claims, further comprising simultaneously performing the following operations according to a well definition mask: Forming a first N-well in which the P-type SBD is located; Forming a second N-well in which the PMOS transistor is located, the second N-well being different from the first N-well.

7. The method according to claim 6, further comprising: Forming an N-type SBD formed in a P-well and formed by bonding an N-type semiconductor and a second barrier metal; and Forming a field oxide to separate the P-well from at least one of the first N-well and the second N-well.

8. The method according to any one of the preceding claims, further comprising: Forming an N-well according to a well definition mask, in which both the P-type SBD and the PMOS transistor are located.

9. The method according to any one of claims 1 to 5, further comprising: Forming a first P-well; and Forming an N-type metal oxide semiconductor (NMOS) transistor in the first P-well, the NMOS transistor being configured to operate with an N-type channel.

10. The method according to claim 9, further comprising: Forming an N-well in which the P-type SBD is located, the N-well having an N-well access region; Simultaneously establishing the doping concentration of the N-type channel of the NMOS transistor and forming a first portion of the N-well access region; and Simultaneously forming an extended drain structure matching the NMOS transistor and a second portion of the N-well access region, the second portion of the N-well access region being formed in the first portion of the N-well access region and having a different silicide contact surface; wherein the first portion and the second portion of the N-well access region together provide a low resistance path for the N-well.

11. The method according to claim 9, further comprising: Forming an N-type SBD formed in a second P-well and formed by bonding an N-type semiconductor and a second barrier metal, wherein the first P-well and the second P-well are merged into a single P-well.

12. The method according to claim 9, further comprising: Forming an N-type SBD formed in a second P-well and formed by bonding an N-type semiconductor and a second barrier metal, wherein the first P-well is different from the second P-well.

13. The method according to any one of the preceding claims, wherein the PMOS transistor has a drain path coupled to the silicide contact surface of the extended drain structure of the PMOS transistor, and the P-type SBD has an anode path coupled to the silicide contact surface of the second portion of the P-type semiconductor, the method further comprising: forming the drain path, the anode path, and the first barrier metal from a first metal layer.

14. The method according to any one of the preceding claims, wherein the extended drain structure of the PMOS device overlaps the second portion of the P-type semiconductor of the P-type SBD.

15. An integrated planar semiconductor device, comprising: a substrate; a P-type metal oxide semiconductor (PMOS) transistor formed on the substrate; and a P-type SBD formed on the substrate and formed by bonding a P-type semiconductor and a first barrier metal; wherein a first doping concentration of the P-type channel of the PMOS transistor is substantially the same as a first doping concentration of the first portion of the P-type semiconductor of the P-type SBD; wherein a doping profile of the extended drain structure of the PMOS transistor is substantially the same as a doping profile of the second portion of the P-type semiconductor; and wherein each of the extended drain structure of the PMOS transistor and the first portion and the second portion of the P-type semiconductor has a different silicide contact surface.

16. The semiconductor device according to claim 15, wherein the first portion of the P-type semiconductor has a first silicide contact surface, and the second portion of the P-type semiconductor has a second silicide contact surface separated from the first silicide contact surface by a lateral distance greater than a predefined critical dimension of a silicide definition mask.

17. The semiconductor device according to claim 15 or 16, further comprising: a silicide resistor formed on the substrate and different from the extended drain structure of the PMOS transistor and the first portion and the second portion of the P-type semiconductor.

18. The semiconductor device according to any one of claims 15 to 17, wherein the PMOS transistor includes a first PMOS transistor, the semiconductor device further comprising: a second PMOS transistor configured to operate with a second P-type channel, wherein the second P-type channel has an alternative doping concentration different from the first doping concentration, such that a first threshold voltage of the first PMOS transistor is different from a second threshold voltage of the second PMOS transistor.

19. The semiconductor device according to any one of claims 15 to 18, wherein: the second portion of the P-type semiconductor includes a second region, and a third region is formed and enclosed in the second region; according to the doping profile, the second region has a second doping concentration, and the third region has a third doping concentration greater than the second doping concentration; and The second doping concentration in the second region is greater than the first doping concentration in the first portion.

20. The semiconductor device according to any one of claims 15 to 19, wherein the P-type SBD is located in a first N-well, and the PMOS transistor is formed in a second N-well different from the first N-well.

21. The semiconductor device according to claim 19, further comprising: an N-type SBD formed in a P-well and formed by bonding an N-type semiconductor and a second barrier metal, wherein the P-well is isolated from at least one of the first N-well and the second N-well by a field oxide.

22. The semiconductor device according to any one of claims 15 to 21, wherein both the P-type SBD and the PMOS transistor are formed in an N-well.

23. The semiconductor device according to any one of claims 15 to 22, further comprising: an N-type metal oxide semiconductor (NMOS) transistor formed in a first P-well and configured to operate with an N-type channel.

24. The semiconductor device according to claim 23, wherein the P-type SBD is located in an N-well having an N-well access region; the doping concentration of the N-type channel of the NMOS transistor is equal to the doping concentration of a first portion of the N-well access region; the doping profile of the extended drain structure of the NMOS transistor matches the doping profile of a second portion of the N-well access region, the second portion of the N-well access region being formed in the first portion of the N-well access region and having a different silicide contact surface; and the first portion and the second portion of the N-well access region together provide a low-resistance path for the N-well.

25. The semiconductor device according to claim 23, further comprising: an N-type SBD formed in a second P-well and formed by bonding an N-type semiconductor and a second barrier metal, wherein the first P-well and the second P-well are merged into a single P-well.

26. The semiconductor device according to claim 23, further comprising: an N-type SBD formed in a second P-well and formed by bonding an N-type semiconductor and a second barrier metal, wherein the first P-well is different from the second P-well.

27. The semiconductor device according to any one of claims 15 to 26, wherein: the PMOS transistor has a drain path coupled to the silicide contact surface of the extended drain structure of the PMOS transistor; the P-type SBD has an anode path coupled to the silicide contact surface of the second portion of the P-type semiconductor; and the drain path, the anode path, and the first barrier metal are formed of a first metal layer.

28. The semiconductor device according to any one of claims 15 to 27, wherein the extended drain structure of the PMOS device overlaps the second portion of the P-type semiconductor of the P-type SBD.

29. A method of forming an integrated planar semiconductor device, comprising: An N-type metal oxide semiconductor (NMOS) transistor and an N-type Schottky barrier diode (SBD) are formed on a substrate, wherein the N-type SBD is formed by bonding an N-type semiconductor and a first barrier metal, and includes: Simultaneously establishing a doping concentration of an N-type channel of the NMOS transistor and forming a first portion of the N-type semiconductor of the N-type SBD; Simultaneously forming an extended drain structure of the NMOS transistor and a second portion of the N-type semiconductor on the substrate; And Simultaneously forming different silicide contact surfaces of the extended drain structure of the NMOS transistor and the first and second portions of the N-type semiconductor of the N-type SBD.

30. The method according to claim 29, further comprising performing the following operations according to a silicide definition mask having a predefined critical dimension: Defining a first silicide contact surface of the first portion of the N-type semiconductor; Defining a second silicide contact surface of the second portion of the N-type semiconductor, the second silicide contact surface being separated from the first silicide contact surface by a lateral distance greater than the predefined critical dimension.

31. The method according to claim 30, further Comprising: Defining a silicide resistor on the substrate according to the silicide definition mask, wherein the silicide resistor is different from the extended drain structure of the NMOS transistor and the first and second portions of the N-type semiconductor.

32. The method according to any one of claims 29 to 31, wherein the NMOS transistor includes a first NMOS transistor, and the method further Comprising: Forming a second NMOS transistor configured to operate with a second N-type channel, wherein the second N-type channel has an alternative doping concentration different from the first doping concentration, such that a first threshold voltage of the first NMOS transistor is different from a second threshold voltage of the second NMOS transistor, and includes: Separately establishing the alternative doping concentration of the second N-type channel of the second NMOS transistor from the N-type channel of the NMOS transistor and the first portion of the N-type semiconductor of the SBD.

33. The method according to any one of claims 29 to 32, wherein each of the second portion of the N-type semiconductor and the extended drain structure of the NMOS transistor includes a corresponding second region, a corresponding third region is formed and enclosed in the second region, and simultaneously forming the extended drain structure of the NMOS transistor and the second portion of the N-type semiconductor on the substrate further includes performing the following operations according to a doping profile: Simultaneously using a first drain doping operation to form the second region of the second portion of the N-type semiconductor having a second doping concentration and the extended drain structure; Simultaneously using a second drain doping operation to form the third region of the second part of the N-type semiconductor in the second region of the second part of the N-type semiconductor and to form the third region of the extended drain structure in the second region of the extended drain structure, the third region having a third doping concentration; wherein the third doping concentration is greater than the second doping concentration, and the second doping concentration is greater than the first doping concentration of the first part.

34. The method according to any one of claims 29 to 33, further comprising simultaneously performing the following operations according to a well definition mask: Forming a first P-well in which the N-type SBD is located; Forming a second P-well in which the NMOS transistor is located, the second P-well being different from the first P-well.

35. The method according to claim 34, further comprising: Forming a P-type SBD formed in an N-well and formed by bonding a P-type semiconductor and a second barrier metal; and Forming a field oxide to separate the N-well from at least one of the first P-well and the second P-well.

36. The method according to any one of claims 29 to 35, further comprising: According to a well definition mask, forming a P-well in which both the N-type SBD and the NMOS transistor are located.

37. The method according to any one of claims 29 to 36, further comprising: Forming a first N-well; and Forming a P-type metal oxide semiconductor (PMOS) transistor in the first N-well, the P-type PMOS transistor being configured to operate with a P-type channel.

38. The method according to claim 37, further comprising: Forming a P-well in which the N-type SBD is located, the P-well having a P-well access region; Simultaneously establishing the doping concentration of the P-type channel of the PMOS transistor and forming a first part of the P-well access region; and Simultaneously forming an extended drain structure matching the PMOS transistor and a second part of the P-well access region, the second part of the P-well access region being formed in the first part of the P-well access region and having a different silicide contact surface; wherein the first part and the second part of the P-well access region together provide a low resistance path for the P-well.

39. The method according to claim 37, further comprising: Forming a P-type SBD formed in a second N-well and formed by bonding a P-type semiconductor and a second barrier metal, wherein the first N-well and the second N-well are combined into a single N-well.

40. The method according to claim 37, further comprising: Forming a P-type SBD formed in a second N-well and formed by bonding a P-type semiconductor and a second barrier metal, wherein the first N-well is different from the second N-well.

41. The method according to any one of claims 29 to 40, wherein the NMOS transistor has a drain path coupled to the silicide contact surface of the extended drain structure of the NMOS transistor, and the N-type SBD has a cathode path coupled to the silicide contact surface of the second portion of the N-type semiconductor, and the method further comprises: forming the drain path, the cathode path, and the first barrier metal from a first metal layer.

42. The method according to any one of claims 29 to 41, wherein the extended drain structure of the NMOS device overlaps the second portion of the N-type semiconductor of the N-type SBD.

43. An integrated planar semiconductor device, comprising: a substrate; an N-type metal oxide semiconductor (NMOS) transistor formed on the substrate; and an N-type SBD formed on the substrate and formed by bonding an N-type semiconductor and a first barrier metal; wherein a first doping concentration of the N-type channel of the NMOS transistor is substantially the same as a first doping concentration of the first portion of the N-type semiconductor of the SBD; wherein a doping profile of the extended drain structure of the NMOS transistor is substantially the same as a doping profile of the second portion of the N-type semiconductor; and wherein each of the extended drain structure of the NMOS transistor and the first portion and the second portion of the N-type semiconductor has a different silicide contact surface.

44. The semiconductor device according to claim 43, wherein the first portion of the N-type semiconductor has a first silicide contact surface, and the second portion of the N-type semiconductor has a second silicide contact surface separated from the first silicide contact surface by a lateral distance greater than a predefined critical dimension of a silicide definition mask.

45. The semiconductor device according to claim 43 or 44, further comprising: a silicide resistor formed on the substrate and different from the extended drain structure of the NMOS transistor and the first portion and the second portion of the N-type semiconductor.

46. The semiconductor device according to any one of claims 43 to 45, wherein the NMOS transistor comprises a first NMOS transistor, and the semiconductor device further comprises: a second NMOS transistor configured to operate with a second N-type channel, wherein the second N-type channel has an alternative doping concentration different from the first doping concentration such that a first threshold voltage of the first NMOS transistor is different from a second threshold voltage of the second NMOS transistor.

47. The semiconductor device according to any one of claims 43 to 46, wherein: the second portion of the N-type semiconductor comprises a second region in which a third region is formed and enclosed; according to the doping profile, the second region has a second doping concentration, and the third region has a third doping concentration greater than the second doping concentration; and The second doping concentration in the second region is greater than the first doping concentration in the first portion.

48. The semiconductor device according to any one of claims 43 to 47, wherein the N-type SBD is located in a first P-well, and the NMOS transistor is formed in a second P-well different from the first P-well.

49. The semiconductor device according to claim 48, further comprising: A P-type SBD formed in an N-well and formed by bonding a P-type semiconductor and a second barrier metal, wherein the N-well is isolated from at least one of the first P-well and the second P-well by a field oxide.

50. The semiconductor device according to any one of claims 43 to 49, wherein both the N-type SBD and the NMOS transistor are formed in a P-well.

51. The semiconductor device according to any one of claims 43 to 50, further comprising: A P-type metal oxide semiconductor (PMOS) transistor formed in a first N-well and configured to operate with a P-type channel.

52. The semiconductor device according to claim 51, wherein the N-type SBD is located in a P-well having a P-well access region; the doping concentration of the P-type channel of the PMOS transistor is equal to the doping concentration of the first portion of the P-well access region; the doping profile of the extended drain structure of the PMOS transistor matches the doping profile of the second portion of the P-well access region, the second portion of the P-well access region being formed in the first portion of the P-well access region and having a different silicide contact surface; and the first portion and the second portion of the P-well access region together provide a low-resistance path for the P-well.

53. The semiconductor device according to claim 51, further comprising: A P-type SBD formed in a second N-well and formed by bonding a P-type semiconductor and a second barrier metal, wherein the first N-well and the second N-well are merged into a single N-well.

54. The semiconductor device according to claim 51, further comprising: A P-type SBD formed in a second N-well and formed by bonding a P-type semiconductor and a second barrier metal, wherein the first N-well is different from the second N-well.

55. The semiconductor device according to any one of claims 43 to 54, wherein: the NMOS transistor has a drain path coupled to the silicide contact surface of the extended drain structure of the NMOS transistor; the N-type SBD has a cathode path coupled to the silicide contact surface of the second portion of the N-type semiconductor; and the drain path, the cathode path, and the first barrier metal are formed of a first metal layer.

56. The semiconductor device according to claim 43, wherein the extended drain structure of the NMOS device overlaps the second portion of the N-type semiconductor of the N-type SBD.

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