Target impedance determination method for power supply integrity analysis and electronic equipment

Abstract

The invention discloses a target impedance determination method for power supply integrity analysis and electronic equipment, and the target impedance determination method comprises the steps: determining a clock frequency range of a chip, and selecting N clock frequencies in the clock frequency range, N being an integer greater than 1; under any clock frequency in the N clock frequencies, current waveforms of the chip in at least two working states are obtained to obtain N current waveforms, and the at least two working states comprise a full-load state and an idle state; generating a frequency spectrum based on each current waveform to generate N frequency spectrums; target impedance is determined according to a preset voltage change value and the N frequency spectrums, and the preset voltage change value is determined based on the voltage drop limiting range of the working voltage of the chip. Through the above mode, the target impedance can be accurately determined so as to prevent a chip designer from making over-design or under-design, reduce the chip design cost and improve the design success rate of the chip.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of target impedance design, and particularly to a method for determining a target impedance for power integrity analysis and an electronic device. Background Art

[0002] In modern electronic industries, circuit PDN (Power Distribution Network) noise is more sensitive because the core voltage level decreases, which means that the power PDN noise amplitude is smaller. As the industry moves towards smaller technology nodes, the current consumption per unit area increases sharply. The clock frequency is getting higher and higher, resulting in a smaller timing margin. All these factors pose great challenges to PDN design, especially in large integrated circuits with high power consumption and fast transient currents.

[0003] With the advent of the era of artificial intelligence, the development of computer-aided engineering, mobile computer-aided engineering, smartphones, robots, and driverless cars, the demand for chips is also increasing continuously, and the requirements for computing power and power consumption are getting higher and higher. The decrease in power supply voltage makes the target impedance a challenge in system-level PDN design. Therefore, a more accurate method must be found to analyze and optimize the PDN, and then verify the proposed design. The design of the target impedance is an important topic in power integrity analysis and the most important link in analyzing and optimizing the PDN. Summary of the Invention

[0004] The embodiments of the present application provide a method for determining a target impedance for power integrity analysis and an electronic device, which can accurately determine the target impedance to avoid over-design or under-design by chip designers, reduce the chip design cost, and improve the chip design success rate.

[0005] In a first aspect, the embodiments of the present application provide a method for determining a target impedance for power integrity analysis, including: determining a clock frequency range of a chip, and selecting N clock frequencies from the clock frequency range, where N is an integer greater than 1; at any one of the N clock frequencies, obtaining current waveforms of the chip in at least two working states to obtain N current waveforms, where the at least two working states include a full-load state and an idle state; generating a spectrum based on each current waveform to generate N spectra; and determining a target impedance according to a preset voltage change value and the N spectra, where the preset voltage change value is determined based on a working voltage drop limit range of the chip.

[0006] In one or more embodiments, the at least two working states further include a state of switching from the full-load state to the idle state and a state of switching from the idle state to the full-load state.

[0007] In one or more embodiments, determining the target impedance according to the preset voltage change value and N spectra includes: determining N impedances corresponding to each frequency point according to the preset voltage change value and N spectra; and determining the target impedance corresponding to each frequency point according to the N impedances corresponding to each frequency point.

[0008] In one or more embodiments, generating one spectrum based on each current waveform includes: converting each current waveform from the time domain to the frequency domain through fast Fourier transform to generate one spectrum.

[0009] In one or more embodiments, determining N impedances corresponding to each frequency point according to the preset voltage change value and N spectra includes: determining N impedances corresponding to each frequency point according to the ratio of the preset voltage change value to the N spectra.

[0010] In one or more embodiments, determining the target impedance corresponding to each frequency point according to the N impedances corresponding to each frequency point includes: determining the target impedance corresponding to each frequency point according to the minimum value among the N impedances corresponding to each frequency point.

[0011] In a second aspect, an embodiment of the present application provides an electronic device, including: at least one processor and a memory; the memory is coupled to the processor, and the memory is used to store instructions or programs. When the instructions or programs are executed by the at least one processor, the at least one processor executes the target impedance determination method for power integrity analysis as described above.

[0012] In a third aspect, an embodiment of the present application provides a power supply system, including a DC-DC conversion module, a chip, and the electronic device as described above.

[0013] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed, the target impedance determination method for power integrity analysis as described above is implemented.

[0014] In a fifth aspect, an embodiment of the present application provides a computer program product, which includes a computer program stored on a computer storage medium. The computer program includes programs or instructions. When the instructions or programs are executed by at least one processor, the at least one processor executes the target impedance determination method as described above.

[0015] The beneficial effects of the present application are as follows: The method for determining the target impedance for power integrity analysis according to an embodiment of the present application includes: determining the clock frequency range of the chip, and selecting N clock frequencies within the clock frequency range, where N is an integer greater than 1; at any one of the N clock frequencies, obtaining the current waveforms of the chip in at least two operating states to obtain N current waveforms, where the at least two operating states include the full-load state and the idle state; generating a spectrum based on each current waveform to generate N spectra; determining the target impedance according to a preset voltage change value and the N spectra, where the preset voltage change value is determined based on the operating voltage drop limit range of the chip. By the above method, the frequency-domain analysis of the current waveforms under different clock frequency conditions can be realized to obtain the electrical performance of the chip in the medium and low frequencies and high frequencies in various situations, and by adjusting the clock, relatively rich frequency-domain characteristics can be obtained. Based on this, the target impedance can be determined more accurately. Thus, it is beneficial to avoid over-design or under-design by chip designers, reduce the chip design cost, and improve the chip design success rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations are not intended to limit the embodiments. Elements with the same reference numerals in the drawings represent similar elements.

[0017] Figure 1 is a schematic diagram of the target impedance and the actual impedance in the related art;

[0018] Figure 2 is the method for determining the target impedance for power integrity analysis provided by an embodiment of the present application;

[0019] Figure 3 is provided by an embodiment of the present application Figure 2 is a schematic diagram of an embodiment of step 203 shown in

[0020] Figure 4 are the current frequency components of two different clock frequencies provided by an embodiment of the present application;

[0021] Figure 5 is a schematic diagram of the current waveform provided by an embodiment of the present application;

[0022] Figure 6 is a schematic diagram of the structure of the electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the following will clearly and detailedly describe the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are part of rather than all of the embodiments of this application. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

[0024] It should be noted that when an element is expressed as "connected to" another element, it can be directly connected to the other element, or there can be one or more intermediate elements therebetween.

[0025] In addition, the technical features involved in the various embodiments of this application described below can be combined with each other as long as there is no conflict in their structures.

[0026] Currently, in the related art, the target impedance for power integrity analysis is usually determined by the maximum current method. Specifically, the ratio of the maximum allowable voltage change value of the chip to the maximum average current is calculated, and this ratio is used as the target impedance. However, this method is very difficult to implement in actual applications. For example, as Figure 1 shown, the abscissa is frequency. In this embodiment, the target impedance determined according to the maximum current method is Z T . In actual applications, after designing the chip according to this target impedance Z T , the actual impedance is as shown by Z PDN . It is easy to have an impedance between frequencies F1 and F2. The impedance in this frequency range is greater than the target impedance Z T , and the actual impedance Z PDN cannot be recognized in this frequency range.

[0027] Based on this, the embodiments of this application provide a method for determining the target impedance for power integrity analysis to accurately determine the target impedance, thereby preventing chip designers from over-designing or under-designing, reducing the chip design cost, and improving the chip design success rate.

[0028] Please refer to Figure 2 , Figure 2 , which is a flowchart of the method for determining the target impedance for power integrity analysis provided by the embodiments of this application. As Figure 2 shown, the method for determining the target impedance includes the following steps:

[0029] Step 201: Determine the clock frequency range of the chip and select N clock frequencies in the clock frequency range, where N is an integer greater than 1.

[0030] Specifically, the clock frequency range of the chip refers to the range of clock frequencies at which the chip can operate normally. In some embodiments, the N clock frequencies include multiple clock frequencies from low frequency to high frequency.

[0031] Step 202: At any one of the N clock frequencies, obtain the current waveforms of the chip in at least two operating states to obtain N current waveforms, where the at least two operating states include a full-load state and an idle state.

[0032] Specifically, the N clock frequencies include F0, F1, …, FN. When the chip is operating at F0, obtain the current waveforms of the chip in at least two operating states; when the chip is operating at F1, obtain the current waveforms of the chip in at least two operating states; …; when the chip is operating at FN, obtain the current waveforms of the chip in at least two operating states, so that N current waveforms can be obtained.

[0033] Among them, the full-load state refers to the state in which all functions of the chip are running; the idle state refers to the sleep state of the chip (also known as the standby state). In the sleep state, most functions of the chip are turned off, but the core part (such as the wake-up controller) still remains running.

[0034] In some embodiments, the at least two operating states further include the state of switching from the full-load state to the idle state and the state of switching from the idle state to the full-load state.

[0035] By further increasing the current waveforms of the states in the change process, the frequency components can be made more abundant, so that the target impedance can be determined more accurately.

[0036] Step 203: Generate a spectrum based on each current waveform to generate N spectra.

[0037] In some embodiments, the specific implementation process of step 203 includes the following steps: Through the fast Fourier transform, each current waveform is converted from the time domain to the frequency domain to generate a spectrum.

[0038] Specifically, the fast Fourier transform (FFT) is an efficient algorithm used to calculate the discrete Fourier transform (DFT) and its inverse transform. Through the FFT, the current waveform in the time domain can be converted into the frequency domain, so that different frequency components in the current waveform can be identified. Among them, since a spectrum is generated based on each current waveform, N spectra are generated based on the N current waveforms.

[0039] Step 204: Determine the target impedance according to the preset voltage change value and the N spectra, where the preset voltage change value is determined based on the operating voltage drop limit range of the chip.

[0040] Specifically, the preset voltage change value can be set based on the actual application scenario. For example, in some embodiments, it is assumed that in actual application, the power supply voltage required for the chip to operate normally (i.e., the typical operating voltage of the chip) is V0, and the operating voltage drop limit range of the chip is V0±A%, then the preset voltage change value is V0*A%, where A>0.

[0041] In some embodiments, as Figure 3 shown, the specific implementation process of step 203 includes the following method steps:

[0042] Step 301: Determine the N impedances corresponding to each frequency point according to the preset voltage change value and the N spectra.

[0043] Step 302: Determine the target impedance corresponding to each frequency point according to the N impedances corresponding to each frequency point.

[0044] In some embodiments, the specific implementation process of step 301 includes the following method steps: Determine the N impedances corresponding to each frequency point according to the ratio of the preset voltage change value to the N spectra.

[0045] Specifically, according to the ratio of the preset voltage change value to one spectrum, assuming that the spectrum has M frequency points, then since each frequency point can correspond to a ratio, M frequency points correspond to M ratios, that is, each spectrum can correspond to M ratios, where M is an integer ≥1. For N spectra, at each of the M frequency points, N impedances can be determined.

[0046] In some embodiments, the specific implementation process of step 302 includes the following method steps: Determine the target impedance corresponding to each frequency point according to the minimum value among the N impedances corresponding to each frequency point.

[0047] Specifically, for the Kth frequency point among the M frequency points, it corresponds to N impedances, where K is an integer and 1≤K≤M. For the Kth frequency point, the minimum value can be selected from the N impedances as the target impedance corresponding to the Kth frequency point. When K ranges from 1 to M, M target impedances corresponding to the M frequency points can be obtained.

[0048] Through the above process, the frequency-domain analysis of the current waveform under different clock frequencies (F0 - FN) can be realized to obtain the electrical performance of the chip in the medium and low frequencies and high frequencies in various situations, and moreover, relatively rich frequency-domain characteristics can be obtained by adjusting the clock.

[0049] Figure 4 Exemplarily shows the current frequency components of two different clock frequencies. Figure 4The (a1) part in it shows the current frequency components of the first clock frequency, with the abscissa being frequency and the ordinate being amplitude; Figure 4 The (a2) part in it shows the current frequency components of the second clock frequency, with the abscissa being frequency and the ordinate being amplitude.

[0050] As can be seen from Figure 4 it, different clocks will generate different frequency components. Moreover, when there is more data, the frequency characteristics when representing the working states at all gate levels (in gate-level design, the circuit is regarded as a network composed of basic logic gates such as AND gates, OR gates, NOT gates, etc.) and transistor levels (the transistor level focuses on the behavior of a single transistor and its connections in the circuit) inside the chip will cover a wider frequency band during the chip's working process. The target impedance obtained from all frequency components can more accurately reflect the working impedance limit of the chip.

[0051] Figure 5 Exemplarily shows the current waveform when the chip switches between the idle state and the full-load state, with the abscissa being time and the ordinate being amplitude. As Figure 5 shown, under different clock conditions, the current waveform contains current components of different frequency bands. Among them, the current waveform between time T1 and time T2 is the current waveform when the chip is in the idle state; the current waveform between time T2 and time T5 is the current waveform when the chip is in the full-load state; the current waveform between time T5 and time T6 is the current waveform when the chip is in the idle state. Since the idle state, full-load state, state from full-load state to idle state, state from idle state to full-load state, rise time of state switching, and fall time are all strongly correlated with the working clock, that is, the magnitude of the clock determines the current change, and the current change will determine whether the PDN of the chip's power supply system can support the chip's operation. Therefore, obtaining the current change under different clock conditions plays a very important role in determining the target impedance.

[0052] In summary, obtaining the current change under different clock conditions plays a very important role in determining the target impedance, and the target impedance obtained from all frequency components can more accurately reflect the working impedance limit of the chip. Therefore, the embodiments of this application perform frequency-domain analysis on the current waveforms under different clock frequencies (F0 - FN) to obtain the target impedance, which can accurately determine the target impedance. Thus, it is beneficial to avoid over-design or under-design by chip designers, reduce the chip design cost, and improve the chip design success rate.

[0053] Please refer to Figure 6 , Figure 6 which is the structural schematic diagram of the electronic device provided by the embodiments of this application. As Figure 6As shown in the figure, the electronic device 600 includes at least one processor 601 and a memory 602. Among them, the memory 602 can be built into the electronic device 600, or can be external to the electronic device 600. The memory 602 can also be a remotely set memory, which is connected to the electronic device 600 through a network.

[0054] The memory 602, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The memory 602 can include a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the terminal, etc. In addition, the memory 602 can include high-speed random access memory, and can also include non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 602 optionally includes a memory remotely set relative to the processor 601, and these remote memories can be connected to the terminal through a network. Examples of the above network include but are not limited to the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0055] The processor 601 executes various functions of the terminal and processes data by running or executing software programs and / or modules stored in the memory 602, and by calling data stored in the memory 602, so as to perform overall monitoring of the terminal. For example, the target impedance determination method for power integrity analysis in any embodiment of the present application is implemented.

[0056] The processor 601 can be one or more. Figure 6 Here, one processor 601 is taken as an example. The processor 601 and the memory 602 can be connected through a bus or other means. The processor 601 can include a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a controller, a field programmable gate array (FPGA) device, etc. The processor 601 can also be implemented as a combination of computing devices. For example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0057] The embodiment of the present application also provides a power supply system, which includes a DC-DC conversion module, a chip, and the electronic device 600 in any embodiment of the present application.

[0058] The DC-DC conversion module is a power management device for converting one DC voltage into another DC voltage. The DC-DC conversion module includes a buck converter or a boost converter, etc.

[0059] The embodiments of the present application also provide a non-volatile computer-readable storage medium, which stores computer-executable instructions. These computer-executable instructions are executed by one or more processors. For example, they execute the Figure 2 and Figure 3 method steps described above.

[0060] The embodiments of the present application also provide a computer program product, including a computing program stored on a non-volatile computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer, the computer is caused to execute the target impedance determination method for power integrity analysis in any of the above method embodiments. For example, it executes the Figure 2 and Figure 3 method steps described above.

[0061] The above are only the embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

[0062] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; under the idea of the present application, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order. Those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for determining target impedance for power integrity analysis, characterized in that: include: Determine a clock frequency range of the chip, and select N clock frequencies in the clock frequency range, where N is an integer greater than 1; At any clock frequency among the N clock frequencies, obtaining current waveforms of the chip in at least two working states to obtain N current waveforms, wherein the at least two working states include a full load state and an idle state; generating a spectrum based on each current waveform to generate N spectrums; The target impedance is determined according to a preset voltage change value and N frequency spectra, wherein the preset voltage change value is determined based on a working voltage drop limit range of the chip.

2. The method according to claim 1, characterized in that: The at least two working states also include a state of switching from the full-load state to the idle state and a state of switching from the idle state to the full-load state.

3. The method according to claim 1 or 2, characterized in that: The step of determining the target impedance according to the preset voltage change value and the N frequency spectra includes: Determine N impedances corresponding to each frequency point according to the preset voltage change value and N frequency spectra; According to the N impedances corresponding to each frequency point, the target impedance corresponding to each frequency point is determined.

4. The method according to claim 1 or 2, characterized in that: The method of generating a spectrum based on each current waveform comprises: Each current waveform is converted from the time domain to the frequency domain via a Fast Fourier Transform to generate a spectrum.

5. The method according to claim 1 or 2, characterized in that: The method of determining N impedances corresponding to each frequency point according to the preset voltage change value and the N frequency spectra includes: According to the ratio of the preset voltage change value to the N frequency spectra, the N impedances corresponding to each frequency point are determined.

6. The method according to claim 1 or 2, characterized in that: The step of determining the target impedance corresponding to each frequency point according to the N impedances corresponding to each frequency point includes: The target impedance corresponding to each frequency point is determined according to the minimum value of the N impedances corresponding to each frequency point.

7. An electronic device, characterized in that: include: at least one processor and memory; The memory is coupled to the processor, and the memory is used to store instructions or programs. When the instructions or programs are executed by the at least one processor, the at least one processor executes the target impedance determination method for power integrity analysis according to any one of claims 1 to 6.

8. A power supply system, characterized in that: The electronic device comprises a DC-DC conversion module, a chip and the electronic device as claimed in claim 7.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed, the target impedance determination method for power integrity analysis according to any one of claims 1 to 6 is implemented.

10. A computer program product, characterized in that The computer program product comprises a computer program stored on a computer storage medium, the computer program comprising a program or instructions, which, when executed by at least one processor, causes the at least one processor to execute the target impedance determination method as described in any one of claims 1-6.

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