Numerical control frequency hopping filter aging system and aging method

Abstract

The invention discloses a numerical control frequency hopping filter aging system and aging method. The system comprises a power supply, an upper computer, a lower computer, an aging tool and a network analyzer. The upper computer is responsible for sending an operation instruction to the lower computer and analyzing data returned by the lower computer and the network analyzer for closed-loop processing, the lower computer takes the microprocessor as a core and is responsible for executing a specific aging process, the aging tool is used for installing an aged numerical control frequency hopping filter, and the network analyzer is used for measuring data of an aged product. According to the aging system, multiple repeated tests of multiple products can be completed at the same time, fault preliminary screening of the multiple products in the aging process is achieved, and aging operation is carried out on fault-free products. And the working stability of the product is ensured after the aging test.

Description

[0001] The present invention relates to the field of frequency hopping filters, and particularly to a numerically controlled frequency hopping filter aging system and an aging method. Background Art

[0002] Currently, most of the frequency hopping filter technologies select different voltages output by the drive circuit according to the output data of the memory to control the on-off of the switching diode, so as to select the capacitor array to adjust the resonance frequency and achieve the purpose of frequency change. Since the frequency hopping filter needs to continuously switch frequency bands during operation, and the process of switching frequency bands is also a process of frequent voltage switching, therefore, it is crucial to solve the reliability of the product by the stability of the components involved in the work. Summary of the Invention

[0003] The purpose of the present invention is to solve the deficiencies existing in the above-mentioned prior art, and particularly provide a numerically controlled frequency hopping filter aging system and an aging method. This system includes a power supply, a host computer, a slave computer, an aging tooling, and a network analyzer. The host computer is responsible for sending operation instructions to the slave computer and analyzing the data returned by the slave computer and the network analyzer for closed-loop processing. The slave computer takes the microprocessor as the core and is responsible for executing the specific aging process. The aging tooling is used to install the numerically controlled frequency hopping filter to be aged, and the network analyzer is used to measure the data of the product to be aged. To ensure the reliability of the product.

[0004] The technical solution adopted by the present invention is: a numerically controlled frequency hopping filter aging system includes a power supply, a host computer installed with a network analyzer drive and a control slave computer program component, a slave computer with an aging program downloaded internally by the microprocessor, an aging tooling, and a network analyzer; the power supply is connected to the slave computer as the power input of the slave computer, the host computer is connected to the slave computer through a serial cable, the slave computer is connected to the network analyzer through a network cable, the slave computer is connected to the aging tooling through a wire, the aging tooling is used to install the workpiece to be aged, and the aging tooling is connected to the network analyzer through a radio frequency test cable.

[0005] An aging method for a numerically controlled frequency hopping filter aging system has the following steps: 1. Install multiple numerically controlled frequency hopping filters to be aged on the aging tooling, turn on the power, and the program control component of the host computer sends an aging execution instruction to the slave computer through the serial port.

[0006] 2. The slave computer executes the aging program and determines whether there are faulty workpieces.

[0007] 3. If there are faulty workpieces, the indicator lights of the faulty workpieces will be on, and the system will automatically cut off the power supply of the faulty workpieces.

[0008] 4. If there are no faulty workpieces, continue to execute the aging program.

[0009] 5. After the aging program is completed, stop aging, and the host computer reads and saves the aging data of the slave computer.

[0010] The beneficial effects of the present invention are as follows: This system can simultaneously complete multiple repeated tests on multiple products, realize the preliminary screening of faults of multiple products during the aging process, and perform aging operations on products without faults. After the aging test, the working stability of the products is ensured. The invention greatly improves the quality control of products, promptly eliminates defective products, and improves work efficiency. The operation of the present invention is convenient. Most of the debugging work can be completed by relevant personnel only on the human-computer interaction interface of the upper computer program control component, and then the full operation can be completed. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is the system connection principle block diagram of the present invention; Figure 2 is the system software execution flow chart of the present invention; Figure 3 is the circuit schematic diagram of the power supply for the lower computer of the present invention; Figure 4 is the circuit schematic diagram of the microprocessor of the lower computer of the present invention; Figure 5 is the circuit schematic diagram of the chip selected for the aging tooling of the lower computer of the present invention; Figure 6 is the circuit schematic diagram of the RF switch chip of the lower computer of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0012] The present invention will be further described below with reference to the drawings and embodiments.

[0013] Referring to Figure 1 , the numerical control frequency hopping filter aging system includes a power supply, an upper computer installed with a network analyzer driver and a control lower computer program component, a lower computer with an aging program downloaded internally by a microprocessor, an aging tooling, and a network analyzer; the power supply is connected to the lower computer as the power input of the lower computer, the upper computer is connected to the lower computer through a serial cable, the lower computer is connected to the network analyzer through a network cable, the lower computer is connected to the aging tooling through a wire, the aging tooling is used to install the workpiece to be aged, and the aging tooling is connected to the network analyzer through a radio frequency test cable.

[0014] The upper computer is a program-controlled computer. It sends debugging instructions to the lower computer through the program control component edited in Microsoft Visual Studio using the C++ language and is responsible for analyzing the data returned by the lower computer and the network analyzer to close the loop for aging; the lower computer is connected to the aging tooling through a wire, parses various instructions issued by the upper computer and executes relevant operations, completes the judgment of whether the workpiece under test is faulty, and executes the aging operation; the aging tooling is used to install the workpiece to be aged; the network analyzer is connected to the aging tooling through a radio frequency test cable, captures the aging data of the workpiece to be aged in real time and transmits it back to the upper computer through a network cable.

[0015] The lower computer takes the microprocessor as the core, parses various instructions sent by the upper computer and executes relevant aging operations, completes the judgment of whether the workpiece under test is faulty, gives a prompt if there is a fault and does not perform aging operations, and continues to perform aging operations if there is no fault; the aging fixture is used to install the workpiece to be aged; the network analyzer is connected to the aging fixture through a radio frequency test cable, measures the aging data of the workpiece under test in real time and transmits it back to the upper computer through the network cable.

[0016] The lower computer includes three parts: a power supply, a microprocessor, and an aging fixture. The power supply converts the power supply voltage required for the microprocessor, fault indication, and aging fixture. The fault indication locates the faulty product; the internal driver program of the microprocessor is edited in IAR Systems using C++ language and then downloaded into the microprocessor, which is used to drive the I / O ports of the microprocessor to simulate the address lines, data lines, and control lines required by the workpiece to be aged, execute the judgment of whether the workpiece under test is faulty, and run the aging program for the non-faulty workpiece; the fault indication locates the faulty workpiece through the fault indicator light.

[0017] Example: Refer to Figure 2 , install 8 aging digital control frequency hopping filters on the aging fixture, turn on the power, the program control component of the upper computer sends an aging execution instruction to the lower computer through the serial port. After the microprocessor of the lower computer receives the instruction, it performs the first aging work on the digital control frequency hopping filter in sequence through the 10-pin drive download interface XP2 and the other 7 download interfaces. If there is a fault, the indicator light corresponding to this workpiece lights up and the aging work is no longer carried out; the non-faulty workpiece continues to perform the aging work. After ten aging tests are executed, the aging stops, and the upper computer saves the collected data to complete the aging of the non-faulty digital control frequency hopping filter. After actual inspection, applying the digital control frequency hopping filter aging system can evaluate the stability of the product under continuous working conditions and improve the reliability of the product.

[0018] This system can support 8 workpieces to be aged to carry out aging work simultaneously. Only the circuit structure of 1 workpiece to be aged is described below, and the circuit structures of the other 7 aging workpieces are consistent.

[0019] Refer to Figure 3, the power supply part of the system includes a single-pole double-throw switch S1, a common-mode suppressor T1, a common-mode suppressor T2, a common-mode suppressor T3, a low-voltage power supply output module M1, a bias power supply output module M2, and a low-voltage power supply output module M3; the specific circuit connection is as follows: the positive pole of the power supply is connected in series with the single-pole double-throw switch S1 through pin 1 of the external interface XP1, and the single-pole double-throw switch S1 is respectively connected to one end of the capacitor C1, capacitor C7, capacitor C13, and the 3rd pin of the common-mode suppressor T1, the 3rd pin of the common-mode suppressor T2, and the 3rd pin of the common-mode suppressor T3; the negative pole of the power supply is respectively connected to the other end of the capacitor C1, capacitor C7, capacitor C13, and the 2nd pin of the common-mode suppressor T1, the 2nd pin of the common-mode suppressor T2, and the 2nd pin of the common-mode suppressor T3 through pin 2 of the external interface XP1 and then grounded; the 4th pin of the common-mode suppressor T1, the 4th pin of the common-mode suppressor T2, and the 4th pin of the common-mode suppressor T3 are respectively connected to one end of the capacitor C2, one end of the inductor L1, one end of the capacitor C8, one end of the inductor L3, one end of the capacitor C14, and one end of the inductor L5; the other end of the inductor L1 is respectively connected to one end of the capacitor C3, one end of the capacitor C4, and pins 1 and 2 of the low-voltage power supply output module M1; the 1st pin of the common-mode suppressor T1 is respectively connected to the other ends of the capacitor C2, capacitor C3, capacitor C4, and pins 3 and 4 of the low-voltage power supply output module M1 and then grounded; the other end of the inductor L3 is respectively connected to one end of the capacitor C9, one end of the capacitor C10, and pin 1 of the low-voltage power supply output module M2; the 1st pin of the common-mode suppressor T2 is respectively connected to the other ends of the capacitor C8, capacitor C9, capacitor C10, and pins 2 and 5 of the low-voltage power supply output module M2 and then grounded; the other end of the inductor L5 is respectively connected to one end of the capacitor C15, one end of the capacitor C16, and pins 1 and 2 of the low-voltage power supply output module M3; the 1st pin of the common-mode suppressor T3 is respectively connected to the other ends of the capacitor C14, capacitor C15, capacitor C16, and pins 3 and 4 of the low-voltage power supply output module M3 and then grounded; pin 10 of the low-voltage power supply output module M1 is connected to one end of the inductor L2 and one end of the capacitor C5, and the other end of the inductor L2 is connected to one end of the capacitor C6 to serve as the low-voltage power supply output VCC1; pins 8 of the low-voltage power supply output module M1, the other end of the capacitor C5, and the other end of the capacitor C6 are grounded; pin 3 of the low-voltage power supply output module M2 is connected to one end of the inductor L4 and one end of the capacitor C11, and the other end of the inductor L4 is connected to one end of the capacitor C12 to serve as the bias power supply output VBB; pins 4 of the low-voltage power supply output module M2, the other end of the capacitor C11, and the other end of the capacitor C12 are grounded; pin 10 of the low-voltage power supply output module M3 is connected to one end of the inductor L6 and one end of the capacitor C17, and the other end of the inductor L6 is connected to one end of the capacitor C18 to serve as the low-voltage power supply output VCC2; pins 8 of the low-voltage power supply output module M3, the other end of the capacitor C17, and the other end of the capacitor C18 are grounded.

[0020] The low-voltage power supply output modules M1 and M3 select DC / DC isolated power supplies with an input range of 18 - 36V and an adjustable output of 3.3 - 5V. The bias power supply output module M2 selects a DC / DC isolated power supply with an input range of 18 - 36V and an adjustable output of 85 - 120V. Differential-mode and common-mode interference filtering circuits are placed at the inputs of the low-voltage power supply output modules M1, M3, and the bias power supply output module M2, and a differential-mode interference filtering circuit is placed at the outputs.

[0021] Refer to Figure 4 For the microprocessor part of the system, it includes a main control chip N1 of model ATmega128L, a crystal oscillator G1 of model 7W-7.3728MBB, a 10-pin drive download interface XP3. Pin 1 of the main control chip N1 is connected to the power supply VCC1 through a resistor R2, and at the same time is connected to the positive pole of the light-emitting diode Ted1 through a resistor R1. The negative pole of the light-emitting diode Ted1 is connected to pin 3 of the triode Q1. Pin 1 of the triode Q1 is connected to one end of a resistor R6 and one end of a resistor R10. The other end of the resistor R6 is connected to pin 10 of the main control chip N1 through a resistor R4, and at the same time is connected to pin 25 of the main control chip N1 through a resistor R8. Pin 1 of the triode Q1 is grounded through a resistor R10 to pin 2 of the triode Q1. Pin 24 of the main control chip N1 is connected to pin 3 of the crystal oscillator G1 through a capacitor C44, and pin 2 of the crystal oscillator G1 is grounded. Pin 4 of the crystal oscillator G1 and pin 21 of the main control chip N1 are connected to the power supply VCC1. Pin 64 of the main control chip N1 is respectively connected to one end of a capacitor C19 and an inductor L7. The other end of the inductor L7, capacitors C20, C21, C22, C23 are connected to the power supply VCC1. The other ends of the capacitors C19, C20, C21, C22, C23 and pin 63 of the main control chip N1 are grounded. Pin 62 of the main control chip N1 is connected to one end of a capacitor C24, and the other end of the capacitor C24 is grounded. Pin 52 of the main control chip N1 is connected to the power supply VCC1. Pins 54, 55, 56, 57 of the main control chip N1 are respectively connected to resistors R9, R7, R5, R3 through pins 1, 5, 3, 9 of the 10-pin drive download interface XP3 and then connected to the power supply VCC1. Pin 4 of the 10-pin drive download interface XP3 is connected to pin 7 of the drive download interface XP3 and one end of a capacitor C42 through a resistor R14, and the other end of the capacitor C42 and pin 10 of the drive download interface XP3 are grounded.

[0022] Refer to Figure 5 and Figure 6, the aging tooling part of the system includes a 10-pin drive download interface XP2, a 20-hole tooling fixture interface XP4, an aging workpiece selection chip N2 of model SN74LVC827A, radio frequency switch chips N3 and N4 both of model HMC253AQS24; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, Pin 8, Pin 9, and Pin 10 of the 10-pin drive download interface XP2 are sequentially connected to Pin 23, Pin 22, Pin 21, Pin 20, Pin 19, Pin 18, Pin 17, Pin 16, Pin 15, and Pin 14 of the aging workpiece selection chip N2; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, Pin 8, Pin 9, and Pin 10 of the aging workpiece selection chip N2 are sequentially connected to Pin 51, Pin 50, Pin 49, Pin 48, Pin 47, Pin 46, Pin 45, Pin 44, Pin 35, and Pin 36 of the main control chip N1; Pin 1 and Pin 13 of the aging workpiece selection chip N2 are connected to Pin 10 of the main control chip N1; Pin 24 of the aging workpiece selection chip N2 is connected to the power supply VCC2; Pin 1 of the 20-hole tooling fixture interface XP4 is connected to Pin 4 of the radio frequency switch chip N3 through a capacitor C25, Pin 10 of the 20-hole tooling fixture interface XP4 is connected to Pin 4 of the radio frequency switch chip N4 through a capacitor C34, and Pin 4, Pin 5, Pin 6, Pin 7, Pin 8, and Pin 9 of the 20-hole tooling fixture interface XP4 are connected to the ground; Pin 11, Pin 12, Pin 13, Pin 14, Pin 15, Pin 16, Pin 17, Pin 18, Pin 19, and Pin 20 of the 20-hole tooling fixture interface XP4 are sequentially connected to Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, Pin 8, Pin 9, and Pin 10 of the 10-pin drive download interface XP2; Pin 2 of the 20-hole tooling fixture interface XP4 is respectively connected to Pin 11 of the radio frequency switch chip N3 and the radio frequency switch chip N4, and Pin 3 of the 20-hole tooling fixture interface XP4 is connected to the bias power supply output VBB of the power supply; Pin 12 of the radio frequency switch chip N3 and Pin 12 of the radio frequency switch chip N4 are respectively connected to Pin 59 of the main control chip N1 through a resistor R11 and a resistor R16; Pin 14, Pin 13 of the radio frequency switch chip N3 and Pin 14, Pin 13 of the radio frequency switch chip N4 are respectively connected to Pin 61, Pin 60 of the main control chip N1 through a resistor R13, a resistor R12, a resistor R15, and a resistor R17; Pin 1 of the radio frequency switch chip N3 is connected to Pin 1 of the radio frequency transfer terminal Z1, and Pin 2 of the radio frequency transfer terminal Z1 is connected to the ground; Pin 2, Pin 3, Pin 5, Pin 7, Pin 16, Pin 18, Pin 20, Pin 22, Pin 23, and Pin 24 of the radio frequency switch chip N3 are connected to the ground; Pin 1 of the radio frequency switch chip N4 is connected to Pin 1 of the radio frequency transfer terminal Z2, and Pin 2 of the radio frequency transfer terminal Z2 is connected to the ground; Pin 2, Pin 3, Pin 5, Pin 7, Pin 16, Pin 18, Pin 20, Pin 22, Pin 23, and Pin 24 of the radio frequency switch chip N4 are connected to the ground.

[0023] The old workpiece is installed on the 20-hole fixture interface XP4; the RF adapter terminals Z1 and Z2 are connected to the network analyzer by plugging in the RF test cables.

Claims

1. A digitally controlled frequency hopping filter aging system, characterized in that: It includes power supply, upper computer with installed network analyzer driver and lower computer program components, lower computer with aging program downloaded by microprocessor, aging equipment, and network analyzer; The power supply is connected to the lower computer as the power input of the lower computer, the upper computer is connected to the lower computer through a serial port line, the lower computer is connected to the network analyzer through a network cable, the lower computer is connected to the aging equipment through a belt line, the aging equipment is used to install the aged workpiece, and the aging equipment is connected to the network analyzer through a radio frequency test cable.

2. The digital controlled frequency hopping filter aging system according to claim 1, characterized in that: The power supply part includes a single-pole double-throw switch S1, a common-mode suppressor T1, a common-mode suppressor T2, a common-mode suppressor T3, a low-voltage power supply output module M1, a bias power supply output module M2, and a low-voltage power supply output module M3; the specific circuit connection is: the positive electrode of the power supply is connected in series with the single-pole double-throw switch S1 through pin 1 of the external interface XP1, and the single-pole double-throw switch S1 is respectively connected to one end of the capacitor C1, the capacitor C7, and the capacitor C13 and pin 3 of the common-mode suppressor T1, pin 3 of the common-mode suppressor T2, and pin 3 of the common-mode suppressor T3; the negative electrode of the power supply is respectively connected to the other end of the capacitor C1, the capacitor C7, and the capacitor C13 and pin 2 of the common-mode suppressor T1, pin 2 of the common-mode suppressor T2, and pin 2 of the common-mode suppressor T3 through pin 2 of the external interface XP1, and then grounded; The 4th pin of the common mode suppressor T1, the 4th pin of the common mode suppressor T2, and the 4th pin of the common mode suppressor T3 are respectively connected to one end of the capacitor C2, one end of the inductor L1, one end of the capacitor C8, one end of the inductor L3, one end of the capacitor C14, and one end of the inductor L5; the other end of the inductor L1 is respectively connected to one end of the capacitor C3, one end of the capacitor C4, and the 1st pin and the 2nd pin of the low voltage power supply output module M1; Pin 1 of the common mode suppressor T1 is respectively connected to the other ends of capacitors C2, C3, C4 and pins 3 and 4 of the low voltage power supply output module M1 and then grounded; the other end of the inductor L3 is respectively connected to one end of capacitor C9, one end of capacitor C10 and pin 1 of the low voltage power supply output module M2; The pin 1 of the common mode suppressor T2 is respectively connected to the other end of the capacitor C8, the capacitor C9, the capacitor C10 and the pin 2 and pin 5 of the low voltage power supply output module M2 and then grounded; the other end of the inductor L5 is respectively connected to one end of the capacitor C15, one end of the capacitor C16 and the pin 1 and pin 2 of the low voltage power supply output module M3; the pin 1 of the common mode suppressor T3 is respectively connected to the other end of the capacitor C14, the capacitor C15, the capacitor C16 and the pin 3 and pin 4 of the low voltage power supply output module M3 and then grounded; The 10th foot of the low-voltage power supply output module M1 is connected to one end of the inductor L2 and one end of the capacitor C5, and the other end of the inductor L2 is connected to one end of the capacitor C6 to serve as the low-voltage power supply output power VCC1; the 8th foot of the low-voltage power supply output module M1, the other end of the capacitor C5, and the other end of the capacitor C6 are grounded; the 3rd foot of the low-voltage power supply output module M2 is connected to one end of the inductor L4 and one end of the capacitor C11, and the other end of the inductor L4 is connected to one end of the capacitor C12 to serve as the bias power supply output power VBB; Pin 4 of the low-voltage power supply output module M2, the other end of the capacitor C11, and the other end of the capacitor C12 are grounded; Pin 10 of the low-voltage power supply output module M3 is connected to one end of the inductor L6 and one end of the capacitor C17, and the other end of the inductor L6 is connected to one end of the capacitor C18 to serve as the low-voltage power supply output power source VCC2; Pin 8 of the low voltage power supply output module M3, the other end of the capacitor C17, and the other end of the capacitor C18 are grounded.

3. The digital controlled frequency hopping filter aging system according to claim 2, characterized in that: The microprocessor part of the system includes a main control chip N1 of model ATmega128L, a crystal oscillator G1 of model 7W-7.3728MBB, and a 10-pin driver download interface XP3. Pin 1 of the main control chip N1 is connected to the power supply VCC1 through a resistor R2, and is connected to the positive electrode of the light-emitting diode Ted1 through a resistor R1. The negative electrode of the light-emitting diode Ted1 is connected to pin 3 of the transistor Q1. Pin 1 of the transistor Q1 is connected to one end of the resistor R6 and one end of the resistor R10. The other end of the resistor R6 is connected to pin 10 of the main control chip N1 through a resistor R4, and is connected to pin 25 of the main control chip N1 through a resistor R8; pin 1 of the transistor Q1 is grounded to pin 2 of the transistor Q1 through a resistor R10; Pin 24 of the main control chip N1 is connected to pin 3 of the crystal oscillator G1 through capacitor C44, and pin 2 of the crystal oscillator G1 is grounded; pin 4 of the crystal oscillator G1 and pin 21 of the main control chip N1 are connected to the power supply VCC1; The 64th pin of the main control chip N1 is connected to one end of the capacitor C19 and the inductor L7 respectively, the other end of the inductor L7, the capacitor C20, the capacitor C21, the capacitor C22, the capacitor C23 are connected to the power supply VCC1, the other ends of the capacitors C19, C20, C21, C22, the capacitor C23 and the 63rd pin of the main control chip N1 are grounded; the 62nd pin of the main control chip N1 is connected to one end of the capacitor C24, the other end of the capacitor C24 is grounded, and the 52nd pin of the main control chip N1 is connected to the power supply VCC1; Pins 54, 55, 56 and 57 of the main control chip N1 are connected to resistors R9, R7, R5 and R3 through pins 1, 5, 3 and 9 of the 10-pin driver download interface XP3 respectively, and then connected to the power supply VCC1; Pin 4 of the 10-pin driver download interface XP3 is connected to pin 7 of the driver download interface XP3 and one end of a capacitor C42 through a resistor R14, and the other end of the capacitor C42 and pin 10 of the driver download interface XP3 are grounded.

4. The digital controlled frequency hopping filter aging system according to claim 3, characterized in that: The aging workpiece part of the system includes 10-pin driver download interface XP2, 20-hole fixture interface XP4, aging workpiece selection chip N2 with model SN74LVC827A, RF switch chip N3 and RF switch chip N4 with model HMC253AQS24; Pin 1, Pin 2, Pin 3, Pin 4, Pin 5, Pin 6, Pin 7, Pin 8, Pin 9, and Pin 10 of the 10-pin driver download interface XP2 are connected to Pin 23, Pin 22, Pin 21, Pin 20, Pin 19, Pin 18, Pin 17, Pin 16, Pin 15, and Pin 14 of the aging workpiece selection chip N2 in sequence; The aging workpiece selects the 1st, 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 9th and 10th pins of the chip N2 to correspond to the 51st, 50th, 49th, 48th, 47th, 46th, 45th, 44th, 35th and 36th pins of the main control chip N1 in sequence; The aging workpiece selection chip N2's pins 1 and 13 are connected to the main control chip N1's pin 10; The 24th pin of the aging workpiece selection chip N2 is connected to the power supply VCC2; Pin 1 of the 20-hole fixture interface XP4 is connected to pin 4 of the RF switch chip N3 via capacitor C25, pin 10 of the 20-hole fixture interface XP4 is connected to pin 4 of the RF switch chip N4 via capacitor C34, and pins 4, 5, 6, 7, 8, and 9 of the 20-hole fixture interface XP4 are connected to the ground; Pins 11, 12, 13, 14, 15, 16, 17, 18, 19 and 20 of the 20-hole fixture interface XP4 correspond to pins 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10 of the 10-pin driver download interface XP2 in sequence; Pin 2 of the 20-hole fixture interface XP4 is connected to pins 11 of the RF switch chip N3 and the RF switch chip N4 respectively, and pin 3 of the 20-hole fixture interface XP4 is connected to the bias power supply output VBB of the power supply; The 12th pin of the RF switch chip N3 and the 12th pin of the RF switch chip N4 are connected to the 59th pin of the main control chip N1 through the resistor R11 and the resistor R16 respectively; the 14th pin and the 13th pin of the RF switch chip N3 and the 14th pin and the 13th pin of the RF switch chip N4 are connected to the 61st pin and the 60th pin of the main control chip N1 through the resistor R13, the resistor R12, the resistor R15 and the resistor R17 respectively; Pin 1 of the RF switch chip N3 is connected to pin 1 of the RF adapter terminal Z1, and pin 2 of the RF adapter terminal Z1 is connected to the ground; Pins 2, 3, 5, 7, 16, 18, 20, 22, 23 and 24 of the RF switch chip N3 are connected to the ground; Pin 1 of the RF switch chip N4 is connected to pin 1 of the RF adapter terminal Z2, and pin 2 of the RF adapter terminal Z2 is connected to the ground; Pins 2, 3, 5, 7, 16, 18, 20, 22, 23 and 24 of the RF switch chip N4 are connected to the ground.

5. The digital controlled frequency hopping filter aging system according to claim 4, characterized in that: The aging workpiece is installed on the 20-hole fixture interface XP4; the RF adapter terminal Z1 and the RF adapter terminal Z2 are connected to the network analyzer by plugging in the RF test cable.

6. An aging method using the digital controlled frequency hopping filter aging system according to any one of claims 1 to 5, characterized in that: The aging method has the following steps:

1. Install multiple aged CNC frequency-hopping filters on the old equipment, turn on the power, and the program control component of the upper computer sends an aging execution instruction to the lower computer through the serial port; Second, the lower computer executes the aging program to determine whether there is a faulty workpiece; 3. If there is a faulty workpiece, the indicator light of the faulty workpiece will light up and the system will automatically cut off the power supply of the faulty workpiece; 4. If there is no faulty workpiece, continue to execute the aging procedure; 5. After the aging program is completed, the aging process stops and the upper computer reads and saves the aging data of the lower computer.

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