Data processing system and method and photomultiplier

Abstract

The invention discloses a data processing system, and relates to the field of data processing. The data processing system is arranged on a photomultiplier, the data processing system comprises at least one data processing module, each data processing module comprises a plurality of first frames and at least one second frame, the plurality of first frames are located between a time-to-digital converter and the second frame, and the plurality of second frames are located between the time-to-digital converter and the time-to-digital converter. Each first frame corresponds to a rising edge channel or a falling edge channel, the plurality of first frames are used for decoding output data of the rising edge channels or the falling edge channels to obtain decoded data, and the second frame is used for judging the validity of a corresponding photon event according to the decoded data. According to the data processing system, the data processing efficiency is high, the functions of completing screening of effective photon events on a photomultiplier chip and extracting effective information are achieved, the data transmission amount is effectively reduced, and the transmission speed is high.

Description

Technical Field

[0001] The present application relates to the field of data processing, and more particularly to a data processing system, method, and photomultiplier tube. Background Art

[0002] An analog silicon photomultiplier (English name: Silicon Photomultiplier, English abbreviation: SiPM) sums the avalanche currents output by each micro-pixel unit (English name: Microcell, English abbreviation: MC) at a node to convert an optical signal into a scintillation pulse, and can directly use a single time-to-digital converter (English name: TimeTo Digital Convert, English abbreviation: TDC) to sample the scintillation pulse to complete the timestamp extraction of photon events. In contrast, in a digital SiPM, each MC outputs a digital signal, and the digital outputs of all MCs are sent to the TDC for sampling through an OR logic to obtain a timestamp. Under this architecture, the first digital SiPM chip was proposed by Thomas Frach et al. in 2009. The chip integrates MC, TDC, and photon counters respectively. Each MC is connected to a separate transistor for active quenching, and is connected to the TDC through a configurable trigger network to obtain the time information of the event. All MCs are connected to the counter through a single synchronization bus to collect the number of triggered MCs during the event occurrence as the energy information of the event.

[0003] Digital SiPM shows great development potential in photon event detection, such as in PET systems, and is developing towards higher detection performance and efficiency. However, the current readout system of digital SiPM usually has problems such as using a pre-discrimination processing method, resulting in a decrease in the counting rate; relatively simple processing logic, a large output interface, and a low operating frequency. These problems limit the digital SiPM's difficulty in meeting the requirements of high real-time detection in terms of counting rate and transmission rate. Therefore, how to balance the data transmission volume and transmission rate in a multi-measurement channel chip architecture, improve the processing speed, and meet the requirements of digital SiPM in high real-time detection application scenarios is still very important.

[0004] The content described in the background art is only for facilitating the understanding of the related technologies in this field and is not regarded as an admission of the prior art. Summary of the Invention

[0005] Therefore, the present application intends to provide a data processing system, a photomultiplier tube, and an application of the data processing system, which can solve at least one problem existing in the prior art.

[0006] In a first aspect, a data processing system is provided. The data processing system is disposed on a photomultiplier tube, and the data processing system includes: At least one data processing module, each of the data processing modules includes a plurality of first frames and at least one second frame. A plurality of the first frames are all located between the time-to-digital converter and the second frame, and each of the first frames corresponds to a rising-edge channel or a falling-edge channel. The plurality of first frames are configured to decode the output data of the rising-edge channel or the falling-edge channel to obtain decoded data, and the second frame is configured to determine the validity of the corresponding photon event according to the decoded data.

[0007] In an embodiment of the present application, the plurality of first frames are arranged in parallel.

[0008] In an embodiment of the present application, the number of the first frames connected to the rising-edge channel is the same as the number of the first frames connected to the falling-edge channel.

[0009] In an embodiment of the present application, the first frame detects a data conversion flag signal of the corresponding rising-edge channel or falling-edge channel. After detecting a change in the data conversion flag signal, the first frame latches the fine-count measurement data output by the time-to-digital converter.

[0010] In an embodiment of the present application, the first frame is further configured to generate an error code error signal when there is an error code after the fine-count measurement data is decoded.

[0011] In an embodiment of the present application, the first frame is configured to select an operating mode according to a data output mode control signal output by the time-to-digital converter, including: When the data output mode control signal is at a low level, the first frame is configured to output the decoded data in a normal mode; When the data output mode control signal is at a high level, the first frame is configured to output the original data of the corresponding channel in a test mode, and the original data is stored as a detection signal by the second frame.

[0012] In an embodiment of the present application, the second frame is configured to select an operating mode according to a data output mode control signal output by the time-to-digital converter, including: When the data output mode control signal is at a low level, the second frame is configured to extract valid events according to the decoded data in a normal mode; When the data output mode control signal is at a high level, the second frame is configured to store the original data of the corresponding channel as a detection signal in a test mode.

[0013] In an embodiment of the present application, the second framework includes an effective event extraction module, the effective event extraction module is connected to all the first frameworks, and the effective event extraction module has at least one of an idle state, a rising edge acquisition state, a falling edge acquisition state, a delay state, an end state, and a waiting state.

[0014] In an embodiment of the present application, the initial state of the second framework is the idle state. When the valid flag signal of the lowest count threshold of the digital count pulse rising edge is detected as high at the clock rising edge, it enters the rising edge acquisition state.

[0015] In an embodiment of the present application, when the second framework enters the rising edge acquisition state, the counter starts counting and latches the count value. The second framework detects the valid flag signal of the highest count threshold at each clock rising edge and latches the decoded data. If the valid flag signal of the highest count threshold is low within the first preset number of clocks, it is determined that the corresponding photon event is an invalid event.

[0016] In an embodiment of the present application, if the valid flag signal of the highest count threshold is high within the first preset number of clocks, the second framework enters the falling edge acquisition state and latches all the data acquired in the rising edge acquisition state.

[0017] In an embodiment of the present application, if in the initial state, the second framework detects that the valid flag signal of the highest count threshold of the digital count pulse rising edge at the clock rising edge is high, the second framework enters the falling edge acquisition state.

[0018] In an embodiment of the present application, in the falling edge acquisition state of the second framework, if within the second preset number of clocks, there is a valid flag signal of the lowest count threshold of the digital count pulse falling edge that is high, the corresponding photon event is a valid event, and the decoded data corresponding to the digital count pulse falling edge at each clock rising edge is latched.

[0019] In an embodiment of the present application, when the second framework acquires a valid event in the falling edge acquisition state, it enters the delay state, maintains the third preset number of clocks, and latches the decoded data of each clock rising edge.

[0020] In an embodiment of the present application, after the second framework maintains the third preset number of clocks in the delay state, it enters the end state, generates a valid flag for packet completion, and maintains the fourth preset number of clocks in the end state.

[0021] In an embodiment of the present application, after the second framework maintains the fourth preset number of clocks in the end state, it enters the waiting state, and after continuing the fifth preset number of clocks in the waiting state, it enters the idle state, waiting for a new photon event to arrive.

[0022] In an embodiment of the present application, the data processing system further includes a counter, which is connected to all the data processing modules and is used to calibrate the coarse time measured by the data processing modules.

[0023] In an embodiment of the present application, the second framework uses the count value corresponding to the high level of the valid flag information of the first channel in the rising edge channel as the initial time of the corresponding photon event.

[0024] In an embodiment of the present application, when the second framework is in the rising edge acquisition state, when it detects that the corresponding valid flag information is high at the rising edge of the clock, it latches the corresponding count value and uses it as the delay difference between the current channel and the first channel. The second framework uses the data, count values, and the delay difference latched by all channels as the output data of the data processing system.

[0025] In a second aspect, a method for processing data on a photomultiplier is provided, and the method includes: Receiving the output after the time-to-digital converter processes the digital counting pulses; Decoding the output data of the rising edge channel or the falling edge channel to obtain decoded data; Judging the validity of the corresponding photon event according to the decoded data.

[0026] In an embodiment of the present application, after receiving the output of the time-to-digital converter, it further includes: Detecting the rising edge of the data conversion flag signal of the corresponding channel, and latching the fine count measurement data output by the time-to-digital converter when detecting the falling edge of the first system working clock after the data conversion flag signal is high.

[0027] In an embodiment of the present application, the decoding the output data of the rising edge channel or the falling edge channel to obtain decoded data includes: Decoding the fine count measurement data through binary conversion to obtain the decoded data.

[0028] In an embodiment of the present application, the decoding the output data of the rising edge channel or the falling edge channel includes: If there is an error code after decoding the fine count measurement data through binary conversion, an error code error signal is generated.

[0029] In an embodiment of the present application, the method further includes: Selecting a working mode according to the data output mode control signal output by the time-to-digital converter, including: When the data output mode control signal is low, selecting the normal mode and extracting valid events according to the decoded data; When the data output mode control signal is at a high level, the test mode is selected, and the original data of the corresponding channel is stored as a detection signal.

[0030] In the embodiment of the present application, the determining the validity of the corresponding photon event according to the decoded data includes: Determining the validity of the corresponding photon event according to a pre-set counting threshold and the decoded data.

[0031] In the embodiment of the present application, the determining the validity of the corresponding photon event according to a pre-set counting threshold and the decoded data includes: When the valid flag signal of the lowest counting threshold is detected as high at the rising edge of the clock, switch from the idle state to the rising-edge acquisition state; When entering the rising-edge acquisition state, the counter starts counting and latches the count value, detects the valid flag signal of the highest counting threshold at each rising edge of the clock, and latches the decoded data. If within the first preset number of clocks, the valid flag signal of the highest counting threshold at the rising edge of the clock is at a low level, it is determined that the corresponding photon event is an invalid event; If within the first preset number of clocks, the valid flag signal of the highest counting threshold at the rising edge of the clock is at a high level, enter the falling-edge acquisition state, and latch all the data acquired in the rising-edge acquisition state; If the valid flag signal of the highest counting threshold at the rising edge of the clock is detected as high in the initial state, enter the falling-edge acquisition state, and latch the decoded data and the count value; In the falling-edge acquisition state, if within the second preset number of clocks, there is a valid flag signal of the lowest counting threshold at the falling edge of the digital counting pulse as high, the corresponding photon event is a valid event, and latch the decoded data corresponding to the falling edge of the digital counting pulse at each rising edge of the clock; When a valid event is acquired in the falling-edge acquisition state, enter the delay state, hold for the third preset number of clocks, and latch the decoded data at each rising edge of the clock; After holding for the third preset number of clocks in the delay state, enter the end state, generate a valid flag for completion of packing, and hold for the fourth preset number of clocks in the end state; After holding for the fourth preset number of clocks in the end state, enter the waiting state, and after continuing for the fifth preset number of clocks in the waiting state, enter the idle state, waiting for a new photon event to arrive.

[0032] In the embodiment of the present application, the method further includes: Taking the count value corresponding to the valid flag information of the first channel in the rising-edge channel being high as the initial time of the corresponding photon event.

[0033] In an embodiment of the present application, the method further includes: In the rising edge acquisition state, when the valid flag information of the corresponding channel is detected as high level at the rising edge of the clock, the corresponding count value is latched and used as the time delay difference between the channel and the first channel; The valid event, the count value, and the time delay difference are used as the output data of the photomultiplier.

[0034] In a third aspect, a photomultiplier is provided, including the data processing system provided in the first aspect.

[0035] The data processing system provided in the present application, in the first aspect, parallelly processes the TDC data of multiple channels through the first framework, with high data processing efficiency, and simultaneously realizes the functions of decoding, error detection, and TDC status detection; in the second aspect, screens and discriminates events through the second framework, realizes the function of screening valid photon events and extracting valid information on the photomultiplier chip, solves the problem of loss of valid events when setting a lower counting threshold, and is of great significance for optimizing the time resolution of digital SiPM; in the third aspect, compared with the prior art, the data screening step is moved to the data processing stage instead of the MC acquisition stage, which will not cause many valid events to be mis-screened and improves the counting rate; in the fourth aspect, the second framework processes and compresses the data after extracting the valid events, effectively reducing the data transmission volume; in the fifth aspect, through the features of multi-channel parallel processing of the first framework and event screening and data compression of the second framework, the processing of a single photon event can be completed within 300 ns, and the transmission speed is fast. The output of a single photon event can be completed within 300 ns, solving the bottleneck problems such as low event acquisition rate and long acquisition and transmission process in real-time detection of digital SiPM.

[0036] Some of the optional features and other effects of the embodiments of the present application are described below, and some can be understood by reading this article. Description of the Drawings

[0037] The present application will be further described by way of exemplary embodiments, which will be described in detail through the drawings. These embodiments are not restrictive. In these embodiments, the same reference numerals represent the same structures, where: Figure 1 Shows the architecture diagram of the data processing system according to an embodiment of the present application; Figure 2 Shows the schematic diagram of the first framework of the data processing system according to an embodiment of the present application; Figure 3 Shows the timing diagram of the first framework of the data processing system according to an embodiment of the present application; Figure 4Shows a schematic diagram of digital counting pulses according to an embodiment of the present application; Figure 5 Shows a schematic diagram of a second framework of a data processing system according to an embodiment of the present application; Figure 6 Shows a schematic diagram of a second framework of a data processing system according to a specific embodiment of the present application; Figure 7 Shows a timing diagram of a second framework of a data processing system according to an embodiment of the present application; Figure 8 Shows a schematic diagram of a state machine of a second framework of a data processing system according to an embodiment of the present application; Figure 9 Shows a schematic diagram of a state machine of a second framework of a data processing system according to a specific embodiment of the present application; Figure 10 Shows a schematic diagram of a second framework of a data processing system according to a specific embodiment of the present application; Figure 11 Shows a timing diagram of a data conversion module of a second framework of a data processing system according to a specific embodiment of the present application; Figure 12 Shows an architecture diagram of a data processing system according to a specific embodiment of the present application; Figure 13 Shows a schematic flowchart of a data processing method according to an embodiment of the present application. Detailed implementation manners

[0038] To make the above objects, features, and advantages of the present application more apparent and understandable, the following will describe the detailed implementation manners of the present application in conjunction with the accompanying drawings. Many specific details are set forth in the following description in order to fully understand the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0039] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only. The described features, structures or characteristics can be combined in one or more embodiments in any suitable manner. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present application. However, those skilled in the art will realize that the technical solutions of the present application can be practiced without one or more of these specific details, or other means, components, materials, devices or operations, etc. can be adopted. In these cases, well-known structures, methods, devices, implementations, materials or operations will not be shown or described in detail.

[0040] The flowcharts shown in the accompanying drawings are only illustrative and do not necessarily include all the contents and operations / steps, nor are they necessarily executed in the order described. For example, some operations / steps can be decomposed, while some operations / steps can be combined or partially combined, so the actual execution order may be changed according to the actual situation.

[0041] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0043] The Digital Photon Counter (DPC) introduced by Philips is the first commercial digital SiPM. Seifert et al. used this device to verify its potential in TOF-PET (Time Of Flight - Positron Emission Computed Tomography) detectors. The DPC includes a 2×2 pixel array, a TDC, and a trigger module. Each pixel integrates 4 sub-pixel arrays. The trigger logic selects four thresholds based on the trigger counts of different sub-pixels. After reaching the threshold, it enters the verification logic to determine whether the event is a photon event or a dark pulse. After passing the verification, it enters the data acquisition stage. The acquired time and energy information are transmitted through a 200Mbit / s serial link. Although the data volume is small, due to pre-discrimination before acquisition, some events are excluded before acquisition, affecting the count rate. Moreover, the architecture is affected by saturation, crosstalk, and dark counts, and the time information only records the trigger timestamp, making its performance more similar to that of a semi-digital SiPM.

[0044] In 2011, the digital SiPM architecture proposed by Veerappan was closer to an image sensor. It used a 160×128 MC array. Each MC integrated an independent 10-bit TDC. The data was output in parallel through 320 independent serial interfaces at a maximum rate of 160Mbit / s, and a single event could be transmitted within 4μs. The digital SiPM designed by Fischer in 2014 also adopted a similar architecture, using an 88×88 MC array. Each MC integrated a memory and a TDC. However, the output rate of the chip was relatively slow, with a maximum readout rate of 400 events / s, greatly increasing the photon information readout time. Although this architecture provided more accurate single-photon event analysis, the large amount of data collected and transmitted increased the interface transmission pressure, limiting its application in PET systems.

[0045] Cristiano et al. designed an optical sensor only for time resolution measurement, which uses 32 TDCs, a 128×128 single-photon pixel array, and a high-speed readout system. Through efficient data transmission and processing, this sensor improves the sampling and transmission speed of photon information and supports a transmission rate of up to 7.68 Gbps. The data of each pixel can be decoded by row and column selection signals, enabling 32 TDCs to share the measurement of the pixel output time to process the data of multiple pixels simultaneously. Moreover, to improve the acquisition efficiency, the TDC data is collected in parallel through a 4:1 time multiplexer, reducing the data acquisition time. However, this design architecture has high requirements for clock frequency, process, and circuit, and the 7.68 Gbps high-speed interface requires a large number of parallel outputs, which is not very practical for the case of limited chip area.

[0046] As mentioned above, in the technologies known to the inventors, digital SiPMs have shown great development potential in photon event detection and have higher detection performance and efficiency compared with analog SiPMs. However, the existing readout systems of digital SiPMs generally adopt a pre-discrimination processing method. For example, in the optical sensor designed by Cristiano et al. for detecting time resolution, after an event arrives, the pixels in each row are address-decoded through row and column selection signals to ensure that only the data of the selected pixels are read out, resulting in a decrease in the counting rate. Moreover, the processing logic output interface is huge, restricting the counting rate and transmission rate of digital SiPMs and making it difficult to meet the high real-time detection requirements.

[0047] In response to this, the present application provides a data processing system, which is disposed on a photomultiplier, and the photomultiplier is preferably a digital SiPM. The data processing system can be applied in multiple fields, such as scientific instruments, medical equipment, high-energy physics, deep space and deep sea exploration, extremely weak light imaging, radiation monitoring, autonomous driving, security inspection equipment, consumer electronics, or smart home appliances, etc. Taking medical equipment as an example, it can be applied in PET equipment. In this scenario, the photomultiplier, scintillation crystal, and some electronic devices together form a detector. The front end of the photomultiplier is coupled to the scintillation crystal. After the scintillation crystal receives 511 keV Gamma rays, it converts them into visible light photons and outputs them to the photomultiplier, and the photomultiplier performs a series of processes on the visible light photons and then outputs. The data processing system is integrated in the photomultiplier. In addition, an MC array, a digital readout circuit, a comparator, a TDC, etc. can also be provided in the photomultiplier. When a photon event occurs, the visible light photons are detected by the MC array and converted into digital counting pulses one by one via the digital interface circuit. The digital readout circuit counts all the counting information of the MC array and compares it with a preset counting threshold in the comparator. The TDC records the time points when all the digital counting pulses pass through the counting threshold, and the data processing system decodes to obtain all the "counting threshold - time" information pairs of this event.

[0048] Figure 1 FIG. shows the architecture diagram of the data processing system according to an embodiment of the present application. To more clearly show the data processing system provided by the present application, in combination with Figure 1 it is described as follows. Generally, the data processing system includes: at least one data processing module 100. The number of data processing modules 100 is related to the readout method of the front-end MC array. When the MC array is read out in two parts, the number of data processing modules 100 is two. When the MC array is read out in three parts, the number of data processing modules 100 is three, and so on. It should be particularly noted that when the number of MCs in the MC array is certain, the number of data processing modules 100 is generally proportional to the data processing efficiency and data processing accuracy, and inversely proportional to the manufacturing cost of the photomultiplier.

[0049] Each of the data processing modules 100 includes a plurality of first frames 110 and at least one second frame 120. The plurality of first frames 110 are all located between the time-to-digital converter and the second frame 120, and each first frame 110 corresponds to a rising-edge channel or a falling-edge channel. The number of the first frames 110 is related to the counting threshold set for screening events. In an application scenario, four counting thresholds are set, and four channels correspond to both the rising edge and the falling edge of the digital counting pulse. Then, eight first frames 110 are correspondingly set. Each first frame 110 corresponds to a rising-edge channel or a falling-edge channel, and the number of the first frames 110 connected to the rising-edge channel is the same as that of the first frames 110 connected to the falling-edge channel. The plurality of first frames 110 are used to decode the output data of the rising-edge channel or the falling-edge channel to obtain decoded data. The plurality of first frames 110 are arranged in parallel, so as to process the output data of N rising-edge channels and the output data of N falling-edge channels in parallel. Among them, the rising-edge channel indicates that the corresponding TDC detects the rising edge of the digital counting pulse. Correspondingly, the falling-edge channel indicates that the corresponding TDC detects the falling edge of the digital counting pulse. The second frame 120 is used to judge the validity of the corresponding photon event according to the decoded data. In an example, the number of the second frames 120 is one, which is connected to all the first frames 110, receives the data decoded by all the first frames 110, extracts valid events, and finally outputs the data in the order of the occurrence of the valid events. When the number of the first frames 110 is small, such as only eight in the above example, the number of the second frames 120 is generally set to one to meet the data processing requirements. However, when the number of the first frames 110 is large, resulting in a large amount of data processing and one second frame 120 being unable to meet the data processing requirements, multiple second frames 120 can be set. It should be noted that when multiple second frames 120 are set, the data processed by the multiple second frames 120 needs to be fused to finally obtain the valid event data.

[0050] Figure 2 is a schematic diagram of the first frame of the data processing system according to an embodiment of the present application. As Figure 2 shown, each first frame 110 is used to receive the system working clock signal CLK, the fine-count measurement data TDC_DATA_I[A-1:0], and the data conversion flag TDC_VALID. Among them, the CLK is provided by the system clock, and both the TDC_DATA_I[A-1:0] and the TDC_VALID are output by the TDC. The first frame 110 performs corresponding actions or processes related data according to the above data, and then outputs the decoded data and the channel data valid flag information.

[0051] Specifically, the first frame 110 detects the TDC_VALID of the corresponding channel. When the first falling edge of the system working clock after detecting that the TDC_VALID is at a high level occurs, the fine-count measurement data output by the time-to-digital converter is latched for subsequent processing. After the latching is completed, the first frame 110 decodes the fine-count measurement data through binary conversion to obtain the decoded data. If there is an error code after the fine-count measurement data is decoded through binary conversion, the first frame 110 generates an error code error signal to implement the function of error code identification.

[0052] Figure 3 Shows the timing diagram of the first frame of the data processing system according to an embodiment of the present application. In one example, in combination with Figure 3 , the fine-count measurement data includes VDL_I[31:0] and DLL_I[15:0]. For example, in the specific decoding process, first, the latched 32-bit thermometer code VDL_I[31:0] is decoded into a 6-bit binary code through data decoding, and then the 16-bit binary code DLL_I[15:0] is decoded into a 4-bit binary code, and it is determined whether there is an error code in the 6-bit binary code and the 4-bit binary code. If there is an error code, a dec_err decoding error signal is generated.

[0053] In addition to being able to decode data and detect error codes, the data processing module 100 can also assist in the state detection of the TDC. Specifically, in one example, each first frame 110 is further configured to receive the data output mode control signal DATA_SEL output by the TDC and select the working mode according to DATA_SEL. When DATA_SEL is at a low level, the first frame 110 selects the normal mode, decodes the fine-count measurement data, and outputs the decoded data; when DATA_SEL is at a high level, the first frame 110 selects the test mode and outputs the raw data of the corresponding channel. The raw data is stored as a detection signal by the second frame 120. For example, in the normal mode, the CH_FRAME_OUT output of the first frame 110 is a combination of the TDC decoded data, and the valid data is a total of 10 bits; in the test mode, the CH_FRAME_OUT output is the raw data that has not been decoded, and the raw data is a 48-bit data formed by combining VDL_I[31:0] and DLL_I[15:0].

[0054] Further, the second frame 120 can also select an operating mode according to the data output mode control signal output by the time-to-digital converter. Here, in one example, after receiving the data output mode control signal DATA_SEL, when outputting data, the first frame 110 outputs DATA_SEL to the second frame 120 together; in another example, in addition to being connected to the first frame 110 for data transmission, the TDC is also connected to the second frame 120 for data transmission. As Figure 5 shown, the second frame 120 directly receives DATA_SEL from the TDC without being forwarded by the first frame 110. In comparison, the processing efficiency of this method is higher.

[0055] Specifically, the details of the second frame 120 selecting an operating mode according to DATA_SEL include: when the data output mode control signal is at a low level, the second frame 120 selects the normal mode and extracts valid events according to the decoded data; when the data output mode control signal is at a high level, the second frame 120 selects the test mode and stores the raw data of the corresponding channel as a detection signal. Exemplarily, in the normal mode, the second frame 120 combines and packs relevant data to form 152-bit valid data and outputs it outside the system; in the test mode, the second frame 120 outputs the 48-bit TDC original code for external devices to test the state of the TDC.

[0056] Regarding the output of the first frame 110, continue to refer to Figure 2 , in addition to the above CH_FRAME_OUT, there is also a valid flag signal LOAD_CH. Each first frame 110 outputs LOAD_CH containing a specific count threshold to the second frame 120, and the count thresholds corresponding to each first frame 110 are different. Specifically, in terms of structural settings, multiple first frames 110 corresponding to the rising edge channel and the falling edge channel are arranged in order according to the count threshold size. For example, multiple first frames 110 corresponding to the rising edge channel are arranged in ascending order of the count threshold; multiple first frames 110 corresponding to the falling edge channel are arranged in descending order of the count threshold. Exemplarily, as Figure 6 shown, LOAD_CH[0] - LOAD_CH[3] are the valid flag information of the four count threshold channels corresponding to the rising edge channel from low to high, and LOAD_CH[4] - LOAD_CH[7] are the valid flag information of the four count threshold channels corresponding to the falling edge channel from high to low.

[0057] To better illustrate the count threshold channels, the entire photomultiplier is described in combination, and at the same time refer toFigure 4 As described above, a comparator and a TDC are provided at the front end of the data processing system in the photomultiplier. The TDC is provided between the comparator and the first frame 110. The number of comparators and TDCs is the same as the number of the first frames 110. Assuming that the number of counting thresholds is four, as Figure 4 shown, the horizontal dashed lines represent the counting thresholds, the curves represent the digital counting pulses. The rising edges of the digital counting pulses are on the left side of the vertical dashed line, and the falling edges are on the right side. Four comparators are provided, each comparator corresponding to a counting threshold. A comparator and a TDC form a counting threshold channel. Figure 4 Among them, there are a total of eight intersections between the counting thresholds and the digital counting pulses from 0 to 7. The detection channels for these eight intersections are the counting threshold channels. Among them, the rising edge channels detect the rising edges of the digital counting pulses, and the falling edge channels detect the falling edges of the digital counting pulses. When a photon event occurs, the comparator compares the counting threshold with the digital counting pulse. When the digital counting pulse crosses the counting threshold, the comparator flips and outputs the flip pulse to the TDC. The TDC completes the function of time measurement by measuring the time of the flip pulse and outputs it to the corresponding first frame 110. The first frame 110 realizes decoding through binary conversion and generates the valid flag information LOAD_CH therefrom. Therefore, LOAD_CH corresponds to the counting threshold channel.

[0058] Further, continue to refer to Figure 3 , the output LOAD_CH of the first frame 110 is set to 1 at the second clock falling edge after the corresponding data conversion flag TDC_VALID = 1 (i.e., the signal changes to a high level), indicating that there is data in the corresponding channel and lasts for one clock cycle, so as to be able to collect the signal at the rising edge of the digital counting pulse in the next clock cycle.

[0059] Figure 5 shows a schematic diagram of the second frame of the data processing system according to an embodiment of the present application. Figure 6 shows a schematic diagram of the second frame of the data processing system according to another specific embodiment of the present application. Refer to Figure 5 and Figure 6 , the second frame 120 includes a valid event extraction module 210, and the valid event extraction module 210 is connected to all the first frames 110. According to the different outputs of the first frame 110, the valid event extraction module 210 has at least one of an idle state, a rising edge acquisition state, a falling edge acquisition state, a delay state, an end state, and a waiting state.

[0060] Specifically, the initial state of the second frame 120 is an idle state, and in this state, it waits for the signal of the first frame 110.Figure 7 is the second frame timing diagram of the data processing system according to the embodiments of the present application. Here, CLK100 represents a clock signal, LOAD_CH[0] represents the lowest count threshold flag signal at the rising edge of the digital count pulse, the channel is 0, LOAD_CH[N - 1] represents the highest count threshold flag signal at the rising edge of the digital count pulse, the channel is N - 1, LOAD_CH[2N - 1] represents the highest count threshold flag signal at the falling edge of the digital count pulse, the channel is 2N - 1, CH0_FRAME_OUT[K - 1:0] represents the decoded data of channel 0, CH(N - 1)_FRAME_OUT[K - 1:0] represents the decoded data of channel N - 1, CH(2N - 1)_FRAME_OUT[K - 1:0] represents the decoded data of channel 2N - 1, LOAD represents the valid flag indicating the completion of data packing, and FRAME_OUT[K - 1:0] represents the output data. As Figure 7 shown, in the idle state, according to the differences in the valid flag signals of the lowest and highest count thresholds of the digital count pulse detected at the rising edge of the clock, the second frame 120 performs different operations.

[0061] In the first case, when the valid flag signal LOAD_CH[0] of the lowest count threshold is detected as high at the rising edge of the clock, a state transition occurs to enter the rising-edge acquisition state. At the same time, the counter 200 is started to count, and the count value is latched during the counting process. In the subsequent process, according to the differences in the valid flag signal LOAD_CH[N - 1] of the highest count threshold of the digital count pulse at the rising edge of the clock, the second frame 120 also performs different operations: including A - D.

[0062] A. In the first preset number of subsequent clocks, the second frame 120 detects the valid flag signal LOAD_CH[N - 1] of the highest threshold at each rising edge of the clock, and latches the decoded data CH0_FRAME_OUT[K - 1:0]~CH(N - 1)_FRAME_OUT[K - 1:0]. If the valid flag signal LOAD_CH[N - 1] of the highest count threshold is low in the first preset number of clocks, it is determined that the corresponding photon event is an invalid event. At this time, the end of this photon event acquisition is reached, and then it immediately switches to the idle state, and starts to monitor the valid flag signal LOAD_CH[0] of the lowest count threshold again at the rising edge of the clock.

[0063] B. In the first preset number of clocks afterwards, if the valid flag signal LOAD_CH[N - 1] of the highest count threshold is high when the rising edge of the clock is collected, the second frame 120 enters the falling edge collection state, and latches all the data collected in the rising edge collection state. In the falling edge collection state, according to the difference of the valid flag signal LOAD_CH[2N - 1] corresponding to the lowest count threshold corresponding to the falling edge of the digital count pulse, the second frame 120 also performs different operations.

[0064] C. If within the second preset number of clocks, the valid flag signal LOAD_CH[2N - 1] corresponding to the lowest count threshold corresponding to the falling edge of the digital count pulse is high, the corresponding photon event is a valid event. Latch all the decoded data CH N_FRAME_OUT[K - 1:0]~CH(2N - 1)_FRAME_OUT[K - 1:0] corresponding to the falling edge of the digital count pulse in each clock rising edge. At this time, the end of the current photon event collection is reached. Then, enter the delay state, hold for the third preset number of clocks, and latch the decoded data of each clock rising edge to ensure that when new data arrives at the lowest count threshold channel of the digital count pulse falling edge, it can be replaced with the new data. After holding for the third preset number of clocks in the delay state, enter the end state, set the valid flag LOAD for data packing to 1, and hold for the fourth preset number of clocks in the end state. After holding for the fourth preset number of clocks in the end state, enter the waiting state, and after continuing for the fifth preset number of clocks in the waiting state, enter the idle state, waiting for a new photon event to arrive. Since the valid flag signal corresponding to the lowest count threshold is usually regarded as valid data, the purpose of continuing for the fifth preset number of clocks in the waiting state is to eliminate the influence of digital noise and wait for the fifth preset number of clocks to detect whether there is a re - trigger at the lowest count threshold channel of the digital count pulse falling edge. If so, replace the existing data.

[0065] D. If within the second preset number of clocks, there is no valid flag signal LOAD_CH[2N - 1] corresponding to the lowest count threshold corresponding to the falling edge of the digital count pulse that is high, it is determined that the corresponding photon event is an invalid event. At this time, the end of the current photon event collection is reached, and then immediately switch to the idle state and start monitoring the valid flag signal LOAD_CH[0] of the lowest count threshold again when the clock rising edge occurs.

[0066] In the second case, when the valid flag signal LOAD_CH[N - 1] of the highest count threshold is high when the clock rising edge is detected, the second frame 120 enters the falling edge collection state, and then executes the steps of the above case C.

[0067] For time calibration, according to an example of the present application, see Figure 1, the data processing system further includes a counter 200. Exemplarily, the counter 200 is a coarse counting module, which can be selected as 100 MHz, and is used to calibrate the coarse time of the measurement and convert it into Gray code for output. The value of the counter 200 is latched before the above-mentioned rising edge acquisition state and directly jumping from the idle state to the falling edge acquisition state. The counter 200 is connected to the second frames 120 of the plurality of data processing modules 100 and performs unidirectional data transmission.

[0068] It should be specifically noted that the values of the above first preset quantity to fifth preset quantity can be set according to the actually collected photon events.

[0069] For data storage, according to an example of the present application, see Figure 1 , the data processing system further includes a readable and writable register 300 and a standard SPI interface.

[0070] In an example of the present application, the valid event extraction module 210 includes a state machine. Figure 8 shows a schematic diagram of the state machine of the second frame of the data processing system according to an embodiment of the present application. As Figure 8 shown, six states of the state machine are shown: IDLE, RINING, FALLING, DELAY, END, and WAIT.

[0071] Figure 9 shows a schematic diagram of the state machine of the second frame of the data processing system according to a specific embodiment of the present application. To more clearly show the working process of the state machine, in combination with Figure 9 and Figure 6, here, taking the counting threshold as four as an example, the present application will be described in more detail. The initial state of the state machine is the idle IDLE state. When the valid flag bit of the lowest counting threshold of the rising edge of the digital counting pulse is detected as LOAD_CH[0]=1 at the rising edge of the clock, it starts to enter the rising edge acquisition RISING state of the digital counting pulse. At this time, a 5-bit counter is started, and the value of the Gray code counter 200 is latched. In the next three clocks (each clock is 10 ns), at the rising edge of each clock, it is detected whether the level of the valid flag bit LOAD_CH[3] of the highest counting threshold of the rising edge of the digital counting pulse is high, and at the same time, the inputs of CH0_FRAME_OUT[9:0]-CH3_FRAME_OUT[9:0] of the rising edge of the digital counting pulse are latched. When LOAD_CH[3] is not detected as high level within the 30 ns time window, it means that this photon event is an invalid event, and it returns to the IDLE state and starts to detect LOAD_CH[0] again. If within the time window, at the rising edge of the clock, it is determined that the valid flag bit of the highest counting threshold of the rising edge of the digital counting pulse is high level, at this time, the state machine jumps to the falling edge acquisition FALLING state, and all the data acquired at the rising edge of the digital counting pulse are latched and will not be changed anymore. If in the IDLE state, at the rising edge of the clock, it is detected that the level of the valid flag bit of the highest counting threshold LOAD_CH[3] of the rising edge of the digital counting pulse is high, then the inputs of CH0_FRAME_OUT[9:0]-CH3_FRAME_OUT[9:0] of the rising edge of the digital counting pulse are directly latched, and at the same time, the value of the Gray code counter 200 is latched, and it directly jumps to the falling edge acquisition FALLING state. After entering the falling edge acquisition FALLING state, a 170 ns time window is opened, and at the rising edge of each clock, the inputs of CH4_FRAME_OUT[9:0]-CH7_FRAME_OUT[9:0] of the falling edge of the digital counting pulse are latched. If within this time window, at the rising edge of the clock, it is detected that the valid flag bit LOAD_CH[7] of the lowest counting threshold of the falling edge of the digital counting pulse is high level, it means that this digital counting pulse is a valid pulse, and all the data of CH4_FRAME_OUT[9:0]-CH6_FRAME_OUT[9:0] of the falling edge of the acquired digital counting pulse are latched and will not be changed anymore. At this time, the state of the state machine jumps to the delay DELAY state, and the duration of this state is 30 ns. In this state, CH7_FRAME_OUT is latched at the rising edge of each clock to ensure that when there is new data in the lowest counting threshold channel, it is replaced with new data. After the DELAY state, it enters the acquisition end END state, which lasts for one cycle. After entering this state, the LOAD signal is set to 1 at the falling edge of the clock and lasts for one cycle.After that, it enters the WAIT state at the rising edge of the clock. After waiting for three cycles in this state, it returns to the IDLE state and waits for a new event to arrive.

[0072] In addition, in order to reduce the amount of data processing, the second frame 120 uses the count value corresponding to the high level of the valid flag information of the first channel in the rising-edge channel as the initial time of the corresponding photon event. That is, the second frame 120 only records the Gray code count value GrayCNT[36:0] when LOAD_CH[0]=1 as the initial time of the corresponding photon event. For the remaining channels, in the rising-edge acquisition state, when the valid flag information of the corresponding channel is detected as high at the rising edge of the clock, the corresponding count value is latched and used as the delay difference between this channel and the first channel. Among them, the first channel is the one with the smallest counting threshold in the rising-edge channels. Exemplarily, for LOAD_CH[1]~LOAD_CH[3], when the LOAD_CH of the corresponding channel is detected as high at the rising edge of the clock, the corresponding 5-bit count value NUM_CYC is latched as the delay difference between this channel and channel 0. After entering the falling-edge acquisition stage, except for the last channel, the second frame 120 latches the count values corresponding to the high-level valid flag signals of all the falling edges of the digital counting pulses. For example, for LOAD_CH[4]~LOAD_CH[6], when the LOAD_CH is detected as high at the rising edge of the clock, the corresponding count value NUM_CYC is latched. In the falling-edge acquisition stage and the waiting detection stage, if the second frame 120 detects that the valid flag signal of the lowest counting threshold of the falling edge of the digital counting pulse is high at the rising edge of the clock, the count value at this time is latched. For example, if LOAD_CH[7] is detected at the rising edge of the clock, the count value at this time is latched. The second frame 120 uses all the latched data, count values, and the delay differences of all channels as the output data of the data processing system. For example, the second frame 120 finally combines the latched data of 8 channels, the data latched by the Gray code counter, and 7 delay data into 152-bit data for output.

[0073] Furthermore, in an example of the present application, see Figure 5 , the second frame 120 further includes a first-in first-out module 220 and a data conversion module 230. Figure 10 Shows a schematic diagram of the second frame of the data processing system according to a specific embodiment of the present application. Exemplarily, see Figure 10 , when it is detected that LOAD=1 at the rising edge of the clock, all the latched data, count values, and the delay differences of all channels are written into the first-in first-out module FIFO, and the data that enters first is preferentially output using the first-in first-out method. Figure 11A timing diagram of the data conversion module of the second framework of the data processing system according to a specific embodiment of the present application is shown. The data conversion module 230, for example, in the DATA_TO_7bit module, detects whether there is data in the first-in first-out module FIFO at each rising edge of the clock. When FIFO_EMPTY = 0, it means that there is data in the first-in first-out module FIFO at this time. Then, the data in the first-in first-out module FIFO is read out, and the output data is converted into a 7-bit serial output and output starting from the low bit to the high bit. Through the high-speed data transmission interface (DATA_TO_7bit), efficient data transmission can be achieved.

[0074] For example, in the present application, the first framework 110 may be the CH_FRAME module, and the second framework 120 may be the DATA_FRAME module. It can be understood that the first framework 110 and the second framework 120 are not limited to the above examples, and any that can implement the functions of the present application can be used as the first framework 110 and the second framework 120.

[0075] The following combines a specific example to elaborate on the present application in more detail, so that those skilled in the art can understand the present application more clearly.

[0076] Figure 12 An architecture diagram of the data processing system according to a specific embodiment of the present application is shown. Refer to Figure 12 , the data transmission system SiPM_DIG_V1 consists of four parts: the register SPI_REG, the counter Gray_CNT, the data processing module TDC8CH_DIG_0, and the data processing module TDC8CH_DIG_1. Among them, SPI_REG is the register module of the chip, including a readable and writable register group and a standard SPI interface; Gray_CNT is the coarse counting module of the chip, which can be a 100MHz counter, used to calibrate the coarse time of the measurement and convert it into a Gray code output; TDC8CH_DIG is a data processing module with 2N channels, where N is, for example, 4, corresponding to processing the upper and lower parts of the output of the pixel array respectively. The main function of the first framework CH_FRAME is to collect the TDC output data at the front end and decode the 50-bit output code of the TDC. 8 channels are collected in parallel. After the data acquisition of the TDC is completed, the subsequent second framework DATA_VALID completes the discrimination and packaging of the data. In DATA_VALID, the coarse count code will be combined, and the data will be compressed and stored in the FIFO in the form of frames, waiting for output. It is output at a rate of 100MHz using a 7-bit serial output interface, and the output rate is 700Mbps.

[0077] In DATA_VALID, when it is detected that the digital counting pulse crosses the lowest counting threshold, a 30-ns time window is opened. Whether the highest counting threshold of the rising edge of the digital counting pulse arrives within the 30-ns time window is detected. When the highest counting threshold of the rising edge of the digital counting pulse is not detected, the photon event is determined to be an invalid event at this time, the collected data is cleared, and it returns to the idle state to wait for a new event to arrive. If the highest counting threshold is detected within the 30-ns time window, DATA_VALID enters the falling-edge acquisition stage. At this time, the data of the rising edge of the digital counting pulse is latched, and new data will not be stored even if it arrives. A new 170-ns time window is opened to detect whether the lowest counting threshold of the falling edge of the digital counting pulse arrives. If the lowest counting threshold of the falling edge of the digital counting pulse arrives within the 170-ns time window, it proves that the event is complete. All the data of the falling edge of the digital counting pulse is latched. And to ensure the accuracy of event point sampling, when the highest counting threshold of the falling edge of the digital counting pulse is collected, the data of the rising edge of the digital counting pulse is latched and will not be changed. For the data of the falling edge of the digital counting pulse, in the falling-edge acquisition stage, when new data arrives, the original data will be overwritten, ensuring that in the face of digital noise, only the first data is taken for the rising-edge channel and only the last-arrived data is taken for the falling-edge channel, so as to ensure the accuracy of data acquisition.

[0078] For the data processing system provided in this application, on the first hand, the TDC data of multiple channels is processed in parallel through the first framework 110, with high data processing efficiency, and at the same time, functions of decoding, error detection, and TDC status detection are realized; on the second hand, event screening and discrimination are carried out through the second framework 120, realizing the function of screening and extracting effective information of effective photon events on the photomultiplier chip, solving the problem of loss of effective events when setting a lower counting threshold, which is of great significance for optimizing the time resolution of the digital SiPM; on the third hand, compared with the prior art, the data screening step is moved to the data processing stage instead of the MC acquisition stage, which will not cause many effective events to be mis-screened and improves the counting rate; on the fourth hand, the second framework 120 processes and compresses the data after the extraction of effective events, effectively reducing the data transmission volume; on the fifth hand, through the multi-channel parallel processing of the first framework 110, the event screening and data compression of the second framework 120 and other features, the processing of a single photon event can be completed within 300 ns, and the transmission speed is fast. The output of a single photon event can be completed within 300 ns, solving the bottleneck problems such as low event acquisition rate and long acquisition and transmission process in the real-time detection of digital SiPM.

[0079] Corresponding to the above data processing system, this application also provides a method for processing data on a photomultiplier, and the photomultiplier is preferably a digital SiPM. Figure 13The flowchart of the data processing method according to an embodiment of the present application is shown. As Figure 13 shown, the method for processing data provided by the present application includes: S10: Receive the output after the time-to-digital converter processes the digital counting pulses.

[0080] When a photon event occurs, visible light photons are detected by the MC array and converted into digital counting pulses one by one via the digital interface circuit. The digital readout circuit counts all the counting information of the MC arrays and compares it with a preset counting threshold in the comparator. The TDC records the time points when all the counting information passes through the counting threshold, and then sends the time points and other information to the data processing system together.

[0081] S20: Decode the output data of the rising edge channel or the falling edge channel to obtain decoded data.

[0082] The decoding process includes: detecting the TDC_VALID of the corresponding channel. When the first system working clock falling edge after detecting that the TDC_VALID is at a high level is detected, the fine count measurement data output by the time-to-digital converter is latched for subsequent processing. After the latching is completed, the fine count measurement data is decoded through binary conversion to obtain the decoded data.

[0083] In addition, an error code detection process is also included. If there is an error code after the fine count measurement data is decoded through binary conversion, the first frame 110 generates an error code error signal.

[0084] In one example, the fine count measurement data includes VDL_I[31:0] and TM_I[15:0]. The specific decoding process is, for example, first decoding the latched 32-bit thermometer code VDL_I[31:0] into a 6-bit binary code through data decoding, and then decoding the 16-bit binary code into a 4-bit binary code, and determining whether there is an error code in the 6-bit binary code and the 4-bit binary code. If there is an error code, a dec_err decoding error signal is generated.

[0085] S30: Determine the validity of the corresponding photon event according to the decoded data.

[0086] In one example, the validity of the corresponding photon event is determined according to the counting threshold and the decoded data.

[0087] Specifically, first, in the idle state, different operations are performed according to the different valid flag signals of the lowest counting threshold and the highest counting threshold when the rising edge of the digital counting pulse is monitored at the clock rising edge.

[0088] In the first case, when the valid flag signal of the lowest counting threshold of the rising edge of the digital counting pulse is high when monitored at the rising edge of the clock, a state transition occurs to enter the rising edge acquisition state. At the same time, the counter 200 is started to count, and the counted value is latched during the counting process. In the subsequent process, different operations are also performed according to the different valid flag signals of the highest counting threshold of the rising edge of the digital counting pulse at the rising edge of the clock. A. Within the first preset number of clocks afterwards, detect the valid flag signal of the highest threshold of the rising edge of the digital counting pulse at each rising edge of the clock, and latch the decoded data. If the valid flag signal of the highest counting threshold of the rising edge of the digital counting pulse at the rising edge of the clock is low within the first preset number of clocks, it is determined that the corresponding photon event is an invalid event. At this time, the end of the current photon event acquisition is reached, and then it immediately transitions to the idle state and starts to monitor the valid flag signal of the lowest counting threshold of the rising edge of the digital counting pulse at the rising edge of the clock again; B. Within the first preset number of clocks afterwards, if the valid flag signal of the highest counting threshold of the rising edge of the digital counting pulse at the rising edge of the clock is high, enter the falling edge acquisition state, and latch all the data acquired in the rising edge acquisition state. In the falling edge acquisition state, different operations are also performed according to the different valid flag signals of the lowest counting threshold of the falling edge of the digital counting pulse.C. If within the second preset number of clocks, the valid flag signal of the lowest counting threshold of the digital counting pulse falling edge is high, then the corresponding photon event is a valid event. Latch the decoded data corresponding to the digital counting pulse falling edge in each clock rising edge. At this time, the end of this photon event acquisition is reached. Then, enter the delay state, maintain the third preset number of clocks, and latch the decoded data of each clock rising edge to ensure that when new data arrives at the lowest counting threshold channel of the digital counting pulse falling edge, it can be replaced with the new data. After maintaining the third preset number of clocks in the delay state, enter the end state, generate a valid flag for the completion of packaging, and maintain the fourth preset number of clocks in the end state. After maintaining the fourth preset number of clocks in the end state, enter the waiting state, and after continuing the fifth preset number of clocks in the waiting state, enter the idle state, waiting for a new photon event to arrive. Since the valid flag signal corresponding to the lowest counting threshold of the digital counting pulse falling edge is usually considered valid data, the purpose of continuing the fifth preset number of clocks in the waiting state is to eliminate the influence of digital noise and wait for the fifth preset number of clocks to detect whether there is a re-trigger at the lowest counting threshold channel of the digital counting pulse falling edge. If so, replace the existing data; D. If within the second preset number of clocks, there is no valid flag signal of the lowest counting threshold of the digital counting pulse falling edge that is high, then determine that the corresponding photon event is an invalid event. At this time, the end of this photon event acquisition is reached, and then immediately switch to the idle state and start monitoring the valid flag signal of the highest counting threshold of the digital counting pulse rising edge again when the clock rising edge is detected.

[0089] In the second case, when the valid flag signal of the highest counting threshold of the digital counting pulse rising edge is high when the clock rising edge is detected, enter the falling edge acquisition state, and then execute the steps in the above case C.

[0090] It should be specifically noted that the values of the above first preset number to fifth preset number can be set according to the actually collected photon events.

[0091] To describe this method more clearly, four counting thresholds are taken as an example here to explain this application in more detail. When extracting valid events, the initial state is set to the idle IDLE state. When the valid flag bit of the lowest counting threshold of the rising edge of the digital counting pulse is detected as LOAD_CH[0]=1 at the rising edge of the clock, it starts to enter the rising edge acquisition RISING state of the digital counting pulse. At this time, a 5-bit counter NUM_CYC is started, and the value GrayCNT[36:0] of the Gray code counter 200 is latched. In the next three clocks (each clock is 10 ns), at the rising edge of each clock, it is detected whether the level of the valid flag bit LOAD_CH[3] of the highest counting threshold of the rising edge of the digital counting pulse is high, and at the same time, the inputs of CH0_FRAME_OUT[9:0]-CH3_FRAME_OUT[9:0] of the rising edge of the digital counting pulse are latched. If LOAD_CH[3] is not detected as high level within the 30 ns time window, it means that this photon event is an invalid event, and it returns to the IDLE state to start detecting LOAD_CH[0] again. If within the time window, at the rising edge of the clock, it is determined that the valid flag bit of the highest counting threshold of the rising edge of the digital counting pulse is high level, at this time, it jumps to the falling edge acquisition FALLING state, and all the data acquired at the rising edge of the digital counting pulse are latched and no longer changed. If in the IDLE state, at the rising edge of the clock, it is detected that the level of the valid flag bit of the highest counting threshold LOAD_CH[3] of the rising edge of the digital counting pulse is high, then the inputs of CH0_FRAME_OUT[9:0]-CH3_FRAME_OUT[9:0] of the rising edge of the digital counting pulse are directly latched, and at the same time, the value of the Gray code counter 200 is latched, and it directly jumps to the falling edge acquisition FALLING state. After entering the falling edge acquisition FALLING state, a 170 ns time window is opened, and at the rising edge of each clock, the inputs of CH4_FRAME_OUT[9:0]-CH7_FRAME_OUT[9:0] of the falling edge of the digital counting pulse are latched. If within this time window, at the rising edge of the clock, it is detected that the valid flag bit LOAD_CH[7] of the lowest counting threshold of the falling edge of the digital counting pulse is high level, it means that this digital counting pulse is a valid pulse, and all the data of CH4_FRAME_OUT[9:0]-CH6_FRAME_OUT[9:0] of the falling edge of the digital counting pulse acquired are latched and no longer changed. At this time, it jumps to the delay DELAY state, and the duration of this state is 30 ns. In this state, CH7_FRAME_OUT is latched at the rising edge of each clock to ensure that when new data arrives at the lowest counting threshold channel, it is replaced with new data.After the DELAY state, it enters the END state of data acquisition and lasts for one cycle. After entering this state, when the clock falls, the LOAD signal is set to 1 and lasts for one cycle. Then, at the rising edge of the clock, it enters the WAIT state. After waiting for three cycles in this state, it returns to the IDLE state and waits for a new event to arrive.

[0092] In addition, to reduce the amount of data processing, during the extraction of valid events, the count value corresponding to the high level of the valid flag information of the first channel in the rising-edge channel is used as the initial time of the corresponding photon event. That is, only the Gray code count value GrayCNT[36:0] when LOAD_CH[0]=1 is recorded as the initial time of the corresponding photon event. For the remaining channels, in the rising-edge acquisition state, when the valid flag information of the corresponding channel is detected as high at the rising edge of the clock, the corresponding count value is latched and used as the time delay difference between this channel and the first channel. Among them, the first channel is the one with the smallest counting threshold in the rising-edge channel. Exemplarily, for LOAD_CH[1]~LOAD_CH[3], when the LOAD_CH of the corresponding channel is detected as high at the rising edge of the clock, the corresponding 5-bit count value NUM_CYC is latched as the time delay difference between this channel and channel 0. After entering the falling-edge acquisition stage, except for the last channel, the count values corresponding to the high level of the valid flag signals of all flashes are latched. For example, for LOAD_CH[4]~LOAD_CH[6], when the LOAD_CH is detected as high at the rising edge of the clock, the corresponding count value NUM_CYC is latched. In the falling-edge acquisition stage and the waiting detection stage, if the valid flag signal of the lowest counting threshold of the falling edge of the digital counting pulse is detected as high at the rising edge of the clock, the count value at this time is latched. For example, if LOAD_CH[7] is detected at the rising edge of the clock, the count value at this time is latched. The data, count values, and the time delay differences latched by all channels are used as the output data of the data processing system. For example, finally, the data latched by 8 channels, the data latched by the Gray code counter, and 7 delay data are combined into 152-bit data for output.

[0093] Furthermore, regarding data output, the first-in-first-out method is adopted to preferentially output the data that enters first, and the data is output after being converted. For example, the output data is converted into 7-bit serial output and output starting from the low bit to the high bit, which can achieve efficient data transmission.

[0094] In the parallel embodiment, the method further includes: S21: Select the working mode according to the data output mode control signal output by the time-to-digital converter.

[0095] Specifically, the process of selecting the working mode includes: receiving the data output mode control signal DATA_SEL output by the TDC, and selecting the working mode according to DATA_SEL. When DATA_SEL is at a low level, the normal mode is selected, the fine count measurement data is decoded, and valid events are extracted according to the decoded data; when DATA_SEL is at a high level, the test mode is selected, and the raw data of the corresponding channel is stored as a detection signal. For example, in the normal mode, CH_FRAME_OUT outputs a combination of TDC decoded data, and the valid data is 10 bits in total. Then, it is packed with other data to form 152-bit valid data and output to the outside of the system; in the test mode, CH_FRAME_OUT outputs the raw data that has not been decoded. The raw data is 48-bit data formed by combining VDL_I[31:0] and TM_I[15:0]. The 48-bit TDC original code is output for external devices to test the status of the TDC.

[0096] For the data processing method provided in this application, on the one hand, by parallel processing the TDC data of multiple channels, the data processing efficiency is high, and at the same time, the functions of decoding, error code detection, and TDC status detection are realized; on the other hand, by screening and discriminating events, the function of screening and extracting valid information of valid photon events on the photomultiplier chip is realized, solving the problem of loss of valid events when setting a lower count threshold, which is of great significance for optimizing the time resolution of digital SiPM; on the third hand, compared with the prior art, the data screening step is moved to the data processing stage instead of the MC acquisition stage, which will not cause a lot of valid events to be mis-screened and improves the count rate; on the fourth hand, after the valid events are extracted, the data is processed and compressed, effectively reducing the data transmission volume; on the fifth hand, through features such as multi-channel parallel processing, event screening, and data compression, the processing of a single photon event can be completed within 300 ns, and the transmission speed is fast. The output of a single photon event can be completed within 300 ns, solving the bottleneck problems such as low event acquisition rate and long acquisition and transmission process in the real-time detection of digital SiPM.

[0097] Corresponding to the above data processing system, this application also provides a photomultiplier, which includes the data processing system provided in any of the above examples. In addition to the above data processing system, the photomultiplier further includes: an MC array, a digital readout circuit, a comparator, a TDC, etc. When a photon event occurs, visible light photons are detected by the MC array and converted into digital count pulses one by one via the digital interface circuit. The digital readout circuit counts all the count information of the MC array and compares it with a preset count threshold in the comparator. The TDC records the time points when all the count information passes through the count threshold, and all the "count threshold - time" information pairs of this event are obtained through decoding by the data processing system.

[0098] Since the photomultiplier includes the above data processing system, it has the same beneficial effects as the above data processing system, which will not be elaborated here.

[0099] Those skilled in the art can understand that the above-mentioned modules can be distributed in the device according to the description of the embodiments, or can be correspondingly changed and distributed in one or more devices that are only different from this embodiment. The multiple modules of the above embodiments can be combined into one module, or one module can be further split into multiple sub-modules.

[0100] Although the present application provides method operation steps as described in the above embodiments or flowcharts, more or fewer operation steps may be included in the method based on routine or non-creative labor. In steps where there is no necessary causal relationship logically, the execution order of these steps is not limited to the execution order provided in the embodiments of the present application.

[0101] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the key point of each embodiment is to illustrate the differences from other embodiments.

[0102] The above has introduced the embodiments of the present application in detail. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. At the same time, changes or deformations made by those skilled in the art based on the idea of the present application, on the specific implementation manner and application scope of the present application, all belong to the protection scope of the present application. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A data processing system, characterized in that: The data processing system is arranged on the photomultiplier, and the data processing system comprises: At least one data processing module, each of the data processing modules includes a plurality of first frames and at least one second frame, the plurality of first frames are located between the time-to-digital converter and the second frame, and each of the first frames corresponds to a rising edge channel or a falling edge channel, the plurality of first frames are configured to decode the output data of the rising edge channel or the falling edge channel to obtain decoded data, and the second frame is configured to determine the validity of the corresponding photon event according to the decoded data.

2. The data processing system according to claim 1, characterized in that A plurality of the first frames are arranged in parallel.

3. The data processing system according to claim 1, characterized in that: The number of the first frames connected to the rising edge channels is the same as the number of the first frames connected to the falling edge channels.

4. The data processing system according to claim 1, characterized in that: The first frame detects a data conversion flag signal corresponding to a rising edge channel or a falling edge channel, and latches the fine count measurement data output by the time-to-digital converter when a change in the data conversion flag signal is detected.

5. The data processing system according to claim 4, characterized in that: The first framework is further configured to generate a bit error signal when there is a bit error in the fine count measurement data after decoding.

6. The data processing system according to claim 1, characterized in that: The first framework is configured to select an operating mode according to a data output mode control signal output by the time-to-digital converter, including: When the data output mode control signal is at a low level, the first framework is configured to output the decoded data in a normal mode; When the data output mode control signal is at a high level, the first framework is configured to output raw data of the corresponding channel according to the test mode, and the raw data is stored as a detection signal by the second framework.

7. The data processing system according to claim 1, characterized in that: The second frame is configured to select an operating mode according to a data output mode control signal output by the time-to-digital converter, including: When the data output mode control signal is at a low level, the second framework is configured to extract valid events according to the decoded data in a normal mode; When the data output mode control signal is at a high level, the second frame is configured to store the raw data as a detection signal according to a test mode.

8. The data processing system according to claim 1, characterized in that: The second frame includes a valid event extraction module, which is connected to all the first frames, and has at least one of an idle state, a rising edge collection state, a falling edge collection state, a delay state, an end state and a waiting state.

9. The data processing system according to claim 1, characterized in that: The initial state of the second frame is an idle state. When the valid flag signal of the lowest counting threshold of the rising edge of the digital counting pulse is detected to be high level at the rising edge of the clock, the rising edge acquisition state is entered.

10. The data processing system according to claim 1, characterized in that: The second framework is configured such that when entering the rising edge acquisition state, the counter starts counting and latches the count value. The second framework detects the valid flag signal of the highest count threshold at each clock rising edge and latches the decoded data. If the valid flag signal of the highest count threshold is at a low level within a first preset number of clocks, the corresponding photon event is determined to be an invalid event.

11. The data processing system according to claim 10, characterized in that: If the valid flag signal of the highest counting threshold is at a high level within the first preset number of clocks, the second frame enters a falling edge acquisition state and latches all data acquired in the rising edge acquisition state.

12. The data processing system according to claim 1, characterized in that: If the second frame is in an idle state and detects that the valid flag signal of the highest counting threshold of the rising edge of the digital count pulse at the rising edge of the clock is high, the second frame enters a falling edge acquisition state.

13. The data processing system according to claim 1, characterized in that: The second framework is configured such that when in the falling edge acquisition state, if within a second preset number of clocks, there is a valid flag signal with a minimum counting threshold of the falling edge of the digital count pulse that is at a high level, then the corresponding photon event is a valid event, and the decoded data corresponding to the falling edge of the digital count pulse in each clock rising edge are latched.

14. The data processing system according to claim 1, characterized in that: The second framework is configured to enter a delay state when a valid event is collected in a falling edge collection state, maintain a third preset number of clocks, and latch decoded data at each rising edge of the clock.

15. The data processing system according to claim 1, characterized in that: The second frame enters the end state after maintaining the delay state for a third preset number of clocks, generates a valid flag of data packaging completion, and maintains the end state for a fourth preset number of clocks.

16. The data processing system according to claim 1, characterized in that: The second frame enters a waiting state after maintaining the end state for a fourth preset number of clocks, and enters an idle state after the waiting state continues for a fifth preset number of clocks, waiting for a new photon event to arrive.

17. The data processing system according to claim 1, characterized in that: It also includes a counter, which is connected to all the data processing modules and is used to calibrate the rough time measured by the data processing modules.

18. The data processing system according to claim 1, characterized in that: The second frame uses the count value corresponding to when the valid flag information of the first channel in the rising edge channel is at a high level as the initial time of the corresponding photon event.

19. The data processing system according to claim 1, characterized in that: When the second frame is in the rising edge acquisition state, when the corresponding valid flag information is detected to be at a high level at the rising edge of the clock, the corresponding count value is latched and used as the delay difference between the current channel and the first channel; The second framework uses the data latched by all channels, the count value and the delay difference as output data of the data processing system.

20. A method for processing data on a photomultiplier, characterized in that: The method comprises: receiving the output of the digital count pulse processed by the time-to-digital converter; Decoding the output data of the rising edge channel or the falling edge channel to obtain decoded data; The validity of the corresponding photon event is determined according to the decoded data.

21. The method according to claim 20, characterized in that After receiving the output of the time-to-digital converter, the method further comprises: The rising edge of the data conversion mark signal of the corresponding channel is detected, and when the first falling edge of the system working clock after the data conversion mark signal is detected to be at a high level, the fine count measurement data output by the time-to-digital converter is latched.

22. The method according to claim 21, characterized in that The output data of the decoding rising edge channel or falling edge channel includes: If there is a bit error in the fine count measurement data after decoding, a bit error signal is generated.

23. The method according to claim 20, characterized in that The method further comprises: Selecting an operating mode according to a data output mode control signal output by the time-to-digital converter comprises: When the data output mode control signal is at a low level, a normal mode is selected to extract valid events according to the decoded data; When the data output mode control signal is at a high level, the test mode is selected, and the original data of the corresponding channel is stored as a detection signal.

24. The method according to claim 20, characterized in that The determining the validity of the corresponding photon event according to the decoded data includes: The validity of the corresponding photon event is determined according to the preset counting threshold and the decoded data.

25. The method according to claim 20, characterized in that The determining the validity of the corresponding photon event according to the preset counting threshold and the decoded data includes: When the valid flag signal of the lowest counting threshold is detected to be high level at the rising edge of the clock, the rising edge acquisition state is switched from the idle state; When entering the rising edge acquisition state, the counter starts counting and latching the count value, detects the valid flag signal of the highest count threshold of each clock rising edge, and latches the decoded data, if within a first preset number of clocks, the valid flag signal of the highest count threshold of the clock rising edge is a low level, then the corresponding photon event is determined to be an invalid event; If within the first preset number of clocks, the valid flag signal of the highest counting threshold of the clock rising edge is at a high level, then the falling edge acquisition state is entered, and all data collected in the rising edge acquisition state is latched; If the valid flag signal of the highest counting threshold of the rising edge of the clock is detected to be high level in the idle state, the falling edge acquisition state is entered, and the decoded data and the counting value are latched; In the falling edge acquisition state, if within the second preset number of clocks, there is a valid flag signal of the lowest counting threshold of the falling edge of the digital count pulse, which is at a high level, then the corresponding photon event is a valid event, and the decoded data corresponding to the falling edge of the digital count pulse in each clock rising edge are latched; When a valid event is collected in the falling edge collection state, entering a delay state, maintaining a third preset number of clocks, and latching decoded data of each clock rising edge; After maintaining the third preset number of clocks in the delay state, entering the end state, generating a packing completion valid flag, and maintaining a fourth preset number of clocks in the end state; After the end state is maintained for the fourth preset number of clocks, the waiting state is entered, and after the waiting state is maintained for a fifth preset number of clocks, the idle state is entered to wait for a new photon event to arrive.

26. The method according to claim 20, characterized in that The method further comprises: The count value corresponding to the time when the valid flag information of the first channel in the rising edge channel is at a high level is used as the initial time of the corresponding photon event.

27. The method according to claim 20, characterized in that The method further comprises: In the rising edge acquisition state, when the valid flag information of the corresponding channel is detected as a high level at the rising edge of the clock, the corresponding count value is latched and used as the delay difference between the channel and the first channel; The effective event, the count value and the delay difference are used as the output data of the photomultiplier.

28. A photomultiplier, characterized in that: A data processing system comprising any one of claims 1 to 19.

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