Array substrate and display device

Abstract

The present application relates to an array substrate and a display device. The array substrate includes a base substrate having a display area and a non-display area. The non-display area is provided with a gate drive circuit. The gate drive circuit also includes a first redundant low-level signal line and a first sacrificial electrode located above the base substrate. A portion of the first redundant low-level signal line is located in the circuit area and is arranged around the drive circuit. Another portion of the first redundant low-level signal line extends to the bus area and is electrically connected to both ends of the first low-level signal line or pulse signal line in the bus area. The first redundant low-level signal line is electrically connected to the first sacrificial electrode through a first transfer hole to consume ions around the electrolytic cell. The first sacrificial electrode on the first redundant low-level signal line can consume some ions in the gate drive circuit, avoiding corrosion at the connection point between the metal trace and the first signal trace, ensuring smooth signal flow and normal display of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] With the continuous advancement of technology, the application of gate driver on array (GOA) technology is gradually increasing. GOA technology integrates the gate driver on the glass substrate to achieve scanning of the display panel. With advantages such as low cost, low power consumption, and narrow bezels, GOA technology is gradually becoming a new research direction for various manufacturers.

[0003] GOA technology is a technology that simultaneously completes the manufacturing process of functional units composed of thin-film transistor (TFT) devices and array substrates to replace traditional driver chips and complete the line-by-line scanning function when displaying images.

[0004] However, when display panels using GOA technology operate in a high temperature and high humidity environment, they will suffer from layer-transfer hole corrosion and burns, which will lead to signal failure. The display panel cannot display the image normally, and abnormalities will occur, affecting the product yield. Summary of the Invention

[0005] The present application provides an array substrate and a display device, which can protect the circuit area from electrochemical corrosion caused by high temperature and high humidity, thereby improving product yield.

[0006] In a first aspect, the present application provides an array substrate, wherein the base substrate has a display area and a non-display area, the non-display area is provided with a gate drive circuit, the gate drive circuit includes a circuit area and a bus area sequentially arranged in a direction away from the display area, the bus area includes a plurality of first signal lines, one end of the circuit area is connected to a portion of the plurality of first signal lines via a metal line, and the other end of the circuit area is connected to a scan line of the display area via a metal line; the plurality of first signal lines include a first high-level signal line, a first low-level signal line, and a pulse signal line;

[0007] The gate drive circuit also includes a first redundant low-level signal line and a first sacrificial electrode located above it. A portion of the first redundant low-level signal line is located in the circuit area and is arranged around the gate drive circuit. Another portion of the first redundant low-level signal line extends to the bus area and is electrically connected to both ends of the first low-level signal line or the pulse signal line in the bus area. The first redundant low-level signal line is electrically connected to the first sacrificial electrode through a first transfer hole.

[0008] In a possible implementation, the first high-level signal line includes a plurality of clock signal lines; the first low-level signal line includes a gate-off signal line, and the pulse signal line includes a frame start signal line; the first signal line further includes a low-frequency signal line;

[0009] The plurality of first signal lines are sequentially arranged in a direction away from the display area;

[0010] Among them, the frame start signal line is located on a side away from the display area, the gate shutdown signal line is set close to the circuit area, the multiple clock signal lines are arranged in sequence from the frame start signal line to the gate shutdown signal line, and the low-frequency signal line is set between the clock signal line and the gate shutdown signal line.

[0011] In one possible implementation, the metal routing includes output routing and input routing, one end of the circuit area is electrically connected to a plurality of the input routings, and the plurality of input routings are respectively electrically connected to corresponding first signal routings, and the other end of the circuit area is electrically connected to one of the output routings.

[0012] In a possible implementation, the first sacrificial electrode located at the output wiring position is disconnected; or,

[0013] The first redundant low-level signal line located at the output wiring position is disconnected.

[0014] In one possible implementation, the gate drive circuit also includes a second redundant low-level signal line and a second sacrificial electrode located above it, the second redundant low-level signal line is located on the outer side of the first redundant low-level signal line, a portion of the second redundant low-level signal line is located in the circuit area and is arranged around the gate drive circuit, another portion of the second redundant low-level signal line extends to the bus area and is electrically connected to the first low-level signal line or the two ends of the pulse signal line in the bus area, and the second redundant low-level signal line is electrically connected to the second sacrificial electrode through the first transfer hole.

[0015] In one possible implementation, the gate drive circuit includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a first electrode layer sequentially arranged on the substrate, the first signal trace is located in the first metal layer, the metal trace is located in the second metal layer, the first transfer hole passes through the first insulating layer and / or the second insulating layer, and the first sacrificial electrode and the second sacrificial electrode are both located in the first electrode layer;

[0016] The first redundant low-level signal line is located in the first metal layer or the second metal layer, and the second redundant low-level signal line is located in the first metal layer or the second metal layer.

[0017] In a possible implementation, the gate driving circuit includes a circuit middle node located in the circuit area, and a second signal line is arranged around the circuit middle node;

[0018] A redundant signal line is provided between the intermediate node of the circuit and the second signal line, a third sacrificial electrode is provided above the redundant signal line, and the redundant signal line is electrically connected to the third sacrificial electrode through a second transfer hole.

[0019] In a possible implementation, the root square voltage of the second signal line is greater than the root square voltage of the middle node of the circuit, and the root square voltage of the middle node of the circuit is greater than the root square voltage of the redundant signal line.

[0020] In a possible implementation, the redundant signal line includes a first sub-redundant routing line and a second sub-redundant routing line;

[0021] The first sub-redundant routing line extends along the outer periphery of the middle node of the circuit, and the second sub-redundant routing line is provided between the first sub-redundant routing line and the second signal line and extends along the outer periphery of the first sub-redundant routing line.

[0022] In a second aspect, the present application provides a display device, comprising a display panel and a housing, wherein the housing is connected to the display panel, and the array substrate as described in the first aspect is disposed within the display panel.

[0023] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art:

[0024] The array substrate and display device provided in the embodiments of the present application utilize a first redundant low-level signal line to surround a circuit area, and a first sacrificial electrode is provided above the first redundant low-level signal line, which can consume some ions in the gate drive circuit, avoid corrosion of metal wiring and first signal wiring connection positions, ensure smooth signal flow and normal display of the display panel, effectively extend the service life of the display panel, and improve product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0026] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0027] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0028] Figure 1 A schematic top view of an array substrate provided in an embodiment of the present application;

[0029] Figure 2 A schematic top view of an array substrate provided in an embodiment of the present application;

[0030] Figure 3 A schematic top view of an array substrate provided in an embodiment of the present application;

[0031] Figure 4 A schematic top view of an array substrate provided in an embodiment of the present application;

[0032] Figure 5 A schematic top view of an array substrate provided in an embodiment of the present application;

[0033] Figure 6 A schematic top view of an array substrate provided in an embodiment of the present application;

[0034] Figure 7 for Figure 1 The schematic cross-sectional view at point d is shown;

[0035] Figure 8 for Figure 1 The schematic cross-sectional view at point a is shown;

[0036] Figure 9 for Figure 2 The cross-sectional schematic diagram at point b is shown;

[0037] Figure 10 A schematic top view of an intermediate node of a circuit provided in an embodiment of the present application;

[0038] Figure 11 A schematic top view of an intermediate node of a circuit provided in an embodiment of the present application;

[0039] Figure 12 for Figure 10 The cross-sectional schematic diagram at c is shown;

[0040] Figure 13 for Figure 10 The schematic cross-sectional view at point e is shown;

[0041] Figure 14 A block diagram of a display device provided in an embodiment of the present application.

[0042] Description of reference numerals:

[0043] 1. Array substrate; 11. Base substrate; 12. Gate drive circuit;

[0044] 121, circuit area; 1211, drive circuit; 1212, metal trace; 12121, output trace; 12122, input trace; 1213, circuit intermediate node; 12131, third transfer layer via; 12132, second electrode layer; 1214, second signal line; 1215, redundant signal line; 12151, first sub-redundant trace; 12152, second sub-redundant trace; 1216, third sacrificial electrode; 1217, second transfer layer via;

[0045] 122, bus area; 1221, first signal line; 12211, first high-level signal line; 12212, first low-level signal line; 12213, pulse signal line; 12214, low-frequency signal line;

[0046] 123, first metal layer; 124, first insulating layer; 125, second metal layer; 1231 / 1251, first redundant low-level signal line; 1232 / 1252, second redundant low-level signal line;

[0047] 126, second insulating layer; 127, first electrode layer; 1271 / 1272, first sacrificial electrode; 1273 / 1274, second sacrificial electrode;

[0048] 13. First transfer layer hole; 131. First sub-transfer layer hole; 132. Second sub-transfer layer hole; 14. Electrode trace; 141. First electrode trace; 142. Second electrode trace; 143. Second fracture;

[0049] AA, display area; IA, non-display area; 2, display panel. DETAILED DESCRIPTION

[0050] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0051] The disclosure below provides many different embodiments or examples for implementing different configurations of the present invention. To simplify the disclosure of the present invention, the components and configurations of specific examples are described below. Of course, these are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numerals and / or letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0052] For ease of description, spatially relative terms may be used herein to describe the relative position or movement of one element or feature relative to another element or feature as shown in the figures, such as "inside," "outside," "inside," "outside," "below," "beneath," "above," "above," "front," "back," and the like. Such spatially relative terms are intended to include different orientations of the device in use or operation other than the orientation depicted in the figures. For example, if the device in the figures undergoes a positional flip or a change in posture or a change in motion, then these directional indications will also change accordingly. For example, an element described as "below" or "below" another element or feature will subsequently be oriented as "above" or "above" another element or feature. Thus, the example term "below" can include both above and below orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein will be interpreted accordingly.

[0053] In the related art, if the display device is in a high temperature and high humidity environment, its water vapor will enter the liquid crystal box in the display device and then mix with ions to form a solvent in the electrolytic cell. At this time, the first electrode layer will be destroyed and gradually reduced to In, which will eventually cause the first electrode layer to fail to open the circuit, affecting the abnormal picture. In order to solve the technical problem of abnormal display caused by layer-transfer hole corrosion and burns in a high temperature and high humidity environment in the related art, the present application provides an array substrate, which uses a first redundant low-level signal line to surround the circuit area, and a first sacrificial electrode is set above the first redundant low-level signal line, which can consume part of the ions in the gate drive circuit, avoid corrosion of the connection position between the metal wiring and the first signal wiring, ensure smooth signal flow and normal display of the display panel, effectively extend the service life of the display panel, and improve product yield.

[0054] First embodiment

[0055] Figure 1 A schematic top view of an array substrate provided in an embodiment of the present application is shown; Figure 7 for Figure 1 The schematic cross-sectional view at point d is shown; Figure 8 for Figure 1 The schematic cross-sectional view at point a is shown; Figure 14 A block diagram of a display device provided in an embodiment of the present application.

[0056] An embodiment of the present application provides an array substrate 1, which is applied to a display panel of a display device to realize the display function of the display panel. The array substrate 1 includes a base substrate 11. The base substrate 11 can be a rigid substrate made of, for example, glass. Alternatively, the base substrate 11 can be a flexible substrate made of a material such as polyimide (PI), forming a transparent base substrate 11. The display device of the present application is not limited to a rigid, non-flexible display panel, but can also be a flexible, bendable display panel.

[0057] The base substrate 11 has a display area AA and a non-display area IA. The non-display area IA is provided with a gate driver circuit 12 (Gate Driver on array, referred to as GOA) to achieve low cost, low power consumption, and narrow frame of the array substrate 1. The gate driver circuit 12 includes a circuit area 121 and a bus area 122 (Busline) arranged in sequence in a direction away from the display area AA. The direction away from the display area AA is, for example, a first direction (refer to Figure 14 X-axis shown).

[0058] The circuit area 121 includes at least one driving circuit 1211, and each driving circuit 1211 is connected to the bus area 122 to facilitate signal transmission. The number of driving circuits 1211 depends on the actual situation and can be one, two or more. The multiple driving circuits 1211 are arranged along the second direction (refer to FIG. Figure 14 One end of the driving circuit 1211 in the circuit region 121 is connected to the bus region 122 via a metal trace 1212, and the other end of the driving circuit 1211 in the circuit region 121 is connected to a scan line (not shown) in the display region AA via a metal trace 1212.

[0059] The bus area 122 includes multiple first signal traces 1221, arranged sequentially away from the display area AA. Each first signal trace 1221 is electrically connected to the corresponding metal trace 1212 via a first transfer hole 13 to the electrode trace 14 above it, forming an electrolytic cell. The electrode trace 14 provides the anode and cathode for the electrolytic cell, completing the circuit. Electrode trace 14 is made, for example, of indium tin oxide (ITO), which offers stable performance and good conductivity.

[0060] The plurality of first signal lines 1221 include a first high-level signal line 12211, a first low-level signal line 12212, and a pulse signal line 12213. The number of first high-level signal lines 12211 is not limited to one. For example, the first high-level signal line 12211 may include multiple clock signal lines, such as CK1, CK2, CK3, and CK4, to facilitate synchronous data transmission, control data exchange rates, and determine data transmission timing. For example, the first low-level signal line 12212 may include a gate-off signal line (VSS), a DC voltage signal used to shut down the driver circuit 1211 of the circuit region 121. The pulse signal line 12213 may include a frame start signal line (STV), a signal used to trigger the start of scanning.

[0061] Among them, the first signal line 1221 also includes a low-frequency signal line 12214, which provides a control signal for eliminating noise in the driving circuit 1211 of the circuit area 121. The low-frequency signal line 12214 can be set as one or two as needed, such as LC1, LC2, etc.

[0062] The frame start signal line (STV) is located on the side away from the display area AA, the gate shutoff signal line (VSS) is located near the circuit area 121, and the multiple clock signal lines CK1, CK2, CK3, and CK4 are arranged in sequence from the frame start signal line (STV) to the gate shutoff signal line (VSS). The low-frequency signal line 12214 is arranged between the clock signal lines and the gate shutoff signal line (VSS). For example, the LC1 low-frequency signal line is arranged adjacent to the CK4 clock signal line, and the LC2 low-frequency signal line is arranged adjacent to the gate shutoff signal line (VSS).

[0063] The first high-level signal line 12211 passes between the first electrode wiring 141 and the corresponding metal wiring 1212 , or the first low-level signal line 12212 passes between the second electrode wiring 142 and the corresponding metal wiring 1212 to form an electrolytic cell.

[0064] In some examples, metal traces 1212 include, for example, output traces 12121 and input traces 12122. One end of a driver circuit 1211 in circuit region 121 is electrically connected to one output trace 12121. Output trace 12121 is, for example, a gate line (G), connected to a scan line in display region AA to implement a scanning function. The output trace 12121 connected to the first driver circuit 1211 in circuit region 121 can be labeled G1, the output trace 12121 connected to the second driver circuit 1211 in circuit region 121 can be labeled G2, and so on. The output trace 12121 connected to the nth driver circuit 1211 can be labeled Gn. The specific designation will depend on the actual situation.

[0065] The other end of the driving circuit 1211 in the circuit region 121 is electrically connected to, for example, a plurality of input traces 12122 , and the plurality of input traces 12122 are electrically connected to corresponding first signal traces 1221 , respectively.

[0066] Exemplarily, the first driving circuit 1211 in the circuit area 121 is taken as an example for further explanation. For example, three input traces 12122 are provided, and the first input trace 12122 extends into the bus area 122, and is electrically connected to the first electrode trace 141 above it through the first sub-transfer layer hole 131, and the first electrode trace 141 is electrically connected to the CK1 clock signal line through the second sub-transfer layer hole 132; the second input trace 12122 extends into the bus area 122, and is electrically connected to the second electrode trace 142 above it through another first sub-transfer layer hole 131, and the second electrode trace 142 is electrically connected to the gate-off signal line (VSS) through another second sub-transfer layer hole 132; the third input trace 12122 extends into the bus area 122, and is electrically connected to the LC1 low-frequency signal line, and its connection method is the same as the connection method of the above-mentioned CK1 clock signal line and the gate-off signal line (VSS), and will not be repeated here.

[0067] It can be understood that the above only lists the connection status of one driving circuit 1211. The connection method of other driving circuits 1211 is the same as the connection method of the first driving circuit 1211 mentioned above. The second driving circuit 1211 is electrically connected to the CK2 clock signal line, for example. The specific connection is subject to actual conditions.

[0068] In this embodiment, the gate driver circuit 12 further includes a first redundant low-level signal line 1231 and a first sacrificial electrode 1271 located thereon. A portion of the first redundant low-level signal line 1231 is located in the circuit region 121 and is disposed around the circuit region 121. The driver circuits 1211 in the circuit region 121 are sequentially arranged along the second direction, and the first redundant low-level signal line 1231 is, for example, disposed along the periphery of the arranged driver circuits 1211, i.e., the periphery of the circuit region 121.

[0069] Another part of the first redundant low-level signal line 1231 extends into the bus area 122 and is electrically connected to the first low-level signal line 12212 of the bus area 122. The first redundant low-level signal line 1231 is electrically connected to the first sacrificial electrode 1271 through the first transfer layer hole 13 to consume ions around the electrolytic cell, thereby protecting the electrode trace 14 in the gate drive circuit 12 to prevent it from failing and affecting the normal display of the display panel.

[0070] It should be noted that when the first redundant low-level signal line 1231 and the first sacrificial electrode 1271 are arranged around the circuit area 121, they intersect with the output line 12121 of the metal line 1212. If the output line 12121 is wrapped, a large capacitance may easily occur. Therefore, the output line 12121 can be avoided to reduce the capacitance.

[0071] First example

[0072] First redundant low-level signal line 1231 is disconnected at the output line 12121 to reduce capacitance at that location and prevent excessive capacitance from affecting normal display and lifespan. The disconnection location can be, for example, a first break (not shown) to avoid output line 12121.

[0073] Second example

[0074] Since the output trace 12121 is relatively thick, in order to minimize the capacitance of the output trace 12121 and the capacitance of the first redundant low-level signal line 1231, the first sacrificial electrode 1271 located at the position of the output trace 12121 can be disconnected, that is, a second break 143 can be set at this position to avoid the output trace 12121 and prevent the output trace 12121 from being wrapped, affecting normal use.

[0075] In this embodiment, the gate drive circuit 12 includes a first metal layer 123, a first insulating layer 124, a second metal layer 125, a second insulating layer 126, and a first electrode layer 127, which are sequentially arranged on the base substrate 11. The first signal trace 1221 is located in the first metal layer 123, the metal trace 1212 is located in the second metal layer 125, the first transfer hole 13 passes through the first insulating layer 124 and / or the second insulating layer 126, the first electrode trace 141, the second electrode trace 142, and the first sacrificial electrode 1271 are located in the first electrode layer 127, and the first redundant low-level signal line 1231 is located in the first metal layer 123. The first insulating layer 124 is used, for example, to separate the first metal layer 123 and the second metal layer 125, and the second insulating layer 126 is used, for example, to protect the second metal layer 125.

[0076] Since the stacking structure is different at different positions, different cutting points are further illustrated below.

[0077] First example

[0078] like Figure 7 , which is a cross-sectional schematic diagram of the connection position of the CK2 clock signal line and the metal trace 1212 at d.

[0079] A first metal layer 123, a first insulating layer 124, a second metal layer 125, a second insulating layer 126 and a first electrode layer 127 are stacked in sequence on the base substrate 11. The orthographic projection area of the second metal layer 125 on the base substrate 11 is smaller than the orthographic projection area of the first metal layer 123 on the base substrate 11, so that the second insulating layer 126 partially covers the second metal layer 125 and the remaining part covers the first insulating layer 124. The second insulating layer 126 can wrap the end of the second metal layer 125 and also isolate the second metal layer 125.

[0080] The second insulating layer 126 is provided with a first sub-transfer layer hole 131 to expose the second metal layer 125. The first electrode layer 127 covers the second insulating layer 126 and the first sub-transfer layer hole 131 and is electrically connected to the second metal layer 125. The second sub-transfer layer hole 132 passes through the second insulating layer 126 and the first insulating layer 124 in sequence to expose the first metal layer 123. The first electrode layer 127 extends into the first sub-transfer layer hole 131 and is connected to the first metal layer 123, thereby realizing the connectivity between the first metal layer 123 and the second metal layer 125.

[0081] The CK1 clock signal line is located in the first metal layer 123 , the input line 12122 in the metal line 1212 is located in the second metal layer 125 , and the first electrode line 141 is located in the first electrode layer 127 , thus achieving line connection.

[0082] Second example

[0083] like Figure 8 , which is a cross-sectional schematic diagram showing the position of the first redundant low-level signal line 1231 and the first sacrificial electrode 1271 located above it at a.

[0084] A first metal layer 123, a first insulating layer 124, a second insulating layer 126, and a first electrode layer 127 are sequentially stacked on the base substrate 11. A first transfer hole 13 sequentially penetrates the first and second insulating layers 124 and 126. A first sacrificial electrode 1271 in the first electrode layer 127 covers the second insulating layer 126 and the first transfer hole 13, achieving electrical connection with the first metal layer 123. A first redundant low-level signal line 1231 is located in the first metal layer 123.

[0085] The array substrate provided in this embodiment has a first redundant low-level signal line arranged on the first low-level signal line. The first redundant low-level signal line surrounds the circuit area. A first sacrificial electrode is arranged above the first redundant low-level signal line, and the metal layer and the first sacrificial electrode are connected by a first transfer layer hole, so that some ions in the gate drive circuit can be consumed by the first sacrificial electrode, that is, ions outside the drive circuit, thereby protecting the first transfer layer hole, metal routing, first signal routing and electrode routing, etc., so that their service life is not affected by electrochemical corrosion caused by high temperature and high humidity within a certain period of time, ensuring that the display panel can display normally and extending the service life of the display panel.

[0086] Second embodiment

[0087] Figure 2 A schematic top view of an array substrate provided in an embodiment of the present application is shown; Figure 9 for Figure 2 The schematic cross-sectional view at point b is shown; Figure 14 A block diagram of a display device provided in an embodiment of the present application.

[0088] The second embodiment of the present application further provides an array substrate having the same or similar structure as the array substrate provided in the first embodiment, except that the gate drive circuit 12 in this embodiment further includes a first redundant low-level signal line 1251 and a first sacrificial electrode 1272 located thereon, and a portion of the first redundant low-level signal line 1251 is located in the circuit region 121 and disposed around the circuit region 121. The drive circuits 1211 in the circuit region 121 are sequentially arranged along the second direction, and the first redundant low-level signal line 1251 is, for example, disposed along the periphery of the arranged circuit region 121.

[0089] Another part of the first redundant low-level signal line 1251 extends into the bus area 122 and is electrically connected to both ends of the pulse signal line 12213 in the bus area 122. The first redundant low-level signal line 1251 is electrically connected to the first sacrificial electrode 1272 through the first transfer layer hole 13 to consume ions around the electrolytic cell, thereby protecting the electrode trace 14 in the gate drive circuit 12 to prevent it from failing and affecting the normal display of the display panel.

[0090] In this embodiment, if Figure 9 , which is a cross-sectional schematic diagram showing the position of the first redundant low-level signal line 1251 and the first sacrificial electrode 1272 located above it at b.

[0091] The gate driver circuit 12 includes a first insulating layer 124, a second metal layer 125, a second insulating layer 126, and a first electrode layer 127, which are sequentially disposed on the base substrate 11. The specific configuration is the same as that in the first embodiment described above and will not be repeated here. The difference is that the first redundant low-level signal line 1251 is located on the second metal layer 125.

[0092] The second insulating layer 126 is provided with a first transfer hole 13. The first sacrificial electrode 1272 in the first electrode layer 127 covers the second insulating layer 126 and the first transfer hole 13 and is connected to the second metal layer 125. The first redundant low-level signal line 1251 is located in the second metal layer 125, and the first sacrificial electrode 1272 is located in the first electrode layer 127.

[0093] It should be noted that when the first redundant low-level signal line 1251 is connected to the pulse signal line 12213, the first sacrificial electrode 1272 is also required to achieve electrical connection. The film layer setting method can refer to the cross-sectional schematic diagram at point d in the first embodiment. The cross-sectional schematic diagram is the same as the cross-sectional schematic diagram at point d in the above-mentioned first embodiment, and will not be repeated here.

[0094] The array substrate provided in this embodiment has a first redundant low-level signal line arranged on the pulse signal line. The first redundant low-level signal line surrounds the circuit area. A first sacrificial electrode is arranged above the first redundant low-level signal line, and the metal layer and the first sacrificial electrode are connected by a first transfer layer hole, so that some ions in the gate drive circuit can be consumed by the first sacrificial electrode, that is, ions outside the drive circuit, thereby protecting the first transfer layer hole, metal routing, first signal routing and electrode routing, etc., so that their service life is not affected by electrochemical corrosion caused by high temperature and high humidity within a certain period of time, ensuring that the display panel can display normally and extending the service life of the display panel.

[0095] Third embodiment

[0096] Figure 3 A schematic top view of an array substrate provided in an embodiment of the present application; Figure 4 A schematic top view of an array substrate provided in an embodiment of the present application; Figure 5 A schematic top view of an array substrate provided in an embodiment of the present application; Figure 6 A schematic top view of an array substrate provided in an embodiment of the present application; Figure 14 A block diagram of a display device provided in an embodiment of the present application.

[0097] The third embodiment of the present application also provides an array substrate, which has the same or similar structure as the array substrate provided in the first embodiment and / or the second embodiment, except that the gate drive circuit 12 in this embodiment also includes a second redundant low-level signal line and a second sacrificial electrode located above it to achieve double protection and further enhance the protection effect.

[0098] First example

[0099] like Figure 3 As shown, the second redundant low-level signal line 1232 is electrically connected to the first low-level signal line 12212 in the bus area 122. The second redundant low-level signal line 1232 is, for example, located on the outer periphery of the first redundant low-level signal line 1231. A portion of the second redundant low-level signal line 1232 is located in the circuit area 121 and is disposed around the circuit area 121. Another portion of the second redundant low-level signal line 1232 extends into the bus area 122 to facilitate electrical connection to the first low-level signal line 12212 in the bus area 122.

[0100] The second redundant low-level signal line 1232 is electrically connected to the second sacrificial electrode 1273 through the first transfer hole 13 to consume ions around the electrolytic cell.

[0101] The connection method between the second redundant low-level signal line 1232 and the first low-level signal line 12212 is the same as the connection method between the first redundant low-level signal line 1231 and the first low-level signal line 12212 in the first embodiment, and is not repeated here.

[0102] Second example

[0103] like Figure 4 As shown, the second redundant low-level signal line 1252 is electrically connected to both ends of the pulse signal line 12213 of the bus area 122, and the second redundant low-level signal line 1252 is electrically connected to the second sacrificial electrode 1274 through the first transfer layer hole 13 to consume ions around the electrolytic cell.

[0104] The second redundant low-level signal line 1252 is located on the outer side of the first redundant low-level signal line 1251, for example. A portion of the second redundant low-level signal line 1252 is located in the circuit area 121 and is arranged around the circuit area 121. Another portion of the second redundant low-level signal line 1252 extends into the bus area 122 to facilitate electrical connection with the pulse signal line 12213 in the bus area 122.

[0105] The second redundant low-level signal line 1252 is electrically connected to the second sacrificial electrode 1274 through the first transfer hole 13 to consume ions around the electrolytic cell.

[0106] The connection method between the second redundant low-level signal line 1252 and the pulse signal line 12213 is the same as the connection method between the first redundant low-level signal line 1251 and the pulse signal line 12213 in the second embodiment, and will not be repeated here.

[0107] Third example

[0108] like Figure 5 As shown, the second redundant low-level signal line 1232 is electrically connected to the first low-level signal line 12212 in the bus area 122. The second redundant low-level signal line 1232 is located on the outer periphery of the first redundant low-level signal line 1251 in the second embodiment. A portion of the second redundant low-level signal line 1232 is located in the circuit area 121 and is arranged around the circuit area 121. Another portion of the second redundant low-level signal line 1232 extends into the bus area 122 to facilitate electrical connection with the first low-level signal line 12212 in the bus area 122.

[0109] The connection method between the second redundant low-level signal line 1232 and the first low-level signal line 12212 is the same as the connection method between the first redundant low-level signal line 1231 and the first low-level signal line 12212 in the first embodiment, and is not repeated here.

[0110] Fourth Example

[0111] like Figure 6 As shown, the second redundant low-level signal line 1252 is electrically connected to both ends of the pulse signal line 12213 of the bus area 122. The second redundant low-level signal line 1252 is located on the outer peripheral side of the first redundant low-level signal line 1231 as in the first embodiment. A portion of the second redundant low-level signal line 1252 is located in the circuit area 121 and is arranged around the circuit area 121. Another portion of the second redundant low-level signal line 1252 extends into the bus area 122 to facilitate electrical connection with the pulse signal line 12213 in the bus area 122.

[0112] The connection method between the second redundant low-level signal line 1252 and the pulse signal line 12213 is the same as the connection method between the first redundant low-level signal line 1251 and the pulse signal line 12213 in the second embodiment, and will not be repeated here.

[0113] The second redundant low-level signal line is configured on the first metal layer 123 or the second metal layer 125. Different configurations of the second redundant low-level signal line can achieve different purposes and effects, thereby increasing the flexibility of the configuration and meeting different requirements.

[0114] The array substrate provided in this embodiment is provided with a first redundant low-level signal line and a second redundant low-level signal line, which can consume part of the ions in the gate drive circuit, that is, the ions outside the drive circuit, and is provided with a double layer, which effectively improves the consumption effect, so that its life is not affected by the electrochemical corrosion caused by high temperature and high humidity within a certain period of time, ensuring that the display panel can display normally and extending the service life of the display panel.

[0115] Fourth embodiment

[0116] Figure 10 A schematic top view of an intermediate node of a circuit provided in an embodiment of the present application; Figure 12 for Figure 10 The cross-sectional schematic diagram at c is shown; Figure 13 for Figure 10 The schematic cross-sectional view at point e is shown; Figure 14 A block diagram of a display device provided in an embodiment of the present application.

[0117] The third embodiment of the present application further provides an array substrate having the same or similar structure as the array substrate provided in the first and / or second embodiments thereof, except that the gate drive circuit 12 includes an intermediate circuit node 1213 located in the circuit region 121. The intermediate circuit node 1213 is a node located between a TFT (Thin Film Transistor) and a plurality of circuits and is used for connecting and transmitting signals. For example, the intermediate circuit node 1213 may be a node between the circuit region 121 and the bus region 122, and functions as a signal transmission and conversion node in the gate drive circuit 12, thereby ensuring the normal operation of the GOA circuit.

[0118] Intermediate circuit nodes 1213, such as the frame synchronization node (Fn), burst control node (Qn), polarity inversion node (Pn), address enable node (An), and gate drive node (Gn), are connected to TFT devices or bus region 122 via traces to receive and transmit signals, enabling the circuit's progressive scan function. These nodes are critical transit points for signal transmission, ensuring accurate signal delivery within complex circuits. The following example illustrates intermediate circuit node 1213 as Qn.

[0119] When a third transfer hole 12131 is present in the circuit region 121 at the mid-circuit node 1213, a second electrode layer 12132 is disposed above the mid-circuit node 1213. Other signal lines, such as a second signal line 1214, are disposed around the mid-circuit node 1213. The root square voltage of the second signal line 1214 is greater than the root square voltage of the mid-circuit node 1213. In this case, the second signal line 1214 may cause corrosion to the second electrode layer 12132.

[0120] In this embodiment, a redundant signal line 1215 is provided between a mid-circuit node 1213 and a second signal line 1214. A third sacrificial electrode 1216 is provided above the redundant signal line 1215. The redundant signal line 1215 is electrically connected to the third sacrificial electrode 1216 via a second transfer hole 1217. The root square voltage of the mid-circuit node 1213 is greater than the root square voltage of the redundant signal line 1215.

[0121] At this time, when the second signal line 1214 causes electrochemical corrosion of the surrounding electrodes, the redundant signal line 1215 will be corroded first, thereby effectively protecting the second electrode layer 12132.

[0122] The second signal line 1214 can be, for example, a metal trace or a TFT device for signals such as An and Pn, and its root-square voltage is relatively high. The second signal line 1214 can be one, two, or three. When the second signal line 1214 is one, it can be in an L shape, half-circling the middle node 1213 of the circuit; or, when the second signal line 1214 is three, it can be along the following lines: Figure 10 In the directions shown, namely, the upper side, the upper right side and the right side, a second signal line 1214 is provided, and the specific location shall be subject to actual conditions.

[0123] A redundant signal line 1215 with a lower root voltage is introduced between the second signal line 1214 and the middle node 1213 of the circuit. When the second signal line 1214 electrochemically corrodes the surrounding electrodes, the redundant signal line 1215 is corroded first, thereby protecting the second electrode layer 12132 on the middle node 1213 of the circuit.

[0124] The redundant signal line 1215 can be adjusted according to the actual situation, and can be set to one or two. Figure 11 As shown, redundant signal line 1215 includes a first sub-redundant routing line 12151 and a second sub-redundant routing line 12152. First sub-redundant routing line 12151 extends along the periphery of a mid-circuit node 1213, while second sub-redundant routing line 12152 is disposed between first sub-redundant routing line 12151 and second signal line 1214 and extends along the periphery of first sub-redundant routing line 12151. First sub-redundant routing line 12151 can be, for example, Z-shaped to completely isolate mid-circuit node 1213 from signal line 1214. Second sub-redundant routing line 12151 can also be Z-shaped, providing dual interception between first sub-redundant routing line 12151 and second sub-redundant routing line 12152, further enhancing protection capabilities.

[0125] In this embodiment, if Figure 12 As shown, a cross-sectional schematic diagram of the position of the second electrode layer 12132 at c is shown.

[0126] The gate drive circuit 12 includes a first metal layer 123, a first insulating layer 124, a second metal layer 125, a second insulating layer 126, and a second electrode layer 12132, which are sequentially disposed on the base substrate 11. The second insulating layer 126 is provided with a third transfer hole 12131, and the second electrode layer 12132 is electrically connected to the second metal layer 125 through the third transfer hole 12131. The intermediate node 1213 of the circuit is, for example, disposed on the first metal layer 123.

[0127] In this embodiment, if Figure 13 As shown, a cross-sectional schematic diagram of the position of the circuit intermediate node 1213 at e is shown.

[0128] The gate drive circuit 12 includes a first metal layer 123, a first insulating layer 124, a second metal layer 125, a second insulating layer 126 and a third sacrificial electrode 1216, which are sequentially arranged on the base substrate 11. The second insulating layer 126 is provided with a second transfer layer hole 1217, and the third sacrificial electrode 1216 is electrically connected to the second metal layer 125 through the second transfer layer hole 1217.

[0129] The redundant signal line 1215 and the circuit intermediate node 1213 are, for example, provided in the first metal layer 123 , the second signal line 1214 is, for example, provided in the second metal layer 125 , and the third sacrificial electrode 1216 is provided in the second electrode layer 12132 .

[0130] The redundant signal line 1215 is, for example, VSS, and the intermediate node 1213 of the circuit can be, for example, an upward pulse wave STV, FN, Qn, Gn that occurs only once in a frame, or a downward pulse wave Pn, An that occurs only once in a frame. From the perspective of the root mean square voltage, the root mean square voltage in this application is sorted from high to low as An / Pn>CK1~CK4 / LC1 / LC2>STV / Fn / Qn / Gn>VSS.

[0131] The array substrate provided in this embodiment has a third sacrificial electrode specifically arranged on the driving circuit to consume excess ions in the circuit area, protect the structure inside the circuit area, and prevent its life from being affected by electrochemical corrosion caused by high temperature and high humidity within a certain period of time, thereby extending its service life and ensuring normal display of the display panel.

[0132] Fifth embodiment

[0133] Figure 14 A block diagram of a display device provided in an embodiment of the present application is shown.

[0134] A fifth embodiment of the present application further provides a display device, comprising a display panel 2 and a housing, wherein the housing is connected to the display panel 2, and an array substrate 1 as described in any one of the first to fourth embodiments is disposed within the display panel. The array substrate 1 is disposed within the display panel 2 to meet the requirements and functions of the display device and to achieve normal display on the display panel.

[0135] It should be understood that the terms used herein are for the purpose of describing specific example embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "comprise", "include", "contain" and "have" are inclusive and therefore specify the presence of stated features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring them to be performed in the specific order described or illustrated, unless the order of execution is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0136] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates otherwise, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.

[0137] The foregoing description is intended only to provide specific embodiments of the present invention, which will enable those skilled in the art to understand and implement the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments shown herein, but is intended to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. An array substrate, comprising a base substrate, the base substrate having a display area and a non-display area, the non-display area being provided with a gate drive circuit, the gate drive circuit comprising a circuit area and a bus area sequentially arranged in a direction away from the display area, the bus area comprising a plurality of first signal lines, one end of the circuit area being connected to a portion of the plurality of first signal lines via a metal line, and the other end of the circuit area being connected to a scan line of the display area via a metal line; the plurality of first signal lines comprising a first high-level signal line, a first low-level signal line, and a pulse signal line; characterized in that: The gate drive circuit further includes a first redundant low-level signal line and a first sacrificial electrode located above the first redundant low-level signal line, a portion of the first redundant low-level signal line being located in and surrounding the circuit area, another portion of the first redundant low-level signal line extending to the bus area and electrically connected to both ends of the first low-level signal line or the pulse signal line in the bus area, and the first redundant low-level signal line being electrically connected to the first sacrificial electrode via a first transfer hole; The metal traces include output traces and input traces, one end of the circuit area is electrically connected to a plurality of the input traces, and the plurality of input traces are electrically connected to corresponding first signal traces, respectively, and the other end of the circuit area is electrically connected to one of the output traces; The first sacrificial electrode located at the output wiring position is disconnected; or the first redundant low-level signal line located at the output wiring position is disconnected.

2. The array substrate according to claim 1, wherein: The first high-level signal line includes a plurality of clock signal lines; the first low-level signal line includes a gate-off signal line, and the pulse signal line includes a frame start signal line; the first signal line also includes a low-frequency signal line; The plurality of first signal lines are sequentially arranged in a direction away from the display area; Among them, the frame start signal line is located on a side away from the display area, the gate shutdown signal line is set close to the circuit area, the multiple clock signal lines are arranged in sequence from the frame start signal line to the gate shutdown signal line, and the low-frequency signal line is set between the clock signal line and the gate shutdown signal line.

3. The array substrate according to claim 1, wherein: The gate drive circuit also includes a second redundant low-level signal line and a second sacrificial electrode located above the second redundant low-level signal line, the second redundant low-level signal line is located on the outer side of the first redundant low-level signal line, a portion of the second redundant low-level signal line is located in the circuit area and is arranged around the gate drive circuit, another portion of the second redundant low-level signal line extends to the bus area and is electrically connected to both ends of the first low-level signal line or the pulse signal line in the bus area, and the second redundant low-level signal line is electrically connected to the second sacrificial electrode through the first transfer hole.

4. The array substrate according to claim 3, wherein: The gate drive circuit includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a first electrode layer sequentially arranged on the base substrate, the first signal trace is located in the first metal layer, the metal trace is located in the second metal layer, the first transfer hole passes through the first insulating layer and / or the second insulating layer, and the first sacrificial electrode and the second sacrificial electrode are both located in the first electrode layer; The first redundant low-level signal line is located in the first metal layer or the second metal layer, and the second redundant low-level signal line is located in the first metal layer or the second metal layer.

5. The array substrate according to claim 1, wherein: The gate driving circuit includes a circuit middle node located in the circuit area, and a second signal line is arranged around the circuit middle node; A redundant signal line is provided between the intermediate node of the circuit and the second signal line, a third sacrificial electrode is provided above the redundant signal line, and the redundant signal line is electrically connected to the third sacrificial electrode through a second transfer hole.

6. The array substrate according to claim 5, wherein: The root square voltage of the second signal line is greater than the root square voltage of the middle node of the circuit, and the root square voltage of the middle node of the circuit is greater than the root square voltage of the redundant signal line.

7. The array substrate according to claim 5, wherein: The redundant signal line includes a first sub-redundant line and a second sub-redundant line; The first sub-redundant routing line extends along the outer periphery of the middle node of the circuit, and the second sub-redundant routing line is provided between the first sub-redundant routing line and the second signal line and extends along the outer periphery of the first sub-redundant routing line.

8. A display device, characterized in that: The invention comprises a display panel and a shell, wherein the shell is connected to the display panel, and the array substrate according to any one of claims 1 to 7 is arranged in the display panel.

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