Circuit structure of programmable logic array, configuration method, terminal, medium and chip

Abstract

The invention provides a circuit structure of a programmable logic array, a configuration method, a terminal, a medium and a chip. The circuit structure comprises a front-stage filtering control module, a front-stage configurable arithmetic logic module, a rear-stage filtering control module, a rear-stage configurable arithmetic logic module and a configurable trigger module which are connected in sequence, wherein the pre-stage filtering control module, the pre-stage configurable arithmetic logic module, the post-stage filtering control module, the post-stage configurable arithmetic logic module and the configurable trigger module are configured according to the obtained target signal generation requirement, so that the output of the circuit structure meets the target signal generation requirement. The programmable logic array can be flexibly configured according to the signal generation requirement, the flexibility of the programmable logic array is improved, and the universality of a control system in which the programmable logic array is introduced is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, and particularly to a circuit structure, configuration method, terminal, medium, and chip of a programmable logic array. Background Art

[0002] In the field of industrial control, there are a rich variety of control methods and hardware circuits. To reduce costs, it has become increasingly common to use application-specific integrated circuits to implement various controls. However, application-specific integrated circuits have strong specificity and poor universality, and it is difficult to flexibly adjust functions after design and production. Summary of the Invention

[0003] In view of the above-mentioned disadvantages of the prior art, the purpose of this application is to provide a circuit structure, control method, terminal, medium, and chip of a programmable logic array, which is used to solve the problems of strong specificity, poor universality, and difficulty in flexibly adjusting functions after design and production in the prior art.

[0004] To achieve the above purpose and other related purposes, the first aspect of this application provides a circuit structure of a programmable logic array, including: a pre-stage filtering control module, a pre-stage configurable arithmetic logic module, a post-stage filtering control module, a post-stage configurable arithmetic logic module, and a configurable flip-flop module connected in sequence; wherein, n inputs and n outputs of the circuit structure are respectively connected to the pre-stage filtering control module; the n outputs of the circuit structure are the n outputs of the configurable flip-flop module; n is a positive integer; according to the generation requirements of the obtained target signal, the pre-stage filtering control module, the pre-stage configurable arithmetic logic module, the post-stage filtering control module, the post-stage configurable arithmetic logic module, and the configurable flip-flop module are respectively configured, so that the n outputs of the circuit structure meet the generation requirements of the target signal.

[0005] In some embodiments of the first aspect of the present application, the pre-stage filtering control module is composed of 2n pre-stage filtering control units; wherein, n of the 2n pre-stage filtering control units are respectively and correspondingly connected to n inputs of the circuit structure, and the remaining n pre-stage filtering control units are respectively and correspondingly connected to n outputs of the circuit structure; the outputs of the 2n pre-stage filtering control units are respectively connected to the pre-stage configurable arithmetic logic module; configuring the pre-stage filtering control module according to the obtained target signal generation requirement includes: determining the filtering mode adopted by each pre-stage filtering control unit and setting the corresponding mode parameters among a variety of pre-set filtering modes according to the obtained target signal generation requirement, so that each pre-stage filtering control unit performs corresponding filtering operations according to the determined filtering mode and the set mode parameters; the variety of pre-set filtering modes include: synchronous shaping mode, input high-level expansion mode, input low-level expansion mode, edge detection mode, and hysteresis jump mode.

[0006] In some embodiments of the first aspect of the present application, configuring the pre-stage configurable arithmetic logic module according to the obtained target signal generation requirement includes: determining the pre-stage arithmetic mode combination corresponding to each output of the pre-stage configurable arithmetic logic module according to the obtained target signal generation requirement and a variety of pre-set arithmetic modes, so that the pre-stage configurable arithmetic logic module performs corresponding pre-stage output arithmetic operations according to the internal pre-stage output arithmetic mode and the determined pre-stage arithmetic mode combinations.

[0007] In some embodiments of the first aspect of the present application, the post-stage filtering control module is composed of m post-stage filtering control units; wherein, the m post-stage filtering control units are respectively and correspondingly connected to m outputs of the pre-stage configurable arithmetic logic module; the outputs of the m post-stage filtering control units are respectively connected to the post-stage configurable arithmetic logic module; configuring the post-stage filtering control module according to the obtained target signal generation requirement includes: determining the filtering mode adopted by each post-stage filtering control unit and setting the corresponding mode parameters among a variety of pre-set filtering modes according to the obtained target signal generation requirement, so that each post-stage filtering control unit performs corresponding filtering operations according to the determined filtering mode and the set mode parameters; the variety of pre-set filtering modes include: synchronous shaping mode, input high-level expansion mode, input low-level expansion mode, edge detection mode, and hysteresis jump mode.

[0008] In some embodiments of the first aspect of the present application, the post-stage configurable arithmetic logic module has n groups of outputs; wherein, configuring the post-stage configurable arithmetic logic module according to the obtained target signal generation requirement includes: determining, according to the obtained target signal generation requirement and a variety of preset arithmetic modes, the post-stage arithmetic mode combination corresponding to each output in each group of outputs of the post-stage configurable arithmetic logic module, so that the post-stage configurable arithmetic logic module performs corresponding post-stage output arithmetic operations according to the internally set post-stage output arithmetic mode and the determined post-stage arithmetic mode combinations.

[0009] In some embodiments of the first aspect of the present application, the configurable flip-flop module is composed of n configurable flip-flop units; wherein, the n configurable flip-flop units are respectively connected in one-to-one correspondence with the n groups of outputs of the post-stage configurable arithmetic logic module; configuring the configurable flip-flop module according to the obtained target signal generation requirement includes: respectively setting the flip-flop type and clock type of each configurable flip-flop unit according to the obtained target signal generation requirement; according to the set flip-flop type of each configurable flip-flop unit, connecting each output in each group of outputs of the post-stage configurable arithmetic logic module to the corresponding configurable flip-flop unit according to the preset flip-flop mapping relationship.

[0010] To achieve the above object and other related objects, the second aspect of the present application provides a configuration method for a circuit structure of a programmable logic array, which is applied to the circuit structure of the programmable logic array. The circuit structure of the programmable logic array includes: a pre-stage filter control module, a pre-stage configurable arithmetic logic module, a post-stage filter control module, a post-stage configurable arithmetic logic module, and a configurable flip-flop module connected in sequence. The method includes: obtaining a target signal generation requirement; respectively configuring the pre-stage filter control module, the pre-stage configurable arithmetic logic module, the post-stage filter control module, the post-stage configurable arithmetic logic module, and the configurable flip-flop module according to the obtained target signal generation requirement, so that the output of the circuit structure meets the target signal generation requirement.

[0011] To achieve the above object and other related objects, the third aspect of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the configuration method for the circuit structure of the programmable logic array is implemented.

[0012] To achieve the above object and other related objects, the fourth aspect of the present application provides an electronic terminal, including a memory, a processor, and a computer program stored on the memory; the processor executes the computer program to implement the configuration method for the circuit structure of the programmable logic array.

[0013] To achieve the above and other related objectives, a fifth aspect of the present application provides a chip, on which a circuit structure of the programmable logic array as described above is provided.

[0014] As described above, the circuit structure, configuration method, terminal, medium, and chip of the programmable logic array of the present application have the following beneficial effects:

[0015] The present application can flexibly configure the programmable logic array according to signal generation requirements, improving the flexibility of the programmable logic array, and thus enhancing the universality of the control system incorporating the programmable logic array. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It shows a schematic block diagram of the circuit structure of the programmable logic array in an embodiment of the present application.

[0017] Figure 2 It shows a specific structural schematic diagram of the circuit structure of the programmable logic array in an embodiment of the present application.

[0018] Figure 3 It shows a configuration schematic diagram of the synchronization levels in an embodiment of the present application.

[0019] Figure 4 It shows a flowchart of the configuration method of the circuit structure of the programmable logic array in an embodiment of the present application.

[0020] Figure 5 It shows a structural schematic diagram of an electronic terminal in an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] The following uses specific specific examples to illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0022] In the embodiments of the present application, terms such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. Those skilled in the art can understand that the terms "first" and "second" do not limit the quantity and execution order, and the terms "first" and "second" do not necessarily limit to being different.

[0023] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0024] In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or its similar expression refers to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a, b or c can represent: a, b, c, a - b, a - c, b - c or a - b - c, where a, b, c can be single or multiple.

[0025] For ease of understanding the embodiments of the present application, first in combination with Figure 1 Detailed description. Figure 1 Fig. shows a schematic block diagram of the circuit structure of a programmable logic array in an embodiment of the present invention. The circuit structure of the programmable logic array in this embodiment includes:

[0026] A pre - stage filtering control module 1, a pre - stage configurable arithmetic logic module 2, a post - stage filtering control module 3, a post - stage configurable arithmetic logic module 4, and a configurable flip - flop module 5 connected in sequence;

[0027] Among them, n inputs and n outputs of the circuit structure are respectively connected to the pre - stage filtering control module 1; the n outputs of the circuit structure are the n outputs of the configurable flip - flop module 5; n is a positive integer;

[0028] According to the obtained target signal generation requirements, the pre - stage filtering control module 1, the pre - stage configurable arithmetic logic module 2, the post - stage filtering control module 3, the post - stage configurable arithmetic logic module 4, and the configurable flip - flop module 5 are respectively configured so that the n outputs of the circuit structure meet the target signal generation requirements.

[0029] It should be noted that the present invention can flexibly configure the programmable logic array to obtain different types of signal outputs. When a control device (such as a chip) adopts the programmable logic array of the present invention, different control signals can be configured through the configuration of the programmable logic array to achieve the universality of the control device.

[0030] In one embodiment, the types of target signal generation requirements include, but are not limited to, combinational logic signal generation requirements, sequential logic signal generation requirements, pulse signal generation requirements, etc. For example, if the target signal generation requirement is a pulse signal generation requirement, under this condition, the output of the circuit structure is a pulse signal.

[0031] In one embodiment, as Figure 2 shown, the pre-stage filtering control module 1 is composed of 2n pre-stage filtering control units 11; among them, n pre-stage filtering control units 11 ( Figure 2 among the pre-stage filtering control unit 1, pre-stage filtering control unit 2,..., pre-stage filtering control unit n) are respectively connected to n inputs of the circuit structure ( Figure 2 among INPUT1, INPUT2,..., INPUTn), and the remaining n pre-stage filtering control units ( Figure 2 among the pre-stage filtering control unit n + 1, pre-stage filtering control unit n + 2,..., pre-stage filtering control unit 2n) are respectively connected to n outputs of the circuit structure ( Figure 2 among OUTPUT1, OUTPUT2,..., OUTPUTn); the outputs of the 2n pre-stage filtering control units 11 ( Figure 2 among L1_FILTER1, L1_FILTER2,..., L1_FILTER2n) are respectively connected to the pre-stage configurable arithmetic logic module 12;

[0032] Configuring the pre-stage filtering control module 1 according to the obtained target signal generation requirement includes: according to the obtained target signal generation requirement, determining the filtering mode adopted by each pre-stage filtering control unit 11 and setting the corresponding mode parameters among a variety of pre-set filtering modes, so that each pre-stage filtering control unit 11 performs the corresponding filtering operation according to the determined filtering mode and the set mode parameters; among them, the variety of pre-set filtering modes include: synchronous shaping mode, input high-level expansion mode, input low-level expansion mode, edge detection mode, and hysteresis jump mode.

[0033] Specifically, according to the target signal generation requirement, select a filtering mode for each pre-stage filtering control unit 11 among a variety of pre-set filtering modes, and after determining the filtering mode of the pre-stage filtering control unit 11, set the corresponding mode parameters according to the determined filtering mode. The pre-stage filtering control unit 11 will perform the corresponding filtering operation according to the selected filtering mode and the configured mode parameters for it.

[0034] The mode parameter corresponding to the synchronous shaping mode is the number of synchronous stages. As Figure 3As shown, the synchronization level is the number of registers for synchronization shaping. The filtering operation corresponding to the synchronization shaping mode specifically includes: the pre-stage filtering control unit uses the system working clock (the working clock of the circuit structure) to sample the signal input to the pre-stage filtering control unit. After sampling by the system working clock, the output of the pre-stage filtering control unit is synchronized with the system working clock.

[0035] The mode parameter corresponding to the input high-level extension mode is the number of high-level working clock cycles K1 for extension. The filtering operation corresponding to the input high-level extension mode specifically includes: after the input of the current-stage filtering control unit jumps from low level to high level in a certain system working clock cycle, the pre-stage filtering control unit also jumps from low level to high level in the next system working clock cycle. After the input of the current-stage filtering control unit jumps from high level to low level in a certain system working clock cycle, the counter inside the pre-stage filtering control unit starts working in the next system working clock cycle, subtracting one for each system working clock cycle starting from K1. The output of the pre-stage filtering control unit remains high level until the counter becomes 0. If during the counting of the counter, the input of the pre-stage filtering control unit jumps from low level to high level, the counter will be reset to K1 and maintained in the next system working clock cycle of the jump cycle until the input of the pre-stage filtering control unit jumps from high level to low level again and then starts counting. The input high-level extension mode can keep the output at high level for K1 more system working clock cycles after the disappearance of the input high level. The input high-level extension mode can expand the input jump.

[0036] The mode parameter corresponding to the input low-level extension mode is the number of low-level working clock cycles K2 for extension. The filtering operation corresponding to the input low-level extension mode specifically includes: after the input of the current-stage filtering control unit jumps from high level to low level in a certain system working clock cycle, the pre-stage filtering control unit also jumps from high level to low level in the next system working clock cycle. After the input of the current-stage filtering control unit jumps from low level to high level in a certain system working clock cycle, the counter inside the pre-stage filtering control unit starts working in the next system working clock cycle, subtracting one for each system working clock cycle starting from K2. The output of the pre-stage filtering control unit remains low level until the counter becomes 0. If during the counting of the counter, the input of the pre-stage filtering control unit jumps from high level to low level, the counter will be reset to K and maintained in the next system working clock cycle of the jump until the input of the pre-stage filtering control unit jumps from low level to high level again and then starts counting. The input low-level extension mode can keep the output at low level for K2 more system working clock cycles after the disappearance of the input low level. The input low-level extension mode can expand the input jump.

[0037] The mode parameter corresponding to the edge detection mode is the jump mode. The types of the jump mode include rising edge (the input jumps from low level to high level), falling edge (the input jumps from high level to low level), and dual edge (both the input jumping from high level to low level and the input jumping from low level to high level are detected). The filtering operation corresponding to the edge detection mode specifically includes: when a jump of a specified type (any one of rising edge, falling edge, or dual edge) occurs at the input, the output is a high level that lasts for one system working clock cycle, and after the end of this system working clock cycle, the output becomes low level. That is, every time a jump of a specified type occurs at the input, a pulse of one system working clock cycle is output.

[0038] The mode parameter corresponding to the hysteresis jump mode is the number of system working clock cycles of hysteresis. The filtering operation corresponding to the hysteresis jump mode specifically includes: when a jump occurs at the input, the output remains unchanged and holds for the number of system working clock cycles corresponding to the number of system working clock cycles of hysteresis. If the input is still the input after the jump after the number of system working clock cycles corresponding to the number of system working clock cycles of hysteresis, the output becomes the input after the jump. If the input jumps back to the initial input within the number of system working clock cycles corresponding to the number of system working clock cycles of hysteresis, the output remains unchanged. The hysteresis jump mode can filter unstable input states. For example, assume the number of system working clock cycles is set to 3. When the input changes from low level to high level, the output remains low for 3 working clock cycles. After 3 working clock cycles, if the input is still high, the output becomes high. If the input changes from high level to low level within 3 working cycles, the output remains low after 3 working clock cycles.

[0039] In one embodiment, configuring the pre-stage configurable arithmetic logic module according to the obtained target signal generation requirements includes: determining the pre-stage arithmetic mode combination corresponding to each output of the pre-stage configurable arithmetic logic module according to the obtained target signal generation requirements and a variety of preset arithmetic modes, so that the pre-stage configurable arithmetic logic module performs corresponding pre-stage output arithmetic operations according to the internal pre-stage output arithmetic mode and the determined pre-stage arithmetic mode combinations.

[0040] Specifically, as Figure 2 shown, the inputs of the pre-stage configurable arithmetic logic module 2 are the outputs of 2n pre-stage filter control units 11 (L1_FILTER1, L1_FILTER2,....... L1_FILTER2n). The pre-stage configurable arithmetic logic module 2 has m outputs (CFG_ALU1_1, CFG_ALU1_2,...... CFG_ALU1_m), where m is a positive integer.

[0041] The x-th output of the pre-stage configurable arithmetic logic module 2 is equipped with a 4n-bit first configurable parameter, where x is any integer in 1, 2, …, m. The pre-stage arithmetic mode combination corresponding to the x-th output is determined by configuring the first configurable parameter. The first configurable parameter consists of 2n first sub-level configurable parameters with a width of 2 bits. The 2n first sub-level configurable parameters correspond one-to-one with the 2n inputs of the pre-stage configurable arithmetic logic module 2, and each first sub-level configurable parameter defines the arithmetic mode of the corresponding input. The first sub-level configurable parameter with a width of 2 bits can represent 4 states, and each state corresponds to an arithmetic mode. The four arithmetic modes are the select low level mode, the select input mode, the select input inverted signal mode, and the select high level mode. For example, when the first configurable parameter is 00, the corresponding arithmetic mode is the select low level mode; when the first configurable parameter is 01, the corresponding arithmetic mode is the select input mode; when the first configurable parameter is 10, the corresponding arithmetic mode is the select input inverted signal mode; when the first configurable parameter is 11, the corresponding arithmetic mode is the select high level mode.

[0042] The pre-stage output arithmetic operation includes: based on the inputs of the pre-stage configurable arithmetic logic module, calculating each output of the pre-stage configurable arithmetic logic module according to the internally set pre-stage output arithmetic mode and each pre-stage arithmetic mode combination, so as to obtain all outputs of the pre-stage configurable arithmetic logic module. Among them, the pre-stage configurable arithmetic logic module 2 performs arithmetic operations on each output of the pre-stage configurable arithmetic logic module 2 according to the following formula 1:

[0043] CFG_ALU1_x = MODE1_x(L1_FILTER1) & MODE2_x(L1_FILTER2) & … & MODE2n_x(L1_FILTER2n); (Formula 1)

[0044] Where x is any integer in 1, 2, …, m, CFG_ALU1_x represents the x-th output of the pre-stage configurable arithmetic logic module, & represents that the internally set pre-stage output arithmetic mode of the pre-stage configurable arithmetic logic module is a logical AND operation, and MODE1_x, MODE2_x, …, MODE2n_x represent the pre-stage arithmetic mode combination corresponding to the x-th output.

[0045] When MODEp_x is the select low level mode, MODEp_x(L1_FILTERp) = 0 (0 represents low level);

[0046] When MODEp_x is the select input mode, MODEp_x(L1_FILTERp) = L1_FILTERp;

[0047] When MODEp_x is in the mode of selecting the input reverse signal, MODEp_x(L1_FILTERp) = ～ L1_FILTERp; where, "~" is the logical inverse operation. When L1_FILTERp is at a high level, ～ L1_FILTERp is at a low level; when L1_FILTERp is at a low level, ～ L1_FILTERp is at a high level;

[0048] When MODEp_x is in the mode of selecting the high level, MODEp_x(L1_FILTERp) = 1 (1 represents the high level);

[0049] where, p is any integer in 1, 2,..., 2n.

[0050] In the case where the built-in operation mode is the logical AND operation, when the results of 2n MODEs are all at the high level, CFG_ALU1_x is at the high level; otherwise, CFG_ALU1_x is at the low level.

[0051] In an embodiment, as Figure 2 shown, the post-stage filter control module 3 is composed of m post-stage filter control units 31; where, the m post-stage filter control units 31 ( Figure 2 the post-stage filter control unit 1, the post-stage filter control unit 2,..., the post-stage filter control unit m) in Figure 2 are respectively and correspondingly connected to the m outputs (

[0052] CFG_ALU1_1, CFG_ALU1_2,..., CFG_ALU1_m) of the pre-stage configurable operation logic module 2; the outputs of the m post-stage filter control units 31 are respectively connected to the post-stage configurable operation logic module 4. Configuring the post-stage filter control module 3 according to the obtained target signal generation requirement includes: determining the filter mode adopted by each post-stage filter control unit 31 and setting the corresponding mode parameters in a plurality of pre-set filter modes according to the obtained target signal generation requirement, so that each post-stage filter control unit 31 performs the corresponding filtering operation according to the determined filter mode and the set mode parameters; the plurality of pre-set filter modes include: synchronous shaping mode, input high level expansion mode, input low level expansion mode, edge detection mode, and hysteresis jump mode.

[0053] Specifically, according to the requirements for generating the target signal, in a variety of preset filtering modes, a filtering mode is selected for each post-stage filtering control unit 11. After determining the filtering mode of the post-stage filtering control unit 11, the corresponding mode parameters are configured according to the determined filtering mode. The post-stage filtering control unit 11 will perform the corresponding filtering operation according to the selected filtering mode and the configured mode parameters. It should be noted that the mode parameters and filtering operations corresponding to the synchronous shaping mode, input high-level expansion mode, input low-level expansion mode, edge detection mode, and hysteresis jump mode have been described in the above embodiments and will not be elaborated here.

[0054] In one embodiment, as Figure 2 shown, the post-stage configurable arithmetic logic module has n groups of outputs. Among them, configuring the post-stage configurable arithmetic logic module according to the obtained requirements for generating the target signal includes: determining the post-stage arithmetic mode combination corresponding to each output in each group of outputs of the post-stage configurable arithmetic logic module according to the obtained requirements for generating the target signal and a variety of preset arithmetic modes, so that the post-stage configurable arithmetic logic module performs the corresponding post-stage output arithmetic operation according to the internally set post-stage output arithmetic mode and the determined post-stage arithmetic mode combinations.

[0055] Specifically, as Figure 2 shown, the input of the post-stage configurable arithmetic logic module 4 is the outputs (L2_FILTER1, L2_FILTER2,....... L2_FILTERm) of m post-stage filtering control units 31.

[0056] The post-stage configurable arithmetic logic module 4 has n groups of outputs (CFG_ALU2_1 / CFG_ALU2_2…CFG_ALU2_7, CFG_ALU2_8 / CFG_ALU2_9…CFG_ALU2_14, ……, CFG_ALU2_6n+1 / CFG_ALU2_6n+2…CFG_ALU2_7n), and each group of outputs consists of 7 outputs. n and m are positive integers.

[0057] The y-th output of the post-stage configurable arithmetic logic module 2 is equipped with a 2m-bit second configurable parameter, where y is any integer in 1, 2, …, 7n. By configuring the second configurable parameter, the pre-stage arithmetic mode combination corresponding to the y-th output is determined. The configurable parameter consists of m 2-bit wide second sub-stage configurable parameters. The m 2-bit wide second sub-stage configurable parameters correspond one-to-one with the m inputs of the post-stage configurable arithmetic logic module 2, and each second sub-stage configurable parameter defines the arithmetic mode of the corresponding input. The 2-bit wide second sub-stage configurable parameter can represent 4 states, and each state corresponds to an arithmetic mode. The four arithmetic modes are the select low level mode, the select input mode, the select input inverted signal mode, and the select high level mode. For example, when the second configurable parameter is 00, the corresponding arithmetic mode is the select low level mode; when the second configurable parameter is 01, the corresponding arithmetic mode is the select input mode; when the second configurable parameter is 10, the corresponding arithmetic mode is the select input inverted signal mode; when the second configurable parameter is 11, the corresponding arithmetic mode is the select high level mode.

[0058] The post-stage output arithmetic operation includes: based on the input of the post-stage configurable arithmetic logic module, according to the internally set post-stage output arithmetic mode and each post-stage arithmetic mode combination, calculate each output of the post-stage configurable arithmetic logic module, and then obtain all the outputs of the post-stage configurable arithmetic logic module. Among them, the post-stage configurable arithmetic logic module 4 performs arithmetic operations on each output of the post-stage configurable arithmetic logic module 4 according to the following formula 2:

[0059] CFG_ALU2_y = MODE1_y(L2_FILTER1)|MODE2_y(L1_FILTER2)|…|MODEm_x(L1_FILTERm); (Formula 2)

[0060] Where y is any integer in 1, 2, …, 7n, CFG_ALU2_y represents the y-th output of the post-stage configurable arithmetic logic module, "|" means that the internally set post-stage output arithmetic mode of the post-stage configurable arithmetic logic module is a logical OR operation, and MODE1_y, MODE2_y, …, MODEm_y represent the pre-stage arithmetic mode combinations corresponding to the y-th output.

[0061] When MODEq_y is the select low level mode, MODEq_y(L2_FILTERq) = 0 (0 represents low level);

[0062] When MODEq_y is the select input mode, MODEq_y(L2_FILTERq) = L2_FILTERq;

[0063] When MODEq_y is in the mode of selecting the input reverse signal, MODEq_y(L2_FILTERq) = ～ L2_FILTERq; where, "~" is the logical inverse operation. When L2_FILTERq is at a high level, ～ L2_FILTERq is at a low level; when L2_FILTERq is at a low level, ～ L2_FILTERq is at a high level;

[0064] When MODEq_y is in the mode of selecting the high level, MODEq_y(L2_FILTERq) = 1 (1 represents the high level);

[0065] where, q is any integer in 1, 2,..., m.

[0066] In the case where the built-in operation mode is the logical OR operation, when the results of m MODEs are all at a low level, CFG_ALU1_y is at a low level; otherwise, CFG_ALU1_y is at a high level.

[0067] In an embodiment, as Figure 1 and Figure 2 shown, the configurable flip-flop module 5 is composed of n configurable flip-flop units 51; where, the n configurable flip-flop units 51 are respectively connected in one-to-one correspondence with n groups of outputs of the subsequent configurable arithmetic logic module 4;

[0068] According to the obtained target signal generation requirements, the configuration of the configurable flip-flop module 5 includes: according to the obtained target signal generation requirements, setting the flip-flop type and clock type of each configurable flip-flop unit 51 respectively; according to the set flip-flop type of each configurable flip-flop unit 51, and in accordance with the pre-set flip-flop mapping relationship, connecting each output in each group of outputs of the subsequent configurable arithmetic logic module to the corresponding configurable flip-flop unit 51 respectively.

[0069] Specifically, each configurable flip-flop unit 51 has 7 inputs (which are 7 outputs in the corresponding group of outputs) and 1 output. According to the target signal generation requirements, set the flip-flop type and clock type of each configurable flip-flop unit 51. The flip-flop types include: D flip-flop, dual-edge clock flip-flop, T flip-flop, JK flip-flop, and latch. The clock types include: self-input clock and system clock. The pre-set flip-flop mapping relationship defines the functions of the 7 inputs of the flip-flop under each flip-flop type. The pre-set flip-flop mapping relationship can refer to Table 1 below:

[0070] Table 1. Flip-flop mapping relationship

[0071]

[0072] It should be noted that cfg_ff_input1 / 2 / 3 / 4 / 5 / 6 / 7 respectively represent the 7 inputs of the configurable flip-flop unit. "N / A" means that the current selected flip-flop type does not require this input bit, and the signal change on this input bit will not affect the state of the output of the configurable register. The self-input clock means that the current selected flip-flop uses the clock of cfg_ff_input2 as the working clock of the current selected flip-flop. When the system clock is selected, the signal change of cfg_ff_input2 will not affect the state of the output of the configurable register. Enable means whether the currently selected configurable flip-flop starts to work. When the input enable is in an invalid state, no matter how other inputs change, the output of the configurable flip-flop remains unchanged. When the input enable is in a valid state, the output of the configurable flip-flop will change accordingly according to other inputs. Input D means that the input is connected to the input terminal of the D flip-flop. Input T means that the input is connected to the input terminal of the T flip-flop. Input K means that the input is connected to the K input terminal of the JK flip-flop, and input J means that the input is connected to the J input terminal of the JK flip-flop. Asynchronous set means that the input is used to implement the asynchronous set function, asynchronous reset means that the input is used to implement the asynchronous reset function, synchronous reset means that the input is used to implement the synchronous reset function, and synchronous set means that the input is used to implement the synchronous set function. The asynchronous set function, asynchronous reset function, synchronous reset function, and synchronous set function can refer to existing flip-flops and will not be elaborated here.

[0073] It should be further noted that Table 1 is only an example of a flip-flop mapping relationship. Those skilled in the art can also set other flip-flop mapping relationships according to requirements, and the present invention does not limit this.

[0074] Figure 4 It is a schematic flowchart of the configuration method for the circuit structure of the programmable logic array provided by the embodiments of the present application. As Figure 4 shown, the configuration method for the circuit structure of the programmable logic array is applied to the circuit structure of the programmable logic array. The circuit structure of the programmable logic array includes: a pre-stage filter control module, a pre-stage configurable arithmetic logic module, a post-stage filter control module, a post-stage configurable arithmetic logic module, and a configurable flip-flop module connected in sequence. The method includes:

[0075] Step S41: Obtain the target signal generation requirement.

[0076] Step S42: According to the obtained target signal generation requirement, configure the pre-stage filter control module, the pre-stage configurable arithmetic logic module, the post-stage filter control module, the post-stage configurable arithmetic logic module, and the configurable flip-flop module respectively, so that the output of the circuit structure meets the target signal generation requirement.

[0077] It should be understood that the specific implementation processes of the above method steps have been described in the above structural embodiments. For the sake of brevity, they will not be repeated here.

[0078] In one embodiment, the n inputs and the n outputs of the circuit structure are respectively connected to the pre-stage filtering control module; the n outputs of the circuit structure are the n outputs of the configurable flip-flop module; n is a positive integer.

[0079] In one embodiment, the pre-stage filtering control module is composed of 2n pre-stage filtering control units; among them, n pre-stage filtering control units of the 2n pre-stage filtering control units are respectively and correspondingly connected to the n inputs of the circuit structure, and the remaining n pre-stage filtering control units are respectively and correspondingly connected to the n outputs of the circuit structure; the outputs of the 2n pre-stage filtering control units are respectively connected to the pre-stage configurable arithmetic logic module; configuring the pre-stage filtering control module according to the obtained target signal generation requirement includes: determining the filtering mode adopted by each pre-stage filtering control unit and setting the corresponding mode parameters in a variety of pre-set filtering modes according to the obtained target signal generation requirement, so that each pre-stage filtering control unit performs corresponding filtering operations according to the determined filtering mode and the set mode parameters; the variety of pre-set filtering modes include: synchronous shaping mode, input high-level expansion mode, input low-level expansion mode, edge detection mode, and hysteresis jump mode.

[0080] In one embodiment, configuring the pre-stage configurable arithmetic logic module according to the obtained target signal generation requirement includes: determining the pre-stage arithmetic mode combination corresponding to each output of the pre-stage configurable arithmetic logic module according to the obtained target signal generation requirement and a variety of pre-set arithmetic modes, so that the pre-stage configurable arithmetic logic module performs corresponding pre-stage output arithmetic operations according to the internal pre-stage output arithmetic mode and the determined pre-stage arithmetic mode combinations.

[0081] In one embodiment, the post-stage filtering control module is composed of m post-stage filtering control units; wherein, the m post-stage filtering control units are respectively and correspondingly connected to the m outputs of the pre-stage configurable arithmetic logic module; the outputs of the m post-stage filtering control units are respectively connected to the post-stage configurable arithmetic logic module; m is a positive integer; configuring the post-stage filtering control module according to the obtained target signal generation requirement includes: determining the filtering mode adopted by each post-stage filtering control unit and setting the corresponding mode parameters among a variety of pre-set filtering modes according to the obtained target signal generation requirement, so that each post-stage filtering control unit performs corresponding filtering operations according to the determined filtering mode and the set mode parameters; the variety of pre-set filtering modes include: synchronous shaping mode, input high-level expansion mode, input low-level expansion mode, edge detection mode, and hysteresis jump mode.

[0082] In one embodiment, the post-stage configurable arithmetic logic module has n groups of outputs; wherein, configuring the post-stage configurable arithmetic logic module according to the obtained target signal generation requirement includes: determining the post-stage arithmetic mode combination corresponding to each output in each group of outputs of the post-stage configurable arithmetic logic module according to the obtained target signal generation requirement and a variety of pre-set arithmetic modes, so that the post-stage configurable arithmetic logic module performs corresponding post-stage output arithmetic operations according to the internal post-stage output arithmetic mode and the determined post-stage arithmetic mode combinations.

[0083] In one embodiment, the configurable flip-flop module is composed of n configurable flip-flop units; wherein, the n configurable flip-flop units are respectively and correspondingly connected to the n groups of outputs of the post-stage configurable arithmetic logic module; configuring the configurable flip-flop module according to the obtained target signal generation requirement includes: respectively setting the flip-flop type and clock type of each configurable flip-flop unit according to the obtained target signal generation requirement; according to the set flip-flop types of each configurable flip-flop unit, connecting each output in each group of outputs of the post-stage configurable arithmetic logic module to the corresponding configurable flip-flop unit respectively according to the pre-set flip-flop mapping relationship.

[0084] Similar to the above embodiment, the present invention further provides a chip, on which the circuit structure of the programmable logic array as described above is provided. It should be noted that the circuit structure of the programmable logic array has been described in the above embodiment and will not be elaborated here.

[0085] Figure 5 It is a schematic block diagram of an electronic terminal provided by an embodiment of the present application. As Figure 5As shown, the electronic terminal includes: at least one processor 501, a memory 502, at least one network interface 503, and a user interface 505. Each component in the device is coupled together through a bus system 504. It can be understood that the bus system 504 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 504 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clear illustration, in Figure 5 all kinds of buses are labeled as the bus system.

[0086] Among them, the user interface 505 may include a display, a keyboard, a mouse, a trackball, a click gun, a button, a button, a touchpad, or a touch screen, etc.

[0087] It can be understood that the memory 502 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM, Read Only Memory), a programmable read-only memory (PROM, Programmable Read-Only Memory), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM, Static Random Access Memory), synchronous static random access memory (SSRAM, Synchronous Static Random Access Memory). The memory described in the embodiments of the present invention is intended to include but not limited to these and any other suitable categories of memories.

[0088] The memory 502 in the embodiments of the present invention is used to store various categories of data to support the operation of the electronic terminal 500. Examples of these data include: any executable program for operating on the electronic terminal 500, such as an operating system 5021 and an application program 5022; the operating system 5021 contains various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application program 5022 can contain various application programs, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The configuration method of the circuit structure for implementing the programmable logic array provided by the embodiments of the present invention can be included in the application program 5022.

[0089] The method disclosed in the embodiments of the present invention above can be applied to or implemented by the processor 501. The processor 501 may be an integrated circuit chip with signal processing capabilities. During implementation, the steps of the above method can be completed by the integrated logic circuit in hardware or instructions in software form in the processor 501. The above-mentioned processor 501 may be a general-purpose processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 501 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor 501 may be a microprocessor or any conventional processor, etc. Combining the steps of the accessory optimization method provided in the embodiments of the present invention can be directly embodied as being executed and completed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, and this storage medium is located in the memory. The processor reads the information in the memory and combines its hardware to complete the steps of the foregoing method.

[0090] In an exemplary embodiment, the electronic terminal 500 may be one or more application-specific integrated circuits (ASICs, Application Specific Integrated Circuit), DSPs, programmable logic devices (PLDs, ProgrammableLogic Device), complex programmable logic devices (CPLDs, Complex Programmable Logic Device) for executing the foregoing method.

[0091] According to the method provided in the embodiments of the present application, the present application also provides a computer program product, which includes: computer program code, when the computer program code runs on a computer, it causes the computer to execute Figure 1 the configuration method of the circuit structure of the programmable logic array in the shown embodiment.

[0092] According to the method provided in the embodiments of the present application, the present application also provides a computer-readable storage medium, which stores program code, when the program code runs on a computer, it causes the computer to execute Figure 1 the configuration method of the circuit structure of the programmable logic array in the shown embodiment.

[0093] As used herein, the terms "component", "module", "system", etc. are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be components. One or more components can reside in a process and / or thread of execution, and a component can be located on one computer and / or distributed between two or more computers. Further, these components can execute from various computer-readable media having various data structures stored thereon. A component can, for example, communicate by signals according to one or more data packets (e.g., data from two components interacting with each other from a local system, a distributed system, and / or a network, such as data interacting with other systems via signals over the Internet) through local and / or remote processes.

[0094] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in connection with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints of the technical solution. Skilled artisans may implement the described functionality in different ways for each particular application, but such implementation should not be considered to exceed the scope of this application.

[0095] Those skilled in the art can clearly understand that for the sake of convenience and brevity of description, the specific working processes of the systems, apparatuses, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0096] In several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the couplings or direct couplings or communication connections shown or discussed with each other can be through some interfaces. The indirect couplings or communication connections of apparatuses or units can be in electrical, mechanical, or other forms.

[0097] The unit described as a separation component may or may not be physically separated, and the component displayed as a unit may or may not be a physical unit, that is, it may be located in one place or distributed across multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0098] In addition, in each embodiment of this application, each functional unit can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0099] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. A computer program product includes one or more computer instructions (programs). When the computer instructions (programs) are loaded and executed on a computer, the processes or functions according to the embodiments of this application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that the computer can access or a data storage device such as a server or data center that includes one or more integrated available media. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a high-density digital video disc (DVD)), or a semiconductor medium (for example, a solid state disk (SSD), etc.).

[0100] If a function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods of various embodiments of this application. The aforementioned storage medium includes: various media such as USB flash drives, external hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0101] As described above, the above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

[0102] In summary, this application provides a circuit structure, a configuration method, a terminal, a medium, and a chip of a programmable logic array. The circuit structure includes: a pre-stage filter control module, a pre-stage configurable arithmetic logic module, a post-stage filter control module, a post-stage configurable arithmetic logic module, and a configurable flip-flop module that are connected in sequence; wherein, according to the obtained requirements for generating a target signal, the pre-stage filter control module, the pre-stage configurable arithmetic logic module, the post-stage filter control module, the post-stage configurable arithmetic logic module, and the configurable flip-flop module are respectively configured so that the output of the circuit structure meets the requirements for generating the target signal. This application can flexibly configure the programmable logic array according to the signal generation requirements, improving the flexibility of the programmable logic array, thereby improving the universality of the control system introducing the programmable logic array. Therefore, this application effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0103] The above embodiments are only illustrative of the principles and effects of this application and are not used to limit this application. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by this application should still be covered by the claims of this application.

Claims

1. A circuit structure of a programmable logic array, characterized in that: include: A pre-stage filter control module, a pre-stage configurable operation logic module, a post-stage filter control module, a post-stage configurable operation logic module and a configurable trigger module connected in sequence; Wherein, the n inputs and n outputs of the circuit structure are respectively connected to the pre-stage filter control module; The n outputs of the circuit structure are the n outputs of the configurable trigger module; n is a positive integer; According to the acquired target signal generation requirements, the front-stage filter control module, the front-stage configurable operation logic module, the post-stage filter control module, the post-stage configurable operation logic module and the configurable trigger module are configured respectively so that the n outputs of the circuit structure meet the target signal generation requirements.

2. The circuit structure of the programmable logic array according to claim 1, characterized in that: The pre-stage filter control module is composed of 2n pre-stage filter control units; wherein n pre-stage filter control units among the 2n pre-stage filter control units are connected to the n inputs of the circuit structure in a one-to-one correspondence, and the remaining n pre-stage filter control units are connected to the n outputs of the circuit structure in a one-to-one correspondence; the outputs of the 2n pre-stage filter control units are respectively connected to the pre-stage configurable operation logic module; According to the acquired target signal generation requirements, the pre-stage filter control module is configured, including: according to the acquired target signal generation requirements, the filtering mode adopted by each pre-stage filter control unit is determined in the pre-set multiple filtering modes and the corresponding mode parameters are set, so that each pre-stage filter control unit performs the corresponding filtering operation according to the determined filtering mode and the set mode parameters; the pre-set multiple filtering modes include: synchronous shaping mode, input high level expansion mode, input low level expansion mode, edge detection mode and hysteresis jump mode.

3. The circuit structure of the programmable logic array according to claim 2, characterized in that: According to the acquired target signal generation requirements, the configuration of the front-stage configurable operation logic module includes: determining the front-stage operation mode combination corresponding to each output of the front-stage configurable operation logic module according to the acquired target signal generation requirements and the pre-set multiple operation modes, so that the front-stage configurable operation logic module performs the corresponding front-stage output operation operation according to the built-in front-stage output operation mode and the determined front-stage operation mode combination.

4. The circuit structure of the programmable logic array according to claim 3, characterized in that: The post-stage filter control module is composed of m post-stage filter control units; wherein the m post-stage filter control units are connected to the m outputs of the pre-stage configurable operation logic module in a one-to-one correspondence; the outputs of the m post-stage filter control units are respectively connected to the post-stage configurable operation logic module; According to the acquired target signal generation requirements, the post-stage filtering control module is configured, including: according to the acquired target signal generation requirements, the filtering mode adopted by each post-stage filtering control unit is determined in the pre-set multiple filtering modes and the corresponding mode parameters are set, so that each post-stage filtering control unit performs the corresponding filtering operation according to the determined filtering mode and the set mode parameters; the pre-set multiple filtering modes include: synchronous shaping mode, input high level expansion mode, input low level expansion mode, edge detection mode and hysteresis jump mode.

5. The circuit structure of the programmable logic array according to claim 4, characterized in that: The post-stage configurable operation logic module has n groups of outputs; wherein, configuring the post-stage configurable operation logic module according to the acquired target signal generation requirements includes: determining the post-stage operation mode combination corresponding to each output in each group of outputs of the post-stage configurable operation logic module according to the acquired target signal generation requirements and a plurality of pre-set operation modes, so that the post-stage configurable operation logic module performs the corresponding post-stage output operation operation according to the built-in post-stage output operation mode and the determined post-stage operation mode combinations.

6. The circuit structure of the programmable logic array according to claim 5, characterized in that: The configurable trigger module is composed of n configurable trigger units; wherein the n configurable trigger units are connected to the n groups of outputs of the subsequent configurable operation logic module in a one-to-one correspondence; Configuring the configurable trigger module according to the acquired target signal generation requirements includes: setting the trigger type and clock type of each configurable trigger unit according to the acquired target signal generation requirements; and connecting each output in each group of outputs of the subsequent configurable operation logic module to the corresponding configurable trigger unit according to the set trigger type of each configurable trigger unit and a preset trigger mapping relationship.

7. A method for configuring a circuit structure of a programmable logic array, characterized in that: A circuit structure applied to a programmable logic array, the circuit structure of the programmable logic array comprising: a pre-stage filter control module, a pre-stage configurable operation logic module, a post-stage filter control module, a post-stage configurable operation logic module and a configurable trigger module connected in sequence, the method comprising: Obtain target signal generation requirements; According to the acquired target signal generation requirements, the front-stage filter control module, the front-stage configurable operation logic module, the post-stage filter control module, the post-stage configurable operation logic module and the configurable trigger module are configured respectively so that the output of the circuit structure meets the target signal generation requirements.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to claim 8 is implemented.

9. An electronic terminal comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the method of claim 8.

10. A chip, characterized in that: The chip is provided with a circuit structure of a programmable logic array as claimed in any one of claims 1 to 6.

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