FPGA-based CNC system

Abstract

The present invention discloses an FPGA-based numerical control system, wherein the numerical control system includes an FPGA chip and multiple drivers. The FPGA chip includes a DMA core, a descriptor management module, a first bus management module, a second bus management module, and multiple transmission channels. The DMA core is connected to the first bus management module, the second bus management module, and the descriptor management module. The first end of the transmission channel is connected to the first bus management module and the second bus management module, and the second end is connected to the driver. The descriptor management module is connected to the first bus management module and is used to generate a descriptor linked list. The DMA core is used to traverse the descriptor linked list to generate data transmission requests. The second bus management module determines the driver based on the data transmission request and selects the transmission channel corresponding to the driver. By configuring the descriptor management module within the FPGA chip, the present invention avoids multiple data exchanges between the CPU and the FPGA chip, significantly reduces the CPU load, and improves the communication efficiency of the numerical control system.

Description

Technical Field

[0001] The present invention belongs to the technical field of numerical control systems, and in particular relates to a numerical control system based on FPGA. Background Art

[0002] At present, the use of CNC systems for processing control in the manufacturing industry has become the norm. During the processing control process, the CNC system needs to process and calculate a large amount of processing data. Smooth throughput processing of large amounts of data is necessary for the CNC system. At the same time, since the CNC system will be adapted to various types of motors, considering the different quantities and types of different types of motors in actual use, the CNC system should have good scalability to facilitate the expansion of equipment functions.

[0003] The main control chip in the existing technology uses the PCIe bus to connect to the motherboard CPU. The main control chip is used to perform protocol conversion between the motherboard CPU's PCIe communication bus and the driver communication bus, as well as transmit motor control data and motor motion data. The main control chip uses the Intel PCIe core to complete the conversion of PCIe protocol transactions to the internal bus protocol. The driver bus corresponds to a set of internal bus protocols. The CPU software program configures the main control chip's internal functional modules and drivers for different communication buses through the driver bus. The main control chip determines which bus protocol conversion is currently running through configuration registers.

[0004] The existing technology has the following drawbacks: FPGAs initiate PCIe communications through a multiplexed Tx interface, which can cause bus conflicts when multiplexing data with the driver communication bus. The PCIe communication rate is much higher than this bus rate, thus reducing communication efficiency. Furthermore, the number of expandable driver communication buses is limited.

[0005] Therefore, in order to solve the above technical problems, it is necessary to provide a numerical control system based on FPGA. Summary of the Invention

[0006] The object of the present invention is to provide a numerical control system based on FPGA, which can reduce the CPU load while improving the driver bus expansion capability.

[0007] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0008] A numerical control system based on FPGA, comprising an FPGA chip and multiple drivers, wherein the FPGA chip comprises a DMA core, a descriptor management module, a first bus management module, a second bus management module and multiple transmission channels;

[0009] The DMA core is connected to the first bus management module, the second bus management module and the descriptor management module, the first end of the transmission channel is connected to the first bus management module and the second bus management module, and the second end is connected to the driver;

[0010] The descriptor management module is connected to the first bus management module and is used to generate a descriptor linked list;

[0011] The DMA core is used to traverse the descriptor linked list to generate a data transmission request, and the second bus management module determines a driver based on the data transmission request and selects a transmission channel corresponding to the driver.

[0012] In one or more embodiments of the present invention, the numerical control system further includes a CPU, and the FPGA chip further includes a PCIE core;

[0013] The PCIE core is connected between the CPU and the DMA core. The CPU is used to issue driver configuration instructions. The PCIE core and the DMA core are used to transmit the driver configuration instructions to the first bus management module. The first bus management module selects the corresponding transmission channel based on the driver configuration instructions and performs initial configuration on the driver.

[0014] In one or more embodiments of the present invention, the DMA core includes multiple DMA engines, the DMA engines are connected to the descriptor management module, and the DMA engines are used to receive and process the descriptor linked list in parallel.

[0015] In one or more embodiments of the present invention, the first bus management module is connected to the DMA core via an AXI_LITE bus, and the first bus management module is used to convert PCIE protocol data into AXI_LITE protocol data;

[0016] The second bus management module is connected to the DMA engine via an AXI_MM bus, and the second bus management module is used to convert PCIE protocol data into AXI_MM protocol data.

[0017] In one or more embodiments of the present invention, the descriptor management module is connected to the first bus management module via an AXI_LITE bus;

[0018] The first bus management module is used to obtain CPU commands, and the descriptor management module is used to generate a descriptor linked list based on the CPU commands. The descriptor linked list includes a source address, a destination address, a transfer length, control information, a next descriptor address and status information.

[0019] In one or more embodiments of the present invention, the FPGA chip also includes a board upgrade control module, which is connected to the second bus management module. The board upgrade control module is used to monitor the board upgrade data between the second bus management module and the FLASH chip, and determine whether the board upgrade data has been transmitted. The FLASH chip is arranged outside the CNC system, and the second bus management module is used to transmit the board upgrade command to the FLASH chip through the AXI_MM bus.

[0020] In one or more embodiments of the present invention, the FPGA chip also includes a power-off save control module, which is connected to the second bus management module. The power-off save control module is used to monitor the power-off save data between the second bus management module and the FRAM chip, and to determine whether the power-off save data has been transmitted. The FRAM chip is arranged outside the CNC system, and the second bus management module is used to transmit a power-off save command to the FRAM chip through the AXI_MM bus.

[0021] In one or more embodiments of the present invention, the transmission channel includes a first protocol conversion module, an AXI_LITE bus interface, a second protocol conversion module, and an AXI_MM bus interface;

[0022] The AXI_LITE bus interface is provided between the first bus management module and a first end of the first protocol conversion module, a second end of the first protocol conversion module is directly or indirectly connected to the driver via a driver bus, and the first protocol conversion module is used to realize mutual conversion between AXI_LITE protocol data and driver bus protocol data;

[0023] The AXI_MM bus interface is arranged between the second bus management module and the first end of the second protocol conversion module. The second end of the second protocol conversion module is directly or indirectly connected to the driver through the driver bus. The second protocol conversion module is used to realize the mutual conversion between AXI_MM protocol data and driver bus protocol data.

[0024] In one or more embodiments of the present invention, the transmission channel further includes an interface gating module;

[0025] The first input end of the interface selection module is connected to the first protocol conversion module, the second input end is connected to the second protocol conversion module, and the output end is connected to the driver through the driver bus;

[0026] The interface selection module is used to select the first protocol conversion module and the driver or the second protocol conversion module and the driver based on the priority of the protocol data, wherein the priority of the AXI_MM protocol data is greater than the priority of the AXI_LITE protocol data.

[0027] In one or more embodiments of the present invention, the FPGA chip further includes a register, the register being connected to the second bus management module and the transmission channel, the register being used to store transmission data between the second bus management module and the transmission channel; and / or,

[0028] The FPGA chip further includes a dynamic configuration module, which is connected to the second bus management module via an AXI_MM bus. The dynamic configuration module is used to store dynamic configuration commands.

[0029] Compared with the prior art, the FPGA-based numerical control system of the present invention configures a descriptor management module within the FPGA chip and connects it between the DMA core and the first bus management module. This allows CPU commands or driver configuration instructions to be directly transmitted to the first bus management module, and the descriptor management module generates a descriptor linked list. This avoids multiple data interactions between the CPU and the FPGA chip. The DMA can automatically complete data reading, transmission, and writing based on the descriptor linked list without frequent CPU intervention, significantly reducing CPU load and improving system efficiency.

[0030] The second bus management module controls different data transmission requests through different buses, ensuring that the motor servo cycle synchronization is not destroyed, avoiding bus access conflicts, and further improving the communication efficiency between the CPU and FPGA chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 Schematic diagram of the structure of a numerical control system based on FPGA in one embodiment of the present invention;

[0033] Figure 2 This is an architectural diagram of an FPGA-based numerical control system in another embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0035] Unless expressly stated otherwise, throughout the specification and claims, the term "comprise" or variations such as "include" or "comprising", etc., will be understood to include the stated elements or components but not to exclude other elements or other components.

[0036] The terms "coupled," "connected," or "connected" as used in this specification encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrically conductive medium, which may have parasitic inductance or capacitance. An indirect connection may also include a connection through other active or passive devices, such as switches, follower circuits, or other circuits or components, to achieve the same or similar functional objectives. Furthermore, in the present invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another and do not necessarily require or imply a specific relationship, quantity, or order between these technical features.

[0037] In the detailed description of the specification, reference is made to the accompanying drawings forming a part hereof, wherein like reference numerals designate like parts throughout, and wherein exemplary embodiments that may be implemented are shown by way of example. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present application. Therefore, the following detailed description should not be construed in a limiting sense.

[0038] The various operations in the specification may be described as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0039] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0040] Various components and devices may be referred to or shown in the singular form in this document (for example, "MOS tube", "transistor", "switch", etc.), but this is only for convenience of discussion, and any element referred to in the singular form may include multiple such elements according to the teachings of this document.

[0041] The description uses the phrases "in this embodiment" or "in other embodiments" or "in some embodiments", which can each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of this application are synonymous.

[0042] like Figure 1 As shown, an embodiment of the present invention provides a numerical control system based on FPGA, wherein the numerical control system includes an FPGA chip 10 and a driver 20, and the FPGA chip includes a DMA core 11, a descriptor management module 12 (i.e. Figure 1 Descriptor_manage), the first bus management module 13 (ie Figure 1 AXI_LITE_BUS_manage shown), the second bus management module 14 (ie Figure 1 As shown in FIG. 1 , the DMA core 11 (Direct Memory Access Core) and multiple transmission channels 15 are provided. Furthermore, in this embodiment, the DMA core 11 (Direct Memory Access Core) is preferably an SGDMA core 11 (Scatter-Gather Direct Memory Access Core).

[0043] The DMA core 11 is connected to the first bus management module 13, the second bus management module 14, and the descriptor management module 12. The first end of the transmission channel 15 is connected to the first and second bus management modules 13 and 14, and the second end is connected to the driver 20. Furthermore, the DMA core 11 and the descriptor management module 12 communicate bidirectionally via a bypass path. The DMA core 11 can directly read the descriptor linked list generated by the descriptor management module 12, eliminating the need for complex processing flows or intermediate modules and consuming CPU or FPGA logic resources. This reduces transmission latency and improves the system's real-time performance and efficiency.

[0044] The descriptor management module 12 is connected to the first bus management module 13 and is used to generate a descriptor linked list.

[0045] The DMA core 11 is used to traverse the descriptor linked list to generate a data transmission request. The second bus management module 14 determines the driver 20 based on the data transmission request and selects the transmission channel 15 corresponding to the driver.

[0046] It should be noted that in order to improve the expansion capability of the CNC system, the number of drivers 20 and transmission channels 15 is often multiple, and the number of drivers 20 and transmission channels 15 is the same and one-to-one corresponding. The specific number depends on the specific application scenario of the CNC system.

[0047] like Figure 2 As shown, another embodiment of the present invention provides an FPGA-based numerical control system. The numerical control system also includes a CPU, which is used to issue driver configuration instructions and various CPU commands. The FPGA chip also includes a PCIE core 16 (Peripheral Component Interconnect Express Core), where the PCIE core 16 is connected between the CPU and the DMA core 11.

[0048] Furthermore, the PCIE core 16 is connected to the CPU via a PCIE bus, and is connected to the DMA core 11. The PCIE core and the DMA core 11 are used to transmit the driver configuration instruction to the first bus management module 13.

[0049] Furthermore, the PCIE core 16 and the DMA core 11 are also connected through an interrupt signal bus DMA_INTERRUPT_BUS. The interrupt signal bus DMA_INTERRUPT_BUS is used to transmit the interrupt signal generated by the DMA core 11 to notify the CPU about the status or event of the DMA core 11 transmission. The interrupt signal includes a transmission completion signal indicating that the DMA transmission task is completed and a transmission error signal indicating that an error occurs during the transmission process (such as address out of bounds, data check error, etc.).

[0050] Based on the driver configuration instructions, the first bus management module 13 selects the corresponding transmission channel 15 and performs initial configuration on the driver 20. It should be noted that in this embodiment, the driver 20 is a motor, and there is a one-to-one correspondence between the transmission channels 15 and the motor 20. That is, if n motors are provided in this embodiment, then the FPGA chip is internally configured with n transmission channels 15, each connected to one of the motors. The motors are connected to the transmission channels 15 via the driver bus BUS. The communication protocol of the driver bus BUS corresponding to each motor can be the same or different.

[0051] like Figure 1 and Figure 2 As shown, the DMA core 11 includes multiple DMA engines 111, which are connected to the descriptor management module 12. The multiple DMA engines 111 receive and process the descriptor linked list in parallel. In one embodiment, the DMA engines 111 correspond to the transmission channels 15 on a one-to-one basis.

[0052] It should be noted that each DMA engine 111 in this embodiment independently corresponds to a group of transmission channels 15 and buses, so all DMA engines 111 can work simultaneously without interfering with each other, thereby realizing parallel data transmission within the FPGA chip.

[0053] The first bus management module 13 is connected to the DMA core 11 via the AXI_LITE bus. The first bus management module 13 is used to convert PCIE protocol data into AXI_LITE protocol data.

[0054] The second bus management module 14 is connected to the DMA engine 111 via the AXI_MM bus and is configured to convert PCIE protocol data into AXI_MM protocol data. It is understood that the driver configuration instructions issued by the CPU, various CPU commands, and data transfer requests generated by the DMA core 11 when traversing the descriptor linked list are all PCIE protocol data.

[0055] like Figure 1 and Figure 2 As shown, the transmission channel 15 in one embodiment includes a first protocol conversion module 151 (ie Figure 1 and Figure 2 AXILITE_BUS_Bridge shown), AXI_LITE bus interface 106, second protocol conversion module 152 (ie Figure 1 and Figure 2 AXIMM_BUS_Bridge shown), AXI_MM bus interface 105 and interface selection module 153 (ie Figure 1 and Figure 2 Bridge_MUX as shown).

[0056] The AXI_LITE bus interface 106 is arranged between the first bus management module 13 and the first end of the first protocol conversion module 151, and the AXI_LITE bus interface 106 and the first bus management module 13 are communicated via the AXI_LITE bus. The second end of the first protocol conversion module 151 is connected to the first input end of the interface selection module 153, that is, it is indirectly connected to the driver via the driver bus BUS. The first protocol conversion module 151 is used to realize mutual conversion between AXI_LITE protocol data and driver bus BUS protocol data.

[0057] The AXI_MM bus interface 105 is provided between the second bus management module 14 and the first end of the second protocol conversion module 152, and the AXI_MM bus interface 105 and the second bus management module 14 are connected via the AXI_MM bus. The second end of the second protocol conversion module 152 is connected to the second input end of the interface selection module 153, that is, indirectly connected to the driver 20 via the driver bus BUS. The second protocol conversion module 152 is used to implement mutual conversion between AXI_MM protocol data and driver bus BUS protocol data. It should be noted that Figure 1 and Figure 2 The medium gray dotted lines represent the AXI_LITE bus, and the thicker black solid lines represent the AXI_MM bus.

[0058] The first input end of the interface selection module 153 is connected to the first protocol conversion module 151, the second input end is connected to the second protocol conversion module 152, and the output end is connected to the driver 20 through the driver bus BUS. The interface selection module 153 is used to select the first protocol conversion module 151 and the driver or select the second protocol conversion module 152 and the driver based on the priority of the protocol data, thereby completing data interaction, wherein the priority of the AXI_MM protocol data is greater than the priority of the AXI_LITE protocol data.

[0059] The descriptor management module 12 is connected to the first bus management module 13 via the AXI_LITE bus. The first bus management module 13 is used to obtain CPU commands and driver configuration instructions. The descriptor management module 12 is used to generate a descriptor linked list based on the CPU commands and driver configuration instructions. The descriptor linked list is a linked list composed of multiple descriptors (Descriptors). The descriptor linked list includes source address, destination address, transfer length, control information, next descriptor address and status information. The control information includes configurations such as transfer direction (read / write), transfer mode (single / loop), and interrupt enable. CPU commands include motor control commands and motor motion feedback commands.

[0060] It should be noted that, in this embodiment, the CPU configures the driver 20 based on the driver configuration instruction before it operates. Specifically, the driver configuration instruction issued by the CPU is transmitted to the first bus management module 13 after passing through the PCIE core 16 and the DMA core 11. The first bus management module 13 selects the corresponding transmission channel 15 based on the driver configuration instruction and performs initial configuration on the driver (i.e., the motor). After the configuration is completed, the configuration information is returned to the first bus management module 13 via the transmission channel 15. At this time, the descriptor management module 12 of the AXI_LITE bus, which is in communication with the first bus management module 13, can obtain the driver configuration information (including the driver's address information, the communication protocol of the driver bus BUS, etc.) from the first bus management module 13.

[0061] After the driver configuration is completed, the controller can enter the working state. At this time, the data transmission between the driver and the FPGA chip is realized through the first bus management module 13 and its corresponding transmission channel 15 and AXI_MM bus. The AXI_MM bus has a high throughput and supports burst transmission and read-write channel separation.

[0062] In an exemplary embodiment of the present invention, the CPU issues a motor control command, which is transmitted to the first bus management module 13 after passing through the PCIE core and the DMA core 11. The descriptor management module 12 obtains the motor control command in the first bus management module 13 through the AXI_LITE bus, and generates a corresponding descriptor linked list in combination with the motor control command and the driver configuration information (including the address information of the driver, the communication protocol of the driver bus BUS, etc.). The DMA core 11 is used to traverse the descriptor linked list to generate a corresponding data transmission request. The second bus management module 14 determines the driver based on the data transmission request and selects the transmission channel 15 corresponding to the driver to realize control of the motor, and the motor returns the motor control data through the transmission channel 15.

[0063] In an exemplary embodiment of the present invention, the CPU issues a motor motion feedback command, which is transmitted to the first bus management module 13 after passing through the PCIE core and the DMA core 11. The descriptor management module 12 obtains the motor motion feedback command in the first bus management module 13 through the AXI_LITE bus, and generates a corresponding descriptor linked list in combination with the motor motion feedback command and the driver configuration information (including the address information of the driver, the communication protocol of the driver bus BUS, etc.). The DMA core 11 is used to traverse the descriptor linked list to generate a corresponding data transmission request. The second bus management module 14 determines the driver based on the data transmission request and selects the transmission channel 15 corresponding to the driver. The motor transmits the motor motion feedback data back through the transmission channel 15.

[0064] like Figure 1 and Figure 2 As shown, the FPGA chip in one embodiment further includes a board upgrade control module 18 (i.e., Update_ctrl). The board upgrade control module 18 is connected to the second bus management module 14. The board upgrade control module 18 is used to monitor the board upgrade data between the second bus management module 14 and the FLASH chip 40, and to determine whether the board upgrade data transmission is complete. The FLASH chip 40 is disposed outside the numerical control system and is connected to the second bus management module 14 and the board upgrade control module 18 via the AXI_MM bus. The second bus management module 14 is used to transmit the board upgrade command to the FLASH chip 40 via the AXI_MM bus. It should be noted that the AXI_MM bus between the FLASH chip 40 and the second bus management module 14 corresponds to a DMA engine 111, that is, one of the DMA engines 111 in the DMA core 11 receives and processes the descriptor linked list associated with the board upgrade.

[0065] In an exemplary embodiment of the present invention, the CPU issues a board upgrade command, which is then transmitted to the first bus management module 13 via the PCIE core 16 and the DMA core 11. The descriptor management module 12 retrieves the board upgrade command from the first bus management module 13 via the AXI_LITE bus and generates a corresponding descriptor list based on the board upgrade command. The DMA engine 111 traverses the descriptor list to generate a corresponding data transfer request (including the board upgrade data in this embodiment). The board upgrade data is transmitted via the AXI_MM bus between the FLASH chip 40 and the second bus management module 14. The board upgrade control module 18 monitors the board upgrade data flowing through this bus. When the board upgrade data transmission is complete, the board upgrade control module 18 generates a board upgrade completion signal, which is transmitted to the second bus management module 14 via the AXI_MM bus. The signal is then transmitted to the CPU via the DMA core 11 and the PCIE core.

[0066] like Figure 2As shown, the FPGA chip in one embodiment further includes a power-off save control module 17 (i.e., FRAM_ctrl), which is connected to the second bus management module 14. The power-off save control module 17 is used to monitor the power-off save data between the second bus management module 14 and the FRAM chip 30, and determine whether the power-off save data transmission is completed. The FRAM chip 30 is disposed outside the numerical control system and is connected to the second bus management module 14 and the power-off save control module 17 via the AXI_MM bus. The second bus management module 14 is used to transmit the power-off save command to the FRAM chip 30 via the AXI_MM bus. It should be noted that the AXI_MM bus between the FRAM chip 30 and the second bus management module 14 corresponds to a DMA engine 111, that is, one of the DMA engines 111 in the DMA core 11 receives and processes the descriptor linked list associated with power-off save.

[0067] In an exemplary embodiment of the present invention, the CPU issues a power-down save command, which is then transmitted to the first bus management module 13 via the PCIE core and DMA core 11. The descriptor management module 12 retrieves the power-down save command from the first bus management module 13 via the AXI_LITE bus and generates a corresponding descriptor list based on the power-down save command. The DMA engine 111 traverses the descriptor list to generate a corresponding data transfer request (including power-down save data in this embodiment). The power-down save data is transmitted via the AXI_MM bus between the FRAM chip 30 and the second bus management module 14. The power-down save control module 17 monitors the power-down save data flowing through the bus. When the power-down save data is transmitted, the power-down save control module 17 generates a power-down save completion signal, which is transmitted to the second bus management module 14 via the AXI_MM bus. The signal is then transmitted to the CPU via the DMA core 11 and PCIE core 16.

[0068] Taking the board upgrade command as an example, the upgrade process may involve a large number of data transmission requests. Therefore, in the existing technology, the CPU needs to interact with the FPGA chip for data multiple times, which takes up a lot of CPU resources. In addition, the communication efficiency of the PCIE bus between the CPU and the FPGA chip is low, which further reduces the communication efficiency.

[0069] The present invention configures a descriptor management module 12 in the FPGA chip, and the descriptor management module 12 is connected between the DMA core 11 and the first bus management module 13. The CPU command or driver configuration instruction is directly transmitted to the first bus management module 13. The descriptor management module 12 obtains information from the first bus management module 13 and generates a descriptor linked list. This is equivalent to the command issued by the CPU being "temporarily stored" in the first bus management module 13 at one time. During the board upgrade process, the CPU can send a command at least once, and multiple data interactions are realized by the AXI_MM bus, and the AXI_MM bus has the characteristics of high connectivity and high compatibility.

[0070] Furthermore, the board upgrade data and the corresponding data transmission request, the motor control data and the corresponding data transmission request, and the motion feedback data and the corresponding data transmission request are transmitted using different AXI_MM buses, but are all managed by the second bus management module 14, ensuring that the motor servo cycle synchronization is not destroyed and avoiding bus access conflicts.

[0071] like Figure 2 As shown, the FPGA chip in another embodiment further includes a register 101, which is connected to the second bus management module 14 and the transmission channel 15. The register 101 is used to store transmission data between the second bus management module 14 and the transmission channel 15.

[0072] like Figure 2 As shown, the FPGA chip in another embodiment further includes a dynamic configuration module 102. The dynamic configuration module 102 is connected to the second bus management module 14 via the AXI_MM bus. The dynamic configuration module 102 is used to store dynamic configuration commands.

[0073] It can be seen from the above technical solutions that the present invention has the following beneficial effects:

[0074] The present invention configures a descriptor management module 12 within the FPGA chip and connects it between the DMA core 11 and the first bus management module 13, so that CPU commands or driver configuration instructions can be directly transmitted to the first bus management module 13. The descriptor management module 12 generates a descriptor linked list, avoiding multiple data interactions between the CPU and the FPGA chip. The DMA can automatically complete the reading, transmission, and writing of data based on the descriptor linked list without frequent CPU intervention, significantly reducing the CPU load and improving system efficiency.

[0075] The present invention realizes data interactive transmission through the AXI_MM bus, takes advantage of its high connectivity and high compatibility, further improves the communication efficiency between the CPU and the FPGA chip, and avoids the problem of low communication efficiency of the traditional PCIE bus.

[0076] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0077] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A numerical control system based on FPGA, characterized in that: The numerical control system includes a CPU, an FPGA chip and multiple drivers, and the FPGA chip includes a PCIE core, a DMA core, a descriptor management module, a first bus management module, a second bus management module and multiple transmission channels; The DMA core is connected to the first bus management module, the second bus management module and the descriptor management module, the first end of the transmission channel is connected to the first bus management module and the second bus management module, and the second end is connected to the driver; The descriptor management module is connected to the first bus management module via the AXI_LITE bus and is used to generate a descriptor linked list. The first bus management module is used to obtain a CPU command. The descriptor management module is used to generate a descriptor linked list based on the CPU command. The descriptor linked list includes a source address, a destination address, a transfer length, control information, a next descriptor address, and status information. The DMA core is used to traverse the descriptor linked list to generate a data transmission request, and the second bus management module determines a driver based on the data transmission request and selects a transmission channel corresponding to the driver; The DMA core includes multiple DMA engines, which are connected to the descriptor management module and are used to receive and process descriptor linked lists in parallel. The first bus management module is connected to the DMA core via an AXI_LITE bus and is used to convert PCIE protocol data into AXI_LITE protocol data. The second bus management module is connected to the DMA engine via an AXI_MM bus and is used to convert PCIE protocol data into AXI_MM protocol data.

2. The FPGA-based numerical control system according to claim 1, characterized in that: The PCIE core is connected between the CPU and the DMA core. The CPU is used to issue driver configuration instructions. The PCIE core and the DMA core are used to transmit the driver configuration instructions to the first bus management module. The first bus management module selects the corresponding transmission channel based on the driver configuration instructions and performs initial configuration on the driver.

3. The FPGA-based numerical control system according to claim 1, characterized in that: The FPGA chip also includes a board upgrade control module, which is connected to the second bus management module. The board upgrade control module is used to monitor the board upgrade data between the second bus management module and the FLASH chip, and determine whether the board upgrade data has been transmitted. The FLASH chip is arranged outside the CNC system, and the second bus management module is used to transmit the board upgrade command to the FLASH chip through the AXI_MM bus.

4. The FPGA-based numerical control system according to claim 1, characterized in that: The FPGA chip also includes a power-off save control module, which is connected to the second bus management module. The power-off save control module is used to monitor the power-off save data between the second bus management module and the FRAM chip, and determine whether the power-off save data has been transmitted. The FRAM chip is arranged outside the CNC system, and the second bus management module is used to transmit the power-off save command to the FRAM chip through the AXI_MM bus.

5. The FPGA-based numerical control system according to claim 1, characterized in that: The transmission channel includes a first protocol conversion module, an AXI_LITE bus interface, a second protocol conversion module and an AXI_MM bus interface; The AXI_LITE bus interface is provided between the first bus management module and a first end of the first protocol conversion module, a second end of the first protocol conversion module is directly or indirectly connected to the driver via a driver bus, and the first protocol conversion module is used to realize mutual conversion between AXI_LITE protocol data and driver bus protocol data; The AXI_MM bus interface is arranged between the second bus management module and the first end of the second protocol conversion module. The second end of the second protocol conversion module is directly or indirectly connected to the driver through the driver bus. The second protocol conversion module is used to realize the mutual conversion between AXI_MM protocol data and driver bus protocol data.

6. The FPGA-based numerical control system according to claim 5, characterized in that: The transmission channel also includes an interface gating module; The first input end of the interface selection module is connected to the first protocol conversion module, the second input end is connected to the second protocol conversion module, and the output end is connected to the driver through the driver bus; The interface selection module is used to select the first protocol conversion module and the driver or the second protocol conversion module and the driver based on the priority of the protocol data, wherein the priority of the AXI_MM protocol data is greater than the priority of the AXI_LITE protocol data.

7. The FPGA-based numerical control system according to claim 1, characterized in that: The FPGA chip further includes a register, the register being connected to the second bus management module and the transmission channel, and the register being used to store transmission data between the second bus management module and the transmission channel; and / or, The FPGA chip further includes a dynamic configuration module, which is connected to the second bus management module via an AXI_MM bus. The dynamic configuration module is used to store dynamic configuration commands.

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