Patch repair method, device and storage medium for read-only code

Abstract

The embodiment of the application discloses a patch repair method and device of read-only code and a storage medium, and relates to the embedded field. The embodiment of the application realizes full-bus patch coverage of arbitrary code / data by monitoring read / write requests on a system bus. The patch repair device is preconfigured with a patch pool containing various information, and when a read / write request of a specific address is detected, corresponding patch data items can be quickly queried and matched. If the matching is successful and the patch is valid, the target data is replaced according to the patch type or a CPU exception instruction is triggered to enter an interrupt processing flow to obtain the patch. The method is universal and flexible, supports full-function patches without distinction, can cope with various code / data errors, and greatly reduces the risk of chip scrapping or re-burning caused by ROM code exceptions. Through bus replacement and exception triggering, effective repair of read-only code is realized, which has a significant economic effect, improves production efficiency and reduces product cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of embedded systems, and in particular to a patch repair method and device for read-only code, and a storage medium. BACKGROUND

[0002] In the development of embedded systems, the selection of the code carrier for the processor chip, as the core component, is of great importance. Common code carriers include ROM (Read-Only Memory), OTP (One-Time Programmable Memory), MTP (Multi-Time Programmable Memory), SPI FLASH, NAND FLASH, and the like. These storage media each have their own characteristics, but they all have in common that they carry the startup code and application code of the embedded system. Among them, the startup code is usually built-in by the chip manufacturer and stored in the ROM to ensure that initialization operations can be automatically performed when the system is powered on. The application code, due to its complexity and space requirements, is often stored in a larger-capacity OTP or even ROM, especially for low-cost solutions.

[0003] However, one significant drawback of these storage media is their read-only property. Once the code is written, it cannot be modified unless special physical means (such as MetalFix light repair) are used. This means that if there are errors or vulnerabilities in the code, it will cause great trouble for developers. Especially in the case of mass production, code errors in a batch of chips can cause the entire batch to be scrapped, resulting in huge economic losses.

[0004] To address this problem, the industry has explored some code patching solutions. One solution is to predict code segments or functions that are prone to problems and pre-define function pointers at these locations. When patching is needed, the value of the function pointer is modified to jump to the patch code for execution, thereby achieving code repair. This solution, although to some extent, solves the problem of code patching, requires developers to have a deep understanding of the code and precise prediction capabilities. At the same time, the introduction of function pointers and patch code also increases the consumption of RAM space, which is undoubtedly a challenge for resource-limited embedded systems.

[0005] Another solution is to externalize the interrupt vector table and execute patch code through peripheral interrupt monitoring exceptions. This solution can handle most hardware exception problems, but it requires hardware modules to work in interrupt mode, and may not be able to handle software vulnerabilities effectively. Similarly, the introduction of the interrupt vector table and patch code also increases the burden on RAM space. SUMMARY

[0006] The embodiment of the present application provides a patch repair method, device and storage medium of read-only code, and can solve the problem of the large RAM space occupation of the patch repair method in the prior art. The technical solution is as follows:

[0007] In a first aspect, the embodiment of the present application provides a patch repair method of read-only code, and the method comprises the following steps:

[0008] Monitoring a system bus, and when detecting a read-write request from a CPU on the system bus, analyzing a read-write address of the read-write request;

[0009] Querying a patch data item matched with the read-write address in a patch pool; wherein the patch pool is preconfigured with a plurality of patch data items, and the patch data item comprises a patch state value, a code data type value, a patch validity period value, a patch type value, a patch address, patch data, and an interrupt vector table;

[0010] If a target patch data item with the same patch address as the read-write address is queried, determining whether the patch state value of the target patch data item indicates a valid state;

[0011] If yes, determining whether the data type of the read-write data indicated by the read-write request matches the code data type value of the target patch data item;

[0012] If yes, obtaining the patch type value of the target patch data item;

[0013] If the patch type value of the target patch data item is a first preset value, replacing the target data indicated by the read-write request with the patch data;

[0014] If the patch type value of the target patch data item is a second preset value, replacing the target data indicated by the read-write request with a CPU exception instruction, and the CPU exception instruction is used to instruct the CPU to enter an interrupt processing flow according to the interrupt vector table of the target patch data item, and the corresponding patch data is obtained in the interrupt processing flow;

[0015] According to the patch validity period, determining whether the target patch data item is invalid, if yes, setting the patch state value to an invalid state, and deleting the patch data from the patch pool, otherwise, keeping in a valid state.

[0016] In a second aspect, the embodiment of the present application provides a patch repair device of read-only code, and the device comprises:

[0017] A monitoring unit, configured to monitor a system bus, and when detecting a read-write request from a CPU on the system bus, analyze a read-write address of the read-write request;

[0018] The query unit is configured to query a patch data item matching the read-write address in a patch pool; wherein the patch pool is preconfigured with a plurality of patch data items, and each patch data item includes a patch state value, a code data type value, a patch validity period value, a patch type value, a patch address, patch data, and an interrupt vector table.

[0019] The determination unit is configured to determine whether the patch state value of the target patch data item indicates a valid state if the patch address of the target patch data item matches the read-write address; determine whether the data type of the read-write data indicated by the read-write request matches the code data type value of the target patch data item if the answer is yes; obtain the patch type value of the target patch data item if the answer is yes; replace the target data indicated by the read-write request with the patch data if the patch type value of the target patch data item is a first preset value; and replace the target data indicated by the read-write request with a CPU exception instruction if the patch type value of the target patch data item is a second preset value, wherein the CPU exception instruction is used to instruct the CPU to enter an interrupt processing flow according to the interrupt vector table of the target patch data item, and the corresponding patch data is obtained in the interrupt processing flow.

[0020] The update unit is configured to determine whether the target patch data item is invalid according to the patch validity period, and set the patch state value to an invalid state and delete the patch data from the patch pool if the answer is yes, or keep the patch data in a valid state if the answer is no.

[0021] In a third aspect, an embodiment of the present application provides a computer storage medium, which stores a plurality of instructions, and the instructions are suitable for being loaded by a processor and performing the method steps described above.

[0022] In a fourth aspect, an embodiment of the present application provides a patch repair device for read-only code, which can include a processor and a memory; wherein the memory stores a computer program, and the computer program is suitable for being loaded by the processor and performing the method steps described above.

[0023] The technical solutions provided by some embodiments of the present application have at least the following beneficial effects:

[0024] The read and write requests on the system bus are monitored to realize the full bus patch coverage of any code / data. The patch repair device is pre-stored with a patch pool containing various information, and when detecting the read and write request of a specific address, the corresponding patch data item can be quickly queried and matched. If the matching is successful and the patch is valid, the target data is replaced according to the patch type or the CPU exception instruction is triggered to enter the interrupt processing flow to obtain the patch. This method is universal and flexible, supports full-function patches without distinction, can cope with various code / data errors, and greatly reduces the risk of chip scrapping or re-burning caused by ROM code exception. Through the bus replacement and exception triggering, the read-only code is effectively repaired, which has a significant economic effect, improves the production efficiency, and reduces the product cost. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0026] Figure 1 is a system architecture schematic diagram of a chip provided by the embodiments of the present application;

[0027] Figure 2 is a flowchart of a read-only code patch repair method provided by the embodiments of the present application;

[0028] Figure 3 is a structure schematic diagram of a read-only code patch repair device provided by the present application;

[0029] Figure 4 is a structure schematic diagram of a terminal device provided by the present application. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0031] As shown in Figure 1 , the system architecture of the chip can include a CPU, a code repair device, a read-only memory, an external memory and an electronic fuse, and the above-mentioned components are connected through a system bus. The running method of the system architecture includes: the CPU starts from the read-only memory indicated by the 0 address after power-on, directly reads and runs the scheme code in the read-only memory; or starts the bootloader, and loads and runs the scheme code in the external memory through the bootloader.

[0032] Among them, the read-only memory can be OTP or ROM, and the external memory can be EEPROM, SPI Flash, etc. The code repair device can be a module inside the chip.

[0033] It should be understood that Figure 1 The number of components in each embodiment is only illustrative. Depending on the implementation needs, it can be any number.

[0034] The following will be combined with the attached Figure 2 The patch repair method of the read-only code provided by the embodiment of the application will be described in detail. Among them, the patch repair device of the read-only code in the embodiment of the application can be Figure 1 The code repair device shown in the figure.

[0035] Please refer to Figure 2 A flowchart of a patch repair method of read-only code is provided for the embodiment of the application. As Figure 2 The method of the embodiment of the application can include the following steps:

[0036] S201, monitoring the system bus, detecting the read-write request from the CPU on the system bus, and analyzing the read-write address of the read-write request.

[0037] Among them, the patch repair device continuously monitors the signal transmission on the system bus in real time through the integrated monitoring unit. When detecting the read-write request from the CPU, the monitoring module will immediately capture the request and enter the analysis stage. In the analysis stage, the device first identifies the type of request (read or write), and then extracts the key information in the request, especially the read-write address. The read-write address is the identification of the memory location that the CPU hopes to access or modify. The device obtains this key information by analyzing the address field in the request packet or instruction. To ensure the legality and accuracy of the address, the device may also perform address range checking to prevent boundary crossing or illegal access.

[0038] S202, querying the patch data item matching the read-write address in the patch pool; wherein the patch pool is pre-configured with a plurality of patch data items, and the patch data item includes: patch state value, code data type value, patch validity period value, patch type value, patch address, patch data, and interrupt vector table.

[0039] Among them, the patch pool is a data structure maintained inside the device, used to store and manage a plurality of patch data items. Each patch data item contains a series of attributes:

[0040] Patch state value: indicates that the patch data is in a valid state or an invalid state. The valid state means that the patch can be applied, and the invalid state means that the patch should be ignored.

[0041] Code data type value: indicates whether the patch data is data, code, or both. This helps the device determine how to apply the patch and to what target.

[0042] Patch expiration: indicates the expiration date of the patch data, which is a timestamp or date range, used to determine whether the patch is still within its usable period.

[0043] Patch type value: includes replacement methods, indicating how the patch should be applied, such as directly replacing data or triggering an interrupt handling process.

[0044] Patch address: indicates the storage address of the patch data, which is the location of the patch data in memory.

[0045] Patch data: is the actual patch content indicated by the patch address, used to replace or modify the original data.

[0046] When the device obtains the read-write address, it uses an efficient search algorithm (such as hash search, binary search tree search, etc.) to search for a patch data item matching the read-write address in the patch pool. The matching criteria is that the patch address and the read-write address are completely identical. If a matching patch data item is found, the device will use it as the target patch data item for subsequent processing.

[0047] Further, to improve storage efficiency and access speed, each patch data item in the patch pool is compressed. Before adding the patch data item to the patch pool, the device uses an efficient compression algorithm (such as gzip, bzip2, etc.) to compress the data.

[0048] The compressed data item includes compressed patch data, patch status value, code data type value, patch expiration, patch type value (including replacement methods, etc.), and decompressed patch address. These information are organized into a structured data format for subsequent query and application.

[0049] Further, in some embodiments of the present application,

[0050] The length of the patch status value is set to 1 bit. Using 1 bit can represent two states (such as valid or invalid), which is simple and efficient.

[0051] The length of the data code type value is set to 2 bits. 2 bits can represent 4 different data types (such as data, code, both data and code, or other reserved types), meeting the basic type differentiation needs.

[0052] The length of patch validity period is set as 1 bit. In this setting, the patch validity period can be simplified as two kinds of representation (such as a simplified representation of N times valid or permanently valid, or a certain mark within a specific validity period, and the actual meaning needs to be defined in combination with the specific implementation). If a more complex representation is needed, it can be extended through other mechanisms or fields.

[0053] The length of patch type value is set as 3 bits. 3 bits can represent 8 different patch types, such as replacement, modification, addition, deletion, etc., and possible combinations or reserved types, providing flexibility for the application of patches.

[0054] The length of patch address is equal to the length of the address bus. This means that the patch address can accurately represent any address position in the system memory, ensuring that the patch can be correctly applied to the target position.

[0055] S203, if the patch address and the read-write address are the same, determine whether the patch state value of the target patch data item represents a valid state.

[0056] Among them, after the device obtains the target patch data item, it will first check its patch state value. By reading the patch state value and comparing it with the valid state value defined internally, it is determined whether the patch is in a valid state. If the patch state value indicates validity, the device will continue the subsequent processing. If the patch state value indicates invalidity, the device will ignore the patch data item and not perform any modification or interruption processing.

[0057] Further, in some embodiments of the present application, in the patch repair process, the patch repair device will query whether there is a matching patch address in the patch pool according to the current read-write request address of the CPU. The patch pool is a collection of multiple patch data items, each of which contains various information of the patch, such as patch state, data code type, patch validity period, patch type and patch address, etc. If the patch repair device finds a target patch data item with the same patch address and read-write request address in the patch pool, it will process the patch data item according to the established patch repair process, such as applying the patch, updating the data, etc. If no matching patch data item is found, it means that the memory address accessed by the current read-write request has no corresponding patch to be applied. In the case where no matching patch data item is found, the patch repair device will no longer intervene in the read-write request, but will directly instruct the CPU to perform the target data operation indicated by the read-write request. This means that the CPU will read data from the specified memory address or write data to the address according to the normal memory access process.

[0058] S204, if yes, determine whether the data type of the read-write data indicated by the read-write request matches the code data type value of the target patch data item.

[0059] In the case that the patch status is valid, the device further verifies whether the data type of the read-write data indicated by the read-write request matches the code data type value in the target patch data item. The device determines whether the data types match by comparing the data type identifier in the read-write request or performing a type compatibility check. If the data types do not match, the device ignores the patch data item. If the data types match, the device proceeds with subsequent processing.

[0060] S205, if yes, obtaining a patch type value of the target patch data item.

[0061] In the case that the data types match, the device obtains the patch type value in the target patch data item. The patch type value indicates how the patch should be applied. By reading the patch type value, the device determines the processing strategy that should be adopted to apply the patch. For example, if the patch type value indicates a replacement mode, the device will prepare to replace the original data.

[0062] S206, if the patch type value of the target patch data item is a first preset value, replacing the target data indicated by the read-write request with the patch data.

[0063] S207, if the patch type value of the target patch data item is a second preset value, replacing the target data indicated by the read-write request with a CPU exception instruction, which is used to instruct the CPU to enter an interrupt processing flow according to an interrupt vector table of the target patch data item, and obtain corresponding patch data in the interrupt processing flow.

[0064] According to different patch type values, the device adopts different processing strategies to apply the patch:

[0065] Replacement mode: if the patch type value indicates direct replacement, the device replaces the target data indicated by the read-write request with the patch data. This involves writing the patch data (stored at the location indicated by the patch address) to the memory location being accessed by the CPU. During the replacement process, the device can perform data integrity verification or backup the original data to prevent data loss or damage.

[0066] Triggering an interrupt processing flow: the device replaces the target data indicated by the read-write request with a CPU exception instruction. The exception instruction is a special instruction that, when executed by the CPU, triggers an interrupt processing flow. The interrupt processing flow jumps to the corresponding interrupt service program according to the interrupt vector table in the patch data item. In the interrupt service program, the device obtains and applies the corresponding patch data, completing the patch application process.

[0067] Further, in the patch repair process, when it is necessary to trigger the CPU exception handling process, the CPU exception instruction is the trap instruction or the break instruction.

[0068] The trap instruction, also known as the self-trapping instruction or the trap instruction, is a special instruction in the computer operating system. It is used to call the operating system kernel program running in the user state, i.e. when the running user process or system utility process needs to request the operating system kernel to serve it, the trap instruction can be executed to trigger a special exception. Trap instruction is commonly used in system call, program debugging and other scenarios. For example, in the program debugging process, trap instruction can be used to set breakpoints to pause execution when the program executes to a specific location, and enter debugging mode. In the patch repair process, the trap instruction can be used to trigger the interrupt handling process, so that the CPU jumps to the corresponding interrupt service program. In the interrupt service program, the patch repair device can obtain and apply the corresponding patch data to complete the repair work of the patch.

[0069] The break instruction is usually used in programming to terminate the execution of the current loop or conditional statement. However, in the context of CPU exception handling, the break instruction can be considered as a kind of general exception triggering mechanism, which is used to interrupt the normal execution flow of the program under certain conditions. Although the direct application of break instruction in programming is different from that of trap instruction, in some exception handling mechanisms, break instruction can be combined with exception handling process through specific implementation. For example, in some embedded systems or specific processor architectures, break instruction may be designed to trigger specific exception handling routines. In specific patch repair scenarios, if break instruction is designed to trigger exception handling process, it can be used to interrupt the execution of the program when a specific error or exception condition is detected, and guide the CPU into exception handling mode. In the exception handling mode, the patch repair device can perform the corresponding repair operation.

[0070] S208, according to the patch validity period, whether the target patch data item is invalid, if yes, set the patch state value to invalid state, delete the patch data from the patch pool, otherwise keep in valid state.

[0071] Among them, after applying the patch, the device will judge whether the target patch data item has been invalid according to the patch validity period value. The device compares the current time with the patch validity period expiration time to determine whether the patch is still within the validity period. If the patch has been invalid, the device will set the patch state value to invalid state, and delete the patch data item from the patch pool, to ensure the accuracy and validity of the patch pool. If the patch is still within the validity period, the device will keep the patch state value as valid state, and continue to monitor and process subsequent read-write requests.

[0072] In some embodiments of the present application, the patch validity period is now represented as N-time valid or permanent valid. Specifically:

[0073] N-time valid: N is an integer greater than 1, representing that the patch data item can be applied N times. Each time the patch is applied, the device will record the number of times the patch is used. When the number of uses reaches N, the patch is considered invalid. Permanent valid: the patch data item is marked as permanent valid, meaning that it has no limit on the number of uses and can be applied indefinitely.

[0074] For N-time valid patches, the device stores a use count counter in the patch data item. Each time the patch is applied, the counter is incremented. The device will check whether the value of the counter is less than or equal to N. If yes, the patch is still valid; if no, the patch is considered invalid, and the device will update the patch status value accordingly and delete the patch data item from the patch pool.

[0075] For permanent valid patches, the device does not need to store a use count counter in the patch data item. The device will directly determine whether the patch is permanent valid. If yes, the patch is always considered valid; if no (i.e., the patch has a specific validity period, but is not permanent valid), the original validity period judgment logic is followed.

[0076] Further, in some embodiments of the present application, the present application adds a step of integrity checking of the target patch data item, and requires that the verification result be passed. This step is a key link to ensure that the patch data item is not tampered with or damaged during storage, transmission, and application.

[0077] The target of the verification is the target patch data item obtained from the patch pool. This data item contains various information of the patch, such as the patch status value, the data code type value, the patch validity period, the patch type value, and the patch address, etc. Integrity verification usually uses mathematical methods such as hash algorithms (e.g., MD5, SHA-1, etc.) or checksum algorithms. These algorithms can perform unique mathematical transformations on the contents of the patch data item to generate a fixed checksum value or hash value. Before the patch data item is stored or transmitted, its checksum value or hash value is calculated and saved or transmitted together with the patch data item. Before the patch data item is applied, its checksum value or hash value is recalculated and compared with the previously saved checksum value or hash value. If the recalculated checksum value or hash value matches the previously saved checksum value or hash value, it means that the patch data item has not been tampered with or damaged during storage, transmission, and application, and the verification result is passed. If the verification result does not pass, it means that the patch data item may have a problem, and the patch repair device will not apply the patch data item and may trigger the corresponding error handling process, such as recording error logs, notifying administrators, etc.

[0078] The present application has the following beneficial effects:

[0079] The technical solution can respond and process access to a specific address in real time by monitoring read and write requests on the system bus, thereby achieving dynamic patch repair of code in read-only storage media. This avoids the limitation of traditional read-only storage media that cannot modify code, greatly reducing economic losses caused by code errors or vulnerabilities. Any code / data can be patched, achieving full-function patching without discrimination. This means that code or data located anywhere in the memory can be repaired by the patch repair device, greatly enhancing the coverage and applicability of the patch. Due to the full-function patching capability of the patch repair device, it can handle various types of code or data errors, including but not limited to logical errors, data corruption, and functional defects. This powerful function enables most bugs to be repaired in a timely and effective manner, improving system stability and reliability. The technical solution replaces code / data through the bus, triggers exceptions such as traps / breakpoints, and other means to implement read-only code patching. This versatile and flexible method greatly reduces the risk of ROM code exceptions requiring chip replacement or chip scrapping for reprogramming. Developers do not need to worry about the entire batch of chips being scrapped due to code errors, thereby saving time and cost. By avoiding the cost of chip scrapping and reprogramming, as well as reducing production downtime and maintenance costs due to code errors, the technical solution has a significant economic effect. It not only improves production efficiency, but also reduces the overall cost of products, enhancing the competitiveness of enterprises.

[0080] The following is an embodiment of the device of the present application, which can be used to execute the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

[0081] Please refer to Figure 3 which shows a structure diagram of a read-only code patch repair device provided by an exemplary embodiment of the present application, hereinafter referred to as device 3. Device 3 includes a monitoring unit 301, a query unit 302, a judgment unit 303, and an update unit 304.

[0082] The monitoring unit 301 is configured to monitor the system bus and, when a read / write request from the CPU is detected on the system bus, analyze the read / write address of the read / write request.

[0083] The query unit 302 is configured to query a patch data item matching the read / write address in a patch pool. The patch pool is pre-configured with a plurality of patch data items, and the patch data item includes a patch status value, a code data type value, a patch validity period value, a patch type value, a patch address, patch data, and an interrupt vector table.

[0084] The judging unit 303 is configured to: if the target patch data item with the patch address same as the read-write address is found, judge whether the patch state value of the target patch data item indicates a valid state; if yes, judge whether the data type of the read-write data indicated by the read-write request matches the code data type value of the target patch data item; if yes, acquire the patch type value of the target patch data item; if the patch type value of the target patch data item is a first preset value, replace the target data indicated by the read-write request with the patch data; if the patch type value of the target patch data item is a second preset value, replace the target data indicated by the read-write request with a CPU exception instruction, the CPU exception instruction being used to instruct the CPU to enter an interrupt processing flow according to the interrupt vector table of the target patch data item, and the corresponding patch data is acquired in the interrupt processing flow.

[0085] The updating unit 304 is configured to: judge whether the target patch data item is invalid according to the patch validity period; if yes, set the patch state value to an invalid state, and delete the patch data from the patch pool; otherwise, keep the patch data in a valid state.

[0086] In one or more possible embodiments, each patch data line item in the patch pool is compressed.

[0087] In one or more possible embodiments, the patch validity period indicates N times of validity or permanent validity, and N is an integer greater than 1.

[0088] In one or more possible embodiments, the length of the patch state value in the patch data item is 1 bit, the length of the data code type value is 2 bits, the length of the patch validity period is 1 bit, the length of the patch type value is 3 bits, and the length of the patch address is equal to the length of the address bus.

[0089] In one or more possible embodiments, the CPU exception instruction is a trap instruction or a break instruction.

[0090] In one or more possible embodiments, the method further comprises:

[0091] The checking unit is configured to perform integrity checking on the target patch data item, and the checking result is passed.

[0092] In one or more possible embodiments, the judging unit 303 is further configured to:

[0093] If the target patch data item with the patch address same as the read-write address is not found, instruct the CPU to directly execute the target data indicated by the read-write request.

[0094] It should be noted that the device 3 provided by the above embodiment is only used for example to divide the above functional modules when performing the patch repair method of the read-only code, and in actual application, the above functions can be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the above functions. In addition, the patch repair device of the read-only code and the patch repair method of the read-only code provided by the above embodiment belong to the same concept, and the implementation process is detailed in the method embodiment, which will not be described here.

[0095] The serial numbers of the above embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0096] The embodiment of the present application further provides a computer storage medium, which can store a plurality of instructions, the instructions being suitable for being loaded and executed by a processor to perform the method steps of the embodiments of the method as shown in the above Figure 2 The specific execution process can refer to the specific description of the embodiments as shown in the above Figure 2 The specific execution process can refer to the specific description of the embodiments as shown in the above

[0097] The present application also provides a computer program product, which stores at least one instruction, the at least one instruction being loaded and executed by the processor to implement the patch repair method of the read-only code as described in each of the above embodiments.

[0098] Please refer to Figure 4 , which provides a structural schematic diagram of a device for the embodiments of the present application. As shown in the above Figure 4 , the device 400 can include at least one processor 401, at least one communication interface 403, a memory 404, and at least one communication bus 402.

[0099] The communication bus 402 is used to realize the connection and communication between the components.

[0100] The communication interface 403 can optionally include a standard wired interface and a wireless interface, and is used to communicate with the CPU inside the chip through the system bus.

[0101] The processor 401 may include one or more processing cores. The processor 401 connects to various parts within the device 400 using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in the memory 404, and by calling data stored in the memory 404. Optionally, the processor 401 may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor 401 may integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display; and the modem handles wireless communication. It is understood that the modem may also be implemented as a separate chip without being integrated into the processor 401.

[0102] The memory 404 may include random access memory (RAM) or read-only memory. Optionally, the memory 404 may include a non-transitory computer-readable storage medium. The memory 404 can be used to store instructions, programs, code, code sets, or instruction sets. The memory 404 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch function, sound playback function, image playback function, etc.), instructions for implementing the above-described method embodiments, etc.; the data storage area may store data involved in the above-described method embodiments, etc. Optionally, the memory 404 may also be at least one storage device located remotely from the aforementioned processor 401. Figure 4 As shown, the memory 404, which serves as a computer storage medium, may include an operating system, a network communication module, a user interface module, and application programs.

[0103] exist Figure 4 In the illustrated device 400, the processor 401 can be used to call the application program stored in the memory 404 and specifically execute, such as Figure 2The method shown, the specific process can refer to Figure 2 As shown, no longer here.

[0104] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The program can be stored in a computer readable storage medium, and when executed, can include the processes of the above-mentioned embodiment methods. The storage medium can be a magnetic disc, an optical disc, a read-only memory or a random access memory, etc.

[0105] The above only discloses the preferred embodiments of the present application, and of course cannot limit the scope of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope of the present application.

Claims

1. A method for patching and fixing read-only code, characterized in that, include: Monitor the system bus, and when a read / write request from the CPU is detected on the system bus, parse the read / write address of the read / write request; The patch pool is used to query the patch data item that matches the read / write address; wherein, the patch pool is pre-configured with multiple patch data items, the patch data items include: patch status value, code data type value, patch validity period value, patch type value, patch address, patch data, and interrupt vector table; If a target patch data item with the same patch address as the read / write address is found, determine whether the patch status value of the target patch data item indicates a valid status; If so, determine whether the data type of the read / write data indicated by the read / write request matches the code data type value of the target patch data item; If so, obtain the patch type value of the target patch data item; If the patch type value of the target patch data item is a first preset value, the target data indicated by the read / write request is replaced with the patch data; If the patch type value of the target patch data item is a second preset value, the target data indicated by the read / write request is replaced with a CPU exception instruction. The CPU exception instruction is used to instruct the CPU to enter the interrupt handling process according to the interrupt vector table of the target patch data item, and to obtain the corresponding patch data in the interrupt handling process. The validity period of the patch is used to determine whether the target patch data item is invalid. If it is, the patch status value is set to invalid and the patch data is deleted from the patch pool. Otherwise, it remains valid.

2. The method according to claim 1, characterized in that, Each patch data item in the patch pool is compressed.

3. The method according to claim 1 or 2, characterized in that, The patch validity period value indicates whether it is valid for N times or permanently, where N is an integer greater than 1.

4. The method according to claim 3, characterized in that, The patch status value in the patch data item is 1 bit long, the code data type value is 2 bits long, the patch validity period value is 1 bit long, the patch type value is 3 bits long, and the length of the patch address is equal to the length of the address bus.

5. The method according to claim 1, 2, or 4, characterized in that, The CPU exception instruction is either a trap instruction or a break instruction.

6. The method according to claim 5, characterized in that, Also includes: The integrity of the target patch data item is verified, and the verification result is passed.

7. The method according to claim 6, characterized in that, Also includes: If no target patch data item with the same patch address as the read / write address is found, the CPU is instructed to directly execute the target data indicated by the read / write request.

8. A read-only code patching and repair device, characterized in that, include: The monitoring unit is used to monitor the system bus and, when a read / write request from the CPU is detected on the system bus, parses the read / write address of the read / write request. The query unit is used to query the patch data item that matches the read / write address in the patch pool; wherein, the patch pool is pre-configured with multiple patch data items, and the patch data items include: patch status value, code data type value, patch validity period value, patch type value, patch address, patch data, and interrupt vector table; The judgment unit is configured to, if a target patch data item with the same patch address as the read / write address is found, determine whether the patch status value of the target patch data item indicates a valid status; if yes, determine whether the data type of the read / write data indicated by the read / write request matches the code data type value of the target patch data item; if yes, obtain the patch type value of the target patch data item; if the patch type value of the target patch data item is a first preset value, replace the target data indicated by the read / write request with the patch data; if the patch type value of the target patch data item is a second preset value, replace the target data indicated by the read / write request with a CPU exception instruction, wherein the CPU exception instruction is used to instruct the CPU to enter the interrupt handling process according to the interrupt vector table of the target patch data item, and obtain the corresponding patch data in the interrupt handling process; The update unit is used to determine whether the target patch data item is invalid based on the patch validity period value. If it is invalid, the patch status value is set to invalid and the patch data is deleted from the patch pool; otherwise, it remains valid.

9. A computer storage medium, characterized in that, The computer storage medium stores a plurality of instructions, which are adapted to be loaded by a processor and executed as method steps as claimed in any one of claims 1 to 7.

10. A read-only code patching and repair device, characterized in that, include: A processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and executed the method steps as claimed in any one of claims 1 to 7.

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