Chip testing method based on FPGA
Through the chip testing method based on FPGA, multiple parallel tests of different types of memory chips are solved, and the problem of being unable to test multiple types of chips at the same time in the prior art is improved, and the testing efficiency is shortened.
Patent Information
- Application Number
- CN202510207821.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-06-13
AI Technical Summary
Existing chip testing methods cannot test multiple types of memory chips at the same time, which is inefficient and requires a long test time.
Using the FPGA-based chip testing method, the programmability and flexibility of FPGA is used to conduct multiple parallel testing of different types of chips to be tested. The FPGA module is used to determine the test address range based on the binding information of the host computer, and test it using the test vector.
Efficient multi-channel parallel testing of different types of chips to be tested is achieved, which significantly reduces the chip test time.
Smart Images
Figure CN120144378A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of chip testing, and particularly relates to a chip testing method based on FPGA. Background Art
[0002] According to different storage methods, storage chips can be divided into two categories: random access memory (RAM) and read-only memory (ROM) according to whether the stored data is lost when the power is off. Among them, RAM can be divided into static random access memory (SRAM) that does not require refreshing and dynamic random access memory (DRAM) that requires periodic refreshing according to whether dynamic refreshing is required, and ROM can be divided into various types such as EPROM, EEPROM, and Flash according to different erasing and writing methods.
[0003] With the continuous development of electronic devices, the scenarios where storage chips need to be used are becoming more and more diverse, the types are becoming more and more complex, and their reliability has received increasing attention. Therefore, it is necessary to fully verify their reliability and yield before use.
[0004] As Figure 1 shown, the existing test solutions can only test one type of the same storage chip at a time, cannot configure test conditions in real time, and are not convenient for simultaneously testing multiple types of storage chips, resulting in low efficiency and long test time. Summary of the Invention
[0005] The present application provides a chip testing method based on FPGA, which uses the programmability and flexibility of FPGA to perform multi-channel parallel testing on different types of chips to be tested, reducing the test time of the chips.
[0006] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.
[0007] To achieve one or part or all of the above objects or other objects, the present invention provides a chip testing method based on FPGA.
[0008] A chip testing method based on FPGA includes:
[0009] Step S1: The FPGA module determines the test address range of different types of chips to be tested according to the binding information of the host computer, reads the test vectors of the chips to be tested from the memory, and performs tests through the test vectors; the FPGA module is connected to different types of chips to be tested through different data buses, and the test data and test vectors of the same type of chips to be tested are the same;
[0010] Step S2: The FPGA module responds to the initialization instruction of the host computer, initializes the chips to be tested in multi-channel parallel, and performs serial initialization on the chips to be tested with unsuccessful initialization;
[0011] Step S3: The FPGA module responds to the write verification instruction of the host computer and writes the test vector of the chip under test to the destination address.
[0012] Step S4: The FPGA module responds to the read verification instruction of the host computer, reads the data in the destination address, compares it with the written data, marks the positions of the destination addresses with inconsistencies, and feeds back the comparison information to the host computer to complete the functional test of the chip under test.
[0013] The FPGA module obtains the type ID, location information, and test vectors of different types of chips under test according to the information bound by the host computer.
[0014] The FPGA module queries the type ID and location information of the chip under test, compares them with the data in the information bound by the host computer, and confirms whether there are differences; if not, the test is carried out; otherwise, the information of the host computer is rebound.
[0015] The host computer transfers the types, quantities, and data to be tested of different types of chips under test to the FPGA module, and the FPGA module caches the data to be tested in the memory.
[0016] The FPGA module analyzes the information of the chip under test, generates corresponding test vectors, and caches them in the memory.
[0017] Before the test vectors are tested, it also includes:
[0018] The FPGA module adjusts the speed setting of the test equipment according to the test speed parameter in the information bound by the host computer.
[0019] The FPGA module responds to the start test instruction of the host computer, performs synchronous multi-channel parallel testing on the chip under test, and marks the chips under test with unsuccessful initialization.
[0020] The step S3 also includes:
[0021] The FPGA module queries the factory mark information of the chip under test, identifies the factory test bad blocks of the chip under test and stores them in the internal storage area of the FPGA module, and the chip under test no longer tests the factory test bad blocks of the chip under test.
[0022] The test vectors corresponding to the addresses of the chip under test are written to the destination addresses of the non-factory test bad blocks of the chip under test.
[0023] The comparison information includes the marked positions of the inconsistent destination addresses and the total number of inconsistent destination addresses.
[0024] Compared with the prior art, the beneficial effects of the present invention mainly include:
[0025] The present application provides a chip testing method based on FPGA, which uses the programmability and flexibility of FPGA to perform multi-channel parallel testing on different types of chips to be tested, reducing the testing time of the chips.
[0026] In order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, provides a detailed description as follows. Description of the Drawings
[0027] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the following described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0028] Figure 1 It is a schematic flow chart of an existing chip testing method.
[0029] Figure 2 It is a schematic flow chart of a chip testing method based on FPGA provided by an embodiment of the present application. Detailed Embodiments
[0030] Regarding the foregoing and other technical contents, features, and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the accompanying drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front, or back, etc., are only references to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.
[0031] The present application provides a chip testing method based on FPGA, which uses the programmability and flexibility of FPGA to perform multi-channel parallel testing on different types of chips to be tested, reducing the testing time of the chips.
[0032] The following will elaborate on each embodiment of the present application in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present application, many technical details are provided for the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.
[0033] Embodiment
[0034] Figure 2 Shown is a schematic flow chart of a chip testing method based on FPGA provided by an embodiment of the present application.
[0035] As shown Figure 2 in the figure, a chip testing method based on FPGA includes:
[0036] First, the host computer transfers the types, quantities, and test data of different types of chips to be tested to the FPGA module, and the FPGA module caches the test data in the memory; the FPGA module parses the information of the chips to be tested, generates corresponding test vectors, and caches them in the memory.
[0037] Specifically, the FPGA module connects different types of chips to be tested through different data buses, and the test data and test vectors of the same type of chips to be tested are the same. The FPGA module obtains the type IDs, location information, and test vectors of different types of chips to be tested according to the information bound by the host computer; the FPGA module compares the type IDs and location information of the chips to be tested queried with the data in the information bound by the host computer to confirm whether there are differences; if not, the test is carried out; otherwise, the information of the host computer is re-bound.
[0038] The FPGA module determines the test address range of different types of chips to be tested according to the binding information of the host computer, reads the test vectors of the chips to be tested from the memory, and performs tests through the test vectors.
[0039] Before the test vectors are used for testing, it also includes:
[0040] The FPGA module adjusts the speed setting of the test equipment according to the test speed parameter in the information bound by the host computer.
[0041] The FPGA module responds to the start test instruction of the host computer and performs synchronous multi-channel parallel testing on the chips to be tested. The specific process includes:
[0042] The host computer sends a start test command to the FPGA module;
[0043] After the FPGA module receives the command sent by the host computer, it generates multi-channel simultaneous start test commands and sends them to all test buses (bus 1, bus 2, bus 3...);
[0044] After the FPGA module receives the test feedback signal of the chip to be tested, it confirms the chip to be tested and sends test commands and test vectors to each test bus.
[0045] For flash devices, first execute the initialization instruction of the host computer to perform multi-channel parallel initialization on the chips to be tested, mark the chips to be tested with unsuccessful initialization, and perform serial initialization on the chips to be tested with unsuccessful initialization.
[0046] The FPGA module responds to the write verification instruction from the host computer, queries the factory mark information of the chip under test, identifies the factory test bad blocks of the chip under test and stores them in the internal storage area of the FPGA module. The chip under test no longer tests the factory test bad blocks of the chip under test; writes the test vector of the corresponding address of the chip under test to the destination address of the non-factory test bad blocks of the chip under test.
[0047] In addition, for the chip under test that is not of the flash type, directly write the test vector to the destination address to be tested.
[0048] The FPGA module responds to the read verification instruction from the host computer, reads the data in the destination address, compares it with the written data, marks the positions of the destination addresses with inconsistencies, and feeds back the compared information to the host computer to complete the functional test of the chip under test.
[0049] Specifically, after receiving the read verification instruction from the host computer, read out the data in sequence according to the test address range for all devices, compare the read data with the written data, mark the inconsistent positions and store the addresses in the FPGA storage space, and then count the number of different bits in the read and write operations; after the verification is completed, feed back the counted comparison information to the host computer. The host computer can query the marked positions of the inconsistent destination addresses and the total number of inconsistent destination addresses to obtain all the compared information.
[0050] This application provides a chip testing method based on FPGA, which uses the programmability and flexibility of FPGA to perform multi-channel parallel testing on different types of chips under test, reducing the testing time of the chips.
[0051] Some common English nouns or letters used in this invention for the convenience of clear description are only for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of this invention should not be limited by their possible Chinese translations or specific letters.
[0052] It should also be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.
Claims
1. A chip testing method based on FPGA, characterized in that: include: Step S1: The FPGA module determines the test address ranges of different types of chips to be tested according to the binding information of the host computer, and reads the test vectors of the chips to be tested from the memory, and performs the test by the test vectors; the FPGA module connects the different types of chips to be tested through different data buses, and the test data and test vectors of the same type of chips to be tested are the same; Step S2: the FPGA module responds to the initialization instruction of the host computer, performs multi-channel parallel initialization on the chips to be tested, and performs serial initialization on the chips to be tested that are not successfully initialized; Step S3: the FPGA module responds to the write verification instruction of the host computer and writes the test vector of the chip to be tested into the destination address; Step S4: The FPGA module responds to the read verification instruction of the host computer, reads the data in the destination address, and compares it with the written data, marks the inconsistent destination address position, and feeds back the compared information to the host computer to complete the functional test of the chip under test.
2. The FPGA-based chip testing method according to claim 1, characterized in that: The FPGA module obtains the type ID, location information and test vectors of different types of chips to be tested according to the information bound by the host computer.
3. The FPGA-based chip testing method according to claim 2, characterized in that: The FPGA module queries the type ID and location information of the chip to be tested, and compares the data with the information bound by the host computer to confirm whether there is a difference; if not, the test is performed; Otherwise, rebind the information of the host computer.
4. The FPGA-based chip testing method according to claim 1, characterized in that: The host computer transmits the types and quantities of different types of chips to be tested and the data to be tested to the FPGA module, and the FPGA module caches the data to be tested in the memory.
5. The FPGA-based chip testing method according to claim 4, characterized in that: The FPGA module parses the information of the chip to be tested, generates corresponding test vectors, and caches them in the memory.
6. The FPGA-based chip testing method according to claim 1, characterized in that: Before the test vector is tested, it also includes: The FPGA module adjusts the speed setting of the test device according to the test speed parameters in the information bound by the host computer.
7. The FPGA-based chip testing method according to claim 1, characterized in that: The FPGA module responds to the test start instruction of the host computer, performs synchronous multi-channel parallel testing on the chip to be tested, and marks the chip to be tested that fails to initialize.
8. The FPGA-based chip testing method according to claim 1, characterized in that: The step S3 further comprises: The FPGA module queries the factory mark information of the chip under test, identifies the factory detection bad blocks of the chip under test and stores them in the internal storage area of the FPGA module, and the chip under test no longer tests the factory detection bad blocks of the chip under test.
9. The FPGA-based chip testing method according to claim 8, characterized in that: The test vector of the address corresponding to the chip under test is written into the destination address of the non-factory detection bad block of the chip under test.
10. The FPGA-based chip testing method according to claim 1, characterized in that: The compared information includes the marked inconsistent destination address positions and the total number of inconsistent destination addresses.