Data transmission method of single-line communication link with variable clock period

Abstract

The invention discloses a data transmission method of a single-line communication link with a variable clock period. The data transmission method comprises the following steps: a host transmits a first signal to a slave based on a preset communication protocol; the slave translates each signal unit in the first signal to obtain data 0 or 1 of a second signal; the duration of the first level signal in each signal unit is recorded as T1, the duration of the second level signal in each signal unit is recorded as T2, and when the duration T1 of the first level signal is within a first threshold range, the signal unit represents data 0; and when the duration T1 of the first level signal in the signal unit is within a second threshold range, the signal unit represents data 1. Based on the data transmission method provided by the invention, the problem that the slave cannot correctly read data due to clock jitter of the host can be avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of serial communication, and particularly to a data transmission method for a single-wire communication link with variable clock cycles. Background Art

[0002] As Figure 1 shown in the schematic diagram of the single-wire communication link structure in the prior art of the LED backlight driving system, multiple LED driving ICs (slaves) are arranged in series. Each LED driving IC is provided with a data input terminal and a data output terminal. On the communication link where multiple LED driving ICs are connected in series, the data input terminal of the previous LED driving IC is connected to the data input terminal of the next LED driving IC. Each LED driving IC is provided with an LED driving channel connected to the LED string, and each LED driving channel is connected to an LED string. At the same time, the first slave among the multiple slaves in serial communication receives the data sent by the host, and the last one of the multiple slaves returns the data to the host, thus forming a single-wire communication link. In the prior art, a specific signal encoding method is adopted for the design of the LED driving IC to represent the LED driving data. This signal encoding method can be the encoding method of the communication protocol in the prior art, such as Manchester encoding or BMC encoding, or a newly developed encoding method. However, when using the newly developed encoding method, it involves the translation of the new signal encoding under the communication protocol of the original host (such as the SPI protocol). No matter which of the above encoding methods is adopted, its characteristic is that the period must be fixed. Based on the fixed period, combined with different duty cycles or the signal inversion characteristics within one period, can 0 / 1 be determined. In the receiving mechanism of the slave, it is necessary to measure both the period and the single-bit time (high or low) simultaneously, and then complete the duty cycle calculation or comparison. It is not applicable to the situation where the period changes, and in addition, the time accuracy requirement for the host is relatively high. For the situation where the period becomes smaller, if the high-level time remains unchanged or becomes longer, the duty cycle becomes larger, and it is possible to misjudge 0 as 1, or misjudge it as a bit with other meanings; for the situation where the period becomes larger, the duty cycle becomes smaller. In addition to possibly misjudging 1 as 0, it may also trigger a timeout and misjudge it as the end of communication, resulting in data loss. For application scenarios with low host clock accuracy, due to clock jitter or signal interference, the period of the OWC is erratic, and the change range of the duty cycle calculation result is relatively large, which is also likely to cause decoding errors of the slave.

[0003] Therefore, it can be seen that in the prior art, a new data transmission method for a single-wire communication link with variable clock cycles is needed, based on which the transcoding error caused by the jitter of the periodic clock signal can be shielded. Summary of the Invention

[0004] The technical objective to be achieved by the present invention is to provide a new data transmission method for a single - wire communication link with variable clock cycles. Based on this method, transcoding errors caused by jitter of the periodic clock signal can be shielded, and even if the host clock signal changes, it does not affect the slave device's ability to correctly read data.

[0005] Based on the above - mentioned technical objective, the present invention provides a data transmission method for a single - wire communication link with variable clock cycles. The single - wire communication link includes a host and multiple slave devices. The host and the slave devices are serially connected using a single data line. The data transmission method includes:

[0006] The host transmits a first signal to the slave device based on a preset communication protocol;

[0007] The slave device translates the first signal to obtain a second signal: The translation includes determining the second signal by using the signal level states of every n clock cycles of the first signal as a signal unit; each signal unit is used as a communication code to represent data 0 or 1;

[0008] The duration of the first - level signal in each signal unit is denoted as T 1 , and the duration of the second - level signal is denoted as T 2 , and the first - level signal and the second - level signal are opposite;

[0009] When the duration T 1 of the first - level signal in the signal unit is between the first threshold M 1 and the second threshold M 2 , that is, M 1 ≤T 1 ≤M 2 ; or when the duration T 2 of the second - level signal is between the third threshold M 3 and the fourth threshold M 4 , that is, M 3 ≤T 2 ≤M 4 , this signal unit represents data 0;

[0010] When the duration T 1 of the first - level signal in the signal unit is between the third threshold M 3 and the fourth threshold M 4 , that is, M 3 ≤T 1 ≤M 4 ; or when the duration T 2 of the second - level signal is between the first threshold M 1 and the second threshold M 2 , that is, M 1 ≤T 2 ≤M2 When this occurs, the signal unit represents data 1;

[0011] The first threshold M 1 to the second threshold M 2 satisfies M 1 ≦n 2 *T≦M 2 ; where n 2 <n / 2, and n 2 is a natural number; the third threshold M 3 to the fourth threshold M 4 satisfies M 3 ≦n 1 *T≦M 4 ; where n 1 >n / 2, n 1 is a natural number; T is the clock period of the first signal.

[0012] In one embodiment, when the clock deviation amplitude between the host and the slave is set to be less than or equal to P%, then M 1 =(1 - P)% * n 2 *T, M 2 =(1 + P)% * n 2 *T; M 3 =(1 - P)% * n 1 *T, M 4 =(1 + P)% * n 1 *T.

[0013] In one embodiment, the preset communication protocol is the SPI communication protocol.

[0014] Other features and advantages of the present invention will be described in the following description, and in part will be obvious from the description, or will be understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained by the structures specifically pointed out in the description, the claims, and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings are used to provide a further understanding of the present invention, and constitute a part of the description. They are used together with the embodiments of the present invention to explain the present invention, and do not constitute a limitation to the present invention. In the drawings:

[0016] Figure 1 is a schematic diagram of the single-line communication link structure in the LED backlight driving system in the prior art;

[0017] Figure 2 is a schematic diagram of the communication protocol and signal coding timing in an embodiment of the present invention;

[0018] Figure 3It is a schematic diagram of signal timing under clock jitter in an embodiment of the present invention; Detailed implementation manners

[0019] To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0020] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be denoted as the second element, component, region, layer or part. And when discussing the second element, component, region, layer or part, it does not imply that the present invention necessarily has a first element, component, region, layer or part.

[0021] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience of description to describe the relationship of one element or feature shown in the drawings with other elements or features. It should be understood that, in addition to the orientation shown in the drawings, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then an element or feature described as "below" or "beneath" or "under" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "under" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0022] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0023] Example 1

[0024] In a single - wire serial communication link as Figure 1 shown, in this embodiment, its host performs data transmission based on the SPI communication protocol. At the same time, as Figure 2 shown, the first signal transmitted by the host to the slave based on a preset communication protocol (SPI communication protocol), Figure 2 taking the clock polarity CPOL = 0 and the clock phase CPHA = 1 as an example, shows the timing state of the first signal. In this embodiment, when the slave receives the first signal transmitted by the host, it encodes and translates the first signal to generate a second signal. The encoding and translation means determining the second signal by taking the signal level state of every 4 clock cycles of the first signal as a signal unit. Specifically, for each signal unit, if the duration of the low - level signal in the first signal of 4 clock cycles exceeds the duration of the high - level signal, that is, the duty cycle of the signal unit is less than 50%, set to 25% in this embodiment, then the communication code translated by this signal unit is data "0"; if the duration of the low - level signal in the first signal of 4 clock cycles is less than the duration of the high - level signal, that is, the duty cycle of the signal unit is greater than 50%, set to 75% in this embodiment, then the communication code translated by this signal unit is data "1". The above is the OWC encoding method of this embodiment.

[0025] In this embodiment, taking the first signal of 4 clock cycles as a signal unit is only one implementation manner of the present invention. Those skilled in the art should know that if using the duty cycle greater than 50% or less than 50% as the determination condition for representing data "0" or "1" of the second signal, and using other numbers of clock cycles as signal units can also be achieved, such as 3, 5, 6, 7 clock cycles, etc. On the other hand, the encoding method used for the second signal in this embodiment is only one implementation manner, and other encoding methods such as Manchester encoding or BMC encoding can be used in the present invention to generate the second signal.

[0026] If the signal duration of each signal unit contains the clock cycles of n first signals, and the clock cycle of the first signal is T, then the signal duration of one bit of the second signal corresponding to one signal unit is n*T. The duration of the first-level signal (high level or low level) in this n*T signal duration is denoted as T 1 The duration of the second-level signal (low level or high level) is denoted as T 2 and the first-level signal is opposite to the second-level signal. According to the above content, when T 1 >T 2 That is, T 1 =n 1 *T, and n 1 >n / 2, where n 1 is a natural number, then one bit of the second signal corresponding to the signal unit represents the data "1". When T 2 >T 1 That is, T 1 =n 2 *T, and n 2 <n / 2, where n 2 is a natural number, then one bit of the second signal corresponding to the signal unit represents the data "0".

[0027] For example Figure 3 as shown, taking the signal unit representing the data "0" as an example, to solve the problem of incorrect recognition of the second signal caused by the jitter of the clock cycle of the first signal, in this embodiment, it is set that when the duration T 1 of the first-level signal in the signal unit is between the first threshold M 1 and the second threshold M 2 , that is, M 1 ≤T 1 ≤M 2 , or when the duration T 2 of the second-level signal in the signal unit is between the third threshold M 3 and the fourth threshold M 4 , that is, M 3 ≤T 2 ≤M 4 , this signal unit represents the data "0".

[0028] Furthermore, it is set that when the duration T 1 of the first-level signal in the signal unit is between the third threshold M 3 and the fourth threshold M 4 , that is, M 3 ≤T 1 ≤M 4 , or when the duration T 2 of the second-level signal in the signal unit is between the first threshold M 1 and the second threshold M2 When it is between, that is, M 1 ≤T 2 ≤M 2 When, this signal unit represents the data "1".

[0029] According to the foregoing definitions of data "0" and "1" under normal clock, the first threshold M 1 to the second threshold M 2 Satisfies M 1 ≤n 2 *T≤M 2 , the n 2 and M 1 The difference between, and n 2 and M 2 The difference between is related to the allowable clock variation amplitude of the slave device. For example, when the allowable clock deviation of the slave device is ±10%, then there is M 1 =90%*n 2 *T, M 2 =110%*n 2 *T. Similarly, the third threshold M 3 to the fourth threshold M 4 Satisfies M 3 ≤n 1 *T≤M 4 , the n 1 and M 3 The difference between, and n 1 and M 4 The difference between is related to the allowable clock variation amplitude of the slave device. For example, when the allowable clock deviation of the slave device is ±10%, then there is M 3 =90%*n 1 *T, M 4 =110%*n 1 *T.

[0030] The present invention can be any possible system, method and / or computer program product at the integrated technology detail level. The computer program product can include a computer-readable storage medium (or multiple media) having computer-readable program instructions thereon for causing a processor to execute various aspects of the present invention.

[0031] A computer-readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer-readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing devices. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanically encoded device such as a punched card or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer-readable storage medium, as used herein, should not be construed as being a transitory signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through an optical fiber cable), or an electrical signal transmitted through a wire.

[0032] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium within the corresponding computing / processing device.

[0033] The computer-readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or source code or object code written in any combination of one or more programming languages and procedural programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server. In the latter case, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, an electronic circuit, including, for example, a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA), may execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit, thereby performing aspects of the present invention.

[0034] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0035] These computer-readable program instructions may be provided to a processor of a computer, or other programmable data processing apparatus, to produce a machine, such that the instructions executed via the processor of the computer or other programmable data processing apparatus create means for implementing the functions / acts specified in the flowchart and / or block Figure 1 diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable storage medium in which the instructions are stored comprises a manufacture including instructions which implement aspects of the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0036] The computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other devices to produce a computer-implemented process, such that the instructions executed on the computer, other programmable apparatus, or other devices implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0037] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of instructions that includes one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, in fact, two consecutive blocks shown may be completed as one step, and depending on the functions involved, may be executed concurrently, substantially concurrently, in a partially or fully time-overlapped manner, or sometimes in the reverse order. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by a system based on dedicated hardware that performs the specified functions or actions or a combination of dedicated hardware and computer instructions.

[0038] Embodiments of the present application are described with reference to the flowcharts and / or block diagrams of methods, apparatuses (devices), and computer program products according to embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, and combinations of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing device generate means for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0039] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufacture including instruction means that implement the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0040] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

Claims

1. A data transmission method for a single - wire communication link with variable clock cycles. The single - wire communication link includes a host and multiple slaves. The host and the slaves are serially connected using a single data line. It is characterized in that: The data transmission method includes: The host transmits a first signal to the slave based on a preset communication protocol; The slave translates the first signal to obtain a second signal: The translation includes determining the second signal by taking the signal - level states of every n clock cycles of the first signal as a signal unit; Each of the signal units is used as a communication code to represent data 0 or 1; The duration of the first - level signal in each signal unit is denoted as T1, and the duration of the second - level signal is denoted as T2, and the first - level signal and the second - level signal are opposite; When the duration T1 of the first - level signal in the signal unit is between a first threshold M1 and a second threshold M2, that is, M1 ≤ T1 ≤ M2; or when the duration T2 of the second - level signal is between a third threshold M3 and a fourth threshold M4, that is, M3 ≤ T2 ≤ M4, this signal unit represents data 0; When the duration T1 of the first - level signal in the signal unit is between the third threshold M3 and the fourth threshold M4, that is, M3 ≤ T1 ≤ M4; or when the duration T2 of the second - level signal is between the first threshold M1 and the second threshold M2, that is, M1 ≤ T2 ≤ M2, this signal unit represents data 1; The first threshold M1 to the second threshold M2 satisfy M1 ≤ n2*T ≤ M2; where n2 < n / 2 and n2 is a natural number; The third threshold M3 to the fourth threshold M4 satisfy M3 ≤ n1*T ≤ M4; where n1 > n / 2 and n1 is a natural number; T is the clock cycle of the first signal.

2. The data transmission method according to claim 1, characterized in that: When the clock deviation amplitude between the host and the slave is set to be less than or equal to P%, then M1=(1 - P)%*n2*T, M2=(1 + P)%*n2*T; M3=(1 - P)%*n1*T, M4=(1 + P)%*n1*T.

3. The data transmission method according to claim 1, characterized in that: The preset communication protocol is the SPI communication protocol.

4. An electronic device, including a memory and a processor; wherein, The memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the steps of the method according to any one of claims 1 - 3.

5. A computer-readable storage medium having computer instructions stored thereon, wherein: When the computer instructions are executed by the processor, the steps of the method according to any one of claims 1 - 3 are implemented.

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