Microprocessor architecture, information interaction method and computer equipment

Abstract

The invention provides a microprocessor architecture, an information interaction method and computer equipment. The microprocessor architecture comprises a first processor and a second processor, wherein the security level of the second processor is higher than that of the first processor, the first processor and the second processor are electrically connected through a first interaction circuit, and the first interaction circuit comprises at least two registers; when the first interaction circuit detects that the first processor writes first request information into the first interaction circuit, the first interaction circuit sends an interrupt signal to the second processor through the at least two registers; the interrupt signal is used for triggering the second processor to execute processing corresponding to the first request information. According to the microprocessor architecture, the information interaction efficiency among different processors in the architecture can be improved.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a microprocessor architecture, an information interaction method, and a computer device. Background Art

[0002] In a microprocessor architecture, different processors are usually set to be responsible for different processing tasks. At this time, information interaction between different processors will be involved to enable the invocation of different processors. For example, in a microprocessor architecture, an application processor is mainly used to run application programs and operating systems, and a system control processor is mainly used to be responsible for system control and management. In some cases, the application processor needs to invoke the system control processor to implement system control functions, such as implementing processor power consumption control, etc.

[0003] Currently, the invocation between different processors is usually achieved by means of a shared memory and an information processing unit. For example, the application processor first writes the request protocol content into the shared memory, and then configures the information processing unit to send a request to the system control processor. After receiving the request, the system control processor checks the protocol content in the shared memory and then makes a corresponding service response after analysis.

[0004] The above-mentioned interaction solution is relatively cumbersome, and the request information that needs to be executed quickly cannot be responded to in a timely manner. Summary of the Invention

[0005] Based on the above technical problems, this application proposes a microprocessor architecture, an information interaction method, and a computer device, which can improve the interaction efficiency between processors, and further improve the response efficiency of request information between processors.

[0006] A first aspect of this application proposes a microprocessor architecture, including: a first processor and a second processor; wherein, the security level of the second processor is higher than that of the first processor, and the first processor and the second processor are electrically connected through a first interaction circuit, and the first interaction circuit includes at least two registers; when the first interaction circuit detects that the first processor writes first request information into the first interaction circuit, it sends an interrupt signal to the second processor through the at least two registers; the interrupt signal is used to trigger the second processor to execute processing corresponding to the first request information.

[0007] A second aspect of the present application proposes an information interaction method, which is applied to a microprocessor architecture. The microprocessor architecture includes a first processor and a second processor. Among them, the security level of the second processor is higher than that of the first processor, and the first processor and the second processor are electrically connected through a first interaction circuit. The first interaction circuit includes at least two registers. The method includes: when the first interaction circuit detects that the first processor writes first request information into the first interaction circuit, the first interaction circuit sends an interrupt signal to the second processor through the at least two registers. The interrupt signal is used to trigger the second processor to execute processing corresponding to the first request information.

[0008] A third aspect of the present application proposes a computer device, which includes the above-mentioned microprocessor architecture, or the computer device is configured to implement the above-mentioned information interaction method.

[0009] The microprocessor architecture proposed in the present application sets an interaction circuit between the first processor and the second processor, and sets registers in the interaction circuit. When the first processor needs to send request information to the second processor, it can directly write the request information into the register of the interaction circuit. The interaction circuit sends an interrupt signal to the second processor, triggering the second processor to execute processing corresponding to the request information. The above-mentioned microprocessor architecture makes the interaction between different processors simpler and more efficient by setting an interaction circuit between different processors, which is beneficial to making the request information sent by the processor get a more timely response.

[0010] In some implementation manners, the at least two registers include a first register and a second register. The first processor writing first request information into the first interaction circuit includes: the first processor writing first request information into the first register. The first interaction circuit sending an interrupt signal to the second processor through the at least two registers when detecting that the first processor writes first request information into the first interaction circuit includes: the second register sending an interrupt signal to the second processor when detecting that the first processor writes first request information into the first register. The second processor executing processing corresponding to the first request information includes: the second processor accessing the first register to obtain the first request information and executing processing corresponding to the first request information.

[0011] Based on this implementation manner, an interaction circuit between the first processor and the second processor can be built with two registers. The interaction circuit has a simple structure, lower energy consumption, and a simple operation logic, which can improve the information interaction efficiency.

[0012] In some implementations, the first processor includes a plurality of processor cores, and each of the processor cores is connected to the second processor through a group of the first interaction circuits; the first processor writing the first request information into the first interaction circuit includes: a first processor core in the first processor writing the first request information into the first interaction circuit connected to the first processor core; the first interaction circuit sending an interrupt signal to the second processor through the at least two registers when detecting that the first processor writes the first request information into the first interaction circuit, including: the first interaction circuit connected to the first processor core sending an interrupt signal to the second processor through at least two registers when detecting that the first processor core writes the first request information into this first interaction circuit; the second processor performing processing corresponding to the first request information, including: the second processor performing processing corresponding to the first request information on the first processor core.

[0013] Based on this implementation, each processor core of the first processor is connected to the second processor through a separate interaction circuit, which can avoid the communication blocking problem caused by multiple first processor cores preempting the interaction circuit. At the same time, the second processor can directly determine the first processor core that sends the request by distinguishing which interaction circuit the received interrupt signal comes from, eliminating the process of parsing the source of the request information, which is beneficial to improving the response efficiency to the request information.

[0014] In some implementations, the first request information includes low-power request information; the first processor writing the first request information into the first interaction circuit includes: the first processor writing the first request information into the first interaction circuit through a co-processor performance control interface.

[0015] Based on this implementation, the first processor sending the request information to the first interaction circuit through the co-processor performance control interface can bypass the forwarding and parsing processes of the intermediate layer of the computer system, improving the sending efficiency of the request information.

[0016] In some implementations, the microprocessor architecture is equipped with one or more of a general execution environment subsystem, a trusted execution environment subsystem, and a security element subsystem; wherein, the first processor is used to respond to access requests initiated by the general execution environment subsystem and / or the trusted execution environment subsystem, and the second processor is used to respond to access requests initiated by the security element subsystem.

[0017] Based on this implementation, by deploying execution environments with different security levels in the microprocessor architecture, it is possible to meet the operation of programs with various security levels, and at the same time ensure the security of the microprocessor architecture.

[0018] In some implementations, the microprocessor architecture further includes an input / output processor and at least one peripheral controller; the input / output processor serves as an intermediate medium when the first processor and / or the second processor interacts with the at least one peripheral controller.

[0019] Based on this implementation, setting an input / output processor in the microprocessor architecture to be responsible for executing the interaction tasks between the first processor and / or the second processor and the peripheral controller can reduce the burden and resource consumption of the first processor and / or the second processor.

[0020] In some implementations, the first processor and / or the second processor is electrically connected to the input / output processor through a second interaction circuit, and the second interaction circuit includes at least two registers; when the second interaction circuit detects that the first processor and / or the second processor writes second request information into the second interaction circuit, it sends an interrupt signal to the input / output processor through at least two registers; the interrupt signal is used to trigger the input / output processor to execute processing corresponding to the second request information.

[0021] Based on this implementation, the interaction efficiency between the first processor and / or the second processor and the input / output processor can be improved.

[0022] In some implementations, the input / output processor includes at least one dedicated processor core; the processor core included in the input / output processor serves as an intermediate medium when the first processor and / or the second processor interacts with the at least one peripheral controller.

[0023] Based on this implementation, setting a dedicated processor core in the input / output processor to execute the interaction tasks between the first processor and / or the second processor and at least one peripheral controller can improve the interaction efficiency and ensure the interaction stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0025] Figures 1-7 Schematic diagrams of partial structures of various microprocessor architectures provided by the embodiments of the present application.

[0026] Figure 8 Flow chart of the information interaction method provided by the embodiment of the present application. Detailed implementation manners

[0027] The technical solution of the embodiment of the present application is applicable to the interaction scenarios between different processors in a microprocessor architecture. For example, it can be applied to the application scenarios where request information is sent between different processors to achieve the call and function control between different processors. By adopting the technical solution of the embodiment of the present application, the request interaction efficiency between processors in the microprocessor architecture can be improved, so that the requests between processors can be processed and responded more timely.

[0028] As an example, Figure 1 FIG. shows a partial structural schematic diagram of a microprocessor architecture. In this microprocessor architecture, there are multiple processors, namely the first processor, the second processor, ···, the Nth processor, where N is a positive integer.

[0029] In some embodiments, Figure 1 The multiple processors shown respectively include one or more processor cores, so that Figure 1 the multiple processors shown respectively correspond to different processor cores. For example, the first processor, the second processor, ···, the Nth processor respectively correspond to the first processor core, the second processor core, ···, the Nth processor core. Thus, this microprocessor architecture constitutes a system-on-chip including multiple processor cores. At this time, the multiple processor cores can be interconnected through a network-on-chip.

[0030] In other embodiments, Figure 1 The multiple processors shown can be respectively different types of processors. For example, they can be CPUs, GPUs, NPUs, etc. In this case, this microprocessor architecture constitutes a system-on-chip including multiple different types of processors. At this time, the multiple different types of processors can be interconnected through a system bus.

[0031] The embodiment of the present application uses Figure 1 the microprocessor architecture shown to represent a microprocessor architecture including multiple processor cores and a microprocessor architecture including multiple types of processors, and optimizes and improves the information interaction method between different processor cores or different processors in the above microprocessor architecture, so as to improve the information interaction efficiency between different processor cores or different processors. In the subsequent embodiments, the similar microprocessor architectures listed also represent different processor cores or different types of processors through different processors.

[0032] In Figure 1In the microprocessor architecture shown, a memory is also included. The memory can be an internal memory such as DDR or an external memory such as SSD. In the internal memory, a cache, shared memory, etc. can be further included. Also, in this microprocessor architecture, a peripheral controller can be included. The peripheral controller is connected to external devices to achieve control of the external devices. In some embodiments, the above-mentioned peripheral controller can also be arranged outside the microprocessor architecture and connected through the on-chip network or system bus of the microprocessor architecture. The numbers of the above-mentioned memory and peripheral controller can be one or more respectively. Both the memory and the peripheral controller are connected to each processor through the on-chip network or system bus, so as to achieve the communication connection among various parts inside the microprocessor architecture.

[0033] In Figure 1 In the microprocessor architecture shown, the call between different processors is usually achieved by means of shared memory and information processing unit.

[0034] For example, in Figure 2 the microprocessor architecture shown, the application processor, system control processor, and DDR (Double Data Rate Synchronous Dynamic Random Access Memory) are interconnected through the on-chip network.

[0035] The application processor is mainly used to run application programs and operating systems, while the system control processor is mainly responsible for the control and management of affairs such as clock reset, temperature, and power consumption. During the system operation, the application processor needs to call the system control processor to achieve system control, such as achieving processor frequency modulation, power consumption control, etc.

[0036] Currently, in the system control processor, the MHU (Message Handing Unit) plus Sharedmemory (shared memory) method is used to form the interaction link between the application processor and the system control processor. The above-mentioned MHU can be a separately set hardware processing unit or a processor core, and the above-mentioned shared memory can be a memory area shared by the system control processor and the application processor divided from the local memory of the system control processor or the application processor. In some other embodiments, the above-mentioned MHU and shared memory can be arranged inside the application processor and connected to the system control processor. Or, the above-mentioned MHU and shared memory can also be dispersedly arranged in the system control processor and the application processor.

[0037] Based on the above information processing unit and shared memory, when the application processor sends a control request (such as a frequency modulation request or a power consumption request) to the system control processor, the application processor first writes the request protocol content into the shared memory, and then configures the information processing unit to send the request to the system control processor. After receiving the request, the system control processor checks the protocol content in the shared memory and then makes a corresponding service response after analysis.

[0038] The above interaction scheme is relatively cumbersome, and for request information that needs to be executed quickly, such as a fast frequency modulation request or a power consumption request, timely response cannot be obtained.

[0039] In view of the above technical problems, an embodiment of the present application proposes a microprocessor architecture. In this microprocessor architecture, an interaction circuit that can be set between different processors is innovatively proposed. Through this interaction circuit, the information interaction efficiency between processors can be improved, thereby improving the request response speed between processors.

[0040] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0041] Figure 3 An exemplary implementation manner of the microprocessor architecture proposed in the embodiment of the present application is shown.

[0042] See Figure 3 , in the microprocessor architecture proposed in the embodiment of the present application, it includes a first processor and a second processor. Among them, the security level of the second processor is higher than that of the first processor. Based on the characteristic of the high security level of the second processor, programs with higher security level requirements can be run on the second processor, and a security measurement service module can be installed in the second processor to perform security measurement on other modules. In practical applications, the second processor can be a security element SE, which can be used to perform security control on the microprocessor architecture.

[0043] In some embodiments, the second processor is a system control processor, and the first processor is an application processor. The above system control processor serves as the clock reset control center of the entire microprocessor architecture, mainly providing working clocks for each module of the microprocessor architecture, as well as clock frequency adjustment, and controlling the reset of each module, so that the chip can complete initialization normally after power-on.

[0044] In the above microprocessor architecture, the first processor and the second processor are electrically connected through a first interaction circuit, and at least two registers are included in the first interaction circuit.

[0045] The above-mentioned at least two registers can be the same registers or different registers. These registers respectively implement different functions, so that the first interaction circuit can implement the information interaction function between different processors. For example, at least one of the registers can be used to store interaction information or interaction data, and at least one of the other registers can be used to send and receive signals, so that multiple different registers cooperate to achieve the transmission of data and signals, that is, to achieve the information interaction between different processors.

[0046] In some embodiments, the above-mentioned first interaction circuit can be arranged outside the first processor and the second processor and between the first processor and the second processor, or can also be arranged inside the first processor or the second processor and be electrically connected to the other party.

[0047] Based on the above-mentioned first interaction circuit, when the first processor needs to send a request message to the second processor, the first processor writes the request message into the first interaction circuit, specifically, writes the data content of the request message into the register for storing information and data among the at least two registers of the first interaction circuit.

[0048] The above-mentioned first interaction circuit detects in real time the operation of the first processor writing data into the first interaction circuit. When it detects that the first processor writes the first request message into the first interaction circuit, the first interaction circuit sends an interrupt signal to the second processor through the at least two registers it includes.

[0049] The above-mentioned first request message is used to represent any request message written by the first processor into the first interaction circuit.

[0050] In some embodiments, the register for sending and receiving signals in the first interaction circuit monitors the state of the register for storing data in real time. In this embodiment, based on Figure 3 the shown system architecture, one end of the first interaction circuit connected to the first processor is the input end, and one end of the first interaction circuit connected to the second processor is the output end. At this time, only the first processor may write data into the register for storing data in the first interaction circuit. Therefore, when the register for sending and receiving signals in the first interaction circuit monitors that the state of the register for storing data has changed, it can be determined that the first processor has written data into the register for storing data, that is, it can be determined that the first processor has written the first request message into the first interaction circuit. At this time, the register for sending and receiving signals sends an interrupt signal to the second processor.

[0051] In some embodiments, the register for storing data in the first interaction circuit is provided with a status flag. When the register does not store data, its status flag is in the first state, and when the register stores data, its status flag is in the second state. Therefore, by monitoring the change in the status of the status flag of the register for storing data, it can be determined whether the first processor writes data to the register. When the register for transmitting and receiving signals detects that the status flag of the register for storing data changes from the first state to the second state, it can be determined that the first processor writes a request message to the first interaction circuit.

[0052] In the embodiment of the present application, the interrupt signal sent by the first interaction circuit to the second processor is used to trigger the second processor to execute processing corresponding to the first request message. That is, when the second processor receives the interrupt signal sent by the first interaction circuit, it executes processing corresponding to the first request message.

[0053] In some embodiments, a one-to-one correspondence between the request message and the interrupt signal can be set. Based on this correspondence, when the second processor receives the interrupt signal, it can quickly determine the request message corresponding to the interrupt signal, and then execute the processing corresponding to the request message.

[0054] For example, the above-mentioned first request message can be a low-power request. The first processor writes the first request message into the first interaction circuit, indicating that the first processor requests to switch the first processor to the low-power operating mode. At this time, when the first interaction circuit detects that the first processor writes the above-mentioned first request message into the first interaction circuit, it sends an interrupt signal to the second processor. When the second processor receives the interrupt signal, it can determine that the first processor issues a low-power request. At this time, the second processor controls the first processor to switch to the low-power operating mode.

[0055] As can be seen from the above introduction, the microprocessor architecture proposed in the embodiment of the present application sets an interaction circuit between the first processor and the second processor, and sets registers in the interaction circuit. When the first processor needs to send a request message to the second processor, it can directly write the request message into the interaction circuit. The interaction circuit sends an interrupt signal to the second processor to trigger the second processor to execute processing corresponding to the request message. The above-mentioned microprocessor architecture makes the interaction between different processors more concise and efficient by setting an interaction circuit between different processors, which is beneficial to making the request message sent by the processor get a more timely response.

[0056] In some embodiments, referring to Figure 4 as shown, the first interaction circuit in this embodiment includes two registers, namely a first register and a second register.

[0057] Among them, the above-mentioned first register is used to store the data written by the first processor to the first interaction circuit, and the second register is used to detect the operation of the first processor writing data to the first register, and send an interrupt signal to the second processor when it detects that the first processor writes data to the first register.

[0058] Based on the above-mentioned first register and second register, when the first processor sends a first request message to the second processor, the first processor writes the first request message to the first register of the first interaction circuit.

[0059] In some embodiments, the above-mentioned first request message may be data representing a specific request. For example, the number "1" represents a clock shutdown request, and the number "2" represents a power shutdown request. Then the first processor writes the first request message to the first register, specifically, it may write the data representing the first request message to the first register.

[0060] The second register in the first interaction circuit continuously detects the write operation of the first processor on the first register. When it detects that the first processor writes the first request message to the first register, for example, when it detects that the status flag bit of the first register changes, the second register sends an interrupt signal to the second processor.

[0061] After receiving the interrupt signal sent by the second register, the second processor accesses the first register, reads the first request message from the first register, and performs processing corresponding to the first request message.

[0062] In some embodiments, the second processor reads the data written by the first processor from the first register, then parses the read data to determine the corresponding processing method, and finally performs processing according to the processing method corresponding to the read data. For example, assuming that the second processor reads the number "1" from the first register, the second processor performs clock shutdown processing. Assuming that the second processor reads the number "2" from the first register, the second processor performs power shutdown processing.

[0063] In the above embodiment, the first interaction circuit collaborates through two registers to quickly issue the request message. In this solution, the structure of the first interaction circuit is simple, the power consumption is lower, and the request sending efficiency is higher.

[0064] In some other embodiments, the first request message written by the first processor to the first interaction circuit may be a low-power request message, that is, a request message for requesting to reduce the power consumption of the first processor.

[0065] In this case, the first processor writes the first request information into the first interaction circuit through the Collaborative Processor Performance Control (CPPC) interface of the operating system.

[0066] Among them, in the low-power protocol specification of the computer system, there is a software interface called CPPC. This CPPC interface allows the operating system to directly operate on the underlying registers by skipping the UEFI interface and the underlying firmware. Since the intermediate layer's forwarding of requests is omitted, the request information can reach the registers faster.

[0067] Therefore, writing the low-power request into the register in the first interaction circuit through the CPPC interface can improve the sending efficiency of the low-power request, and further improve the low-power control efficiency.

[0068] In some other embodiments, as shown in Figure 5 the first processor includes multiple processor cores, and each processor core is connected to the second processor through a group of first interaction circuits respectively.

[0069] Among them, the structure of each group of the above first interaction circuits can respectively adopt the Figure 4 first interaction circuit structure shown in

[0070] Based on the Figure 5 system architecture shown, each processor core in the first processor is connected to the second processor through a separate first interaction circuit. For example, the i-th processor core in the first processor is connected to the input / output processing through the m-th first interaction circuit, where the values of i and m are respectively 1 to n, and n is a positive integer. This can enable each processor core in the first processor to communicate with the second processor one-on-one without interference, avoiding the problem of communication blocking.

[0071] Based on the Figure 5 system architecture shown, any processor core in the first processor can send request information to the second processor through the first interaction circuit connected to it. For example, the first processor core in the first processor can write the first request information into the first interaction circuit connected to this first processor core.

[0072] When the first interaction circuit connected to the first processor core detects that the first processor core writes first request information to the first interaction circuit, it sends an interrupt signal to the second processor through at least two registers in the first interaction circuit. For example, the first processor core writes the first request information to the first register of the first interaction circuit connected to it. When the second register in the first interaction circuit detects that the first processor core writes data to the first register, it sends an interrupt signal to the second processor.

[0073] When the second processor receives the interrupt signal sent by the first interaction circuit connected to the first processor core, it performs processing corresponding to the first request information on the first processor core.

[0074] That is, when the second processor receives the interrupt signal sent by the second register in the first interaction circuit connected to the first processor core, it reads the first request information written by the first processor core from the first register of the first interaction circuit, and then performs processing corresponding to the first request information on the first processor core. For example, assuming that the first request information is low-power request information, the second processor adjusts the first processor core to the low-power operating mode.

[0075] Based on Figure 5 the system architecture shown, the second processor receives request information from different processor cores of the first processor through different interaction circuits respectively. That is, by distinguishing the interaction circuit that sends the interrupt signal to the second processor, the second processor can determine which processor core of the first processor sends the request information to the second processor, and then can directly respond to the request of the processing core. The above processing process omits the operation of the second processor to determine which first processor core the request information comes from by parsing the request information, and can further improve the response efficiency of the second processor to the request information sent by the first processor.

[0076] In some other embodiments, in the above microprocessor architecture, one or more of a Rich Execution Environment (REE) subsystem, a Trusted Execution Environment (TEE) subsystem, and a Secure Element (SE) subsystem are also carried.

[0077] Among them, the general execution environment subsystem REE may include a general operating system running on a processor, on which application programs are installed. The application programs running in the REE may be called general applications (Client Application, CA), which have low security and are vulnerable to attacks. Although many security measures such as device access control, device data encryption mechanism, isolation mechanism during application runtime, and access control based on permission verification are taken in the REE, the security of important data in the application still cannot be guaranteed.

[0078] The trusted execution environment subsystem TEE may be an independent operating environment running outside the general operating system, which can provide trusted services to the REE and is isolated from the REE. One or more trusted applications (TEE Application, TA) can be executed in the TEE. Through the trusted applications, a trustworthy operating environment is provided for the general execution environment subsystem REE. Then, through the protection of confidentiality and integrity and the control of data access permissions, end-to-end security is ensured. In addition, the TEE can run in parallel with the REE, and for example, the TEE interacts with the REE through a secure application programming interface (Application Programming Interface, API).

[0079] The TEE provides a higher security level operating environment than the REE, but it cannot provide a secure key storage and key operating environment at the hardware isolation level. Generally, the TEE can provide many application programming interfaces for the REE to call the resources of the TEE. The more application programming interfaces provided by the TEE for services, the greater the risk faced by the TEE. It is difficult to ensure that there are no security hazards in the application programming interfaces themselves, such as security vulnerabilities, which may lead to security risks for resources such as keys in the TEE. Further, multiple trusted applications TA will run in the TEE. The trusted applications TA completely rely on the isolation mechanism provided by the TEE operating system without hardware-level isolation. This means that if there are security vulnerabilities in the trusted applications TA themselves or the trusted applications TA actively access the keys or root keys corresponding to other trusted applications TA, it will also lead to great security risks for sensitive resources such as keys.

[0080] The secure element subsystem is a software system running on the secure element (SE). It provides security services based on the hardware of the secure element SE. Since the secure element subsystem is carried on an independent hardware environment, it is easy to establish physical protection and implement security guarantees, thereby improving the security strength of the secure element subsystem to serve security systems with higher security requirements. As an example, the TEE can transfer security service requests to the secure element subsystem to request the provision of corresponding security services and make responses based on the requests. For example, the security service can be a request for the secure element subsystem to perform services related to cryptographic operations, etc.

[0081] In some embodiments, based on the above microprocessor architecture, the regular execution environment subsystem (REE) and the trusted execution environment subsystem (TEE) can be carried on the first processor, and the secure element subsystem can be carried on the second processor. This microprocessor architecture enables the secure element subsystem to have the ability to independently process tasks and respond to requests, making the task execution of the secure element subsystem completely independent and not affected by the execution environments of other subsystems, which is beneficial to improving the security of the microprocessor architecture and also beneficial to enhancing the task execution efficiency of the secure element subsystem. Further, this implementation method can reduce the hardware resource consumption of the processor and improve the processing performance of the processor.

[0082] In the above microprocessor architecture, the first processor is used to respond to access requests initiated by the regular execution environment subsystem (REE) and / or the trusted execution environment subsystem (TEE). For example, in response to access requests initiated by the regular execution environment subsystem (REE) and / or the trusted execution environment subsystem (TEE) for any peripheral controller, it sends an access request to the peripheral controller; the second processor is used to respond to access requests initiated by the secure element subsystem. For example, in response to an access request initiated by the secure element subsystem for any peripheral controller, it sends a corresponding access request to the peripheral controller.

[0083] Based on the above microprocessor architecture, by deploying execution environments with different security levels in the microprocessor architecture, it is possible to meet the operation of programs with various security levels while ensuring the security of the microprocessor architecture.

[0084] In some other embodiments, as shown in Figure 6 the microprocessor architecture provided in this embodiment further includes an input / output processor (IOP) and at least one peripheral controller.

[0085] The first processor and the second processor are respectively communicatively connected to the input / output processor through the network-on-chip, and the input / output processor is respectively connected to at least one peripheral controller.

[0086] The input / output processor serves as an intermediate medium when the first processor and / or the second processor interact with at least one peripheral controller.

[0087] In some other embodiments, the input / output processor includes at least one dedicated processor core, which serves as an intermediate medium when the first processor and / or the second processor interact with at least one peripheral controller.

[0088] The input / output processor is a hardware structure specifically provided in the microprocessor architecture of the embodiments of the present application for performing data communication operations between the first processor and / or the second processor and each peripheral controller. The input / output processor includes at least one processor core dedicated to performing data communication operations between the first processor and / or the second processor and the peripheral controller.

[0089] In the embodiments of the present application, the above-mentioned processor core is specifically a RISC-V (Reduced Instruction Set Computer - Five, the fifth generation of reduced instruction set computer) core, that is, a processor core with the RISC-V instruction architecture, mainly completing instruction access for modules with low real-time requirements such as low-speed peripherals.

[0090] The above-mentioned at least one peripheral controller may include any external device connected to the microprocessor architecture or the controller corresponding to the external device interface, such as a UART (Universal Asynchronous Receiver / Transmitter) controller, an I2C (Inter-Integrated Circuit) controller, an SPI (Serial Peripheral Interface) controller, an SD (Secure Digital) controller, a GMAC controller (Gigabit Media Access Controller), and so on.

[0091] The above-mentioned input / output processor serves as an intermediate medium between the first processor and / or the second processor and each peripheral controller. The first processor and / or the second processor only need to be connected to the input / output processor, and the input / output processor is respectively connected to each peripheral controller. In this way, there is no need for the first processor and / or the second processor to separately establish communication links with each peripheral controller.

[0092] Meanwhile, based on the above settings of the input / output processor, in the interaction scenario between the first processor and / or the second processor and the peripheral controller, the input / output processor can replace the first processor and / or the second processor to perform at least part of the interaction operations with the peripheral controller, thereby saving the processing resources of the first processor and / or the second processor.

[0093] For example, when the first processor and / or the second processor needs to access any target peripheral controller among various peripheral controllers, it only needs to send an access request for the target peripheral controller to the input / output processor. The processor core in the input / output processor executes the access to the target peripheral controller according to the access request sent by the first processor and / or the second processor. For example, the access request is sent to the target peripheral controller, and when receiving the access result returned by the target peripheral controller for the above access request, the access result returned by the target peripheral controller is fed back to the first processor and / or the second processor. In the above process, the first processor and / or the second processor only needs to send an access request for the target peripheral controller to the input / output processor. At this time, the first processor and / or the second processor can perform other operations and does not need to perform subsequent interaction operations with the target peripheral controller. Instead, the input / output processor issues the access request to perform the actual access to the peripheral controller and feeds back the access result to the first processor and / or the second processor. It can be seen that the above processing process greatly reduces the resource consumption when the first processor and / or the second processor interacts with the peripheral controller.

[0094] When any one of the target peripheral controllers in each peripheral controller needs to send data to the first processor and / or the second processor, it first sends a data transfer request to the input / output processor. The data transfer request can be a set request or signal, such as an interrupt request or interrupt signal. After receiving the data transfer request, the processor core in the input / output processor accesses the target peripheral controller to obtain the data to be transferred and stores the data to be transferred in the input / output processor. Then, the processor core in the input / output processor sends a notification message to the first processor and / or the second processor, notifying the first processor and / or the second processor to read the above-mentioned data to be transferred from the input / output processor. When the first processor and / or the second processor receives the notification message, it can read the data to be transferred from the input / output processor at an opportune time. In the above data upstream interaction scenario, the input / output processor performs the operations of receiving the data transfer request sent by the target peripheral controller and obtaining the data to be transferred from the target peripheral controller. For the first processor and / or the second processor, it only needs to read the data from the input / output processor when receiving the notification message sent by the processor core in the input / output processor. This process reduces the interference with the work of the first processor and / or the second processor compared to the direct interaction between the peripheral controller and the first processor and / or the second processor, which is beneficial to reducing the work pressure of the first processor and / or the second processor.

[0095] In some embodiments, at least one peripheral controller in the above microprocessor architecture can be arranged outside the input / output processor. At this time, each peripheral controller is communicatively connected to the input / output processor through the peripheral controller interface of the input / output processor. The above arrangement of the peripheral controller can more conveniently delete or add the peripheral controllers connected to the input / output processor, so as to flexibly adjust whether the peripheral controller directly communicates with the first processor and / or the second processor, or communicates with the first processor and / or the second processor through the input / output processor.

[0096] In some other embodiments, one or more of the at least one peripheral controller in the above microprocessor architecture may be disposed inside the input / output processor. The peripheral controller disposed inside the input / output processor may be connected to other parts of the input / output processor through a communication link inside the input / output processor. The above-described manner of disposing the peripheral controller can, on the one hand, improve the security of the peripheral controller. That is, the first processor and / or the second processor must interact with the peripheral controller through the input / output processing, rather than directly interacting with the peripheral controller. In this way, the input / output processor can ensure the security of the peripheral controller. For example, the input / output processor can perform security verification and security control on the interaction process between the first processor and / or the second processor and the peripheral controller, etc. On the other hand, disposing the peripheral controller inside the input / output processor can facilitate operations such as modification, adjustment, and optimization of the peripheral controller inside the input / output processor, enabling the manufacturer of the input / output processor to completely privatize the peripheral controller without the need to externally describe any information about the peripheral controller.

[0097] Moreover, in other embodiments, the above at least one peripheral controller may also be disposed outside the microprocessor architecture and connected to the input / output processor through a peripheral port of the unprocessed architecture. The present application does not limit the connection manner or the setting position of the above at least one peripheral controller to the microprocessor architecture.

[0098] In the above embodiments, since the first processor and / or the second processor no longer perform actual interaction operations with at least some of the peripheral controllers (low-speed peripheral controllers), there is no need to install drivers for these peripheral controllers in the first processor and / or the second processor, and there is no operation of upgrading or updating the drivers of these peripheral controllers, thereby further reducing the burden on the first processor and / or the second processor and reducing resource consumption.

[0099] Based on the setting of the input / output processor, in some other embodiments, the first processor and / or the second processor are electrically connected to the input / output processor through a second interaction circuit, and the structure of the second interaction circuit may be the same as the structure of the first interaction circuit described in any of the above embodiments.

[0100] In some embodiments, it may be that the first processor is electrically connected to the input / output processor through the second interaction circuit, or it may be that the second processor is electrically connected to the input / output processor through the second interaction circuit, or as Figure 7 shown, the first processor and the second processor are respectively electrically connected to the input / output processor through a group of second interaction circuits.

[0101] In some embodiments, the above-mentioned second interaction circuit may be disposed outside the first processor and / or the second processor and the input / output processor, and located between the first processor and / or the second processor and the input / output processor. Alternatively, the above-mentioned second interaction circuit may also be disposed inside the first processor and / or the second processor, or disposed inside the input / output processor, and electrically connected to each other, so as to realize the communication connection between the first processor and / or the second processor and the input / output processor.

[0102] The above-mentioned second interaction circuit has the same structure as the first interaction circuit described in the above embodiments, and realizes the fast request information interaction function through the same processing logic.

[0103] Based on the setting of the above-mentioned second interaction circuit, when the first processor and / or the second processor needs to send request information to the input / output processor, the first processor and / or the second processor writes the request information into the second interaction circuit, specifically, writes the specific data content of the request information into the register for storing information and data in at least two registers of the second interaction circuit.

[0104] The above-mentioned second interaction circuit continuously detects the operation of the first processor and / or the second processor writing data into the second interaction circuit. When it detects that the first processor and / or the second processor writes the second request information into the second interaction circuit, the second interaction circuit sends an interrupt signal to the input / output processor through at least two registers it includes.

[0105] The above-mentioned second request information is used to represent any request information written by the first processor and / or the second processor into the second interaction circuit. In this embodiment, the above-mentioned second request information may be, for example, a control request, a data read / write request, etc.

[0106] In some embodiments, the register for receiving and transmitting signals in the second interaction circuit continuously monitors the state of the register for storing data. When the register for receiving and transmitting signals in the second interaction circuit monitors that the state of the register for storing data has changed, it can be determined that the first processor and / or the second processor has written data into the register for storing data, that is, it can be determined that the first processor and / or the second processor has written the second request information into the second interaction circuit. At this time, the register for receiving and transmitting signals sends an interrupt signal to the input / output processor.

[0107] In some embodiments, a status flag bit is set in the register for storing data in the second interaction circuit. When the register does not store data, its status flag bit is in the first state, and when the register stores data, its status flag bit is in the second state. Therefore, by monitoring the status change of the status flag bit of the register for storing data, it can be determined whether the first processor and / or the second processor writes data to the register. When the register for receiving and transmitting signals detects that the status flag bit of the register for storing data changes from the first state to the second state, it can be determined that the first processor and / or the second processor writes request information to the second interaction circuit.

[0108] In the embodiments of the present application, the interrupt signal sent by the second interaction circuit to the input / output processor is used to trigger the input / output processor to execute processing corresponding to the second request information. That is, when the input / output processor receives the interrupt signal sent by the second interaction circuit, it executes processing corresponding to the second request information.

[0109] For the specific processing procedure of the above-mentioned second interaction circuit, reference can also be made to the specific processing procedure of the first interaction circuit in the above embodiments.

[0110] In other embodiments, the first processor and / or the second processor may include multiple processor cores. On this basis, in some embodiments, each processor core included in the first processor and / or the second processor is electrically connected to the input / output processor through a set of the above-mentioned second interaction circuits.

[0111] Based on this system architecture, each processor core included in the first processor and / or the second processor communicates with the input / output processor through an independent second interaction circuit, thereby improving communication efficiency and avoiding communication blocking problems.

[0112] For the specific processing procedure of each processor core included in the first processor and / or the second processor to interact with the input / output processor through the second interaction circuit connected thereto, reference can be made to the specific processing procedure of each processor core of the first processor interacting with the second processor through the first interaction circuit connected thereto as introduced in the above embodiments, which will not be elaborated here.

[0113] Based on the above microprocessor architecture, another embodiment of the present application also proposes an information interaction method. Refer to Figure 8 As shown, the method includes:

[0114] S101. When the first interaction circuit detects that the first processor writes first request information into the first interaction circuit, it sends an interrupt signal to the second processor through the at least two registers; the interrupt signal is used to trigger the second processor to execute processing corresponding to the first request information.

[0115] In some embodiments, the at least two registers include a first register and a second register;

[0116] The first processor writing first request information into the first interaction circuit includes: the first processor writing first request information into the first register;

[0117] When the first interaction circuit detects that the first processor writes first request information into the first interaction circuit and sends an interrupt signal to the second processor through the at least two registers, it includes:

[0118] When the second register detects that the first processor writes first request information into the first register, it sends an interrupt signal to the second processor;

[0119] The second processor executing processing corresponding to the first request information includes:

[0120] The second processor accesses the first register to obtain the first request information and executes processing corresponding to the first request information.

[0121] In some embodiments, the first processor includes a plurality of processor cores, and each processor core is respectively connected to the second processor through a group of the first interaction circuits;

[0122] The first processor writing first request information into the first interaction circuit includes: the first processor core in the first processor writing first request information into the first interaction circuit connected to the first processor core;

[0123] When the first interaction circuit detects that the first processor writes first request information into the first interaction circuit and sends an interrupt signal to the second processor through the at least two registers, it includes:

[0124] When the first interaction circuit connected to the first processor core detects that the first processor core writes first request information into this first interaction circuit, it sends an interrupt signal to the second processor through at least two registers;

[0125] The second processor executing processing corresponding to the first request information includes:

[0126] The second processor performs processing corresponding to the first request information on the first processor core.

[0127] In some embodiments, the first request information includes low-power request information;

[0128] The first processor writes the first request information to the first interaction circuit, including:

[0129] The first processor writes the first request information to the first interaction circuit through a coprocessor performance control interface.

[0130] In some embodiments, the microprocessor architecture is equipped with one or more of a general execution environment subsystem, a trusted execution environment subsystem, and a security element subsystem;

[0131] Among them, the first processor is used to respond to access requests initiated by the general execution environment subsystem and / or the trusted execution environment subsystem, and the second processor is used to respond to access requests initiated by the security element subsystem.

[0132] In some embodiments, the microprocessor architecture further includes an input / output processor and at least one peripheral controller;

[0133] The input / output processor serves as an intermediate medium when the first processor and / or the second processor interact with the at least one peripheral controller.

[0134] In some embodiments, the first processor and / or the second processor is electrically connected to the input / output processor through a second interaction circuit, and the second interaction circuit includes at least two registers;

[0135] When the second interaction circuit detects that the first processor and / or the second processor writes second request information to the second interaction circuit, it sends an interrupt signal to the input / output processor through at least two registers; the interrupt signal is used to trigger the input / output processor to perform processing corresponding to the second request information.

[0136] In some embodiments, the input / output processor includes at least one dedicated processor core; the processor core included in the input / output processor serves as an intermediate medium when the first processor and / or the second processor interact with the at least one peripheral controller.

[0137] The information interaction method provided in this embodiment belongs to the same inventive concept as the microprocessor architecture provided in the foregoing embodiments of the present application. Each processing step of this information interaction method realizes its respective function through each part of the microprocessor architecture provided in the foregoing embodiments. For the technical details of this information interaction method not described in detail in this embodiment, reference may be made to the specific processing content of the information interaction process implemented by the microprocessor architecture provided in the foregoing embodiments of the present application, and details will not be elaborated here.

[0138] Another embodiment of the present application further proposes a computer device, which includes the microprocessor architecture described in any of the foregoing embodiments, or the computer device is configured to implement the information interaction method described in any of the foregoing embodiments.

[0139] The computer device may specifically be a personal computer, a server, a smart device, a smart terminal, a wearable device, etc.

[0140] For the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present application is not limited by the described action sequence, because according to the present application, certain steps may be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present application.

[0141] It should be noted that the embodiments in this specification are all described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments may be referred to each other. For device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts may refer to the partial description of the method embodiments.

[0142] The steps in the methods of the embodiments of the present application may be adjusted, combined, and deleted according to actual needs, and the technical features recorded in each embodiment may be replaced or combined.

[0143] The modules and sub-modules in the devices and terminals in the embodiments of the present application may be combined, divided, and deleted according to actual needs.

[0144] In several embodiments provided by this application, it should be understood that the disclosed terminals, devices, and methods can be implemented in other ways. For example, the terminal embodiments described above are merely illustrative. For example, the division of modules or sub-modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple sub-modules or modules can be combined or integrated into another module, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling, direct coupling, or communication connection between each other can be an indirect coupling or communication connection through some interfaces, devices, or modules, and can be in electrical, mechanical, or other forms.

[0145] The modules or sub-modules described as separate components may or may not be physically separated. The components as modules or sub-modules may or may not be physical modules or sub-modules, that is, they can be located in one place, or can be distributed to multiple network modules or sub-modules. Some or all of the modules or sub-modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0146] In addition, in each embodiment of this application, each functional module or sub-module can be integrated in a processing module, or each module or sub-module can exist physically alone, or two or more modules or sub-modules can be integrated in one module. The above-mentioned integrated modules or sub-modules can be implemented in the form of hardware or in the form of software functional modules or sub-modules.

[0147] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0148] The steps of the methods or algorithms described in combination with the embodiments disclosed in this article can be directly implemented by hardware, software units executed by a processor, or a combination of the two. The software units can be placed in a random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0149] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0150] The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A microprocessor architecture, characterized in that: include: a first processor and a second processor; Wherein, the security level of the second processor is higher than that of the first processor, and the first processor and the second processor are electrically connected via a first interactive circuit, and the first interactive circuit includes at least two registers; When the first interactive circuit detects that the first processor writes the first request information into the first interactive circuit, the first interactive circuit sends an interrupt signal to the second processor through the at least two registers; the interrupt signal is used to trigger the second processor to perform processing corresponding to the first request information.

2. The microprocessor architecture according to claim 1, characterized in that: The at least two registers include a first register and a second register; The first processor writes the first request information into the first interactive circuit, including: the first processor writes the first request information into the first register; When the first interactive circuit detects that the first processor writes the first request information into the first interactive circuit, the first interactive circuit sends an interrupt signal to the second processor through the at least two registers, including: When the second register detects that the first processor writes the first request information into the first register, the second register sends an interrupt signal to the second processor; The second processor performs processing corresponding to the first request information, including: The second processor accesses the first register to obtain first request information, and performs processing corresponding to the first request information.

3. The microprocessor architecture according to claim 1, characterized in that: The first processor includes a plurality of processor cores, each of the processor cores is connected to the second processor via a group of the first interaction circuits; The first processor writes the first request information into the first interactive circuit, including: a first processor core in the first processor writes the first request information into a first interactive circuit connected to the first processor core; When the first interactive circuit detects that the first processor writes the first request information into the first interactive circuit, the first interactive circuit sends an interrupt signal to the second processor through the at least two registers, including: The first interactive circuit connected to the first processor core sends an interrupt signal to the second processor through at least two registers when detecting that the first processor core writes the first request information into the first interactive circuit; The second processor performs processing corresponding to the first request information, including: The second processor executes a process corresponding to the first request information on the first processor core.

4. The microprocessor architecture according to claim 1, characterized in that: The first request information includes low power consumption request information; The first processor writes the first request information into the first interaction circuit, including: The first processor writes the first request information into the first interaction circuit through the coprocessor performance control interface.

5. The microprocessor architecture according to claim 1, characterized in that: The microprocessor architecture is equipped with one or more of a common execution environment subsystem, a trusted execution environment subsystem, and a secure element subsystem; The first processor is used to respond to access requests initiated by the common execution environment subsystem and / or the trusted execution environment subsystem, and the second processor is used to respond to access requests initiated by the secure element subsystem.

6. The microprocessor architecture according to any one of claims 1 to 5, characterized in that: The microprocessor architecture also includes an input-output processor and at least one peripheral controller; The input-output processor serves as an intermediate medium when the first processor and / or the second processor interacts with the at least one peripheral controller.

7. The microprocessor architecture according to claim 6, characterized in that: The first processor and / or the second processor is electrically connected to the input-output processor via a second interactive circuit, wherein the second interactive circuit includes at least two registers; When the second interaction circuit detects that the first processor and / or the second processor writes second request information into the second interaction circuit, the second interaction circuit sends an interrupt signal to the input-output processor through at least two registers; the interrupt signal is used to trigger the input-output processor to perform processing corresponding to the second request information.

8. The microprocessor architecture according to claim 6, characterized in that: The input-output processor includes at least one dedicated processor core; the processor core included in the input-output processor serves as an intermediate medium when the first processor and / or the second processor interacts with the at least one peripheral controller.

9. An information interaction method, characterized in that: Applied to a microprocessor architecture, the microprocessor architecture includes a first processor and a second processor; wherein the security level of the second processor is higher than that of the first processor, and the first processor and the second processor are electrically connected via a first interactive circuit, and the first interactive circuit includes at least two registers; The method comprises: When the first interactive circuit detects that the first processor writes the first request information into the first interactive circuit, the first interactive circuit sends an interrupt signal to the second processor through the at least two registers; the interrupt signal is used to trigger the second processor to perform processing corresponding to the first request information.

10. A computer device, characterized in that: The computer device comprises a microprocessor architecture as claimed in any one of claims 1 to 8, or the computer device is configured to implement the information interaction method as claimed in claim 9.

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