Microprocessor architecture, information interaction method and computer equipment

Abstract

The invention provides a microprocessor architecture, an information interaction method and computer equipment, and the microprocessor architecture comprises a first processor, an input / output processor and at least one peripheral controller, the input / output processor is used as an intermediate medium when the first processor interacts with the at least one peripheral controller; the first processor is electrically connected with the input / output processor through a first interaction circuit, and the first interaction circuit comprises at least two registers; under the condition that the first interaction circuit detects that the first processor writes first request information into the first interaction circuit, the first interaction circuit sends an interrupt signal to the input / output processor through the at least two registers; the interrupt signal is used for triggering the input / output processor to execute processing corresponding to the first request information. According to the microprocessor architecture, the interaction efficiency between the processors can be improved, and then the response efficiency of request information between the processors is improved.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a microprocessor architecture, an information interaction method, and a computer device. Background Art

[0002] In a microprocessor architecture, different processors are usually used to execute different processing tasks. At this time, information interaction between different processors is involved to enable the invocation of different processors. For example, in a microprocessor architecture, an application processor is mainly used to run application programs and operating systems, while an input / output processor is mainly responsible for information interaction between the application processor and peripherals. In some cases, the application processor needs to invoke the input / output processor to implement system control functions.

[0003] Currently, the invocation between different processors is usually achieved by means of shared memory and an information processing unit. For example, the application processor first writes the request protocol content into the shared memory, and then configures the information processing unit to send a request to the input / output processor. After receiving the request, the input / output processor checks the protocol content in the shared memory and then makes a corresponding service response after analysis.

[0004] The above interaction scheme is relatively cumbersome, and request information that needs to be executed quickly cannot be responded to in a timely manner. Summary of the Invention

[0005] Based on the above technical problems, this application proposes a microprocessor architecture, an information interaction method, and a computer device, which can improve the interaction efficiency between processors, and further improve the response efficiency of request information between processors.

[0006] A first aspect of this application proposes a microprocessor architecture, including: a first processor, an input / output processor, and at least one peripheral controller; the input / output processor serves as an intermediate medium when the first processor interacts with the at least one peripheral controller; the first processor is electrically connected to the input / output processor through a first interaction circuit, and the first interaction circuit includes at least two registers; when the first interaction circuit detects that the first processor writes first request information into the first interaction circuit, the first interaction circuit sends an interrupt signal to the input / output processor through the at least two registers; the interrupt signal is used to trigger the input / output processor to execute processing corresponding to the first request information.

[0007] A second aspect of the present application proposes an information interaction method, which is applied to a microprocessor architecture. The microprocessor architecture includes a first processor, an input / output processor, and at least one peripheral controller; the input / output processor serves as an intermediate medium when the first processor interacts with the at least one peripheral controller; the first processor is electrically connected to the input / output processor through a first interaction circuit, and the first interaction circuit includes at least two registers; the method includes: when the first interaction circuit detects that the first processor writes first request information into the first interaction circuit, the first interaction circuit sends an interrupt signal to the input / output processor through the at least two registers; the interrupt signal is used to trigger the input / output processor to execute processing corresponding to the first request information.

[0008] A third aspect of the present application proposes a computer device, including the above-mentioned microprocessor architecture, or the computer device is configured to implement the above-mentioned information interaction method.

[0009] The microprocessor architecture proposed in the present application sets an interaction circuit between the first processor and the input / output processor, and sets at least two registers in the interaction circuit. When the first processor needs to send request information to the input / output processor, it can directly write the request information into the registers of the interaction circuit. At least two registers of the interaction circuit send an interrupt signal to the second processor, triggering the second processor to execute processing corresponding to the request information. The above-mentioned microprocessor architecture makes the interaction between different processors simpler and more efficient by setting an interaction circuit between different processors, which is conducive to making the request information sent by the processor get a more timely response.

[0010] In some implementation manners, the at least two registers include a first register and a second register; the first processor writing first request information into the first interaction circuit includes: the first processor writing first request information into the first register; the first interaction circuit sending an interrupt signal to the input / output processor through the at least two registers when detecting that the first processor writes first request information into the first interaction circuit includes: the second register sending an interrupt signal to the input / output processor when detecting that the first processor writes first request information into the first register; the input / output processor executing processing corresponding to the first request information includes: the input / output processor accessing the first register to obtain the first request information and executing processing corresponding to the first request information.

[0011] Based on this implementation manner, an interaction circuit between the first processor and the input / output processor can be built with two registers. The interaction circuit has a simple structure, lower energy consumption, and a simple operation logic, which can improve the information interaction efficiency.

[0012] In some implementations, the first processor includes a plurality of processor cores, and each of the processor cores is respectively connected to the input / output processor through a set of the first interaction circuits; the first processor writing first request information into the first interaction circuits includes: a first processor core in the first processor writing the first request information into a first interaction circuit connected to the first processor core; the first interaction circuit sending an interrupt signal to the input / output processor through the at least two registers when detecting that the first processor writes the first request information into the first interaction circuit, including: the first interaction circuit connected to the first processor core sending an interrupt signal to the input / output processor through at least two registers when detecting that the first processor core writes the first request information into the first interaction circuit; the input / output processor performing processing corresponding to the first request information, including: the input / output processor performing processing corresponding to the first request information on the first processor core.

[0013] Based on this implementation, each processor core of the first processor is connected to the input / output processor through a separate interaction circuit, which can avoid the communication blocking problem caused by multiple first processor cores preempting the interaction circuit. At the same time, the input / output processor can directly determine the first processor core that sends the request by distinguishing which interaction circuit the received interrupt signal comes from, eliminating the process of parsing the source of the request information, which is beneficial to improving the response efficiency to the request information.

[0014] In some implementations, the input / output processor includes at least one dedicated processor core, and the processor core included in the input / output processor serves as an intermediate medium when the first processor interacts with the at least one peripheral controller.

[0015] Based on this implementation, setting a dedicated processor core in the input / output processor to execute the interaction task between the first processor and the at least one peripheral controller can improve the interaction efficiency and ensure the interaction stability.

[0016] In some implementations, the first processor is electrically connected to the input / output processor through a first interaction circuit, including: the first processor being electrically connected to the processor core included in the input / output processor through a first interaction circuit.

[0017] Based on this implementation, the first processor is electrically connected to the processor core included in the input / output processor through the interaction circuit, which can improve the interaction efficiency between the first processor and the processor core included in the input / output processor.

[0018] In some implementations, the microprocessor architecture further includes a second processor, and the security level of the second processor is higher than that of the first processor; the second processor is electrically connected to the input / output processor through a second interaction circuit, and the second interaction circuit includes at least two registers; when the second interaction circuit detects that the second processor writes second request information into the second interaction circuit, the second interaction circuit sends an interrupt signal to the input / output processor through the at least two registers; the interrupt signal is used to trigger the input / output processor to execute processing corresponding to the second request information.

[0019] Based on this implementation, the second processor in the unprocessed architecture is also electrically connected to the input / output processor through an interaction circuit, so that the interaction efficiency between the second processor and the input / output processor can be improved through this interaction circuit.

[0020] In some implementations, the microprocessor architecture is equipped with one or more of a general execution environment subsystem, a trusted execution environment subsystem, and a security element subsystem; wherein, the first processor is used to respond to access requests initiated by the general execution environment subsystem and / or the trusted execution environment subsystem, and the second processor is used to respond to access requests initiated by the security element subsystem.

[0021] Based on this implementation, by deploying execution environments with different security levels in the microprocessor architecture, the operation of programs with various security levels can be satisfied, and at the same time, the security of the microprocessor architecture can be guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0023] Figures 1-7 Schematic diagrams of partial structures of various microprocessor architectures provided by the embodiments of the present application are respectively shown.

[0024] Figure 8 It is a schematic flowchart of the information interaction method provided by the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] The technical solution of the embodiment of the present application is applicable to the interaction scenario between different processors in a microprocessor architecture. For example, it can be applied to the application scenario of sending request information between different processors to achieve the call and function control between different processors. By adopting the technical solution of the embodiment of the present application, the request interaction efficiency between processors in the microprocessor architecture can be improved, so that the requests between processors can be processed and responded to more timely.

[0026] Figure 1 FIG. shows a partial structural schematic diagram of a microprocessor architecture, which includes a first processor, an input / output processor, and at least one peripheral controller.

[0027] Among them, the first processor and the input / output processor are interconnected through a network-on-chip or a system bus. At least one peripheral controller is connected to the input / output processor. In addition, in this microprocessor architecture, there is also a memory, which can be an internal memory such as DDR or an external memory such as SSD. In the internal memory, there can further be a cache, a shared memory, etc.

[0028] The above-mentioned first processor can specifically be an application processor, which is used to run application programs and operating systems.

[0029] The above-mentioned input / output processor, as an intermediate medium when the first processor interacts with at least one peripheral controller, is mainly used to execute the interaction tasks between the first processor and at least one peripheral controller.

[0030] The above-mentioned at least one peripheral controller can include any external device connected to the microprocessor architecture or the controller corresponding to the external device interface, such as a UART (Universal Asynchronous Receiver / Transmitter) controller, an I2C (Inter-Integrated Circuit) controller, an SPI (Serial Peripheral Interface) controller, an SD (Secure Digital) controller, a GMAC controller (Gigabit Media Access Controller), and so on.

[0031] The above-mentioned input / output processor serves as an intermediate medium between the first processor and each peripheral controller. The first processor only needs to be connected to the input / output processor, and the input / output processor is respectively connected to each peripheral controller. In this way, there is no need for the first processor to establish communication links with each peripheral controller separately.

[0032] Meanwhile, based on the above settings of the input / output processor, in the interaction scenario between the first processor and the peripheral controller, the input / output processor can replace the first processor to perform at least part of the interaction operations with the peripheral controller, thereby saving the processing resources of the first processor.

[0033] For example, when the first processor needs to access any target peripheral controller among various peripheral controllers, it only needs to send an access request for the target peripheral controller to the input / output processor. The input / output processor executes the access to the target peripheral controller according to the access request sent by the first processor. For example, the access request is sent to the target peripheral controller, and when the access result returned by the target peripheral controller for the above access request is received, the access result returned by the target peripheral controller is fed back to the first processor. In the above process, the first processor only needs to send the access request for the target peripheral controller to the input / output processor. At this time, the first processor can execute other operations and does not need to execute the subsequent interaction operations with the target peripheral controller. Instead, the input / output processor issues the access request to perform the actual access to the peripheral controller and feeds back the access result to the first processor. It can be seen that the above processing process greatly reduces the resource consumption when the first processor interacts with the peripheral controller.

[0034] When any target peripheral controller among various peripheral controllers needs to send data to the first processor, it first sends a data transmission request to the input / output processor. The data transmission request can be a set request or signal, such as an interrupt request or interrupt signal. After the processor core in the input / output processor receives the data transmission request, it accesses the target peripheral controller to obtain the data to be transmitted and stores the data to be transmitted in the input / output processor. Then, the processor core in the input / output processor sends a notification message to the first processor to notify the first processor to read the above data to be transmitted from the input / output processor. When the first processor receives the notification message, it can read the data to be transmitted from the input / output processor at an opportune time. In the above data upstream interaction scenario, the input / output processor executes the operations of receiving the data transmission request sent by the target peripheral controller and obtaining the data to be transmitted from the target peripheral controller. For the first processor, it only needs to read the data from the input / output processor when it receives the notification message sent by the processor core in the input / output processor. This process reduces the interference with the work of the first processor compared with the direct interaction between the peripheral controller and the first processor, which is beneficial to reducing the working pressure of the first processor.

[0035] In some embodiments, at least one peripheral controller in the above microprocessor architecture may be disposed outside the input / output processor. In this case, each peripheral controller is communicatively connected to the input / output processor through the peripheral controller interface of the input / output processor. The above setting manner of the peripheral controller can more conveniently delete or add the peripheral controllers connected to the input / output processor, so that the communication interaction between the peripheral controllers and the first processor can be flexibly adjusted, either directly or through the input / output processor.

[0036] In other embodiments, one or more of the at least one peripheral controller in the above microprocessor architecture may be disposed inside the input / output processor. The peripheral controller disposed inside the input / output processor may be connected to other parts of the input / output processor through the communication link inside the input / output processor. The above setting manner of the peripheral controller, on the one hand, can improve the security of the peripheral controller, that is, the first processor must interact with the peripheral controller through the input / output processor, rather than directly with the peripheral controller, so that the security of the peripheral controller can be ensured through the input / output processor, such as performing security verification and security control on the interaction process between the first processor and the peripheral controller by the input / output processor; on the other hand, disposing the peripheral controller inside the input / output processor can facilitate operations such as modification, adjustment, and optimization of the peripheral controller inside the input / output processor, enabling the manufacturer of the input / output processor to completely privatize the peripheral controller without the need to externally describe any information about the peripheral controller.

[0037] Moreover, in other embodiments, the above at least one peripheral controller may also be disposed outside the microprocessor architecture and connected to the input / output processor through the peripheral port of the unprocessed architecture. The present application does not limit the connection manner or setting position of the above at least one peripheral controller to the microprocessor architecture.

[0038] In the above embodiments, since the first processor no longer performs the actual interaction operations with at least some of the peripheral controllers (low-speed peripheral controllers), there is no need to install the drivers of these peripheral controllers in the first processor, and there is no operation of upgrading or updating the drivers of these peripheral controllers, thus further reducing the burden on the first processor and reducing resource consumption.

[0039] Currently, in Figure 1 the microprocessor architecture shown, the call between different processors is usually achieved by sharing memory and information processing units.

[0040] For example, in Figure 1In the microprocessor architecture shown, an interaction link between the first processor and the input / output processor is formed by using an MHU (Message Handling Unit) plus a shared memory. In some embodiments, the above-mentioned MHU and shared memory can be disposed inside the input / output processor and connected to the first processor. Or, in some other embodiments, the above-mentioned MHU and shared memory can be disposed inside the first processor and connected to the input / output processor. Or, the above-mentioned MHU and shared memory can also be dispersedly disposed in the input / output processor and the first processor. The above-mentioned MHU can be a separately provided hardware processing unit or a processor core, and the above-mentioned shared memory can be a memory area shared by the input / output processor and the first processor that is divided from the local memory of the input / output processor or the first processor.

[0041] Based on the above-mentioned information processing unit and shared memory, when the first processor sends a control request to the input / output processor, the first processor first writes the request protocol content into the shared memory, and then configures the information processing unit to send the request to the input / output processor. After receiving the request, the input / output processor checks the protocol content in the shared memory and then makes a corresponding service response after analysis.

[0042] The above-mentioned interaction scheme is relatively cumbersome, and for request information that needs to be executed quickly, timely response cannot be obtained.

[0043] In view of the above technical problems, an embodiment of the present application proposes a microprocessor architecture. In this microprocessor architecture, an interaction circuit is innovatively proposed to be provided between the first processor and the input / output processor. Through this interaction circuit, the information interaction efficiency between processors can be improved, thereby the request response speed between processors can be improved.

[0044] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0045] An embodiment of the present application proposes a microprocessor architecture, as shown in Figure 2 shown, this microprocessor architecture includes a first processor, an input / output processor, and at least one peripheral controller. The input / output processor serves as an intermediate medium when the first processor interacts with the at least one peripheral controller.

[0046] For the specific functions, structural forms, specific types, etc. of the above-mentioned first processor, input / output processor, and peripheral controller, reference can be made to the above-mentioned embodiments.

[0047] In Figure 2 In the microprocessor architecture shown, the first processor is electrically connected to the input / output processor through a first interaction circuit, and the first interaction circuit includes at least two registers.

[0048] The above-mentioned at least two registers can be the same registers or different registers. These registers respectively implement different functions, so that the first interaction circuit can implement the information interaction function. For example, at least one of the registers can be used to store interaction information or interaction data, and at least one of the other registers can be used to receive and send signals, so that multiple different registers cooperate to realize the transmission of data and signals, that is, to realize the information interaction between different processors.

[0049] In some embodiments, the above-mentioned first interaction circuit can be set outside the first processor and the input / output processor and located between the first processor and the input / output processor, or can also be set inside the first processor or the input / output processor and be electrically connected to the other party.

[0050] Based on the above-mentioned first interaction circuit, when the first processor needs to send request information to the input / output processor, the first processor writes the request information into the first interaction circuit, specifically writes the data content of the request information into the register for storing information and data in at least two registers of the first interaction circuit.

[0051] The above-mentioned first interaction circuit continuously detects the operation of the first processor writing data into the first interaction circuit. When it detects that the first processor writes the first request information into the first interaction circuit, the first interaction circuit sends an interrupt signal to the input / output processor through at least two registers it includes.

[0052] The above-mentioned first request information is used to represent any request information written by the first processor into the first interaction circuit.

[0053] In some embodiments, the register for receiving and sending signals in the first interaction circuit continuously monitors the state of the register for storing data. In this embodiment, based on Figure 2In the microprocessor architecture shown, one end of the first interaction circuit connected to the first processor is the input end, and one end of the first interaction circuit connected to the input / output processor is the output end. At this time, only the first processor may write data into the register for storing data in the first interaction circuit. Therefore, when the register for receiving and transmitting signals in the first interaction circuit detects a change in the state of the register for storing data, it can be determined that the first processor has written data into the register for storing data, that is, it can be determined that the first processor has written the first request information into the first interaction circuit. At this time, the register for receiving and transmitting signals sends an interrupt signal to the input / output processor.

[0054] In some embodiments, the register for storing data in the first interaction circuit is provided with a status flag bit. When the register does not store data, its status flag bit is in the first state, and when the register stores data, its status flag bit is in the second state. Therefore, by monitoring the change in the status of the status flag bit of the register for storing data, it can be determined whether the first processor writes data into the register. When the register for receiving and transmitting signals detects that the status flag bit of the register for storing data changes from the first state to the second state, it can be determined that the first processor has written the request information into the first interaction circuit.

[0055] In the embodiments of the present application, the interrupt signal sent by the first interaction circuit to the input / output processor is used to trigger the input / output processor to execute processing corresponding to the first request information. That is, when the input / output processor receives the interrupt signal sent by the first interaction circuit, it executes processing corresponding to the first request information.

[0056] In some embodiments, a one-to-one correspondence relationship between the request information and the interrupt signal can be set. Based on this correspondence relationship, when the input / output processor receives the interrupt signal, it can quickly determine the request information corresponding to the interrupt signal, and then can execute the processing corresponding to the request information.

[0057] For example, the above-mentioned first request information may be a data acquisition request. The first processor writes the first request information into the first interaction circuit, indicating that the first processor requests the input / output processor to send the data that needs to be processed by the first processor to the first processor. At this time, when the first interaction circuit detects that the first processor writes the above-mentioned first request information into the first interaction circuit, it sends an interrupt signal to the input / output processor. When the input / output processor receives the interrupt signal, it can determine that the first processor has sent a data acquisition request. At this time, the input / output processor sends the data that needs to be processed by the first processor to the first processor.

[0058] As can be seen from the above introduction, in the microprocessor architecture proposed in the embodiments of the present application, an interaction circuit is provided between the first processor and the input / output processor, and a register is provided in the interaction circuit. When the first processor needs to send a request message to the input / output processor, it can directly write the request message into the interaction circuit. The interaction circuit sends an interrupt signal to the input / output processor to trigger the input / output processor to execute the processing corresponding to the request message. The above microprocessor architecture makes the interaction between processors simpler and more efficient by providing an interaction circuit between the processors, which is conducive to making the request messages sent by the processors be responded to more timely.

[0059] In some embodiments, referring to Figure 3 as shown, the first interaction circuit in this embodiment includes two registers, namely the first register and the second register.

[0060] Among them, the above-mentioned first register is used to store the data written by the first processor into the first interaction circuit, and the second register is used to detect the operation of the first processor writing data into the first register, and send an interrupt signal to the input / output processor when it detects that the first processor writes data into the first register.

[0061] Based on the above first register and second register, when the first processor sends a first request message to the input / output processor, the first processor writes the first request message into the first register of the first interaction circuit.

[0062] In some embodiments, the above-mentioned first request message may be data representing a specific request. For example, the digital "1" is used to represent a clock shutdown request, and the digital "2" is used to represent a power shutdown request. Then the first processor writes the first request message into the first register, specifically, it can write the data representing the first request message into the first register.

[0063] The second register in the first interaction circuit continuously detects the write operation of the first processor on the first register. When it detects that the first processor writes the first request message into the first register, for example, when it detects that the status flag bit of the first register changes, the second register sends an interrupt signal to the input / output processor.

[0064] After receiving the interrupt signal sent by the second register, the input / output processor accesses the first register, reads the first request message from the first register, and executes the processing corresponding to the first request message.

[0065] In some embodiments, the input / output processor reads the data written by the first processor from the first register, then parses the read data to determine the processing method corresponding to the read data, and finally processes it according to the processing method corresponding to the read data. For example, assume that the input / output processor reads the number "1" from the first register, then the input / output processor performs clock shutdown processing. Assume that the input / output processor reads the number "2" from the first register, then the input / output processor performs power shutdown processing.

[0066] In the above embodiment, the first interaction circuit collaborates through two registers to quickly send down the request information. In this solution, the structure of the first interaction circuit is simple, the power consumption is lower, and the request sending efficiency is higher.

[0067] In some embodiments, referring to Figure 4 as shown, the first processor includes multiple processor cores, and each processor core is respectively connected to the input / output processor through a group of first interaction circuits.

[0068] Among them, the structure of each group of the above first interaction circuits can respectively adopt Figure 3 the circuit structure shown.

[0069] Based on Figure 4 the microprocessor architecture shown, each processor core in the first processor is respectively connected to the input / output processor through a separate first interaction circuit. For example, the i-th processor core in the first processor is connected to the input / output processor through the m-th first interaction circuit, where the values of i and m are respectively 1 to n, and n is a positive integer. This can enable each processor core in the first processor to communicate with the input / output processor one-to-one without interference, avoiding the problem of communication blockage.

[0070] Based on Figure 4 the microprocessor architecture shown, any processor core in the first processor can send request information to the input / output processor through the first interaction circuit connected to it. For example, the first processor core in the first processor can write the first request information into the first interaction circuit connected to the first processor core.

[0071] When the first interaction circuit connected to the above first processor core detects that the first processor core writes the first request information into the first interaction circuit, it sends an interrupt signal to the input / output processor through at least two registers in the first interaction circuit. For example, the first processor core writes the first request information into the first register of the first interaction circuit connected to it, and when the second register in the first interaction circuit detects that the first processor core writes data into the first register, it sends an interrupt signal to the input / output processor.

[0072] When the input / output processor receives an interrupt signal sent by a first interaction circuit connected to a first processor core, it performs processing corresponding to first request information on the first processor core.

[0073] That is, when the input / output processor receives an interrupt signal sent by a second register in the first interaction circuit connected to the first processor core, it reads the first request information written by the first processor core from a first register of the first interaction circuit, and then performs processing corresponding to the first request information on the first processor core. For example, assuming that the first request information is a data acquisition request message, the input / output processor sends the data that needs to be processed by the first processor core to the first processor core.

[0074] Based on Figure 4 In the microprocessor architecture shown, the input / output processor receives request information from different processor cores of the first processor through different interaction circuits respectively. That is, the input / output processor can determine which processor core of the first processor sends the request information to the input / output processor by distinguishing the interaction circuit that sends the interrupt signal to the input / output processor, and then can directly respond to the request of this processing core. The above processing process omits the operation of the input / output processor to determine which first processor core the request information comes from by parsing the request information, and can further improve the response efficiency of the input / output processor to the request information sent by the first processor.

[0075] In some embodiments, the input / output processor in the above microprocessor architecture includes at least one dedicated processor core, which serves as an intermediate medium when the first processor interacts with at least one peripheral controller.

[0076] The input / output processor is a hardware structure specifically provided in the microprocessor architecture of this application embodiment for performing data communication operations between the first processor and each peripheral controller. The input / output processor includes at least one processor core dedicated to performing data communication operations between the first processor and the peripheral controller.

[0077] In the embodiment of this application, the above processor core is specifically a RISC-V (Reduced Instruction Set Computer - Five, the fifth generation of reduced instruction set computer) core, that is, a processor core with the RISC-V instruction architecture, mainly completing instruction access for modules with low real-time requirements such as low-speed peripherals.

[0078] Based on the above microprocessor architecture, the first processor therein is electrically connected to the input / output processor through a first interaction circuit. Specifically, the first processor is electrically connected to the processor core in the input / output processor through the first interaction circuit. Thus, the processor core in the input / output processor can receive an interrupt signal through the first interaction circuit and perform processing corresponding to the first request information sent by the first processor when the interrupt signal is received.

[0079] In some other embodiments, as shown in Figure 5 the microprocessor architecture provided in this embodiment further includes a second processor, and the security level of the second processor is higher than that of the first processor. Based on the characteristic of the high security level of the second processor, programs with higher security level requirements can be run on the second processor, and a security measurement service module can be carried in the second processor to perform security measurement on other modules. For example, the second processor can be a security element SE and can be used for security control of the microprocessor architecture.

[0080] In some embodiments, the above-mentioned first processor and second processor each include one or more processor cores, so that Figure 5 the first processor and the second processor shown respectively correspond to different processor cores. For example, the first processor and the second processor respectively correspond to the first processor core and the second processor core, so that the microprocessor architecture constitutes a system-on-chip including multiple processor cores.

[0081] Or, in some other embodiments, Figure 5 the first processor and the second processor shown can be different types of processors. For example, they can be a CPU, a GPU, etc. respectively. In this case, the microprocessor architecture constitutes a system-on-chip including multiple different types of processors.

[0082] In some embodiments, the second processor is a system control processor and the first processor is an application processor. The above-mentioned system control processor serves as the clock reset control center of the entire microprocessor architecture, mainly provides working clocks for each module of the microprocessor architecture, as well as clock frequency adjustment, and controls the reset of each module, so that the chip can complete initialization normally after power-on.

[0083] As shown in Figure 5 the above-mentioned second processor is electrically connected to the input / output processor through a second interaction circuit, and the second interaction circuit includes at least two registers. The structure of the second interaction circuit can be the same as the structure of the first interaction circuit introduced in the above embodiment.

[0084] In some embodiments, the above-mentioned second interaction circuit may be disposed outside the second processor and the input / output processor and located between the second processor and the input / output processor. Alternatively, the above-mentioned second interaction circuit may be disposed inside the second processor or the input / output processor and electrically connected to the other party, so as to realize the communication connection between the second processor and the input / output processor.

[0085] The above-mentioned second interaction circuit adopts the same processing logic as the above-mentioned first interaction circuit to implement the fast request information interaction function.

[0086] When the second processor needs to send a request message to the input / output processor, the second processor writes the request message into the second interaction circuit. Specifically, the specific data content of the request message is written into the register for storing information and data among at least two registers of the second interaction circuit.

[0087] The above-mentioned second interaction circuit detects in real time the operation of the second processor writing data into the second interaction circuit. When it detects that the second processor writes the second request message into the second interaction circuit, the second interaction circuit sends an interrupt signal to the input / output processor through at least two registers it includes.

[0088] The above-mentioned second request message is used to represent any request message written by the second processor into the second interaction circuit. In this embodiment, the above-mentioned second request message may be, for example, a control request, a data read / write request, etc.

[0089] In some embodiments, the register for receiving and transmitting signals in the second interaction circuit monitors the state of the register for storing data in real time. When the register for receiving and transmitting signals in the second interaction circuit monitors that the state of the register for storing data has changed, it can be determined that the second processor has written data into the register for storing data, that is, it can be determined that the second processor has written the second request message into the second interaction circuit. At this time, the register for receiving and transmitting signals sends an interrupt signal to the input / output processor.

[0090] In some embodiments, the register for storing data in the second interaction circuit is provided with a status flag bit. When the register does not store data, its status flag bit is in the first state. When the register stores data, its status flag bit is in the second state. Therefore, by monitoring the state change of the status flag bit of the register for storing data, it can be determined whether the second processor writes data into the register. When the register for receiving and transmitting signals detects that the status flag bit of the register for storing data changes from the first state to the second state, it can be determined that the second processor has written a request message into the second interaction circuit.

[0091] In the embodiment of the present application, the interrupt signal sent by the second interaction circuit to the input / output processor is used to trigger the input / output processor to execute the processing corresponding to the second request information. That is, when the input / output processor receives the interrupt signal sent by the second interaction circuit, it executes the processing corresponding to the second request information.

[0092] For the specific processing procedure of the above-mentioned second interaction circuit, reference may also be made to the specific processing procedure of the first interaction circuit in the above embodiment.

[0093] In some other embodiments, the above-mentioned second processor may include multiple processor cores. On this basis, each processor core included in the second processor is electrically connected to the input / output processor through a set of the above-mentioned second interaction circuits.

[0094] Based on this microprocessor architecture, each processor core included in the second processor communicates and interacts with the input / output processor through an independent second interaction circuit, thereby improving communication efficiency and avoiding communication blocking problems.

[0095] For the specific processing procedure of each processor core included in the second processor to interact with the input / output processor through the second interaction circuit connected thereto, reference may be made to the specific processing procedure of each processor core of the first processor in the above embodiment to interact with the input / output processor through the first interaction circuit connected thereto, which will not be elaborated herein.

[0096] In some other embodiments, refer to Figure 6 As shown, the first processor and the second processor in the above microprocessor architecture may be electrically connected through a third interaction circuit.

[0097] In this third interaction circuit, there are at least two registers. The above-mentioned at least two registers may be the same registers or different registers. These registers respectively implement different functions, so that the first interaction circuit can implement the information interaction function between different processors. For example, at least one of the registers can be used to store interaction information or interaction data, and at least one of the other registers can be used to send and receive signals, so that multiple different registers cooperate to realize the transmission of data and signals, that is, to realize the information interaction between different processors.

[0098] In some embodiments, the above-mentioned third interaction circuit may be arranged outside the first processor and the second processor and between the first processor and the second processor, or may also be arranged inside the first processor or the second processor and electrically connected to the other party.

[0099] Based on the above-mentioned third interaction circuit, when the first processor needs to send a request message to the second processor, the first processor writes the request message into the third interaction circuit. Specifically, the data content of the request message is written into the register for storing information and data among at least two registers of the third interaction circuit.

[0100] The above-mentioned third interaction circuit detects in real time the operation of the first processor writing data into the third interaction circuit. When it detects that the first processor writes the third request message into the third interaction circuit, the third interaction circuit sends an interrupt signal to the second processor through at least two registers it includes.

[0101] The above-mentioned third request message is used to represent any request message written by the first processor into the third interaction circuit.

[0102] In some embodiments, the register for receiving and transmitting signals in the third interaction circuit monitors the state of the register for storing data in real time. In this embodiment, based on Figure 6 the microprocessor architecture shown, one end of the third interaction circuit connected to the first processor is the input end, and one end of the third interaction circuit connected to the second processor is the output end. At this time, only the first processor may write data into the register for storing data in the third interaction circuit. Therefore, when the register for receiving and transmitting signals in the third interaction circuit monitors that the state of the register for storing data has changed, it can be determined that the first processor has written data into the register for storing data, that is, it can be determined that the first processor has written the third request message into the third interaction circuit. At this time, the register for receiving and transmitting signals sends an interrupt signal to the second processor.

[0103] In some embodiments, the register for storing data in the third interaction circuit is provided with a status flag bit. When the register does not store data, its status flag bit is in the first state, and when the register stores data, its status flag bit is in the second state. Therefore, by monitoring the state change of the status flag bit of the register for storing data, it can be judged whether the first processor writes data into the register. When the register for receiving and transmitting signals detects that the status flag bit of the register for storing data switches from the first state to the second state, it can be determined that the first processor has written a request message into the third interaction circuit.

[0104] In the embodiment of the present application, the interrupt signal sent by the third interaction circuit to the second processor is used to trigger the second processor to execute the processing corresponding to the third request message. That is, when the second processor receives the interrupt signal sent by the third interaction circuit, it executes the processing corresponding to the third request message.

[0105] In some embodiments, a one-to-one correspondence between request information and interrupt signals can be set. Based on this correspondence, when the second processor receives an interrupt signal, it can quickly determine the request information corresponding to the interrupt signal, and then can execute the processing corresponding to the request information.

[0106] For example, the above-mentioned third request information may be a low-power request. The first processor writes the third request information into the third interaction circuit, indicating that the first processor requests to switch the first processor to the low-power operating mode. At this time, when the third interaction circuit detects that the first processor writes the above-mentioned third request information into the third interaction circuit, it sends an interrupt signal to the second processor. When the second processor receives the interrupt signal, it can determine that the first processor has issued a low-power request. At this time, the second processor controls the first processor to switch to the low-power operating mode.

[0107] The application of the above-mentioned third interaction circuit makes the interaction between the first processor and the second processor more concise and efficient, which is conducive to making the request information sent by the first processor get a more timely response.

[0108] For the specific structure of the above-mentioned third interaction circuit, reference may be made to the structures of the first interaction circuit and the second interaction circuit in the above embodiments.

[0109] In other embodiments, the third request information written by the first processor into the third interaction circuit may be low-power request information, that is, request information for requesting to reduce the power consumption of the first processor.

[0110] In this case, the first processor writes the third request information into the third interaction circuit through the Collaborative Processor Performance Control (CPPC) interface of the operating system.

[0111] Among them, in the low-power protocol specification of the computer system, there is a software interface of CPPC. This CPPC interface can enable the operating system to directly operate the underlying registers by skipping the uefi interface and the underlying firmware. Since the forwarding of requests by the intermediate layer is omitted, the request information can reach the registers faster.

[0112] Therefore, writing the low-power request into the register in the third interaction circuit through the CPPC interface can improve the sending efficiency of the low-power request, and thus can improve the low-power control efficiency.

[0113] In other embodiments, as shown in Figure 7 In the first processor, there are multiple processor cores, and each processor core is electrically connected to the second processor through a group of third interaction circuits.

[0114] Among them, the structure of each group of the third interaction circuits described above can respectively adopt the circuit structure of the first interaction circuit or the second interaction circuit described above.

[0115] Based on Figure 7 In the microprocessor architecture shown, each processor core in the first processor is respectively connected to the second processor through a separate third interaction circuit, so that each processor core in the first processor can communicate with the second processor one-on-one without interference, avoiding the problem of communication blockage.

[0116] Based on Figure 7 In the microprocessor architecture shown, any processor core in the first processor can send a request message to the second processor through the third interaction circuit connected thereto. For example, the first processor core in the first processor can write the third request message into the third interaction circuit connected to the first processor core.

[0117] When the third interaction circuit connected to the first processor core detects that the first processor core writes the third request message into the third interaction circuit, it sends an interrupt signal to the second processor through at least two registers in the third interaction circuit. For example, the first processor core writes the third request message into the first register of the third interaction circuit connected thereto, and the second register in the third interaction circuit sends an interrupt signal to the second processor when it detects that the first processor core writes data into the first register.

[0118] When the second processor receives the interrupt signal sent by the third interaction circuit connected to the first processor core, it performs processing corresponding to the third request message on the first processor core.

[0119] That is, when the second processor receives the interrupt signal sent by the second register in the third interaction circuit connected to the first processor core, it reads the third request message written by the first processor core from the first register of the third interaction circuit, and then performs processing corresponding to the third request message on the first processor core. For example, assuming that the third request message is a low-power request message, the second processor adjusts the first processor core to the low-power operating mode.

[0120] Based on Figure 7In the microprocessor architecture shown, the second processor receives request information from different processor cores of the first processor through different interaction circuits respectively. That is, by distinguishing the interaction circuit that sends an interrupt signal to the second processor, the second processor can determine which processor core of the first processor sends the request information, and then can directly respond to the request of this processing core. The above processing process omits the operation of the second processor to determine which first processor core the request information comes from by parsing the request information, and can further improve the response efficiency of the second processor to the request information sent by the first processor.

[0121] In some other embodiments, one or more of a Rich Execution Environment (REE) subsystem, a Trusted Execution Environment (TEE) subsystem, and a Secure Element (SE) subsystem are also installed in the above microprocessor architecture.

[0122] Among them, the REE subsystem of the general execution environment may include a general operating system running on the processor, in which application programs are installed. The application programs running in the REE can be called client applications (CAs), and their security is relatively low and they are vulnerable to attacks. Although many security measures such as device access control, device data encryption mechanism, isolation mechanism during application runtime, and access control based on permission verification are taken in the REE, the security of important data in the application still cannot be guaranteed.

[0123] The TEE subsystem of the trusted execution environment can be an independent running environment outside the general operating system. It can provide trusted services to, for example, the REE and is isolated from the REE. One or more trusted applications (TEAs) can be executed in the TEE. The TEE provides a trustworthy running environment for the REE subsystem of the general execution environment through the trusted applications, and then ensures end-to-end security through the protection of confidentiality, integrity, and control of data access permissions. In addition, the TEE can run in parallel with the REE, and for example, the TEE interacts with the REE through a secure Application Programming Interface (API).

[0124] The TEE provides a running environment with a higher security level than the REE, but it cannot provide a secure key storage and key running environment at the hardware isolation level. Generally, the TEE can provide many application programming interfaces for the REE to call the resources of the TEE. The more application programming interfaces provided by the TEE for services, the greater the risk faced by the TEE. It is difficult to ensure that there are no security hazards in the application programming interfaces themselves, such as security vulnerabilities, which may further lead to security risks for resources such as keys within the TEE. Further, multiple trusted applications (TAs) will run within the TEE. The TAs are completely dependent on the isolation mechanism provided by the TEE operating system and there is no hardware-level isolation. This means that if there are security vulnerabilities in the TAs themselves or if the TAs actively access the keys or root keys corresponding to other TAs, it will also lead to significant security risks for sensitive resources such as keys.

[0125] The secure element subsystem is a software system running on the secure element (SE). It provides security services based on the hardware of the SE. Since the secure element subsystem is hosted in an independent hardware environment, it is easy to establish physical protection and implement security safeguards, thereby enhancing the security strength of the secure element subsystem to serve security systems with higher security requirements. As an example, the TEE can transmit a security service request to the secure element subsystem to request the provision of corresponding security services and make a response based on the request. For example, the security service can be a request for the secure element subsystem to perform services related to cryptographic operations, etc.

[0126] In some embodiments, based on the above microprocessor architecture, the regular execution environment subsystem (REE) and the trusted execution environment subsystem (TEE) can be hosted on the first processor, and the secure element subsystem can be hosted on the second processor. This microprocessor architecture enables the secure element subsystem to have the ability to independently process tasks and respond to requests, making the task execution of the secure element subsystem completely independent and not affected by the execution environments of other subsystems. This is beneficial for improving the security of the microprocessor architecture and also for enhancing the task execution efficiency of the secure element subsystem. Further, this implementation method can reduce the hardware resource consumption of the processor and improve the processing performance of the processor.

[0127] In the above microprocessor architecture, the first processor is used to respond to access requests initiated by the regular execution environment subsystem REE and / or the trusted execution environment subsystem TEE. For example, in response to access requests initiated by the regular execution environment subsystem REE and / or the trusted execution environment subsystem TEE for any peripheral controller, it sends an access request to the peripheral controller; the second processor is used to respond to access requests initiated by the security element subsystem. For example, in response to an access request initiated by the security element subsystem for any peripheral controller, it sends a corresponding access request to the peripheral controller.

[0128] Based on the above microprocessor architecture, by deploying execution environments with different security levels in the microprocessor architecture, it is possible to meet the operation of programs with various security levels while ensuring the security of the microprocessor architecture.

[0129] Another embodiment of the present application further proposes an information interaction method. This method is applied to a microprocessor architecture, which includes a first processor, an input / output processor, and at least one peripheral controller; the input / output processor serves as an intermediate medium when the first processor interacts with the at least one peripheral controller; the first processor is electrically connected to the input / output processor through a first interaction circuit, and the first interaction circuit includes at least two registers;

[0130] See Figure 8 As shown, the method includes:

[0131] S101. When the first interaction circuit detects that the first processor writes first request information into the first interaction circuit, it sends an interrupt signal to the input / output processor through the at least two registers; the interrupt signal is used to trigger the input / output processor to execute processing corresponding to the first request information.

[0132] In some implementation manners, the at least two registers include a first register and a second register;

[0133] The first processor writing first request information into the first interaction circuit includes: the first processor writing first request information into the first register;

[0134] When the first interaction circuit detects that the first processor writes first request information into the first interaction circuit and sends an interrupt signal to the input / output processor through the at least two registers, it includes:

[0135] When the second register detects that the first processor writes first request information into the first register, it sends an interrupt signal to the input / output processor;

[0136] The input / output processor performs processing corresponding to the first request information, including:

[0137] The input / output processor accesses the first register to obtain the first request information and performs processing corresponding to the first request information.

[0138] In some implementations, the first processor includes a plurality of processor cores, and each of the processor cores is respectively connected to the input / output processor through a group of the first interaction circuits;

[0139] The first processor writes the first request information into the first interaction circuit, including: a first processor core in the first processor writes the first request information into the first interaction circuit connected to the first processor core;

[0140] When the first interaction circuit detects that the first processor writes the first request information into the first interaction circuit, the first interaction circuit sends an interrupt signal to the input / output processor through the at least two registers, including:

[0141] When the first interaction circuit connected to the first processor core detects that the first processor core writes the first request information into the first interaction circuit, the first interaction circuit sends an interrupt signal to the input / output processor through at least two registers;

[0142] The input / output processor performs processing corresponding to the first request information, including:

[0143] The input / output processor performs processing corresponding to the first request information on the first processor core.

[0144] In some implementations, the input / output processor includes at least one dedicated processor core, and the processor core included in the input / output processor serves as an intermediate medium when the first processor interacts with the at least one peripheral controller.

[0145] In some implementations, the first processor is electrically connected to the input / output processor through a first interaction circuit, including:

[0146] The first processor is electrically connected to the processor core included in the input / output processor through a first interaction circuit.

[0147] In some implementations, the microprocessor architecture further includes a second processor, and the security level of the second processor is higher than that of the first processor;

[0148] The second processor is electrically connected to the input / output processor through a second interaction circuit, and the second interaction circuit includes at least two registers;

[0149] The method further includes:

[0150] When the second interaction circuit detects that the second processor writes second request information into the second interaction circuit, the second interaction circuit sends an interrupt signal to the input / output processor through at least two registers; the interrupt signal is used to trigger the input / output processor to execute processing corresponding to the second request information.

[0151] In some implementation manners, the microprocessor architecture is equipped with one or more of a general execution environment subsystem, a trusted execution environment subsystem, and a security element subsystem;

[0152] Wherein, the first processor is used to respond to access requests initiated by the general execution environment subsystem and / or the trusted execution environment subsystem, and the second processor is used to respond to access requests initiated by the security element subsystem.

[0153] The information interaction method provided in this embodiment belongs to the same inventive concept as the microprocessor architecture provided in the above embodiments of the present application. Each processing step of this information interaction method realizes its respective functions through each part of the microprocessor architecture provided in the above embodiments. For the technical details of this information interaction method not described in detail in this embodiment, reference may be made to the specific processing content of the information interaction process implemented by the microprocessor architecture provided in the above embodiments of the present application, which will not be elaborated here.

[0154] Another embodiment of the present application further proposes a computer device, which includes the microprocessor architecture described in any of the above embodiments, or the computer device is configured to implement the information interaction method described in any of the above embodiments.

[0155] The computer device may specifically be a personal computer, a server, a smart device, a smart terminal, a wearable device, etc.

[0156] For the foregoing method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the present application is not limited by the described action sequence, because according to the present application, certain steps may be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the present application.

[0157] It should be noted that the embodiments in this specification are all described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. For device embodiments, since they are basically similar to method embodiments, they are described relatively simply. For related parts, reference can be made to the corresponding descriptions in the method embodiments.

[0158] The steps in the methods of the embodiments of the present application can be adjusted, combined, and deleted according to actual needs. The technical features recorded in each embodiment can be replaced or combined.

[0159] The modules and sub-modules in the devices and terminals in the embodiments of the present application can be combined, divided, and deleted according to actual needs.

[0160] In several embodiments provided by the present application, it should be understood that the disclosed terminals, devices, and methods can be implemented in other ways. For example, the terminal embodiments described above are merely illustrative. For example, the division of modules or sub-modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple sub-modules or modules can be combined or integrated into another module, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of devices or modules can be in electrical, mechanical, or other forms.

[0161] The modules or sub-modules described as separate components may or may not be physically separated. The components serving as modules or sub-modules may or may not be physical modules or sub-modules. That is, they can be located in one place or distributed to multiple network modules or sub-modules. Some or all of the modules or sub-modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0162] In addition, the functional modules or sub-modules in each embodiment of the present application can be integrated in a processing module, or each module or sub-module can exist physically alone, or two or more modules or sub-modules can be integrated in one module. The above-mentioned integrated modules or sub-modules can be implemented in the form of hardware or in the form of software functional modules or sub-modules.

[0163] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0164] The steps of the methods or algorithms described in combination with the embodiments disclosed herein can be directly implemented by hardware, software units executed by a processor, or a combination of the two. The software units can be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium well-known in the technical field.

[0165] Finally, it should also be noted that in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0166] The above description of the disclosed embodiments enables those skilled in the art to implement or use this application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application will not be limited to the embodiments shown herein, but rather will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A microprocessor architecture, characterized in that: include: a first processor, an input-output processor, and at least one peripheral controller; The input-output processor acts as an intermediary when the first processor interacts with the at least one peripheral controller; The first processor is electrically connected to the input-output processor via a first interactive circuit, wherein the first interactive circuit includes at least two registers; When the first interactive circuit detects that the first processor writes the first request information into the first interactive circuit, the first interactive circuit sends an interrupt signal to the input-output processor through the at least two registers; the interrupt signal is used to trigger the input-output processor to perform processing corresponding to the first request information.

2. The microprocessor architecture according to claim 1, characterized in that: The at least two registers include a first register and a second register; The first processor writes the first request information into the first interactive circuit, including: the first processor writes the first request information into the first register; When the first interactive circuit detects that the first processor writes the first request information into the first interactive circuit, the first interactive circuit sends an interrupt signal to the input-output processor through the at least two registers, including: The second register sends an interrupt signal to the input-output processor when detecting that the first processor writes the first request information into the first register; The input-output processor performs processing corresponding to the first request information, including: The input / output processor accesses the first register to obtain first request information, and executes processing corresponding to the first request information.

3. The microprocessor architecture according to claim 1, characterized in that: The first processor includes a plurality of processor cores, each of the processor cores is connected to the input-output processor via a set of the first interaction circuits; The first processor writes the first request information into the first interactive circuit, including: a first processor core in the first processor writes the first request information into a first interactive circuit connected to the first processor core; When the first interactive circuit detects that the first processor writes the first request information into the first interactive circuit, the first interactive circuit sends an interrupt signal to the input-output processor through the at least two registers, including: The first interactive circuit connected to the first processor core sends an interrupt signal to the input-output processor through at least two registers when detecting that the first processor core writes the first request information into the first interactive circuit; The input-output processor performs processing corresponding to the first request information, including: The input / output processor performs a process corresponding to the first request information on the first processor core.

4. The microprocessor architecture according to claim 1, characterized in that: The input-output processor includes at least one dedicated processor core, and the processor core included in the input-output processor serves as an intermediate medium when the first processor interacts with the at least one peripheral controller.

5. The microprocessor architecture according to claim 4, characterized in that: The first processor is electrically connected to the input-output processor via a first interactive circuit, comprising: The first processor is electrically connected to the processor core included in the input-output processor via a first interactive circuit.

6. The microprocessor architecture according to any one of claims 1 to 5, characterized in that: The microprocessor architecture further includes a second processor having a higher security level than the first processor; The second processor is electrically connected to the input-output processor via a second interactive circuit, wherein the second interactive circuit includes at least two registers; When the second interactive circuit detects that the second processor writes second request information into the second interactive circuit, the second interactive circuit sends an interrupt signal to the input-output processor through at least two registers; the interrupt signal is used to trigger the input-output processor to perform processing corresponding to the second request information.

7. The microprocessor architecture according to claim 6, characterized in that: The microprocessor architecture is equipped with one or more of a common execution environment subsystem, a trusted execution environment subsystem, and a secure element subsystem; The first processor is used to respond to access requests initiated by the common execution environment subsystem and / or the trusted execution environment subsystem, and the second processor is used to respond to access requests initiated by the secure element subsystem.

8. An information interaction method, characterized in that: Applied to a microprocessor architecture, the microprocessor architecture includes a first processor, an input-output processor, and at least one peripheral controller; the input-output processor serves as an intermediate medium when the first processor interacts with the at least one peripheral controller; The first processor is electrically connected to the input-output processor via a first interactive circuit, wherein the first interactive circuit includes at least two registers; The method comprises: When the first interactive circuit detects that the first processor writes the first request information into the first interactive circuit, the first interactive circuit sends an interrupt signal to the input-output processor through the at least two registers; the interrupt signal is used to trigger the input-output processor to perform processing corresponding to the first request information.

9. The method according to claim 8, characterized in that The microprocessor architecture further includes a second processor, the security level of the second processor is higher than that of the first processor; the second processor is electrically connected to the input-output processor via a second interactive circuit, the second interactive circuit including at least two registers; The method further comprises: When the second interactive circuit detects that the second processor writes second request information into the second interactive circuit, the second interactive circuit sends an interrupt signal to the input-output processor through at least two registers; the interrupt signal is used to trigger the input-output processor to perform processing corresponding to the second request information.

10. A computer device, characterized in that: The computer device comprises a microprocessor architecture as claimed in any one of claims 1 to 7, or the computer device is configured to implement the information interaction method as claimed in claim 8 or 9.

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