Electronic system with integrated master circuit and integrated slave circuit

Abstract

The present disclosure relates to an electronic system comprising a master IC, a slave IC, and a serial communication interface having a bidirectional data line and a clock line, where the communication interface is designed to transfer data between the master IC and the slave IC. The master IC is designed to send a data request command to the slave IC via the data line. The slave IC is designed to start providing requested data in response to the data request command. The master IC is designed to transmit a data read command for reading requested data to the slave IC via the data line after the data request command. The slave IC is designed to deactivate the clock line after receiving a data read command until the slave IC can provide requested data. The master IC is designed to measure a duration of deactivating the clock line. The main IC is designed to set a latency between the next data request command and the next data read command as a function of the measured duration.

Description

Technical Field

[0001] The present disclosure relates to an electronic system including a master integrated circuit (master IC) and slave ICs. A serial communication interface having bidirectional data lines and a clock line is designed to transfer data between the master IC and the slave ICs. The serial communication interface can be an I 2 C (Inter-Integrated Circuit). Background Art

[0002] I 2 C refers to a serial data bus that has evolved into a widely accepted industry standard. It can be used within a device for communication between different circuit components, such as within a television or between a controller and peripheral ICs.

[0003] I 2 C is designed as a master-slave bus. Data transfer can be initiated by a host (controller); a slave (target) addressed by an address responds thereto. Multiple controllers (multi-controller operation) can be used. If a controller component also works as a target in a multi-controller operation, another controller can directly communicate with it by addressing it as a target.

[0004] I 2 A feature of I

[0005] Although I 2 C is slower than new bus systems, it is advantageous for peripheral devices that do not require speed due to its low cost. I 2 C can be used to transfer control and configuration data. For example, a volume controller, an analog-to-digital or digital-to-analog converter with a low sampling rate, a real-time clock, a small non-volatile memory, or a bidirectional switch and multiplexer. An electronic sensor can also have an integrated analog-to-digital converter with an I 2 C interface.

[0006] When using I 2 C, conflicting requirements may arise. For example, if data (such as measurement data) is available on the sensor side, it may be necessary to immediately read the data. The system may need to use less power consumption. It may be necessary to use inexpensive I 2 C-slave ICs without additional interrupt pins. It may also be necessary to increase the I 2 C bandwidth. Summary of the Invention

[0007] The device and method according to the present invention take into account one or more of the above requirements. The following presents advantageous further embodiments.

[0008] According to a first aspect, an electronic system is provided. The electronic system includes an integrated master circuit (master IC) and a slave IC. The electronic system further includes a serial communication interface having bidirectional data lines and a clock line. The communication interface is designed to transfer data between the master IC and the slave IC. The master IC is designed to send a data request command to the slave IC via the data line. The slave IC is designed to start providing the requested data in response to the data request command. The master IC is designed to send a data read command for reading the requested data to the slave IC via the data line after the data request command. The slave IC is designed to deactivate the clock line until the slave IC can provide the requested data after receiving the data read command. The master IC is designed to measure the duration for which the clock line is deactivated. The master IC is designed to set the waiting time between the next data request command and the next data read command based on the measured duration.

[0009] According to some embodiments, the master IC is designed to: send the data read command to the slave IC after a specified minimum data provision time has elapsed since the data request command. The slave IC is designed to: deactivate the clock line if the requested data is not yet fully available after the specified minimum data provision time until the slave IC can provide the requested data. The master IC is designed to measure the duration for which the clock line is deactivated and set the waiting time between the next data request command and the next data read command based on the minimum data provision time and the measured duration.

[0010] According to some embodiments, the master IC is designed to: maintain the waiting time for a plurality of subsequent data request commands and subsequent data read commands and then determine an updated waiting time according to one of the described embodiments.

[0011] According to some embodiments, the master IC is designed to: use the waiting time set for the data request command and the subsequent data read command and then gradually reduce the waiting time between the data request command and the data read command until the re - deactivation of the clock line is detected by the slave IC so that the requested data can be provided on the data line.

[0012] According to some embodiments, the master IC is designed to: measure the duration for which the clock line is re - deactivated and set a re - updated waiting time between the next data provision command and the subsequent data read command based on the measured duration.

[0013] According to some embodiments, the master IC includes a microcontroller.

[0014] According to some embodiments, the slave IC includes a sensor IC, such as a magnetic field sensor IC. The magnetic field sensor IC may include a 3D Hall sensor IC.

[0015] According to some embodiments, the serial communication interface includes an I 2 C communication interface.

[0016] According to a second aspect, a communication method for an electronic system including a master IC and a slave IC is provided. The electronic system further includes a serial communication interface having bidirectional data lines and a clock line for transmitting data between the master IC and the slave IC. The communication method includes sending a data request command from the master IC to the slave IC via the data line. The communication method includes the slave IC starting to provide the requested data in response to the data request command. The communication method includes, after the data request command, the master IC sending a data read command for reading the requested data to the slave IC via the data line. The communication method includes the slave IC deactivating the clock line after receiving the data read command until the slave IC can provide the requested data. The communication method includes the master IC measuring the duration of the deactivated clock line. The communication method includes the master IC setting a waiting time between the next data request command and the next data read command according to the measured duration.

[0017] According to another aspect, an integrated circuit (IC) is provided. The IC includes a serial communication interface having bidirectional data lines and a clock line. The communication interface is designed to transmit data between the IC and another IC via the data line. The IC further includes a processor designed to: send a data request command to another IC via the data line; after a waiting time after the data request command, send a data request command to another IC via the data line; after the data read command, measure the duration of the deactivated clock line of the other IC; and update the waiting time between the next data request command and the subsequent data read command according to the measured duration.

[0018] According to some embodiments, the processor is designed to: send a data read command to another IC after a specified minimum data provision time has elapsed since the data request command.

[0019] According to some embodiments, the processor is designed to: maintain an updated waiting time for a plurality of next data request commands and data read commands, and then determine a re-updated waiting time.

[0020] According to some embodiments, the processor is designed to: use the updated waiting time for the next data request command and the next data read command, and then gradually reduce the waiting time between the data request command and the data read command until a re-deactivation of the clock line is detected by another IC.

[0021] According to some embodiments, the IC is designed as a microcontroller.

[0022] According to some embodiments, the data providing command includes a command to measure sensor data to the sensor IC. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Some examples of the device and / or method will now be explained in more detail by way of example only with reference to the accompanying drawings. Herein:

[0024] Figure 1A An example of an electronic system having a master IC and a slave IC is shown;

[0025] Figure 1B Examples representing a data request command and a data readout command are shown;

[0026] Figure 2A Another example of an electronic system having a master IC and a slave IC is shown;

[0027] Figure 2B Another example of a data request command and a data read command having clock stretching is shown;

[0028] Figure 3 Another example of a data request command and a data read command having a long latency is shown;

[0029] Figure 4 An embodiment of the communication between the master IC and the slave IC is shown;

[0030] Figure 5 Another embodiment of the communication between the master IC and the slave IC is shown;

[0031] Figure 6 Another embodiment of the communication between the master IC and the slave IC is shown;

[0032] Figure 7 Another embodiment of the communication between the master IC and the slave IC is shown; and

[0033] Figure 8 A communication method between the master IC and the slave IC according to an embodiment is shown. DETAILED DESCRIPTION

[0034] The various examples will now be described more fully with reference to the accompanying drawings which show some examples. However, further possible examples are not limited to the features of these embodiments described in detail. These can include modifications of the features as well as equivalents and alternatives of the features. In addition, the terms used herein to describe the specific examples are not intended to limit other possible examples.

[0035] Throughout the description of the drawings, the same or similar reference numerals refer to the same or similar elements or features, which may be implemented identically or in a modified form while providing the same or similar functions. Additionally, in the drawings, the thickness of lines, layers, and / or regions may be exaggerated for clarity.

[0036] If two elements A and B are combined using "or", all possible combinations are understood to be disclosed, namely only A, only B, and A and B. An alternative phrase for the same combination is "at least one of A and B". This also applies to combinations of more than two elements.

[0037] Whenever singular forms such as "a" and "an" are used, and only a single element is neither explicitly nor implicitly defined as mandatory, additional examples may also use multiple elements to perform the same function. Similarly, when a function is subsequently described as being performed using multiple elements, additional examples may use a single element or processing entity to perform the same function. It will be further understood that the terms "comprising", "comprised of", "including", and / or "included of", when used, specify the presence of the stated features, wholes, steps, operations, processes, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, processes, elements, components, and / or any groups thereof.

[0038] Figure 1A An electronic system 100 having a main IC 110 and a slave IC 120 is shown. In the example shown, the main IC 110 is designed as a microcontroller (μC), and the slave IC 120 is designed as a sensor IC. Other implementations of the slave IC 120, such as a display module, a real-time clock (RTC), etc., are also possible.

[0039] The main IC 110 and the slave IC 120 are connected to each other via a serial communication interface 130. The serial communication interface 130 may be an I 2 C bus communication interface. The I 2 C bus communication interface 130 includes a bidirectional data line (SDA) and a clock line (SCL) between the main IC 110 and the slave IC 120. In the example shown, there is also an interrupt line (INTN) between the main IC 110 and the slave IC 120.

[0040] The main IC or microcontroller 110 is an electronic component that acts as a host or master device in an I 2 C bus system. The microcontroller 110 controls and coordinates the communication between various I 2 C-supporting components (referred to as slave components). The tasks of the microcontroller 110 in an I 2 C system may include, for example:

[0041] - Initiate communication: The microcontroller 110 starts communication by selecting the desired slave device (e.g., slave IC 120) on the I 2 C bus and starting the communication.

[0042] - Send commands and data: The microcontroller 110 sends commands or data to the selected slave device (e.g., slave IC 120) to perform certain actions or retrieve information.

[0043] - Receive data: The microcontroller 110 can receive data from the slave device (e.g., slave IC 120) to collect information or monitor the status of the slave device.

[0044] - Handle errors and conflicts: The microcontroller 110 may be able to identify I 2 conflicts or collisions on the C bus and take appropriate measures to ensure that the communication can continue.

[0045] - Stop communication: At the end of the communication, the microcontroller 110 can stop the transmission and release the I 2 C bus to other devices.

[0046] Thus, the microcontroller 110 can play a core role in controlling and coordinating I 2 C communication in the electronic system 100 and enable the connection and interaction of various components (e.g., sensors, displays, memory chips, and other peripheral devices).

[0047] The microcontroller 110 can start communication in the I 2 C protocol by creating a so-called "start condition" (S) 141 on the I 2 C bus. This is shown in Figure 1B "The start condition" (S) 141 can be part of a command 140 that is the first step in establishing a connection with one or more I 2 C slave devices (e.g., slave IC 120). The start condition 141 can signal the start of a new transmission. The microcontroller 110 can start communication as follows:

[0048] - Send the start condition 141: The microcontroller 110 can pull the data line (SDA) from a high level to a low level, for example, while the clock line (SCL) remains at a high level. This creates a start condition that can be recognized by all I 2 C devices (e.g., slave IC 120) on the bus.

[0049] - Address Transmission 142: After generating the start condition, the microcontroller 110 can send, for example, the 7-bit address of the slave device (e.g., slave IC 120) it wants to communicate with. The eighth bit of the address byte can indicate whether the microcontroller 110 wants to send data to the slave device 120 (0) or whether it wants to receive data 160 from the slave device 120 (1). In the latter case and in the absence of data, the command 140 can be understood as, for example, a data request command to the slave device 120.

[0050] - Wait for Acknowledgment (ACK / NACK): After sending the address 142, the microcontroller 110 can expect an acknowledgment (ACK, confirmation) from the slave IC 120. The ACK can be a brief low level on the data line (SDA), which signals that the slave IC 120 is reachable. If the slave IC 120 is not reachable, it sends a NACK (not acknowledged) instead of an ACK, and the microcontroller 110 can take appropriate action, such as interrupting the communication.

[0051] - Continue Communication: After receiving the ACK, the microcontroller 110 can send data 143 to the slave device 120 or receive data from the slave device 120 according to the purpose of the communication.

[0052] - End Communication: At the end of the communication, the microcontroller 110 can send a stop condition 144 by pulling the data line (SDA) from a low level to a high level, for example, while the clock line remains at a high level. This signals the end of the transmission.

[0053] The exact order of these steps can vary according to the needs of the communication. The microcontroller 110 can be responsible for controlling these steps and ensuring that the communication proceeds correctly and reliably.

[0054] As Figure 1B shown, the stop condition 144 of the data request command 140 triggers the measurement of the sensor IC 120. Therefore, the stop condition (possibly together with the eighth bit of the address byte) can also be understood as a data request command to the sensor IC 120. In response to the data request command 140, the sensor IC 120 can start measuring the required data 160. This can include detecting information such as temperature, pressure, humidity, light intensity, or other physical parameters. For example, the sensor IC 120 can be designed as a 3D magnetic field sensor and measure the x, y, and z coordinates. If necessary, the sensor IC 120 can also have a temperature sensor and provide temperature measurements.

[0055] In Figure 1A and Figure 1BIn the example shown, an interrupt line (INTN) is provided between the main IC 110 and the slave IC 120. For example, once the measured data 160 is ready in the sensor IC 120, the interrupt line can be pulled, for example, from a high level to a low level (or vice versa) by the sensor IC 120. After the sensor IC 120 signals an interrupt, the sensor IC 120 can transmit the measured data upon request of the microcontroller 110. The data 160 can be sent back to the microcontroller 110 via the I 2 C bus.

[0056] The microcontroller 110 can read the data 160 from the sensor IC 120 as follows:

[0057] - After the interrupt, the microcontroller 110 can send a start condition 151 again as part of the command 150. To this end, the microcontroller 110 can pull the data line (SDA) from a high level to a low level, for example, while the clock line (SCL) remains at a high level, for example. This creates a start condition that can be recognized by all I 2 C devices (such as the slave IC 120) on the bus.

[0058] - Address transmission 152: After generating the start condition, the microcontroller 110 can send the 7-bit address of the slave device (such as the slave IC 120) from which it wants to read data. The eighth bit of the address byte indicates whether the microcontroller wants to receive data (1) from the slave device. In the latter case and in the presence of data 160, the command 150 can be understood as a data read command for the slave device 120, for example.

[0059] - Wait for acknowledgment (ACK / NACK): After sending the address 152, the microcontroller 110 waits for an acknowledgment (ACK) from the slave IC 120. The ACK is a short low level on the data line (SDA), which signals that the slave IC 120 is reachable. If the slave IC 120 is not reachable, it sends a NACK instead of an ACK, and the microcontroller 110 can take appropriate action, such as interrupting the communication.

[0060] - Continue communication: After receiving the ACK, the microcontroller 110 can receive the data 160 from the slave device 120.

[0061] - End communication: At the end of the communication, the microcontroller 110 sends a stop condition 154 by pulling the data line (SDA) from a low level to a high level, for example, while the clock line remains at a high level, for example. This signals the end of the transmission.

[0062] The stop condition 154, like the stop condition 144, can initiate or trigger a new measurement of the sensor data 160. Therefore, both the stop conditions 144 and 154 can be understood as data request commands, and the eighth bit of the address bytes 142 and 152 can be understood as data read commands.

[0063] In the example described in Figure 1A and Figure 1B once the data 160 is ready, due to the interruption, these data can be read by the slave device 120 in a time-optimized manner. This means relatively high communication bandwidth and low power consumption. However, its disadvantage is that an additional hardware consumption is required for the interrupt line (INTN) between the master IC 110 and the slave IC 120.

[0064] Figure 2A and Figure 2B show possible implementation ways of data exchange between the master IC 110 and the slave IC 120 via the I 2 C bus 130 without an interrupt line (INTN). Figure 2A shows an electronic system 200 having a master IC 110 and a slave IC 120. Different from the examples in Figure 1A and Figure 1B there is no interrupt line between the master IC 110 and the slave IC 120 here.

[0065] As in the examples in Figure 1A and Figure 1B the master IC 110 is designed to send a data request command 140 or 144 to the slave IC 120 via the data line (SDA). The slave IC 120 is designed to start providing (measuring) the requested data 160 in response to the data request command 140 or its stop condition 144. The slave IC 120 starts providing or measuring the requested data 160 immediately or directly after the data request command 140 or its stop condition 144. In this example, the master IC 110 is designed to: while measuring the data 160 (i.e., before the measurement data is ready), send a data read command 150 or 152 for reading the requested data to the sensor IC 120. The slave IC 120 is designed to deactivate the clock line (SCL) after receiving the eighth bit of the address byte (data read command) 152 until the slave IC 120 can provide the requested data 160. This concept is called "Clock Stretching". I 2 The I

[0066] C communication protocol is a technology in which the slave device 120 can temporarily "stretch" the clock line (SCL) to slow down or stop the transmission when it is not ready to transfer the data 160. "Clock Stretching" can work as follows:

[0067] Normal clock cycle: In the I 2 C protocol, there is a master IC 110 and one or more slave ICs 120. The master IC controls the clock (SCL) and data (SDA), and one or more slave ICs respond to requests from the master IC 110. The clock cycle is typically controlled by the master IC110 and the communication occurs synchronously with this clock.

[0068] Clock cycle with clock stretching: If the slave IC 120 is not ready to send (or receive) data 160, it can temporarily "stretch" the clock cycle, for example, by pulling the clock line (SCL) low. This signals to the master IC 110 that the slave IC 120 needs more time to prepare or process the data 160. The master IC 110 recognizes the "clock stretching" signal from the slave IC 120 and waits until the clock line (SCL) returns to high. During the "clock stretching", the master IC 110 remains inactive and gives the slave IC 120 the necessary time to complete its task. Once the slave IC 120 is ready, it resets the clock line (SCL) to high and the communication can continue. The master IC 110 continues the clock cycle and the data transfer can occur as normal.

[0069] Clock stretching is an I 2 C protocol feature because it allows the slave device 120 to slow down or stop communication when it cannot process data in real time. This is particularly useful in applications where the slave device 120 may not be able to operate as fast as the master device 110 or there are unforeseen delays. Clock stretching makes the I 2 C communication more reliable and more resistant to delays.

[0070] In the example described in reference Figure 2A and 2B the data 160 can also be read when the slave device 120 is ready. This implies a relatively high communication bandwidth. However, the disadvantage of doing this is high power consumption because current can flow from the power supply VDD to ground through the clock line (SCL) pulled low in the manner shown in Figure 2A . In addition, parallel communication between the master device 110 and other slave devices is not possible.

[0071] Figure 3 Shows another communication possibility between the master device 110 and the slave device 120, where neither an interrupt line (INTN) nor "clock stretching" is required.

[0072] As in the previous example, the master IC 110 is designed here to send data request commands 140, 144 to the slave IC 220 via the data line (SDA). The slave IC 220 is designed to start providing (measuring) the requested data 160 immediately in response to the data request commands 140, 144. However, in this example, the master IC 110 is designed to send data read commands 150, 152 for reading the requested data to the sensor IC 220 after a long, strictly defined waiting time T. The waiting time T between the data request command 140 and the data read command 150 can be chosen long enough to exceed the data providing time (measurement time) and also take into account possible oscillator variations on the clock line (SCL). This can result in a long waiting time and thus a relatively low communication bandwidth.

[0073] In view of the disadvantages of the above example, the present disclosure proposes an electronic system 200 having a master IC 110 and at least one slave IC 120. The electronic system 200 further includes a serial communication interface 230 having a bidirectional data line (SDA) and a clock line (SCL). The communication interface 230 is designed to transfer data between the master IC 110 and the slave IC 120. The master IC 110 is designed to send data request commands 140, 144 to the slave IC 120 via the data line (SDA). The slave IC 120 is designed to start providing (e.g., measuring) the requested data 160 in response to the data request commands 140, 144. The master IC 110 is designed to send data read commands 150, 152 for reading out the requested data 160 to the slave IC 120 via the data line (SDA) after the data request commands 140, 144. The slave IC 120 is designed to: after receiving the data read commands 150, 152, deactivate the clock line (SCL) by means of clock stretching until the slave IC 120 can provide the requested data 160. According to the proposed embodiment, the master IC 110 is designed to measure the duration of the clock line deactivation or the duration of the clock stretching. According to the proposed embodiment, the master IC 110 is designed to set the waiting time between at least one next data request command 154 and the next data read command according to the measured duration. This is as Figure 4 shown.

[0074] Therefore, the proposed process corresponds to a combination of the methods described with reference to Figure 2B and Figure 3 described.

[0075] The master IC 110 is designed to send a data request command 144 to the slave IC 120 via the data line (SDA). The slave IC 120 is designed to start providing (measuring) the requested data 160 in response to the data request command 144. After the data request command 144, the slave IC 120 immediately starts providing or measuring the data 160. The master IC 110 is designed to send a data read command 152 for reading out the requested data to the sensor IC 120 during the measurement or immediately after the data request command 144. Therefore, the time between the data request command 144 and the data read command 152 is shorter than the expected measurement duration. The slave IC 120 is designed to: after receiving the data read command 152, deactivate the clock line (SCL) (clock stretching) until the slave IC 120 can provide the requested data 160 (after the measurement duration). The master IC 110 is designed to measure the duration of the clock stretching and set the waiting time between the next or subsequent data request commands 144, 154 and the next data read commands 142, 152 based on the measured duration of the clock stretching. Between the subsequent data request commands 144, 154 and the subsequent data read commands 142, 152, clock stretching is no longer required due to the set appropriate waiting time.

[0076] Figure 4 The step marked (1) involves data readout with clock stretching and starting the readout immediately after the data request command 144. At (2), the microcontroller 110 measures the clock stretching time and calculates the optimized readout start time (waiting time) after the subsequent data request commands 144, 154 based on this according to (3). If the data 160 is available, this can also cause the immediate readout of the data 160. In addition, the power consumption of the system 200 may be lower than Figure 2B in. Inexpensive I 2 C slaves 120 without an interrupt pin are possible. I 2 C bandwidth can also be increased.

[0077] In Figure 5In the illustrated embodiment, the master IC 110 is designed to send data read commands 150, 152 to the slave IC 120 after the minimum data supply time Tmin specified in the data sheet has elapsed since the data request command 144. The slave IC 120 is designed to deactivate the clock line (SCL) (clock stretching) if the requested data 160 is not yet fully available after the specified minimum data supply time Tmin until the slave IC 120 can supply the requested data 160. The master IC 110 is designed to measure the duration T (clock stretching time) of the deactivated clock line and to set the waiting time between the next data request commands 144, 154 and the next data read commands 142, 152 of the clock line based on the minimum data supply time and the measured clock stretching time. The waiting time between the next data request commands 144, 154 and the next data read commands 142, 152 can basically correspond to the sum of the minimum data supply time and the measured clock stretching time.

[0078] In Figure 5 the illustrated embodiment, the reading of the data 160 starts with clock stretching according to the minimum measurement time Tmin specified in the data sheet (of the sensor IC 120). The microcontroller 110 measures the clock stretching time. The microcontroller 110 calculates the optimized read start time based on this. Then, this optimized read start time can be used for all subsequent measurements and communications, for example.

[0079] In Figure 6 the illustrated embodiment, the master IC 110 is designed to maintain the waiting time between the data request command and the data read command according to Figure 4 or Figure 5 determined for a plurality of subsequent data request commands and subsequent data read commands, and then to determine the updated waiting time again according to Figure 4 or Figure 5 Again.

[0080] Therefore, the embodiment according to Figure 4 or Figure 5 can be combined with the embodiment according to Figure 6 . (1) Accordingly, the reading of the data 160 with clock stretching starts immediately after or after the minimum measurement time specified in the data sheet. (2) The microcontroller 110 measures the clock stretching time. (3) The microcontroller 110 calculates the optimized read start time. (4) This optimized read start time is used for a predetermined number x of measurements without clock stretching. (5) Then return to (1) to update the clock stretching time and repeat steps (2) to (5).

[0081] In Figure 7In the illustrated embodiment, the master IC 110 is designed to use the waiting time set according to Figures 4 to 6 for one of the embodiments in the data request command 144 and the subsequent data read commands 150, 152, and then gradually reduce the waiting time between the additional data request command 144 and the data read commands 150, 152 until a clock stretch is detected again from the IC 120 so that the requested data 160 can be provided on the data line (SDA). The master IC 110 is designed to measure the updated clock stretch and set a re-updated waiting time between the next data request command 144 and the subsequent data read commands 150, 152 based on the measured clock stretch again.

[0082] Therefore, the implementation according to Figures 4 to 6 can be combined with the implementation according to Figure 7 . (1) Start reading data immediately after the minimum measurement time specified in the data sheet or after the minimum measurement time specified in the data sheet. (2) The microcontroller 110 measures the clock stretch time. (3) The microcontroller 110 calculates the optimized read start time and uses the optimized read start time for measurement. (4) Compared with the previous read start time (waiting time), the microcontroller 110 slightly reduces the read start time for each subsequent measurement until a clock stretch gap can be detected. Return to (2).

[0083] Figure 8 A flowchart of the communication method 800 between the master IC 110 and the slave IC 120 is generally shown.

[0084] At 802, the master IC 110 sends the data request commands 140; 144 to the slave IC 120 via the data line (SDA). At 804, the slave IC 120 starts to provide the requested data 160 in response to the data request commands 140; 144. At 806, the master IC 110 sends the data read commands 150; 152 for reading the requested data 160 to the slave IC 120 via the data line after the data request commands 140; 144. In step 808, the slave IC 120 deactivates the clock line (SCL) until the slave IC 120 can provide the requested data 160 after receiving the data read commands 150; 152. In step 810, the master IC 110 measures the duration of the deactivated clock line. In step 812, the master IC 110 sets the waiting time between the next data request commands 140; 144 and the next data read commands 150; 152 based on the measured duration.

[0085] Aspects and features described in connection with a particular one of the previous examples can also be combined with one or more additional examples to replace the same or similar features of the additional example or to additionally introduce that feature into the additional example.

[0086] Examples can further be or relate to a computer program having program code for performing one or more of the above methods when the computer program runs on a computer or a processor. The steps, operations or processes of the various above methods can be executed by a programmed computer or processor. Examples can also cover program storage devices, such as digital data storage media, which are machine, processor or computer readable and which encode a program executable by a machine, executable by a processor or executable by a computer. The commands direct some or all of the steps of the above methods or cause the implementation of these steps. The program storage devices can include or be, for example, digital storage, magnetic storage media such as disks and tapes, hard disk drives or optically readable digital data storage media. Other examples can include computers, processors, control units, field programmable logic arrays ((F)PLAs = (field) programmable logic arrays), field programmable gate arrays ((F)PGAs = (field) programmable gate arrays), graphics processing units (GPUs = graphics processing units), application specific integrated circuits (ASICs = application specific integrated circuits), integrated circuits (ICs = integrated circuits) or systems on a chip (SoCs = systems on a chip), programmed to execute the steps of the above processes.

[0087] It can be understood that the disclosure of multiple steps, processes, operations or functions in the specification and claims may not be constructed in a particular order, unless expressly or implicitly stated otherwise, for example for technical reasons. Thus, the disclosure of multiple actions or functions will not limit them to a particular order, unless these actions or functions are not interchangeable for technical reasons. Additionally, in some examples, a single step, function, process or operation can respectively include and / or can expose multiple sub-steps, sub-functions, sub-processes or sub-operations therein.

[0088] Although some aspects are described in connection with an apparatus or a system, it should be understood that these aspects are also a description of the corresponding method. For example, a block of an apparatus or system or an aspect of a device or function can also correspond to a feature of the corresponding method, such as a method step. Thus, aspects described in connection with a method can also be understood as a description of the corresponding block, corresponding element, property or functional feature of the corresponding apparatus or corresponding system.

[0089] The following claims are hereby incorporated into the detailed description, where each claim can stand on its own as a separate example. Additionally, it should be noted that while dependent claims in the claims refer to a specific combination with one or more other claims, other examples can also include combinations of dependent claims with the subject matter of any other dependent or independent claim. Such combinations are expressly presented herein, unless the specific combination is undesirable. Further, the features of the claims are also included in any other independent claim, even if the claim is not directly defined as being dependent on another independent claim.

Claims

1. An electronic system (200), comprising: Main integrated circuit, main IC (110); From IC(120); a serial communication interface (230) having a bidirectional data line and a clock line, wherein the communication interface (230) is designed to transmit data between the master IC (110) and the slave IC (120), The master IC (110) is designed to send a data request command (140; 144) to the slave IC (120) via the data line. wherein the slave IC (120) is designed to start providing requested data (160) in response to the data request command (140; 144), wherein the master IC (110) is designed to send a data read command (150; 152) for reading the requested data (160) to the slave IC (120) via the data line after the data request command (140; 144), wherein the slave IC (120) is designed to: after receiving the data read command (150; 152), disable the clock line until the slave IC (120) can provide the requested data (160), wherein the master IC (110) is designed to measure the duration of deactivation of the clock line, and The master IC (110) is designed to set a waiting time between a next data request command (140; 144) and a next data read command (150; 152) according to the measured duration.

2. The electronic system (200) according to claim 1, wherein the master IC is designed to: send the data read command to the slave IC after a specified minimum data provision time has passed since the data request command, wherein the slave IC is designed to, if the requested data is not fully available after the specified minimum data provision time, disable the clock line until the slave IC can provide the requested data, wherein the master IC is designed to measure the duration of deactivation of the clock line, and The master IC is designed to set the waiting time between the next data request command and the next data read command according to the minimum data providing time and the measured duration.

3. The electronic system (200) according to any one of the preceding claims, wherein the master IC is designed to maintain the waiting time for a plurality of subsequent data request commands and subsequent data read commands, and then determine an updated waiting time according to any one of the preceding claims.

4. An electronic system (200) according to any one of the preceding claims, wherein the master IC is designed to: use the waiting time set for a data request command and a subsequent data read command, and then gradually reduce the waiting time between the data request command and the data read command until the re-deactivation of the clock line is detected by the slave IC so that the requested data can be provided on the data line.

5. The electronic system (200) according to claim 4, wherein the master IC is designed to measure the duration of re-deactivation of the clock line, and A re-updating waiting time between the next data providing command and the subsequent data reading command is set according to the measured duration.

6. The electronic system (200) of any preceding claim, wherein the master IC comprises a microcontroller.

7. The electronic system (200) of any preceding claim, wherein the slave IC comprises a sensor IC.

8. The electronic system (200) of any preceding claim, wherein the slave IC comprises a magnetic field sensor IC.

9. The electronic system (200) of any preceding claim, wherein the slave IC comprises a 3D Hall sensor IC.

10. The electronic system (200) according to any one of the preceding claims, wherein the serial communication interface comprises an I 2 C communication interface.

11. An integrated circuit IC (110), comprising: a serial communication interface (230) having a bidirectional data line and a clock line, wherein the communication interface (230) is designed to transmit data between the IC (110) and another IC (120) via the data line; and A processor, the processor being designed to: sending a data request command (140; 144) to the other IC (120) via the data line, after a waiting time after the data request command (140; 144), sending a data read command (150; 152) to the other IC via the data line, measuring the duration for which the clock line is disabled by the other IC (120) after the data read command (150; 152), and The waiting time between a next data request command (140; 144) and a subsequent data read command (150; 152) is updated according to the measured duration.

12. The IC (110) of claim 11, wherein the processor is designed to send the data read command (150; 152) to the other IC (120) after a specified minimum data provision time has elapsed from the data request command (140; 144).

13. The IC (110) of claim 11 or 12, wherein the processor is designed to maintain the updated waiting time for a plurality of subsequent data request commands (140; 144) and data read commands (150; 152) and then determine a re-updated waiting time.

14. The IC (110) according to any one of claims 11 to 13, wherein the processor is designed to: The updated waiting time for the next data request command (140; 144) and the next data read command (150; 152) is used, and the waiting time between the data request command (140; 144) and the data read command (150; 152) is then gradually reduced until the re-deactivation of the clock line is detected by the other IC (120).

15. The IC (110) according to any one of claims 11 to 14, wherein the IC (110) is designed as a microcontroller.

16. The IC (110) of any one of claims 11 to 15, wherein the data request command (140; 144) comprises a command (144) for measuring sensor data at a sensor IC (120).

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