Efficient clock tree synthesis method based on two-partition four-branch tree

Abstract

This invention discloses an efficient clock tree synthesis method based on a two-partition, four-branch tree, belonging to the field of integrated circuits. It uses the GBC greedy clustering algorithm to iteratively select points and cluster the flip-flops in the clock tree. Based on the bottom-level clustering, a buffer reselection algorithm with low clock skew is used to reselect buffers according to the principle of near-far pairing. A two-partition, four-branch H-tree structure is used to construct an H-tree at the top level of the clock tree, uniformly inserting a fixed number of buffers along long paths. Geometric Boolean operations are used to adjust the buffer positions. By expanding and gridding the free area, insertable points for buffers are generated. Then, the buffer positions are dynamically adjusted based on the Manhattan rectangle property. This invention effectively improves the efficiency and accuracy of clock tree design by combining multiple strategies such as clustering optimization and buffer position adjustment, and is suitable for clock tree synthesis design of high-performance integrated circuits.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, specifically relating to an efficient clock tree synthesis method based on a two-partition four-branch tree. Background Technology

[0002] Clock tree synthesis (CTS) is a critical step in digital integrated circuit design, playing a vital role in timing design. The main task of the clock tree is to distribute the clock signal from the source node to the various flip-flops (FFs) and logic modules in the circuit, ensuring the signals arrive at the required timings. Clock tree optimization directly impacts system performance, power consumption, and area, especially in the design of high-frequency, large-scale integrated circuits, where the clock tree's performance determines the maximum operating frequency and signal synchronization of the entire system.

[0003] In traditional clock tree synthesis methods, the choice of clock tree structure and buffer (Buf) insertion strategy are key factors determining clock tree performance. Common clock tree structures include H-trees and fishbone trees, each with its own advantages and disadvantages.

[0004] The H-tree structure is one of the most common structures in clock tree synthesis. It possesses good symmetry, effectively reducing clock skew and achieving uniform clock signal delivery. The advantages of the H-tree lie in its simple structure, ease of implementation, and low clock skew in a symmetrical layout, which can well meet the timing requirements of high-frequency circuits. However, the H-tree also has certain limitations, mainly its insufficient flexibility for complex circuits. As the circuit size increases, the depth of the H-tree structure increases, leading to a gradual increase in clock tree delay, affecting system performance.

[0005] The main characteristic of a fishbone tree is that it optimizes the propagation path of the clock signal through multiple shorter paths, thereby significantly reducing the total delay of the clock signal. Compared to the traditional H-tree structure, the fishbone tree can reduce the long-term cumulative delay in signal transmission to a certain extent, especially in multi-level clock paths, where it can effectively reduce clock propagation delay and improve timing performance. However, the design of the fishbone tree focuses on optimizing path delay, and does not specifically balance the clock arrival time of each branch in the clock tree. This may result in the clock skew control effect being less effective than that of an H-tree.

[0006] In clock tree synthesis, the buffer insertion strategy plays a crucial role in clock tree performance. Typically, the goal of buffer insertion is to reduce signal propagation delay and clock tree skew. However, choosing the number, location, and type of buffers is a complex multi-objective optimization problem involving trade-offs between power consumption, area, clock delay, and clock skew. To address this, many studies have proposed buffer insertion methods based on different optimization strategies, such as top-down insertion, local optimization methods, and constraint-based insertion methods. Summary of the Invention

[0007] In summary, this invention proposes a novel clock tree synthesis method based on a two-partition, four-branch tree through innovative algorithms and optimization strategies. This aims to improve clock tree performance and address the challenges faced by traditional clock tree structures in large-scale integrated circuit design. The purpose of this invention is to overcome the shortcomings of existing clock tree optimization methods in terms of clock path delay, clock skew control, and the number of buffers, providing a clock tree synthesis method based on a two-partition, four-branch H-tree-like structure. Considering the area and power consumption issues caused by an excessive number of buffers, a greedy GBC clustering method is used at the bottom layer to maximize buffer fan-out utilization, thereby significantly reducing the number of buffers used. For clock skew and clock delay optimization, a delay-optimized buffer insertion algorithm is combined with top-down H-tree construction to achieve effective control of clock delay under low clock skew. Through a combined bottom-up and top-down optimization strategy, the three key performance indicators of clock tree synthesis are comprehensively improved, and compared with traditional clock tree structures, the flexibility of optimizing different key indicators is increased.

[0008] To achieve the above-mentioned objectives, the present invention employs the following technical solution:

[0009] An efficient clock tree synthesis method based on a two-partition, four-branch H-tree includes the following steps:

[0010] Step 1: Using the GBC greedy clustering algorithm, the greedy strategy iteratively selects points to cluster the flip-flops (FFs) in the clock tree, maximizing the utilization of the buffer fanout and minimizing the number of buffers required.

[0011] Step 2: Based on the underlying clustering, a buffer reselection algorithm with low clock skew is used to reselect the buffers according to the principle of matching near and far buffers, so as to optimize the clock skew and appropriately sacrifice latency to balance the needs of multiple objectives.

[0012] Step 3: A two-partition, four-branch H-tree structure is adopted. An H-tree is built at the top level of the clock tree. By uniformly inserting a fixed number of buffers along the long path, low clock skew is ensured while effectively reducing latency along the path.

[0013] Step four involves adjusting the buffer positions using geometric Boolean operations. This is achieved by expanding the free area and dividing it into grids to generate insertable points for the buffers. Then, based on the Manhattan rectangle property, the buffer positions are dynamically adjusted to optimize local clock tree metrics while avoiding buffer overlap.

[0014] As an efficient clock tree synthesis method based on a two-partition, four-branch H-tree, the first step of clustering the clock tree triggers is as follows:

[0015] The GBC greedy clustering algorithm iteratively selects flip-flops from the clock tree based on a greedy strategy and clusters them. During clustering, the algorithm considers the connectivity between flip-flops, fan-out, and resource requirements of the buffers, maximizing the fan-out utilization of the buffers to effectively reduce the number of buffers required. Each flip-flop in a cluster is treated as an independent clustering unit, reducing the complexity of the subsequent synthesis algorithm.

[0016] As an efficient clock tree synthesis method based on a two-partition, four-branch H-tree, step two, which optimizes the clock skew using a low-clock-skew buffer reselection algorithm, is as follows:

[0017] Based on flip-flop clustering, a low-clock-skew buffer reselection algorithm is used to reselect the selected buffers. A "near-far pairing" principle is adopted, meaning the buffer positions are optimized and adjusted according to the relative distance between the flip-flops and the buffers to minimize clock skew. In this process, some clock path delay is appropriately sacrificed to balance the multiple objectives of clock skew control and clock path delay.

[0018] As an efficient clock tree synthesis method based on a two-partition, four-branch H-tree, step three involves constructing the clock tree using a two-partition, four-branch H-tree structure as follows:

[0019] A two-partition, four-branch H-tree-like structure is used at the top level of the clock tree to construct its trunk. The H-tree-like structure effectively reduces latency on long paths by uniformly inserting a fixed number of buffers along the clock path. In the two-partition, four-branch structure, the clock path is rationally partitioned, and symmetrical buffers are allocated to control the clock signal offset, thereby further improving the timing performance of the clock tree.

[0020] As an efficient clock tree synthesis method based on a two-partition, four-branch H-tree, step four involves adjusting the buffer position using geometric Boolean operations:

[0021] Geometric Boolean operations are used to optimize and adjust the positions of buffers. During the clock tree layout process, the insertion points of buffers are extracted by expanding the free area and dividing it into grids. Based on the Manhattan rectangle property, the positions of buffers are dynamically adjusted to avoid buffer overlap while ensuring the optimization of key indicators of the clock tree within local areas.

[0022] The present invention, by adopting the above technical solution, has the following beneficial effects:

[0023] (1) This invention proposes an efficient clock tree synthesis method based on a two-partition four-branch H-tree. By using the GBC greedy clustering algorithm, the number of buffers required to build the clock tree at the bottom layer is reduced as much as possible while satisfying the constraints, thereby reducing the algorithm complexity of the later synthesis and improving the program running speed.

[0024] (2) By constructing a two-partition four-branch H-tree and combining it with a long path delay optimization algorithm, this invention effectively optimizes the global delay of the clock tree from top to bottom while keeping the clock deviation extremely low, thus greatly improving the overall performance of the clock tree. Attached Figure Description

[0025] The accompanying drawings are included as part of the specification to further understand the invention, and, together with the embodiments of the invention, are used to explain the invention but do not constitute a limitation thereof;

[0026] Figure 1 This is a flowchart of the efficient clock tree synthesis method based on a two-partition, four-branch H-tree according to the present invention;

[0027] Figure 2 This is a schematic diagram of the two-partition, four-branch H-tree established by this invention;

[0028] Figure 3 This is a schematic diagram of the buffer reselection algorithm based on low clock skew of the present invention;

[0029] Figure 4 This is a schematic diagram of the buffer position adjustment based on geometric Boolean operations according to the present invention;

[0030] Figure 5 middle Figure 5-1 To optimize the curve for the number of inserted BUFs, taking case 10 as an example, Figure 5-2 It is a piecewise function. Detailed Implementation

[0031] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0032] To make the inventive objectives, technical features, and advantages of this invention more apparent and understandable, the specific embodiments of this invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this invention.

[0033] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0034] The invention will now be further described with reference to the accompanying drawings.

[0035] 1) GBC Greedy Clustering Algorithm

[0036] First, determine the number of regions based on the given layout dimensions and the number of fanouts (FFs). Then, select the FF furthest from the region center in each region as the initial cluster point. Greedily select neighboring FFs to join the cluster and check the max_fanout and max_rc constraints. If they are not satisfied, set the point as a new class. Repeat the above steps until all points have been assigned to clusters. Here, FF is the trigger, max_fanout is the maximum fanout, and max_rc is the maximum resistance / capacitance.

[0037] 2) Construction of a two-partition, four-branch H-tree

[0038] Traditional H-tree structures are simple, so we constructed a structure like... Figure 2 The H-tree-like structure shown allows for more flexible adjustment of buffer positions while maintaining low clock skew. In fact, the construction of an H-tree relies heavily on long-path buffer insertion algorithms. Experiments demonstrate that inserting a fixed number of buffers along a given path effectively reduces clock latency. Based on this, the mean-mean-mean inequality derives that uniformly inserting buffers along the same path yields the lowest clock latency for that path. Taking the insertion of a single buffer as an example, ensuring that the Manhattan distance from buffer A to buffer B equals the Manhattan distance from buffer B to buffer C optimizes the clock latency for the current path. Overall, the H-tree-like structure optimizes clock latency from top to bottom.

[0039] 3) Long-path buffer insertion delay optimization algorithm

[0040] Analyzing the definitions of buffer delay and net unit delay given in the problem, we can conclude that inserting a fixed number of buffers (BUFs) can effectively reduce latency for a given path. The derivation of the number and position of these BUFs is as follows:

[0041] The latency 1 for a certain path without inserting a buffer: In equation (2) above, r is the resistance per unit length, c is the capacitance per unit length, D is the Manhattan distance between the two points, and k is a defined constant. The latency 2 of a certain path when n buffers are inserted is: In equation (3) above, r is the resistance per unit length, c is the capacitance per unit length, D is the Manhattan distance of the path between the two points, and k is a defined constant. According to the mean inequality, when inserting BUFs on the same path, the lowest delay can be obtained under the current conditions when the BUFs are uniformly distributed. Therefore, the method of uniformly inserting BUFs is adopted. The following is the derivation of the optimal number of insertions:

[0042] To satisfy this condition, the following relation exists: In equation (4) above, k is a defined constant, D is the Manhattan distance of the path between two points, and n is the number of buffers inserted in the path. Solving for a certain Manhattan distance D yields the optimal number of insertions. : Since the number of insertions, n, is discrete, the number of BUFs to be inserted in the current path can be determined by traversal. Figure 5 To optimize the curve for the number of inserted BUFs, taking case 10 as an example ( Figure 5-1 ), Figure 5-2 It is a piecewise function.

[0043] Therefore, in the subsequent clock tree synthesis algorithm, the piecewise function curve is first calculated using the values ​​given in the problem, and the number of buffers inserted at different distance segments is adjusted using a lookup table.

[0044] The above specific implementation methods and embodiments are specific support for the technical ideas proposed in this invention, and should not be used to limit the scope of protection of this invention. Any equivalent changes or modifications made based on the technical solutions of this invention in accordance with the technical ideas proposed in this invention shall still fall within the scope of protection of this invention.

Claims

1. A high-efficiency clock tree synthesis method based on a two-partition four-branch tree, characterized in that, Includes the following steps: Step 1: Using the GBC greedy clustering algorithm, the triggers in the clock tree are clustered by iteratively selecting points using a greedy strategy. Step 2: Based on the underlying clustering, a buffer reselection algorithm based on low clock skew is used to reselect the buffers according to the principle of pairing near and far nodes. Step 3: Using a two-partition, four-branch H-tree structure, construct an H-tree at the top level of the clock tree and insert a fixed number of buffers evenly along the long path. Step 4: Adjust the position of the buffer using geometric Boolean operations. By expanding the free area and dividing it into grids, insertable points for the buffer are generated. Then, the position of the buffer is dynamically adjusted based on the Manhattan rectangle property. In step four, the application of geometric Boolean operations expands the design region and then divides the design region into buffer-sized grids to generate buffer insertion points. In step four, when inserting BUFs along the same path, a uniform BUF distribution yields the lowest latency under the current conditions. Therefore, a uniform BUF insertion method is adopted to obtain the optimal number of insertions for a given Manhattan distance D. : （1） In equation (1) above, n is the number of buffers inserted, and k is a constant. delay buf The intrinsic delay of the buffer is determined by traversing the path to determine the number of BUFs inserted in the current path, since the number of insertions variable n is discrete.

2. The efficient clock tree synthesis method based on a two-partition four-branch tree according to claim 1, characterized in that, In step one, the GBC greedy clustering algorithm iteratively selects suitable points by not requiring the initial number of clusters to be specified.

3. The efficient clock tree synthesis method based on a two-partition four-branch tree according to claim 2, characterized in that, First, determine the number of regions based on the given map dimensions and the number of FFs. Then, select the FF farthest from the region center in each region as the initial cluster point. Greedily select neighboring FFs to join the cluster and check the max_fanout and max_rc constraints. If they are not satisfied, set the point as a new class. Repeat the above steps until all points have been assigned to clusters.

4. The efficient clock tree synthesis method based on a two-partition four-branch tree according to claim 1, characterized in that, In step two, the buffer reselection algorithm based on low clock skew optimizes the buffer position by matching the clustering results based on the principle of proximity. Specifically, it connects the buffers far from the center point of the clock tree to the buffers near the center point.

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