Method for configuring buffer and image synthesis device

Abstract

The invention discloses a method for configuring a buffer and an image synthesis device. The image synthesis apparatus includes a memory including a plurality of column buffers, and the method includes the following steps. According to a plurality of depths of a plurality of target planes, each target column buffer is divided into a plurality of sections for respectively storing column pixel information of the plurality of target planes. The plurality of sections respectively correspond to a plurality of depths of a plurality of target planes.

Description

Technical Field

[0001] The present invention relates to a technical solution for sharing a line buffer, and more particularly to a method for configuring a buffer and an image synthesis device, which can configure each target line buffer in a memory into multiple segments to store column (row) pixel information of multiple target planes respectively. Background Art

[0002] A set-top box usually has an image synthesis device for processing multiple videos and multiple graphics, and each video or graphic can be regarded as a plane. In addition, the image synthesis device includes a memory, and the memory includes multiple line buffers for storing display information of multiple planes.

[0003] However, the size of each line buffer is fixed, and each line buffer is usually used to store column pixel information of a single plane. Therefore, if it is necessary to simultaneously display multiple planes through the image synthesis device, a larger number of line buffers are required, resulting in a significant increase in the cost of the memory. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a method for configuring a buffer and an image synthesis device in view of the deficiencies of the prior art, which can configure each target line buffer in a memory into multiple segments to store column pixel information of multiple target planes respectively.

[0005] To solve the above technical problem, one of the technical solutions adopted by the present invention is to provide a method for configuring a buffer. The method is applicable to an image synthesis device, the image synthesis device includes a memory, the memory includes multiple line buffers, and the method includes the following steps: configuring the image synthesis device to obtain display information of multiple planes, and multiple depths respectively corresponding to multiple planes; determining whether a first number of multiple planes is a fixed number of planes; and in response to determining that the first number of multiple planes is a fixed number of planes, for multiple target line buffers among multiple line buffers, dividing each target line buffer into multiple segments in a first configuration mode. The step of dividing each target line buffer into multiple segments in the first configuration mode includes: setting a second number of multiple target planes among multiple planes; setting multiple ratios of the sizes occupied by the column pixel information of multiple planes in the target line buffer respectively to determine multiple target planes among multiple planes; calculating multiple depths of multiple target planes according to multiple ratios of multiple target planes; and dividing each target line buffer into multiple segments according to multiple depths of multiple target planes to store column pixel information of multiple target planes respectively. Multiple segments respectively correspond to multiple depths of multiple target planes.

[0006] To solve the above technical problems, another technical solution adopted by the present invention is to provide an image synthesis device. The image synthesis device includes a memory and a processing circuit. The memory includes a plurality of column buffers. The processing circuit is coupled to the memory and is configured to perform the following steps: configuring the image synthesis device to obtain display information of a plurality of planes, and a plurality of depths respectively corresponding to the plurality of planes; determining whether a first number of the plurality of planes is a fixed number of planes; and in response to determining that the first number of the plurality of planes is the fixed number of planes, dividing each of the plurality of target column buffers among the plurality of column buffers into a plurality of sections in a first configuration mode. The step of dividing each target column buffer into a plurality of sections in the first configuration mode includes: setting a second number of a plurality of target planes among the plurality of planes; setting a plurality of ratios of the sizes of the column pixel information of the plurality of planes respectively occupying the target column buffer to determine the plurality of target planes among the plurality of planes; calculating a plurality of depths of the plurality of target planes according to the plurality of ratios of the plurality of target planes; and dividing each target column buffer into a plurality of sections according to the plurality of depths of the plurality of target planes for respectively storing the column pixel information of the plurality of target planes. The plurality of sections respectively correspond to the plurality of depths of the plurality of target planes.

[0007] To enable a further understanding of the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the provided drawings are only for reference and illustration, and are not used to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a functional block diagram of an image synthesis device according to an embodiment of the present invention.

[0009] Figure 2 is a flowchart of steps of a method for configuring a buffer according to an embodiment of the present invention.

[0010] Figure 3 is a flowchart of steps of dividing each target column buffer into a plurality of sections in a first configuration mode according to an embodiment of the present invention.

[0011] Figure 4A and Figure 4B is a flowchart of steps of dividing each target column buffer into a plurality of sections in a second configuration mode according to an embodiment of the present invention.

[0012] Figure 5A is a schematic diagram of simultaneously displaying a plurality of target planes through an image synthesis device according to a first embodiment of the present invention.

[0013] Figure 5B is a schematic diagram of simultaneously displaying a plurality of target planes through an image synthesis device according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014] The following are specific embodiments to illustrate the implementation manners of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content provided in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Additionally, the drawings of the present invention are only for simple schematic illustration and are not drawn according to actual sizes, hereby stating in advance. The following embodiments will further detail the related technical content of the present invention, but the content provided is not used to limit the protection scope of the present invention.

[0015] Please refer to Figure 1 and Figure 2 , Figure 1 which is a functional block diagram of an image synthesis device according to an embodiment of the present invention, Figure 2 and Figure 1 which is a flowchart of steps of a method for configuring a buffer according to an embodiment of the present invention. As

[0016] shown, the image synthesis device 1 of this embodiment includes a memory 11 and a processing circuit 13. The memory 11 can be a Static Random - Access Memory (SRAM), and includes a plurality of column buffers 11_1 to 11_m, that is, m is an integer greater than 1.

[0016] The processing circuit 13 is coupled to the memory 11. The processing circuit 13 can be implemented by hardware (such as a central processing unit and a computer memory) in combination with software and / or firmware. However, the present invention does not limit the specific implementation manner of the processing circuit 13. Additionally, the processing circuit 13 is configured to execute the method for configuring a buffer of this embodiment. As Figure 2 shown, the method of this embodiment includes the following steps.

[0017] Step S101: Configure the image synthesis device to obtain display information of multiple planes, and multiple depths respectively correspond to the multiple planes.

[0018] Specifically, the image synthesis device 1 can be, for example, disposed in a display. The display screen of the display can be divided into multiple regions, and each region can display a video or a graphic. Therefore, each video or graphic can correspond to the displayed region as a plane. Thus, when the image synthesis device 1 needs to display multiple planes simultaneously, the multiple planes can include multiple video planes and multiple graphic planes. For the convenience of the following description, this embodiment takes the image synthesis device 1 obtaining display information of six planes as an example, and these six planes include four video planes P1 to P4 and two graphic planes P5 to P6, but the present invention is not limited thereto.

[0019] Step S102: Determine whether the first quantity of multiple planes is the fixed number of planes. If so, the method proceeds to step S110; if not, the method proceeds to step S120.

[0020] Step S110: For multiple target column buffers among multiple column buffers, divide each target column buffer into multiple sections in a first configuration mode.

[0021] Step S120: For multiple target column buffers among multiple column buffers, divide each target column buffer into multiple sections in a second configuration mode.

[0022] Further, please also refer to Figure 3 , Figure 3 which is the flowchart of the step of dividing each target column buffer into multiple sections in the first configuration mode in an embodiment of the present invention. As Figure 3 shown, step S110 includes the following steps.

[0023] Step S111: Set the second quantity of multiple target planes among multiple planes.

[0024] Step S112: Set multiple ratios of the sizes of the column pixel information of multiple planes respectively occupying the target column buffer to determine multiple target planes among multiple planes.

[0025] Specifically, the processing circuit 13 can set the image synthesizing device 1 to simultaneously display some or all of multiple planes, and each plane simultaneously displayed by the image synthesizing device 1 can be called a target plane. Therefore, the second quantity of multiple target planes is less than or equal to the first quantity of multiple planes.

[0026] Please also refer to Figure 5A and Figure 5B . Taking the foregoing content as an example, although the image synthesizing device 1 obtains the display information of six planes P1 to P6, in the Figure 5A embodiment, if only the video plane P1, the video plane P2, and the graphic plane P5 need to be simultaneously displayed through the image synthesizing device 1 (that is, only some of these six planes P1 to P6 need to be simultaneously displayed), the processing circuit 13 can set the second quantity of target planes to 3, and according to the actual image quality and requirements of the video plane P1, the video plane P2, and the graphic plane P5, set multiple ratios of the sizes of the column pixel information of the planes P1 to P6 respectively occupying the target column buffer to be 1 / 2, 1 / 4, 0, 0, 1 / 4, and 0.

[0027] In other words, when the ratio of the size of the column pixel information of a certain plane occupying the target column buffer is set to 0, it means that the display of that plane is temporarily not required. Therefore, there is no need to allocate or reserve storage space in the target column buffer for the column pixel information of that plane. However, the present invention is not limited to the above example.

[0028] In contrast, in Figure 5B the embodiment, if all six planes P1 to P6 need to be simultaneously displayed by the image synthesis device 1, the processing circuit 13 can set the second number of target planes to 6, and set a plurality of ratios of the sizes of the column pixel information of the planes P1 to P6 respectively occupying the target column buffer according to the actual image quality and requirements of the planes P1 to P6. Since the relevant details have been described above, they will not be elaborated here.

[0029] Step S113: Calculate the depths of a plurality of target planes according to the plurality of ratios of the plurality of target planes.

[0030] Step S114: Divide each target column buffer into a plurality of sections according to the depths of the plurality of target planes to respectively store the column pixel information of the plurality of target planes.

[0031] Specifically, the depth of each target plane is calculated by the following mathematical formula:

[0032]

[0033] D p is the depth of the p-th target plane, TD is the size of the target column buffer, R p is the ratio of the p-th target plane, R k is the ratio of the k-th target plane, and n is the second number of the plurality of target planes. For the convenience of the following description, in this embodiment, the column buffer 11_1 is taken as one of the target column buffers as an example, and the plurality of target planes are represented by TP 1 ~TP n to represent.

[0034] Therefore, in step S113, the processing circuit 13 can calculate the depths D 1 ~D n of the target planes TP 1 ~TP n according to the ratios R 1 ~R n of the target planes TP 1 ~TP n . However, Figure 1 the target planes TP 1 ~TP n , the ratios R 1 ~R nand depth D 1 ~D n .

[0035] Further, according to the target plane TP 1 ~TP n Depth D 1 ~D n , the processing circuit 13 may divide each target column buffer into segments SC 1 ~SC n To store the target plane TP separately 1 ~TP n In this embodiment, each target column buffer has a segment SC 1 ~SC n Can correspond to the target plane TP respectively 1 ~TP n Depth D 1 ~D n .

[0036] by Figure 5A As an example, the video plane P1, the video plane P2 and the graphics plane P5 will be respectively used as the first target plane TP 1 , the second target plane TP 2 and the third target plane TP 3 Therefore, when the target column buffer size is 3840 pixels, the first target plane TP 1 (ie, the depth D of the video plane P1) 1 It can be calculated as 1920 pixels using the above mathematical formula.

[0037] In addition, the second target plane TP 2 and the third target plane TP 3 (ie, the depth D of the video plane P2 and the graphics plane P5) 2 and D 3 Therefore, the processing circuit 13 can divide each target column buffer into three sections SC of 1920 pixels, 960 pixels and 960 pixels. 1 ~SC 3 To store the target plane TP separately 1 ~TP 3 However, the present invention is not limited to the above example.

[0038] It should be noted that, in the first configuration mode, each target column buffer is divided into segments SC 1 ~SC nIn this case, the processing circuit 13 can set the target plane TP through a Graphical User Interface (GUI). 1 ~TP n The second quantity ratio R 1 ~R n , but the present invention is not limited thereto. That is to say, in the first configuration mode, the processing circuit 13 can dynamically set the target plane TP 1 ~TP n The depth D 1 ~D n . However, the depth D of the target plane TP 1 ~TP n The depth D 1 ~D n Can also be fixed.

[0039] Therefore, in this embodiment, multiple information structures can also respectively correspond to multiple planes, and the information structure of each plane records the depth of that plane. In addition, please also refer to Figure 4A and Figure 4B , Figure 4A and Figure 4B is a flowchart of the steps of dividing each target column buffer into multiple sections in the second configuration mode of the embodiment of the present invention. As Figure 4A shown, step S120 includes the following steps.

[0040] Step S121: Read the multiple information structures of the multiple planes to obtain the multiple depths of the multiple planes, and obtain the total depth of the multiple planes.

[0041] Taking the embodiment of Figure 1 as an example, six information structures Str1~Str6 can respectively correspond to planes P1~P6. Therefore, in step S121, the processing circuit 13 can read the information structures Str1~Str6 to obtain the multiple depths of planes P1~P6, and obtain the total depth of planes P1~P6. However, Figure 1 The information structures Str1~Str6 are not shown either.

[0042] Step S122: Determine whether the total depth of the multiple planes exceeds the size of the target column buffer. If not, the method proceeds to step S123; if so, the method proceeds to step S124.

[0043] Step S123: Take all the planes as target planes, and divide each target column buffer into multiple sections according to the multiple depths of the multiple target planes to respectively store the column pixel information of the multiple target planes.

[0044] Taking Figure 1Taking the embodiment as an example, if the total depth of planes P1 to P6 does not exceed the size of the target column buffer, the processing circuit 13 can use all of the planes P1 to P6 as the target planes TP 1 ~TP 6 and, according to the depth D 1 ~D 6 of the target planes TP 1 ~D 6 (i.e., the multiple depths of planes P1 to P6 obtained by reading the information structures Str1 to Str6), divide each target column buffer into sections SC 1 ~SC 6 for storing the column pixel information of the target planes TP 1 ~TP 6 respectively.

[0045] On the contrary, if the total depth of planes P1 to P6 exceeds the size of the target column buffer, the processing circuit 13 can only determine some of the planes from planes P1 to P6 as the target planes TP 1 ~TP n . To achieve the above object, the information structures Str1 to Str6 also respectively record the multiple priorities of planes P1 to P6. In addition, as Figure 4B shown, step S124 includes the following steps.

[0046] Step S1241: Rank the multiple planes in descending order of the multiple priorities.

[0047] Step S1242: Determine whether the depth of the k-th ranked plane does not exceed the remaining size of the target column buffer. If so, the method proceeds to steps S1243 and S1244 in sequence; if not, the method directly proceeds to step S1244.

[0048] Specifically, k is a variable starting from 1, and when the method first enters step S126, the remaining size of the target column buffer is the original size of the target column buffer. Taking the foregoing content as an example, when the method first enters step S126, the remaining size of the target column buffer is 3840 pixels.

[0049] Step S1243: Use the k-th ranked plane as one of the target planes, and according to the depth of the k-th ranked plane, determine one of the sections of each target column buffer and update the remaining size of the target column buffer.

[0050] Step S1244: Determine whether the k-th plane after ranking is the last plane after ranking. If so, the method proceeds to step S1245, which is the end of the process; if not, the method proceeds to step S1246 to update the value of k, that is, increment k by 1, and after step S1246, the method returns to step S1242.

[0051] Taking the foregoing content as an example, if the video plane P1 is the first plane after ranking, and the depth of the video plane P1 is 1920 pixels and does not exceed the current remaining size of the target column buffer (i.e., 3840 pixels), the processing circuit 13 can use the video plane P1 as the first target plane TP. 1 In addition, according to the depth of the video plane P1, the processing circuit 13 can determine the section SC of each target column buffer. 1 is 1920 pixels, and update the remaining size of the target column buffer to the result of 3840 pixels minus 1920 pixels (i.e., 1920 pixels).

[0052] As previously mentioned, the section SC 1 will be used to store the column pixel information of the video plane P1. Then, if the video plane P3 is the second plane after ranking, but the depth of the video plane P3 exceeds the current remaining size of the target column buffer (i.e., 1920 pixels), the processing circuit 13 will not use the video plane P3 as one of the target planes, but will make a judgment on the third plane after ranking.

[0053] Similarly, if the video plane P2 is the third plane after ranking, and the depth of the video plane P2 is 960 pixels and does not exceed the current remaining size of the target column buffer (i.e., 1920 pixels), the processing circuit 13 can use the video plane P2 as the second target plane TP. 1 In addition, according to the depth of the video plane P2, the processing circuit 13 can determine the section SC of each target column buffer. 2 is 960 pixels, and update the remaining size of the target column buffer to the result of 1920 pixels minus 960 pixels (i.e., 960 pixels). Since the subsequent details are the same as the foregoing content, they will not be elaborated here.

[0054] In other words, for each ranked plane in sequence, the processing circuit 13 can determine whether the depth of the current plane does not exceed the remaining size of the target column buffer. Additionally, in response to determining that the depth of the current plane does not exceed the remaining size of the target column buffer, the processing circuit 13 can use the current plane as one of the target planes and determine one of the segments of each target column buffer according to the depth of the current plane. Therefore, in the case where the first quantity of multiple planes is not the fixed number of planes (i.e., new planes can be added), the processing circuit 13 can optimize the space utilization of the target column buffer in the second configuration mode.

[0055] On the other hand, the image synthesizing apparatus 1 may further include a decompression circuit, a scaling circuit, etc. ( Figure 1 not shown in the figures) for processing multiple videos and multiple graphics to update the display information of multiple planes. Therefore, the multiple segments into which each target column buffer is divided can also be temporarily used to store the column pixel information of multiple target planes processed by a decompression circuit, a scaling circuit, etc., respectively.

[0056] In summary, one beneficial effect of the present invention is that the method for configuring a buffer and the image synthesizing apparatus provided by the present invention can achieve the technical effect of sharing a column buffer by the technical means of "dividing each target column buffer into multiple segments according to the multiple depths of multiple target planes to store the column pixel information of multiple target planes respectively", and thus avoid increasing the cost of the memory.

[0057] Furthermore, the method for configuring a buffer and the image synthesizing apparatus provided by the present invention can divide each target column buffer into multiple segments in the first configuration mode or the second configuration mode. In the first configuration mode, the method for configuring a buffer and the image synthesizing apparatus provided by the present invention can dynamically set the multiple depths of multiple target planes by the technical means of "setting multiple ratios of the sizes of the column pixel information of multiple planes occupying the target column buffer respectively". Additionally, in the second configuration mode, the method for configuring a buffer and the image synthesizing apparatus provided by the present invention can optimize the space utilization of the target column buffer by the technical means of "reading multiple information structures of multiple planes to obtain the multiple depths of multiple planes", "responding to determining that the total depth of multiple planes exceeds the size of the target column buffer, ranking multiple planes in the order of multiple priorities from high to low", "for each ranked plane in sequence, determining whether the depth of the plane does not exceed the remaining size of the target column buffer", and "responding to determining that the depth of the plane does not exceed the remaining size of the target column buffer, using the plane as one of the target planes and determining one of the segments of each target column buffer according to the depth of the plane".

[0058] The content provided above is only a preferred and feasible embodiment of the present invention, and does not limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made by using the content of the specification and drawings of the present invention are included in the scope of the patent application of the present invention.

[0059]

Symbol Explanation

[0060] 1: Image synthesis device

[0061] 11: Memory

[0062] 11_1~11_m: Column buffer

[0063] 13: Processing circuit

[0064] P1~P6: Plane

[0065] SC 1 ~SC n : Section

[0066] S101, S102, S110, S120, S111~S114, S121~S124, S1241~S1246: Steps.

Claims

1. A method for configuring a buffer, applicable to an image synthesis device, the image synthesis device including a memory, the memory including a plurality of column buffers, and the method comprises: Configuring the image synthesis device to obtain display information of a plurality of planes, and a plurality of depths respectively corresponding to the plurality of planes; Determining whether a first quantity of the plurality of planes is a fixed quantity of planes; and In response to determining that the first quantity of the plurality of planes is the fixed quantity of planes, for a plurality of target column buffers among the plurality of column buffers, dividing each of the target column buffers into a plurality of segments in a first configuration mode; wherein, the step of dividing each of the target column buffers into the plurality of segments in the first configuration mode includes: Setting a second quantity of a plurality of target planes among the plurality of planes; Setting ratios of column pixel information of the plurality of planes respectively occupying a size of the target column buffer to determine the plurality of target planes among the plurality of planes; Calculating the plurality of depths of the plurality of target planes according to the ratios of the plurality of target planes; and Dividing each of the target column buffers into the plurality of segments according to the plurality of depths of the plurality of target planes for respectively storing the column pixel information of the plurality of target planes, wherein the plurality of segments respectively correspond to the plurality of depths of the plurality of target planes.

2. The method according to claim 1, wherein, The depth of each of the target planes is calculated by the following mathematical formula: where D p is the depth of the p-th target plane, TD is the size of the target column buffer, R p is the ratio of the p-th target plane, R k is the ratio of the k-th target plane, and n is the second number of the plurality of target planes.

3. The method according to claim 1, further comprises: In response to determining that the first quantity of the plurality of planes is not the fixed quantity of planes, for the plurality of target column buffers among the plurality of column buffers, dividing each of the target column buffers into the plurality of segments in a second configuration mode.

4. The method according to claim 3, wherein, A plurality of information structures also respectively correspond to the plurality of planes, and the information structure of each plane records the depth of the plane.

5. The method according to claim 4, wherein, The step of dividing each of the target column buffers into the plurality of segments in the second configuration mode includes: Reading the plurality of information structures of the plane to obtain the plurality of depths of the plurality of planes, and obtaining a total depth of the plurality of planes; Determining whether the total depth of the plurality of planes exceeds the size of the target column buffer; and In response to determining that the total depth of the plurality of planes does not exceed the size of the target column buffer, taking all of the plurality of planes as the plurality of target planes, and dividing each of the target column buffers into the plurality of segments according to the plurality of depths of the plurality of target planes for respectively storing the column pixel information of the plurality of target planes.

6. The method according to claim 5, wherein, The plurality of information structures also respectively record a plurality of priorities of the plurality of planes, and the step of dividing each of the target column buffers into the plurality of segments in the second configuration mode further includes: In response to determining that the total depth of the plurality of planes exceeds the size of the target column buffer, ranking the plurality of planes in descending order according to the plurality of priorities; For each of the ranked planes in sequence, determine whether the depth of the plane does not exceed a remaining size of the target column buffer; and In response to determining that the depth of the plane does not exceed the remaining size of the target column buffer, take the plane as one of the target planes, and determine one of the sections of each target column buffer according to the depth of the plane, where the section is used to store the column pixel information of the plane.

7. An image synthesis device comprising: a memory including a plurality of column buffers; and a processing circuit coupled to the memory and configured to perform the following steps: Configure the image synthesis device to obtain display information of a plurality of planes, and a plurality of depths respectively correspond to the plurality of planes; Determine whether a first quantity of the plurality of planes is a fixed quantity of planes; and In response to determining that the first quantity of the plurality of planes is the fixed quantity of planes, divide each of the target column buffers among the plurality of column buffers into a plurality of sections in a first configuration mode; wherein the step of dividing each of the target column buffers into the plurality of sections in the first configuration mode includes: Set a second quantity of a plurality of target planes among the plurality of planes; Set a plurality of ratios of the column pixel information of the plurality of planes respectively occupying a size of the target column buffer to determine the plurality of target planes among the plurality of planes; Calculate the plurality of depths of the plurality of target planes according to the plurality of ratios of the plurality of target planes; and Divide each of the target column buffers into the plurality of sections according to the plurality of depths of the plurality of target planes to be used to store the column pixel information of the plurality of target planes respectively, where the plurality of sections respectively correspond to the plurality of depths of the plurality of target planes.

8. The image synthesis device according to claim 7, wherein the depth of each of the target planes is calculated by the following mathematical formula: where D p is the depth of the p-th such target plane, TD is the size of the target column buffer, R p is the ratio of the p-th such target plane, R k is the ratio of the k-th such target plane, and n is the second quantity of the plurality of target planes.

9. The image synthesis device according to claim 7, wherein the processing circuit is further configured to perform the following steps: In response to determining that the first quantity of the plurality of planes is not the fixed quantity of planes, divide each of the target column buffers among the plurality of column buffers into the plurality of sections in a second configuration mode.

10. The image synthesis device according to claim 9, wherein a plurality of information structures respectively correspond to the plurality of planes, and the information structure of each plane records the depth of the plane.

Images