Display device

Abstract

There is provided a display device including: a display panel including a pixel, in which the pixel includes: a light emitting element including a cathode and an anode connected with a first power line; a first transistor connected between the cathode and the second power line, and configured to operate based on a potential of the first node; a second transistor connected between the first node and a data line, and configured to receive a first scan signal; a third transistor connected between the first node and a reference voltage line, and configured to receive a second scan signal; and a fourth transistor connected between the first transistor and the first power line.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2023-0179771, filed with the Korean Intellectual Property Office on December 12, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Embodiments of the present disclosure described herein relate to a display device, and more particularly, to a display device having improved display quality. Background Art

[0003] Among display devices, emissive display devices use light-emitting elements that generate light through the recombination of electrons and holes to display images. Emissive display devices have a high response speed and are driven at low power consumption.

[0004] An emissive display device includes pixels connected to data lines and scan lines. Generally, each of the pixels includes a light-emitting element and a pixel circuit for controlling the amount of current flowing through the light-emitting element. The pixel circuit controls the amount of current flowing through the light-emitting element in response to a data signal. At this time, light having a certain brightness is generated according to the amount of current flowing through the light-emitting element. Summary of the Invention

[0005] Embodiments of the present disclosure provide a display device having improved display quality.

[0006] Embodiments of the present disclosure provide a display device having reduced power consumption.

[0007] According to one or more embodiments, a display device includes: a display panel including pixels, wherein the pixels include: a light-emitting element including a cathode and an anode connected to a first power line; a first transistor connected between the cathode and a second power line and configured to operate based on the potential of a first node; a second transistor connected between the first node and a data line and configured to receive a first scan signal; a third transistor connected between the first node and a reference voltage line and configured to receive a second scan signal; and a fourth transistor connected between the first transistor and the first power line.

[0008] The second scan signal has an active level during a first initialization period, and the first scan signal has an inactive level during the first initialization period, and wherein the second scan signal has an active level during a compensation period, and the first scan signal has an inactive level during the compensation period.

[0009] The fourth transistor is configured to receive a third scan signal, and wherein the third scan signal has an inactive level during the first initialization period and has an active level during the compensation period.

[0010] The fourth transistor is configured to receive a second scan signal.

[0011] The first transistor includes a first electrode connected to the cathode, a second electrode connected to the second power line, and a gate connected to the first node, and wherein the fourth transistor includes a first electrode connected to the first power line, a second electrode connected to the first electrode of the first transistor, and a gate configured to receive a third scan signal.

[0012] The pixel further includes: a first initialization transistor connected between the second electrode of the first transistor and the first initialization voltage line and configured to receive a fourth scan signal; and a first capacitor connected between the second node and the first node, the second node being connected to the first transistor and the first initialization transistor.

[0013] The fourth scan signal is activated during a first initialization period and deactivated during a data writing period during which the first scan signal is activated, and wherein the first initialization period is located before the data writing period.

[0014] The fourth scan signal is also activated during a second initialization period located after the data writing period.

[0015] The second transistor, the third transistor, and the fourth transistor are turned off during the second initialization period.

[0016] The pixel includes a plurality of pixels, and the plurality of pixels include a first light-emitting element and a second light-emitting element, the first light-emitting element being configured to emit light of a first color, the second light-emitting element being configured to emit a second color different from the first color, and wherein the first initialization voltage line includes a first-first initialization voltage line and a first-second initialization voltage line, the first-first initialization voltage line being connected to the first light-emitting element and configured to receive a first-first initialization voltage, the first-second initialization voltage line being connected to the second light-emitting element and configured to receive a first-second initialization voltage different from the first-first initialization voltage.

[0017] The pixel further includes a second initialization transistor connected between the cathode of the light-emitting element and the second initialization voltage line, and wherein the first initialization voltage line and the second initialization voltage line are configured to receive different initialization voltages.

[0018] The fourth transistor is configured to receive a third scan signal, wherein the second initialization transistor is configured to receive a fourth scan signal, and wherein the period during which the third scan signal is activated and the period during which the fourth scan signal is activated do not overlap with each other.

[0019] The display panel is configured to display an image during a plurality of frames, and at least one of the plurality of frames includes a write frame and a hold frame, wherein a first scan signal, a second scan signal, and a third scan signal have an active level in the write frame and remain in an inactive state during the hold frame, and wherein a fourth scan signal has an active level in the write frame and the hold frame.

[0020] The pixel includes a plurality of pixels, and the plurality of pixels include a first light-emitting element and a second light-emitting element. The first light-emitting element is configured to emit light of a first color, and the second light-emitting element is configured to emit light of a second color different from the first color. And wherein the second initialization voltage line includes a second-first initialization voltage line and a second-second initialization voltage line. The second-first initialization voltage line is connected to the first light-emitting element and is configured to receive a second-first initialization voltage, and the second-second initialization voltage line is connected to the second light-emitting element and is configured to receive a second-second initialization voltage different from the second-first initialization voltage.

[0021] The second initialization transistor is configured to receive a fifth scan signal, wherein the fourth scan signal is activated during a first initialization period, and the fifth scan signal is activated during the first initialization period and a second initialization period. Wherein the fourth scan signal and the fifth scan signal are deactivated during a data write period during which the first scan signal is activated, and wherein the first initialization period is located before the data write period, and the second initialization period is located after the data write period.

[0022] The fourth scan signal is also activated during the second initialization period.

[0023] The display panel is configured to display an image during a plurality of frames, and at least one of the plurality of frames includes a write frame and a hold frame, wherein the fourth scan signal has an active level in the write frame and remains in an inactive state during the hold frame, and wherein the fifth scan signal has an active level in the write frame and the hold frame.

[0024] The pixel further includes: a first emission control transistor connected between a first electrode of the first transistor and the cathode and configured to receive an emission control signal; and a second emission control transistor connected between a second electrode of the first transistor and a second power line and configured to receive the emission control signal.

[0025] The pixel further includes a second capacitor connected between a second electrode of the first transistor and one of a first power line and a second power line, and wherein the first transistor further includes a back gate connected to the second electrode of the first transistor.

[0026] Each of the first transistor, the second transistor, the third transistor, and the fourth transistor is an N-type transistor.

[0027] The first driving voltage received by the first power line is higher than the second driving voltage received by the second power line, and the reference voltage received by the reference voltage line is between the first driving voltage and the second driving voltage.

[0028] The light-emitting element further includes: an electron control layer on the cathode; an emission layer on the electron control layer; and a hole control layer on the emission layer, wherein the anode is on the hole control layer.

[0029] The second power line has a structure of Ti / Al / Ti.

[0030] The anode includes a MgAg alloy, and the cathode has a structure of ITO / Ag / ITO.

[0031] The second power line and the data line are at the same layer and include the same material.

[0032] The second power line and the first power line are at the same layer and include the same material.

[0033] The anode is directly connected to the first power line.

[0034] The display device further includes a connection conductive pattern configured to connect the anode and the first power line.

[0035] The display panel includes a display area in which pixels are located and a non-display area around at least a part of the display area, and wherein the pixels include a plurality of pixels, the anode includes a plurality of anodes, and the plurality of anodes are respectively located in corresponding ones of the plurality of pixels and are connected to the first power line in the display area.

[0036] The display panel includes a display area in which pixels are located and a non-display area around at least a part of the display area, and wherein the pixels include a plurality of pixels, and the anode is commonly provided in the plurality of pixels and is connected to the first power line in the non-display area.

[0037] The light-emitting element further includes an intermediate layer that at least includes the emission layer, the intermediate layer is on the anode, and the cathode is on the intermediate layer.

[0038] The display panel further includes a separator having an obtuse inclination angle, wherein the pixels include a plurality of pixels, and the plurality of pixels include a first light-emitting element and a second light-emitting element, the first light-emitting element is configured to emit light of a first color, the second light-emitting element is configured to emit a second color different from the first color, and the separator separates the cathode of the first light-emitting element from the cathode of the second light-emitting element.

[0039] The display panel further includes a connection line configured to electrically connect the first transistor and the cathode.

[0040] The connection line includes a first layer, a second layer on the first layer, and a third layer on the second layer, and wherein a side surface of the third layer protrudes outward from a side surface of the second layer, and the cathode contacts the side surface of the second layer.

[0041] The display panel further includes: a pixel defining layer having an opening defined therein, the opening exposing at least a part of the anode; a connection electrode on the pixel defining layer and electrically connected to the first transistor and the cathode; and a separator on the pixel defining layer, wherein, in a contact area adjacent to the separator, a lower surface of the cathode contacts an upper surface of the connection electrode.

[0042] The connection electrode has an annular shape surrounding the opening.

[0043] The separator includes a first side surface and a second side surface, and the first side surface and the second side surface have different inclination angles with respect to an upper surface of the pixel defining layer.

[0044] The pixel includes a plurality of pixels, and the connection electrode includes a plurality of connection electrodes, wherein each of the plurality of connection electrodes electrically connects the first transistor and the cathode in a corresponding pixel among the plurality of pixels, and wherein a gap between adjacent connection electrodes among the plurality of connection electrodes overlaps with the separator.

[0045] The display device includes: a display panel including pixels, wherein the pixel includes: a light emitting element including a cathode and an anode connected to a first power line; a driving transistor including a first electrode connected to the cathode, a second electrode connected to a second power line, and a gate connected to a first node; a switching transistor connected between the first node and a data line; an emission control transistor connected between the first electrode of the driving transistor and the cathode; a compensation transistor connected between the first electrode of the driving transistor and the first power line; and an initialization transistor connected between the cathode and an initialization voltage line, wherein the compensation transistor and the initialization transistor are configured to receive different scan signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The above and other aspects and features of the present disclosure will become apparent by referring to the embodiments of the present disclosure described in detail with reference to the drawings.

[0047] Figure 1 is a block diagram of a display device according to one or more embodiments of the present disclosure.

[0048] Figure 2A and Figure 2B is a timing diagram for explaining the operation of a display device according to one or more embodiments of the present disclosure.

[0049] Figure 3 is a circuit diagram of a pixel according to one or more embodiments of the present disclosure.

[0050] Figure 4A and Figure 4B is a timing diagram for explaining the operation of a pixel according to one or more embodiments of the present disclosure Figure 3 of.

[0051] Figure 4C is a timing diagram for explaining the operation of a pixel according to one or more embodiments of the present disclosure Figure 3 of.

[0052] Figure 5A is a circuit diagram of a pixel according to one or more embodiments of the present disclosure.

[0053] Figure 5B and Figure 5C is a timing diagram for explaining the operation of a pixel according to one or more embodiments of the present disclosure Figure 5A of.

[0054] Figure 6A is a circuit diagram of a pixel according to one or more embodiments of the present disclosure.

[0055] Figure 6B is a circuit diagram of a pixel according to one or more embodiments of the present disclosure.

[0056] Figure 6C is a circuit diagram of a pixel according to one or more embodiments of the present disclosure.

[0057] Figure 7A and Figure 7B is a circuit diagram of a pixel according to one or more embodiments of the present disclosure.

[0058] Figure 8A and Figure 8B is a circuit diagram of a pixel according to one or more embodiments of the present disclosure.

[0059] Figure 9A and Figure 9B is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure.

[0060] Figure 10 is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure.

[0061] Figure 11 is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure.

[0062] Figure 12A cross-sectional view of a display panel according to one or more embodiments of the present disclosure.

[0063] Figure 13A is according to one or more embodiments of the present disclosure Figure 12 An enlarged cross-sectional view of region AA in

[0064] Figure 13B is according to one or more embodiments of the present disclosure Figure 12 An enlarged cross-sectional view of region BB in

[0065] Figure 14 A cross-sectional view of a display panel according to one or more embodiments of the present disclosure.

[0066] Figures 15A to 15C An enlarged plan view of a partial region of a display panel according to one or more embodiments of the present disclosure.

[0067] Figures 16A to 16D An enlarged plan view of a partial region of a display panel according to one or more embodiments of the present disclosure.

[0068] Figure 17 A cross-sectional view of a display panel according to one or more embodiments of the present disclosure.

[0069] Figure 18 An enlarged cross-sectional view of a partial region of a display panel according to one or more embodiments of the present disclosure.

[0070] Figure 19 A cross-sectional view of a display panel according to one or more embodiments of the present disclosure. Detailed Description

[0071] In the present disclosure, when a component (or region, layer, part, etc.) is referred to as being "on" another component, "connected to" or "coupled to" another component, this means that the component can be directly on the other component, directly connected to or directly coupled to the other component, or there can be a third component between them.

[0072] The same (or identical) reference numerals refer to the same (or identical) components. Further, in the drawings, the thickness, proportions, and dimensions of the components are exaggerated for effective description. As used herein, the term "and / or" includes all of one or more combinations defined by the related components.

[0073] Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used only to distinguish one component from other components. For example, without departing from the spirit or scope of the present disclosure, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. Unless otherwise stated, terms in the singular form may include the plural form.

[0074] In addition, terms such as "below", "beneath", "above", and "on" are used to describe the relationship of components shown in the drawings. The terms are relative concepts and are described based on the directions shown in the drawings.

[0075] It should be understood that when terms such as "comprising", "including", and "having" are used herein, it indicates the presence of the stated features, numbers, steps, operations, components, parts, or combinations thereof, but does not exclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0076] Unless otherwise defined, all terms (including technical terms or scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure pertains. Terms defined in a general dictionary will be interpreted as having the same meaning as their context in the relevant field, and will not be interpreted as having an idealized or overly formal meaning, unless clearly defined as such in the present application.

[0077] Expressions such as "at least one of" and "any one of" modify the entire list of elements when they are after (before) a list of elements, rather than modifying individual elements in the list. When phrases such as "at least one of A, B, and C", "at least one of the group consisting of A, B, and C", or "at least one of A, B, and C" are used to specify a series of elements A, B, and C, the phrase may refer to any suitable combination or subset of A, B, and C and all suitable combinations or subsets, such as A, B, C, A and B, A and C, B and C, or A and B and C.

[0078] Those of ordinary skill in the art will understand that, given the overall content of the present disclosure, each suitable feature of each embodiment of the present disclosure may be partially or fully combined or combined with each other, and may be interlocked and operated in various suitable ways technically, and unless otherwise stated or implied, each embodiment may be implemented independently of each other or in any suitable way in combination with each other.

[0079] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0080] Figure 1 It is a block diagram of a display device DD according to one or more embodiments of the present disclosure.

[0081] Referring to Figure 1 , the display device DD may include a display panel DP, a driving controller 100, and a panel driver. In one or more embodiments of the present disclosure, the panel driver may include a data driving circuit 200 (or data driver), a scan driving circuit 300, an emission driving circuit 350, and a voltage generator 400.

[0082] The display panel DP may include a display area DA and a non-display area NDA around at least a part of the display area DA (e.g., surrounding at least a part of the display area DA). The display panel DP may include a plurality of pixels PX disposed in the display area DA. The display panel DP may include first scan lines GWL1 to GWLn, second scan lines GRL1 to GRLn, third scan lines GCL1 to GCLn, fourth scan lines GIL1 to GILn, and emission control lines EML1 to EMLn. The first scan lines GWL1 to GWLn may be referred to as write scan lines, the second scan lines GRL1 to GRLn may be referred to as reference scan lines, the third scan lines GCL1 to GCLn may be referred to as compensation scan lines, and the fourth scan lines GIL1 to GILn may be referred to as initialization scan lines.

[0083] The display panel DP may be driven at a specific driving frequency (e.g., 60 Hz, 120 Hz, and / or 240 Hz). Optionally, the display panel DP may be driven at a fixed driving frequency in a first mode and / or may be driven at a variable driving frequency in a second mode. For example, the driving frequency in the second mode may vary diversely within a range of 1 Hz to 240 Hz, but is not particularly limited thereto.

[0084] The driving controller 100 receives an image signal RGB and a control signal CTRL. The driving controller 100 generates an image data signal DATA by converting the data format of the image signal RGB according to the specifications of the interface with the data driving circuit 200. The driving controller 100 outputs a scan control signal SCS, a data control signal DCS, and an emission driving control signal ECS.

[0085] The data driving circuit 200 (or data driver) receives a data control signal DCS and an image data signal DATA from the driving controller 100. The data driving circuit 200 converts the image data signal DATA into a data signal and outputs the data signal to data lines DL1, DL2 to DLm. The data signal is an analog voltage corresponding to the gray level value of the image data signal DATA. The data lines DL1 to DLm may be arranged along the first direction DR1. Each of the data lines DL1 to DLm may extend in the second direction DR2.

[0086] The scan driving circuit 300 (or scan driver) and the emission driving circuit 350 (or emission driver) may be disposed in the non-display area NDA of the display panel DP. In one or more embodiments of the present disclosure, the scan driving circuit 300 may be disposed adjacent to one side of the display area DA, and the emission driving circuit 350 may be disposed adjacent to the opposite side of the display area DA that is opposite to the said one side of the display area DA. Although in the embodiment shown in Figure 1 the scan driving circuit 300 and the emission driving circuit 350 are disposed on opposite sides of the display area DA, the present disclosure is not limited thereto. For example, the scan driving circuit 300 and the emission driving circuit 350 may be disposed adjacent to one of the opposite sides of the display panel DP. In one or more embodiments, the scan driving circuit 300 and the emission driving circuit 350 may be integrated into one circuit.

[0087] Each of a plurality of pixels PX according to one or more embodiments of the present disclosure includes a light-emitting element ED (refer to Figure 3 ), and a pixel circuit PXC (refer to Figure 3 ) that controls the light emission of the light-emitting element ED (refer to Figure 3 ).

[0088] The pixel circuit PXC (refer to Figure 3 ) may include at least one transistor and at least one capacitor. The scan driving circuit 300 and the emission driving circuit 350 may include transistors formed by the same process as the pixel circuit PXC (refer to Figure 3 ). The pixel circuit PXC (refer to Figure 3 ) may be referred to as a pixel driver.

[0089] The scan driving circuit 300 receives a scan control signal SCS from the driving controller 100. The scan driving circuit 300 may output a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to the first scan lines GWL1 to GWLn, the second scan lines GRL1 to GRLn, the third scan lines GCL1 to GCLn, and the fourth scan lines GIL1 to GILn in response to the scan control signal SCS, respectively. The emission driving circuit 350 may output an emission control signal to the emission control lines EML1 to EMLn in response to an emission driving control signal ECS from the driving controller 100.

[0090] The first scan lines GWL1 to GWLn, the second scan lines GRL1 to GRLn, the third scan lines GCL1 to GCLn, the fourth scan lines GIL1 to GILn, and the emission control lines EML1 to EMLn may all extend in a first direction DR1. The first scan lines GWL1 to GWLn, the second scan lines GRL1 to GRLn, the third scan lines GCL1 to GCLn, the fourth scan lines GIL1 to GILn, and the emission control lines EML1 to EMLn may be separated from each other (e.g., spaced apart) in a second direction DR2.

[0091] Each of the plurality of pixels PX may be electrically connected to four scan lines, one emission control line, and one data line. For example, as Figure 1 shown, the pixels PX in the first row may be connected to the scan lines GWL1, GRL1, GCL1, and GIL1 and the emission control line EML1. The pixels PX in the first column may be connected to the data line DL1. In addition, the pixels PX in the i-th row may be connected to the scan lines GWLi, GRLi, GCLi, and GILi and the emission control line EMLi. However, the present disclosure is not limited thereto, and each of the pixels PX may be connected to less than four scan lines, or may be connected to more than four scan lines.

[0092] The voltage generator 400 (or power supply unit) generates voltages required for the operation of the display panel DP. In the present embodiment, the voltage generator 400 may generate a first driving voltage ELVDD, a second driving voltage ELVSS, a reference voltage VREF, a first initialization voltage VINT, and a second initialization voltage VAINT.

[0093] Figure 2A and Figure 2B are timing diagrams for explaining the operation of the display device DD (refer to Figure 1 ) according to one or more embodiments of the present disclosure. Figure 2A is a timing diagram for explaining the case where the display device DD (refer to Figure 1 ) according to one or more embodiments of the present disclosure operates at a first driving frequency. Figure 2Bis a timing diagram for explaining the case where the display device DD (refer to Figure 1 ) operates at a second driving frequency.

[0094] Refer to Figure 1 and Figure 2A , the driving frequency of the display device DD can vary diversely. In one or more embodiments of the present disclosure, the first driving frequency may be the highest driving frequency at which the display device DD can operate. The first driving frequency may be referred to as a reference frequency or a maximum frequency.

[0095] When the display device DD operates at the first driving frequency, the scan driving circuit 300 may sequentially activate the scan signals (e.g., the first scan signals GW1 to GWn) to a high level in each of the multiple frames F11, F12, F13, and F14. Although, for ease of description, only the first scan signals GW1 to GWn are shown in Figure 2A and Figure 2B , the second scan signals, the third scan signals, and the fourth scan signals may also be activated in a similar form according to the driving frequency.

[0096] When the first driving frequency is the maximum frequency, each of the frames F11, F12, F13, and F14 may include only the write frame WP. In this case, the duration of the write frame WP may be equal to the duration of each of the frames F11, F12, F13, and F14.

[0097] Refer to Figure 1 and Figure 2B , the display device DD may operate at a second driving frequency lower than the first driving frequency.

[0098] When the display device DD operates at a second driving frequency lower than the first driving frequency, the duration of each of the frames F21 and F22 may be longer than the duration of each of the frames F11, F12, F13, and F14 shown in Figure 2A . Figure 2B shows an example where the duration of each of the frames F21 and F22 operating at the second driving frequency is twice the duration of each of the frames F11, F12, F13, and F14. However, the duration of each of the frames F21 and F22 operating at the second driving frequency is not limited to any one embodiment.

[0099] Each of the frames F21 and F22 may include a write frame WP and a hold frame HP. Figure 2B shows an example where the write frame WP has the same duration as the duration of each of the frames F11, F12, F13, and F14 shown in Figure 2A .

[0100] During a write frame WP, the scan driving circuit 300 may sequentially activate the first scan signals GW1 to GWn to an active level (e.g., a high level). In one or more embodiments, the scan driving circuit 300 and the emission driving circuit 350 may sequentially activate the scan signal and the emission control signal to an active level (e.g., a high level) during the write frame WP. A detailed description thereof will be given below.

[0101] During a hold frame HP, the scan driving circuit 300 may hold the first scan signals GW1 to GWn at an inactive level (e.g., a low level). During the hold frame HP, the scan driving circuit 300 may hold the second scan signal and the third scan signal at an inactive level.

[0102] Figure 3 is a circuit diagram of a pixel PXij according to one or more embodiments of the present disclosure. Figure 4A and Figure 4B is for explaining Figure 3 the operation of the pixel PXij according to one or more embodiments of the present disclosure

[0103] In Figure 3 , a pixel PXij connected to the i-th first scan line GWLi among the first scan lines GWL1 to GWLn (refer to Figure 1 ), and connected to the j-th data line DLj among the plurality of data lines DL1 to DLm (refer to Figure 1 ) is representatively shown. The pixel PXij is connected to the i-th second scan line GRLi among the second scan lines GRL1 to GRLn (refer to Figure 1 ), the i-th third scan line GCLi among the third scan lines GCL1 to GCLn (refer to Figure 1 ), and the i-th fourth scan line GILi among the fourth scan lines GIL1 to GILn (refer to Figure 1 ). In addition, the pixel PXij is connected to the i-th emission control line EMLi among the emission control lines EML1 to EMLn.

[0104] The pixel PXij may include a pixel circuit PXC (or a pixel driving circuit) and a light emitting element ED electrically connected to the pixel circuit PXC. In the present embodiment, the pixel circuit PXC may include eight transistors (hereinafter referred to as a first transistor T1 to an eighth transistor T8) and two capacitors (hereinafter referred to as a first capacitor C1 and a second capacitor C2). In one or more embodiments of the present disclosure, at least one of the first transistor T1 to the eighth transistor T8 may be omitted from the pixel PXij, or additional transistors may be further included in the pixel PXij.

[0105] The i-th first scan line GWLi can transmit the i-th first scan signal GWi to the pixel PXij, the i-th second scan line GRLi can transmit the i-th second scan signal GRi to the pixel PXij, the i-th third scan line GCLi can transmit the i-th third scan signal GCi to the pixel PXij, and the i-th fourth scan line GILi can transmit the i-th fourth scan signal GIi to the pixel PXij. The i-th emission control line EMLi can transmit the i-th emission control signal EMi to the pixel PXij. The j-th data line DLj can transmit the data signal DS to the pixel PXij. The data signal DS can have a voltage level corresponding to the gray level value of the image data signal DATA (refer to Figure 1 ) output from the driving controller 100 (refer to Figure 1 ).

[0106] In addition, the pixel PXij can be connected to a first power line PL1 receiving a first driving voltage ELVDD, a second power line PL2 receiving a second driving voltage ELVSS, a reference voltage line VL1 receiving a reference voltage VREF, a first initialization voltage line VL2 receiving a first initialization voltage VINT, and a second initialization voltage line VL3 receiving a second initialization voltage VAINT. The first driving voltage ELVDD has a voltage level higher than that of the second driving voltage ELVSS, and the reference voltage VREF has a voltage level higher than that of the second driving voltage ELVSS and lower than that of the first driving voltage ELVDD. The first initialization voltage VINT can have a voltage level lower than that of the second initialization voltage VAINT.

[0107] In this embodiment, each of the first transistor T1 to the eighth transistor T8 can be an N-type thin film transistor (TFT) using an oxide semiconductor as a semiconductor layer. Specifically, compared with the case where a P-type thin film transistor is applied to the first transistor T1, when an N-type thin film transistor is applied to the first transistor T1 called a driving transistor, changes in device characteristics due to previous data can be reduced. Therefore, the characteristics of overcoming transient afterimages can be improved.

[0108] The light-emitting element ED can include an anode AE and a cathode CE. When the light-emitting element ED is an organic light-emitting element, the light-emitting element ED can further include an organic layer provided between the anode AE and the cathode CE. The anode AE of the light-emitting element ED can be connected to the first power line PL1. In this embodiment, the anode AE of the light-emitting element ED can be directly connected to the first power line PL1. The cathode CE of the light-emitting element ED can be connected to the pixel circuit PXC. The light-emitting element ED can emit light in response to the amount of current flowing through the first transistor T1 of the pixel circuit PXC.

[0109] The first transistor T1 is connected between the cathode CE of the light-emitting element ED and the second power line PL2 that receives the second driving voltage ELVSS. The first transistor T1 may be referred to as a driving transistor. The first transistor T1 may include a first electrode D1, a second electrode S1, and a gate electrode G1_1. The gate electrode G1_1 may be connected to the first node N1, the second electrode S1 may be connected to the second node N2, and the first electrode D1 may be connected to the third node N3. The first electrode D1 may be referred to as the drain of the first transistor T1, and the second electrode S1 may be referred to as the source of the first transistor T1. The first transistor T1 may operate according to the potential of the first node N1. In the present embodiment, the first transistor T1 may further include a back gate electrode (or referred to as a "back gate") G1_2. The back gate electrode G1_2 may be connected to the second electrode S1 of the first transistor T1.

[0110] According to one or more embodiments of the present disclosure, the first transistor T1 may be an N-type thin film transistor, and the cathode CE of the light-emitting element ED may be connected to the drain (or the first electrode D1) of the first transistor T1 via the sixth transistor T6.

[0111] The second transistor T2 is connected between the j-th data line DLj and the first node N1 and receives the i-th first scan signal GWi. The second transistor T2 may be referred to as a switching transistor. The second transistor T2 may include a first electrode D2 connected to the j-th data line DLj, a second electrode S2 connected to the first node N1, and a gate electrode G2 connected to the i-th first scan line GWLi. The second transistor T2 may transmit the data signal DS received through the j-th data line DLj to the first node N1 in response to the i-th first scan signal GWi received through the i-th first scan line GWLi.

[0112] The third transistor T3 is connected between the reference voltage line VL1 and the first node N1 and receives the i-th second scan signal GRi. The third transistor T3 may be referred to as a first compensation transistor. The third transistor T3 may include a first electrode D3 connected to the reference voltage line VL1, a second electrode S3 connected to the first node N1, and a gate electrode G3 connected to the i-th second scan line GRLi. The third transistor T3 may be turned on by the i-th second scan signal GRi received through the i-th second scan line GRLi and may transmit the reference voltage VREF to the first node N1. In the present embodiment, the reference voltage VREF may have a voltage level between the first driving voltage ELVDD and the second driving voltage ELVSS. For example, when the first driving voltage ELVDD is 13V and the second driving voltage ELVSS is 0V, the reference voltage VREF may be 1.3V.

[0113] The fourth transistor T4 is connected between the first power line PL1 and the third node N3 and receives the i-th third scan signal GCi. The fourth transistor T4 may be referred to as a second compensation transistor. The fourth transistor T4 may include a first electrode D4 connected to the first power line PL1, a second electrode S4 connected to the first electrode D1 of the first transistor T1 (i.e., the third node N3), and a gate electrode G4 connected to the i-th third scan line GCLi. The fourth transistor T4 may be turned on by the i-th third scan signal GCi received through the i-th third scan line GCLi and may transfer the first driving voltage ELVDD to the third node N3.

[0114] When the fourth transistor T4 is not connected to the first power line PL1 and receives a voltage using a separate power line, the number of power lines connected to the pixel PXij increases. However, since the fourth transistor T4 according to the present embodiment uses the first driving voltage ELVDD supplied through the first power line PL1, the voltage generator 400 (refer to Figure 1 ) may not further include a separate power line. Accordingly, the area of the non-display area NDA (refer to Figure 1 ) can be reduced. In addition, the number of power lines connected to the pixel PXij can be reduced. Accordingly, the gap between the lines connected to the pixel PXij can be increased, and thus signal interference between the lines can be reduced. As a result, the pixel PXij and the display device DD (refer to Figure 1 ) having improved display quality can be provided.

[0115] The fifth transistor T5 is connected between the first initialization voltage line VL2 and the second node N2 and receives the i-th fourth scan signal GIi. The fifth transistor T5 may be referred to as a first initialization transistor. The fifth transistor T5 may include a first electrode D5 connected to the second electrode S1 of the first transistor T1, a second electrode S5 connected to the first initialization voltage line VL2, and a gate electrode G5 connected to the i-th fourth scan line GILi. The fifth transistor T5 may be turned on by the i-th fourth scan signal GIi received through the i-th fourth scan line GILi and may transfer the first initialization voltage VINT to the second node N2.

[0116] The sixth transistor T6 may be connected between the first transistor T1 and the cathode CE of the light-emitting element ED, and may receive the i-th emission control signal EMi. The sixth transistor T6 may be referred to as a first emission control transistor. The sixth transistor T6 may include a first electrode D6 connected to the cathode CE of the light-emitting element ED, a second electrode S6 connected to the first electrode D1 of the first transistor T1, and a gate electrode G6 connected to the i-th emission control line EMLi. The sixth transistor T6 may be turned on by the i-th emission control signal EMi received through the i-th emission control line EMLi, and may electrically connect the cathode CE of the light-emitting element ED to the first electrode D1 of the first transistor T1.

[0117] The seventh transistor T7 may be connected between the first transistor T1 and the second power line PL2, and may receive the i-th emission control signal EMi. The seventh transistor T7 may be referred to as a second emission control transistor. The seventh transistor T7 may include a first electrode D7 connected to the second electrode S1 of the first transistor T1, a second electrode S7 connected to the second power line PL2, and a gate electrode G7 connected to the i-th emission control line EMLi. The seventh transistor T7 may be turned on by the i-th emission control signal EMi received through the i-th emission control line EMLi, and may electrically connect the second power line PL2 to the second electrode S1 of the first transistor T1.

[0118] The eighth transistor T8 may be connected between the second initialization voltage line VL3 and the cathode CE of the light-emitting element ED, and may receive the i-th fourth scan signal GIi. The eighth transistor T8 may be referred to as a second initialization transistor. The eighth transistor T8 may include a first electrode D8 connected to the fourth node N4, a second electrode S8 connected to the second initialization voltage line VL3, and a gate electrode G8 connected to the i-th fourth scan line GILi. The cathode CE of the light-emitting element ED and the first electrode D6 of the sixth transistor T6 may be connected to the fourth node N4. The eighth transistor T8 may be turned on by the i-th fourth scan signal GIi received through the i-th fourth scan line GILi, and may transmit the second initialization voltage VAINT to the cathode CE of the light-emitting element ED.

[0119] In this embodiment, the fourth transistor T4 and the eighth transistor T8 can receive different scan signals. In addition, the fourth transistor T4 and the eighth transistor T8 can be connected to different voltage lines. Therefore, the initialization operation of the cathode CE through the eighth transistor T8 and the compensation operation of the first transistor T1 through the fourth transistor T4 can be independently performed. In addition, in the compensation operation, the third node N3 to which the drain D1 of the first transistor T1 is connected and the fourth node N4 to which the cathode CE of the light-emitting element ED is connected can be separated from each other. Therefore, in the compensation operation, the influence of the parasitic capacitance formed at the fourth node N4 can be reduced. Therefore, the compensation stability can be improved.

[0120] On the contrary, when the fourth transistor T4 and the eighth transistor T8 receive the same scan signal and are connected to the same voltage line differently from this embodiment, the third node N3 and the fourth node N4 are not separated from each other in the compensation operation, so the parasitic capacitance formed at the fourth node N4 affects the amount of compensation.

[0121] The first capacitor C1 can be connected between the first node N1 and the second node N2. The first capacitor C1 can include a first electrode E1 connected to the first node N1 and a second electrode E2 connected to the second node N2. The first capacitor C1 can store the voltage difference between the first node N1 and the second node N2. The first capacitor C1 can be referred to as a storage capacitor.

[0122] The second capacitor C2 can be connected between the first power line PL1 and the second node N2. The second capacitor C2 can include a first electrode E3 connected to the first power line PL1 and a second electrode E4 connected to the second node N2. The second capacitor C2 can store the voltage difference between the first driving voltage ELVDD and the second node N2. The second capacitor C2 can be referred to as a holding capacitor.

[0123] will be described Figures 3 to 4C in more detail the operation of the pixel PXij.

[0124] The display device DD (refer to Figure 1 ) displays an image in each frame. The first scan lines GWL1 to GWLn (refer to Figure 1 ), the second scan lines GRL1 to GRLn (refer to Figure 1 ), the third scan lines GCL1 to GCLn (refer to Figure 1 ), the fourth scan lines GIL1 to GILn (refer to Figure 1 ) and the emission control lines EML1 to EMLn can sequentially receive scan signals and / or emission control signals during a frame. Figure 4A shows the pixel PXij at Figure 2AOperations during the write frame WP within one of the frames F11 to F14 shown in, and Figure 4B shows the operations of the pixel PXij during the write frame WP within Figure 2B the frames F21 and F22 shown in. Figure 4C shows the operations of the pixel PXij during Figure 2B the hold frame HP within the frames F21 and F22 shown in.

[0125] As Figures 4A to 4C shown in, the scan signals GRi, GWi, GCi, and GIi and the emission control signal EMi can all have an active level (or high level) during a partial period and can have an inactive level (or low level) during a partial period. Each of the above-described N-type first transistor T1 to N-type eighth transistor T8 conducts when the corresponding scan signal or the corresponding emission control signal has a high level.

[0126] Referring to Figures 3 to 4B , the write frame WP can include a first initialization period t1, a compensation period t2, a data write period t3, a second initialization period t4, and an emission period t5. In this embodiment, the first initialization period t1 can be located before the data write period t3, and the second initialization period t4 can be located after the data write period t3.

[0127] During the first initialization period t1, the second scan signal GRi and the fourth scan signal GIi can have an active level. In this embodiment, the first initialization period t1 can correspond to the first period AP1_I or AP1_I' (or first-first activation period) during which the fourth scan signal GIi has an active level. During the first initialization period t1, the first scan signal GWi, the third scan signal GCi, and the emission control signal EMi can have an inactive level.

[0128] During the first initialization period t1, the third transistor T3, the fifth transistor T5, and the eighth transistor T8 can conduct. During the first initialization period t1, the first node N1 can be initialized to the reference voltage VREF, the second node N2 can be initialized to the first initialization voltage VINT, and the cathode CE of the light-emitting element ED can be initialized to the second initialization voltage VAINT.

[0129] A part of the period AP_R or AP_R' (or the second activation period) during which the second scan signal GRi has an active level overlaps with the first period AP1_I or AP1_I' during which the fourth scan signal GIi has an active level. Thus, when the first node N1 and the second node N2 are concurrently (e.g., simultaneously) initialized during the first initialization period t1, the first capacitor C1 can be initialized to the difference between the reference voltage VREF and the first initialization voltage VINT. The second capacitor C2 can be initialized to the difference between the first driving voltage ELVDD and the first initialization voltage VINT. The first initialization period t1 can be the period during which the gate electrode G1_1 and the source S1 of the first transistor T1 are initialized and the cathode CE of the light-emitting element ED is initialized.

[0130] In one or more embodiments, as Figure 4A shown, the time point at which the second activation period AP_R of the second scan signal GRi starts can be after the time point at which the first-first activation period AP1_I of the fourth scan signal GIi starts. However, the present disclosure is not limited thereto. For example, as Figure 4B shown, the time point at which the first-first activation period AP1_I' of the fourth scan signal GIi starts can be after the time point at which the second activation period AP_R' of the second scan signal GRi starts. In this case, the first-first activation period AP1_I' of the fourth scan signal GIi can entirely overlap with the second activation period AP_R' of the second scan signal GRi. Optionally, the first-first activation period AP1_I' and the second activation period AP_R' can start simultaneously.

[0131] During the compensation period t2, the second scan signal GRi and the third scan signal GCi can have active levels. In the present embodiment, the second scan signal GRi can substantially maintain an active level during the first initialization period t1 and the compensation period t2. During the compensation period t2, the first scan signal GWi, the fourth scan signal GIi, and the emission control signal EMi can have inactive levels.

[0132] During the compensation period t2, the third transistor T3 and the fourth transistor T4 can be turned on in response to the second scan signal GRi and the third scan signal GCi, respectively. Another part of the period AP_R or AP_R' during which the second scan signal GRi has an active level overlaps with the period AP_C or AP_C' (or the third active period) during which the third scan signal GCi has an active level. During the compensation period t2, the threshold voltage (Vth) of the first transistor T1 can be compensated by the combination of the first capacitor C1. A voltage "VREF - Vth" that is lower than the reference voltage VREF provided to the gate electrode G1_1 of the first transistor T1 by the threshold voltage (Vth) of the first transistor T1 can be provided to the second node N2.

[0133] In one or more embodiments, as Figure 4A shown, the time point at which the third active period AP_C of the third scan signal GCi ends can be located after the time point at which the second active period AP_R of the second scan signal GRi ends. However, the present disclosure is not limited thereto. For example, as Figure 4B shown, the time point at which the second active period AP_R' of the second scan signal GRi ends can be located after the time point at which the third active period AP_C' of the third scan signal GCi ends. In this case, the third active period AP_C' of the third scan signal GCi can entirely overlap with the second active period AP_R' of the second scan signal GRi. Optionally, the second active period AP_R' and the third active period AP_C' can end simultaneously.

[0134] In the present embodiment, the period during which the third scan signal GCi is active and the period during which the fourth scan signal GIi is active can not overlap with each other. Therefore, the compensation period t2 can not overlap with the first initialization period t1. That is to say, the compensation period t2 and the first initialization period t1 can be performed independently without being performed simultaneously. Therefore, during the compensation period t2, the third node N3 to which the drain D1 of the first transistor T1 is connected and the fourth node N4 to which the cathode CE of the light-emitting element ED is connected can be kept in a separated state, and the influence of the parasitic capacitance formed at the fourth node N4 can be reduced in the compensation operation. Therefore, the compensation stability can be improved.

[0135] During the data writing period t3, the first scan signal GWi can have an active level. During the data writing period t3, the second scan signal GRi, the third scan signal GCi, the fourth scan signal GIi, and the emission control signal EMi can have non-active levels.

[0136] During a data writing period t3, the second transistor T2 may be turned on. The second transistor T2 may output a voltage corresponding to the data signal DS, and the data signal DS may be supplied to the first node N1. The potential of the first node N1 may change from the reference voltage VREF to the data signal DS. For example, the voltage of the first node N1 may increase from the reference voltage VREF to the data signal DS in response to a certain gray level. Optionally, the voltage of the first node N1 may decrease from the reference voltage VREF to the data signal DS in response to a black gray level.

[0137] The data signal DS may be charged into the first capacitor C1. The threshold voltages (Vth) of the first transistors T1 of the respective pixels PX (refer to Figure 1 ), may be different from each other, but Figure 3 the pixel PXij shown in

[0138] During a second initialization period t4, the fourth scan signal GIi may have an active level. In the present embodiment, the second initialization period t4 may correspond to a second period AP2_I (or first-second activation period) during which the fourth scan signal GIi has an active level. During the second initialization period t4, the first scan signal GWi, the second scan signal GRi, the third scan signal GCi, and the emission control signal EMi may have inactive levels. Different from the first initialization period t1, in the second initialization period t4, the second scan signal GRi may have an inactive level, and only the fourth scan signal GIi may have an active level.

[0139] During the second initialization period t4, the fifth transistor T5 and the eighth transistor T8 may be turned on. During the second initialization period t4, the second node N2 may be initialized to a first initialization voltage VINT, and the cathode CE of the light-emitting element ED may be initialized to a second initialization voltage VAINT.

[0140] In the present embodiment, when the eighth transistor T8 initializes the cathode CE of the light-emitting element ED, due to the residual voltage remaining in the cathode CE of the light-emitting element ED in the initial stage of the operation of the light-emitting element ED, it is possible to prevent the light-emitting element ED from instantaneously emitting light with high brightness. Deterioration of the characteristics of the black gray level can be prevented, and stains on the display panel DP (refer to Figure 1 ), can be prevented from being visually recognized by providing the initialization voltage to the light-emitting element ED at a low gray level. Therefore, it is possible to provide pixels PX (refer to Figure 1 ), and a display device DD (refer to Figure 1). In one or more embodiments, the second initialization voltage VAINT may have the same voltage level as the first driving voltage ELVDD (e.g., 13V). However, the present disclosure is not limited thereto.

[0141] In this embodiment, the fourth scan signal GIi may concurrently (e.g., simultaneously) control the fifth transistor T5 and the eighth transistor T8. Since the fifth transistor T5 and the eighth transistor T8 can be turned on by the same scan signal, the operation of initializing the source S1 of the first transistor T1 through the fifth transistor T5 and the operation of initializing the cathode CE of the light-emitting element ED through the eighth transistor T8 can be performed concurrently (e.g., simultaneously). Therefore, compared with the case where separate scan lines are used to control the fifth transistor T5 and the eighth transistor T8, the number of scan lines connected to the pixel PXij can be reduced, and the structure of the pixel circuit PXC or the scan driving circuit 300 for panel driving (refer to Figure 1 ). Therefore, the area of the non-display area NDA (refer to Figure 1 can be reduced, and the gap between the lines included in the pixel PXij can be increased. As a result, signal interference between the lines can be reduced.

[0142] In this embodiment, since the second period AP2_I occurs after the data writing period t3, the second period AP2_I occurs in a state where the data signal DS is charged in the first capacitor C1. In this case, since the first node N1 is set to a floating state, even if the first initialization voltage VINT is supplied to the second node N2 through the conduction operation of the fifth transistor T5, the voltage difference between the first node N1 and the second node N2 stored in the first capacitor C1 does not change. Therefore, the driving current in the emission period t5 can be determined by the gate-source voltage of the first transistor T1 corresponding to the voltage difference stored in the first capacitor C1, and the driving current also does not change.

[0143] In one or more embodiments of the present disclosure, the second period AP2_I may have a shorter duration than the first period AP1_I. For example, the duration of the second period AP2_I may be set short so that the voltage difference stored in the first capacitor C1 does not change. Therefore, even after the second initialization period t4 has passed, the voltage difference stored in the first capacitor C1 can remain substantially constant in response to the data signal DS (e.g., can remain constant in response to the data signal DS). Thereafter, during the emission period t5, the emission control signal EMi may have an active level. During the emission period t5, the first scan signal GWi, the second scan signal GRi, the third scan signal GCi, and the fourth scan signal GIi may have an inactive level.

[0144] During the emission period t5, the sixth transistor T6 may be turned on, and the cathode CE of the light-emitting element ED and the first transistor T1 may be electrically connected. In addition, during the emission period t5, the seventh transistor T7 may be turned on, and the first transistor T1 may be electrically connected to the second power line PL2. When the sixth transistor T6 and the seventh transistor T7 are turned on, the drive current may flow from the first power line PL1 receiving the first drive voltage ELVDD to the second power line PL2 receiving the second drive voltage ELVSS via the light-emitting element ED, the sixth transistor T6, the first transistor T1, and the seventh transistor T7.

[0145] The drive current flowing through the light-emitting element ED may be proportional to the square of the difference between the gate-source voltage (Vgs) and the threshold voltage (Vth) of the first transistor T1, i.e., "(Vgs - Vth) 2 ". Since the gate voltage level of the first transistor T1 is "(DS + ELVSS - (VREF - Vth))" and the source voltage level of the first transistor T1 is the second drive voltage ELVSS, the current flowing through the light-emitting element ED may be proportional to the square of the difference between the data signal DS and the reference voltage VREF, i.e., "(DS - VREF) 2 ".

[0146] According to the present disclosure, the threshold voltage (Vth) of the first transistor T1 may not affect the current flowing through the light-emitting element ED. The threshold voltages of the first transistors T1 included in the respective pixels PX (refer to Figure 1 ) may differ from each other according to the characteristics of the first transistors T1. However, the current flowing through the light-emitting element ED during the emission period t5 may be substantially constant (e.g., constant), regardless of the characteristics of the first transistors T1 included in each of the pixels PX (refer to Figure 1 ). That is, since the current flowing through the light-emitting element ED is proportional to "(DS - VREF) 2 ", pixels PX (refer to Figure 1 ) and a display device DD (refer to Figure 1 ) with improved display quality can be provided.

[0147] According to one or more embodiments of the present disclosure, the fourth scan signal GIi may be activated only during the first period AP1_I or AP1_I', and may be provided only during the first initialization period t1. That is, the second initialization period t4 may be omitted. The emission period t5 may be performed without a separate initialization period after the data write period t3.

[0148] Refer to Figures 3 to 4C, the holding frame HP may include a first initialization period t1_h, a second initialization period t4_h, and a emission period t5_h. The first initialization period t1_h, the second initialization period t4_h, and the emission period t5_h within the holding frame HP may be located at time points corresponding to the first initialization period t1, the second initialization period t4, and the emission period t5 within the write frame WP described above with reference to Figure 4A .

[0149] Within the holding frame HP, the fourth scan signal GIi may have an active level during a first period AP1_Ih and a second period AP2_Ih. Within the holding frame HP, the first scan signal GWi, the second scan signal GRi, the third scan signal GCi, and the emission control signal EMi may all have inactive levels during the remaining periods except for the emission period t5_h. That is, within the holding frame HP, during the remaining periods except for the emission period t5_h, only the fourth scan signal GIi may have an active level.

[0150] The first period AP1_Ih and the second period AP2_Ih within the holding frame HP may be located at time points corresponding to the first period AP1_I and the second period AP2_I within the write frame WP described above with reference to Figure 4A . That is, according to the present embodiment, even in low-frequency operation, the fourth scan signal GIi may be activated according to a fixed period, and the cathode CE of the light-emitting element ED may also be initialized according to a fixed period. Therefore, the variation of the driving current within the holding frame HP can be reduced or minimized, and the flicker phenomenon due to the luminance deviation caused by the current deviation can be prevented.

[0151] The emission period t5_h within the holding frame HP may be driven in the same manner as the emission period t5 within the write frame WP. During the emission period t5_h within the holding frame HP, the sixth transistor T6 and the seventh transistor T7 may be turned on, and the driving current may flow from the first power line PL1 receiving the first driving voltage ELVDD to the second power line PL2 receiving the second driving voltage ELVSS via the light-emitting element ED, the sixth transistor T6, the first transistor T1, and the seventh transistor T7.

[0152] According to one or more embodiments of the present disclosure, the first initialization period t1_h and the second initialization period t4_h may be omitted within the holding frame HP. That is, within the holding frame HP, the scan signals may all have an inactive state during the remaining periods except for the emission period t5_h.

[0153] Figure 5A is a circuit diagram of a pixel PXij_a according to one or more embodiments of the present disclosure. Figure 5B and Figure 5Cis a timing diagram for explaining the operation of pixel PXij_a according to one or more embodiments of the present disclosure. Among the components shown in Figure 5A , components that are the same as those shown in Figure 5A will be assigned the same reference numerals, and specific descriptions thereof will be omitted. Figure 3

[0154] Referring to Figures 5A to 5C , pixel PXij_a according to one or more embodiments includes pixel circuit PXCa and light-emitting element ED. In the present embodiment, pixel circuit PXCa may include eight transistors T1 to T4, T5a, T6, T7, and T8a, and two capacitors C1 and C2.

[0155] In the present embodiment, display panel DP (refer to Figure 1 ) may further include a fifth scan line that outputs a fifth scan signal. Figure 5A An example is shown in which pixel PXij_a is connected to the i-th fifth scan line GBLi that outputs the i-th fifth scan signal GBi among the fifth scan lines.

[0156] The eighth transistor T8a may be connected between the second initialization voltage line VL3 and the cathode CE of the light-emitting element ED, and may receive the i-th fifth scan signal GBi. The gate electrode G8 of the eighth transistor T8a may be connected to the i-th fifth scan line GBLi. That is, the eighth transistor T8a may receive a scan signal different from the scan signal received by the fifth transistor T5a, and the fifth transistor T5a and the eighth transistor T8a may be independently controlled.

[0157] As shown in Figure 5B , write frame WPa may include a first initialization period t1a, a compensation period t2a, a data write period t3a, a second initialization period t4a, and an emission period t5a.

[0158] According to this embodiment, the fifth scan signal GBi may have an active level during a first period AP1_B and a second period AP2_B in the write frame WPa. The first period AP1_B may be located before the data write period t3a, and the second period AP2_B may be located after the data write period t3a. In this embodiment, the first initialization period t1a may correspond to the first period AP1_B during which the fifth scan signal GBi has an active level, and the second initialization period t4a may correspond to the second period AP2_B during which the fifth scan signal GBi has an active level. The fifth scan signal GBi may have an inactive level during the compensation period t2a, the data write period t3a, and the emission period t5a. The initialization operation of the cathode CE may be performed during the first initialization period t1a and the second initialization period t4a.

[0159] The fifth scan signal GBi may have an active level during a first period AP1_Bh and a second period AP2_Bh in the hold frame HPa. The first period AP1_Bh and the second period AP2_Bh within the hold frame HPa may be located at time points corresponding to the first period AP1_B and the second period AP2_B within the write frame WPa. That is, according to this embodiment, even in low-frequency operation, the fifth scan signal GBi may be activated according to a fixed period, and the cathode CE of the light-emitting element ED may also be initialized according to a fixed period. Therefore, the variation of the driving current within the hold frame HPa may be reduced or minimized, and the occurrence of a flicker phenomenon due to current deviation may be prevented (for example, the flicker phenomenon caused by current deviation may be reduced).

[0160] According to this embodiment, the fourth scan signal GIi_a may be activated during a first period AP1_Ia and a second period AP2_Ia in the write frame WPa, and the first period AP1_Ia and the second period AP2_Ia during which the fourth scan signal GIi_a is activated may overlap with the first period AP1_B and the second period AP2_B during which the fifth scan signal GBi is activated. That is, the fourth scan signal GIi_a may have an active level during the first initialization period t1a and the second initialization period t4a.

[0161] According to one or more embodiments of the present disclosure, the period during which the fourth scan signal GIi_a is activated in the write frame WPa may overlap only with the first period AP1_B during which the fifth scan signal GBi is activated and may not overlap with the second period AP2_B during which the fifth scan signal GBi is activated. That is, the fourth scan signal GIi_a may be activated only during the first initialization period t1a and may be deactivated during the second initialization period t4a. Accordingly, the initialization operation of the cathode CE of the light-emitting element ED may be performed only during the second initialization period t4a. Therefore, the initialization operation of the source S1 of the first transistor T1 may be performed during the first initialization period t1a before the data write period t3a and may not be performed after the data write period t3a. That is, since the fifth transistor T5a and the eighth transistor T8a are independently controlled, a separate initialization voltage may not be provided to the second node N2 after the data write period t3a, and the voltage difference stored in the first capacitor C1 may remain substantially constant (e.g., may remain constant) in response to the data signal DS even after the second initialization period t4a has elapsed.

[0162] The fourth scan signal GIi_a may be deactivated in the hold frame HPa. That is, in the present embodiment, the initialization operation of the cathode CE of the light-emitting element ED may be performed only during the first initialization period t1a_h and the second initialization period t4a_h within the hold frame HPa. Since the change in the driving current can be reduced or minimized by the initialization operation of only the cathode CE in the hold frame HPa to prevent the flicker phenomenon, the power consumption may be reduced by maintaining the fourth scan signal GIi_a at a non-activated level in the hold frame HPa.

[0163] Figure 6A is a circuit diagram of a pixel PXij_b according to one or more embodiments of the present disclosure. Among the components shown in Figure 6A Among the components shown in Figure 3 the same components as those shown in

[0164] Referring to Figure 6A According to one or more embodiments of the present disclosure, the pixel PXij_b includes a pixel circuit PXCb and a light-emitting element ED. In the present embodiment, the pixel circuit PXCb may include seven transistors T1 to T7 and two capacitors C1 and C2. That is, different from the embodiment described with reference to Figure 3 in the present embodiment, the transistor that provides the initialization voltage to the cathode CE of the light-emitting element ED (i.e., the eighth transistor T8 (refer to Figure 3). Therefore, the structure of the pixel circuit PXCb can be simplified, and thus the degree of freedom in the design of the pixel circuit PXCb can be increased. In addition, a separate initialization voltage line for supplying an initialization voltage to the cathode CE (i.e., the second initialization voltage line VL3 (refer to Figure 3 )) can be omitted. Therefore, the area of the non-display area NDA (refer to Figure 1 ) can be reduced, and the gap between the lines connected to the pixel PXij_b can be increased. Therefore, signal interference between the lines can be reduced.

[0165] In one or more embodiments of the present disclosure, the fourth scan signal GIi may operate as described above with reference to Figure 5B and Figure 5C . That is, the fourth scan signal GIi may have an active level during a first initialization period t1a (refer to Figure 5B ) and a second initialization period t4a (refer to Figure 5B ) within the write frame WPa (refer to Figure 5B ) and may have an inactive level within the hold frame HPa (refer to Figure 5C ). Optionally, the fourth scan signal GIi may have an active level only during the first initialization period t1a (refer to Figure 5B ) within the write frame WPa (refer to Figure 5B ).

[0166] Figure 6B is a circuit diagram of the pixel PXij_c according to one or more embodiments of the present disclosure. Among the components shown in Figure 6B , components that are the same as those shown in Figure 3 will be assigned the same reference numerals, and detailed descriptions thereof will be omitted.

[0167] Referring to Figure 6B , according to one or more embodiments of the present disclosure, the pixel PXij_c includes a pixel circuit PXCc and a light-emitting element ED. In the present embodiment, the pixel circuit PXCc may include eight transistors T1 to T3, T4c, and T5 to T8 and two capacitors C1 and C2. In the present embodiment, the third scan lines GCL1 to GCLn (refer to Figure 1 ) for outputting the third scan signal may be omitted. As shown in Figure 6B , the fourth transistor T4c may receive the i-th second scan signal GRi. The gate electrode G4 of the fourth transistor T4c may be connected to the i-th second scan line GRLi. That is, the fourth transistor T4c may receive the same scan signal as the third transistor T3, and the third transistor T3 and the fourth transistor T4c may be controlled concurrently (e.g., simultaneously).

[0168] According to this embodiment, compared with the case of using separate scan lines to control the third transistor T3 and the fourth transistor T4c, the number of scan lines can be reduced, and the structure of the pixel circuit PXCc or the structure of the scan driving circuit 300 for panel driving (refer to Figure 1 ) can be simplified. Therefore, the area of the non-display area NDA (refer to Figure 1 ) can be reduced, and the gap between the lines connected to the pixel PXij_c can be increased. Therefore, the signal interference between the lines can be reduced.

[0169] In one or more embodiments of the present disclosure, the second scan signal GRi can operate as described above with reference to Figures 4A to 4C . That is, the second scan signal GRi can have an active level during the first initialization period t1 (refer to Figure 4A ) and the compensation period t2 (refer to Figure 4A ) within the write frame WP (refer to Figure 4A ) and can have an inactive level within the hold frame HP (refer to Figure 4C ).

[0170] Figure 6C is a circuit diagram of the pixel PXij_d according to one or more embodiments of the present disclosure. Among the components shown in Figure 6C , the components that are the same as those shown in Figure 3 will be assigned the same reference numerals, and the specific description thereof will be omitted.

[0171] Referring to Figure 6C , according to one or more embodiments of the present disclosure, the pixel PXij_d includes a pixel circuit PXCd and a light-emitting element ED. In this embodiment, the pixel circuit PXCd may include eight transistors T1 to T8 and two capacitors C1 and C2d.

[0172] According to this embodiment, the second capacitor C2d may be connected between the second power line PL2 and the second node N2. The second capacitor C2d may include a first electrode E3d connected to the second power line PL2 and a second electrode E4 connected to the second node N2. Therefore, in this embodiment, the second capacitor C2d can store the voltage difference between the second driving voltage ELVSS and the second node N2.

[0173] Figure 7A and Figure 7B are circuit diagrams of the pixels PX1a and PX2a according to one or more embodiments of the present disclosure.

[0174] Figure 7Ashows a pixel PX1a (hereinafter referred to as the first pixel PX1a) connected to the i-th first scan line GWLi and the j-th data line DLj, and Figure 7B shows a pixel PX2a (hereinafter referred to as the second pixel PX2a) connected to the i-th first scan line GWLi and the (j + 1)-th data line DLj+1. The first pixel PX1a and the second pixel PX2a are shown to be arranged in the same row. The first pixel PX1a and the second pixel PX2a can be commonly connected to the i-th first scan line GWLi, the i-th second scan line GRLi, the i-th third scan line GCLi, the i-th fourth scan line GILi, and the i-th emission control line EMLi.

[0175] The first pixel PX1a can include a first pixel circuit PXC1a and a first light-emitting element ED1a electrically connected to the first pixel circuit PXC1a. The second pixel PX2a can include a second pixel circuit PXC2a and a second light-emitting element ED2a electrically connected to the second pixel circuit PXC2a. The first light-emitting element ED1a and the second light-emitting element ED2a can emit lights of different colors. For example, the first light-emitting element ED1a can emit light of a first color (e.g., one of red light, blue light, and green light), and the second light-emitting element ED2a can emit light of a second color (e.g., another one of red light, blue light, and green light).

[0176] A fifth transistor T5_1 included in the first pixel circuit PXC1a can be connected to a first-first initialization voltage line VL2_1. The first-first initialization voltage line VL2_1 can receive a first-first initialization voltage VINT_1. A fifth transistor T5_2 included in the second pixel circuit PXC2a can be connected to a first-second initialization voltage line VL2_2. The first-second initialization voltage line VL2_2 can receive a first-second initialization voltage VINT_2. The first-second initialization voltage VINT_2 can have a voltage level different from that of the first-first initialization voltage VINT_1. That is, according to this embodiment, the first-first initialization voltage VINT_1 provided to the source S1 of the first transistor T1 in the first pixel circuit PXC1a and the first-second initialization voltage VINT_2 provided to the source S1 of the first transistor T1 in the second pixel circuit PXC2a can be independently provided according to the characteristics of the light-emitting elements ED1a and ED2a.

[0177] Figure 8A and Figure 8B are circuit diagrams of pixels PX1b and PX2b according to one or more embodiments of the present disclosure.

[0178] Figure 8AShows a pixel PX1b (hereinafter referred to as the first pixel PX1b) connected to the i-th first scan line GWLi and the j-th data line DLj, and Figure 8B shows a pixel PX2b (hereinafter referred to as the second pixel PX2b) connected to the i-th first scan line GWLi and the (j + 1)-th data line DLj+1. The first pixel PX1b and the second pixel PX2b are shown to be set in the same row. The first pixel PX1b and the second pixel PX2b can be commonly connected to the i-th first scan line GWLi, the i-th second scan line GRLi, the i-th third scan line GCLi, the i-th fourth scan line GILi, and the i-th emission control line EMLi.

[0179] The first pixel PX1b can include a first pixel circuit PXC1b and a first light-emitting element ED1b electrically connected to the first pixel circuit PXC1b. The second pixel PX2b can include a second pixel circuit PXC2b and a second light-emitting element ED2b electrically connected to the second pixel circuit PXC2b. The first light-emitting element ED1b and the second light-emitting element ED2b can provide light of different colors. For example, the first light-emitting element ED1b can provide light of a first color (e.g., one of red light, blue light, and green light), and the second light-emitting element ED2b can provide light of a second color (e.g., another one of red light, blue light, and green light).

[0180] An eighth transistor T8_1 included in the first pixel circuit PXC1b can be connected to a second-first initialization voltage line VL3_1. The second-first initialization voltage line VL3_1 can receive a second-first initialization voltage VAINT_1. An eighth transistor T8_2 included in the second pixel circuit PXC2b can be connected to a second-second initialization voltage line VL3_2. The second-second initialization voltage line VL3_2 can receive a second-second initialization voltage VAINT_2. The second-second initialization voltage VAINT_2 can have a voltage level different from the voltage level of the second-first initialization voltage VAINT_1. That is, according to this embodiment, the second-first initialization voltage VAINT_1 provided to the cathode CE of the light-emitting element ED1b in the first pixel circuit PXC1b and the second-second initialization voltage VAINT_2 provided to the cathode CE of the light-emitting element ED2b in the second pixel circuit PXC2b can be independently provided according to the characteristics of the light-emitting elements ED1b and ED2b.

[0181] For example, different amounts of parasitic capacitance may be formed in light-emitting elements ED1b and ED2b that provide light of different colors. According to one or more embodiments, a second-first initialization voltage VAINT_1 and a second-second initialization voltage VAINT_2 having different levels may be provided to the cathodes CE of the first light-emitting element ED1b and the second light-emitting element ED2b, respectively, to reflect the parasitic capacitance formed in the first light-emitting element ED1b that provides light of a first color and the parasitic capacitance formed in the second light-emitting element ED2b that provides light of a second color. Accordingly, gray scale may be improved, and the ability to express changed colors may also be improved. Accordingly, a display device DD having improved display quality may be provided (refer to Figure 1 )

[0182] Figure 9A and Figure 9B are cross-sectional views of display panels DP and DPa according to one or more embodiments of the present disclosure. Figure 10 is a cross-sectional view of a display panel DPb according to one or more embodiments of the present disclosure. Figure 11 is a cross-sectional view of a display panel DPc according to one or more embodiments of the present disclosure. Figures 9A to 10 respectively show enlarged views of portions of the display area DA, and Figure 11 shows an enlarged view of a portion of the display area DA and a portion of the non-display area NDA.

[0183] Refer to Figure 9A , the display panel DP may include a substrate layer BL and a circuit element layer DP-CL, a display element layer DP-ED, and a encapsulation layer ESL disposed on the substrate layer BL. The circuit element layer DP-CL includes at least a plurality of insulating layers and circuit elements. The insulating layers described below may include organic layers and / or inorganic layers.

[0184] The insulating layer, the semiconductor layer, and the conductive layer are formed by coating and / or deposition, etc. Thereafter, the insulating layer, the semiconductor layer, and the conductive layer may selectively undergo patterning through a photolithography process and an etching process. A semiconductor pattern, a conductive pattern, and signal lines are formed through these processes. Patterns disposed in the same layer are formed through the same process.

[0185] The substrate layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. Specifically, the synthetic resin layer may be a polyimide-based resin layer, and its material is not particularly limited. The synthetic resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane-based resin, a cellulose resin, a silicone resin, a polyamide resin, and a perylene resin. In addition, the substrate layer BL may include a glass substrate, a metal substrate, and / or an organic / inorganic composite substrate. The substrate layer BL may include a first polyimide layer, a second polyimide layer, and / or an inorganic layer disposed therebetween.

[0186] At least one inorganic layer is formed on the upper surface of the substrate layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed of multiple layers. The multiple inorganic layers may constitute the barrier layer BRL described below. The barrier layer BRL prevents the penetration of foreign substances from the outside. The barrier layer BRL may include a silicon oxide layer and / or a silicon nitride layer. A plurality of silicon oxide layers and / or a plurality of silicon nitride layers may be provided. The silicon oxide layer and / or the silicon nitride layer may be stacked alternately with each other. For example, the substrate layer BL may include a first synthetic resin layer, a silicon oxide (SiO x ) layer provided on the first synthetic resin layer, an amorphous silicon (a-Si) layer provided on the silicon oxide layer, and / or a second synthetic resin layer provided on the amorphous silicon layer. The silicon oxide layer and / or the amorphous silicon layer may be referred to as a substrate barrier layer.

[0187] The lower conductive layer BML may be provided on the barrier layer BRL. The lower conductive layer BML may be provided in a patterned form and may be provided to overlap each of the transistors. The lower conductive layer BML may block the influence of the electric potential caused by the polarization phenomenon of the substrate layer BL on the transistors. In addition, the lower conductive layer BML may block light incident on the transistors from below.

[0188] The lower conductive layer BML may include a reflective metal. For example, the lower conductive layer BML may include titanium (Ti), molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride, and / or copper (Cu).

[0189] The lower conductive layer BML may be provided in an isolated form. Optionally, the lower conductive layer BML may be synchronized with the source and / or gate of the transistor. In another case, the lower conductive layer BML may be connected to another electrode and may independently receive a constant voltage and / or a pulse signal. The lower conductive layer BML according to one or more embodiments of the present disclosure may be provided in various forms and is not limited to any one embodiment.

[0190] The first insulating layer 10 may be disposed on the barrier layer BRL and the lower conductive layer BML. The first insulating layer 10 may be referred to as a buffer layer. The first insulating layer 10 may improve the adhesion between the barrier layer BRL and the semiconductor pattern and / or the conductive pattern. The first insulating layer 10 may include a silicon oxide layer and / or a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be stacked alternately with each other.

[0191] The semiconductor layer may be disposed on the first insulating layer 10. The semiconductor layer may include a plurality of oxide semiconductor patterns SP1 and SP2. Each of the oxide semiconductor patterns SP1 and SP2 may include a crystalline and / or amorphous oxide semiconductor. For example, each of the oxide semiconductor patterns SP1 and SP2 may include a metal oxide of zinc (Zn), indium (In), gallium (Ga), tin (Sn), and / or titanium (Ti). Optionally, each of the oxide semiconductor patterns SP1 and SP2 may include a mixture of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and / or titanium (Ti) and / or its oxide. Each of the oxide semiconductor patterns SP1 and SP2 may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZnO), zinc indium oxide (ZIO), indium oxide (In 2 O 3 ), titanium oxide (TiO), indium zinc tin oxide (IZTO), and / or zinc tin oxide (ZTO).

[0192] Each of the oxide semiconductor patterns SP1 and SP2 may include a plurality of regions distinguishable according to whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, referred to as the reduced region) has higher conductivity than the region where the metal oxide is not reduced (hereinafter, referred to as the non-reduced region). The reduced region basically serves as the source region, drain region, and / or signal transmission region of the transistor. The non-reduced region basically corresponds to the channel region (or semiconductor region or non-reduced region) of the transistor. In other words, a part of the semiconductor pattern may be the channel region of the transistor, another part may be the source region or drain region of the transistor, and another part may be the signal transmission region.

[0193] The source region or drain region may be the source electrodes S1 to S8 or drain electrodes D1 to D8 of the transistors T1 to T8 described with reference to Figure 3 The source electrodes S1 to S8 or drain electrodes D1 to D8 of the transistors T1 to T8 may include the source region or drain region of the above-described oxide semiconductor patterns SP1 and SP2 and the conductive pattern connected thereto. Hereinafter, for convenience of description, the source region or drain region of the oxide semiconductor patterns SP1 and SP2 is referred to as the source electrode or drain electrode.

[0194] In Figure 3Among the transistors T1 to T8, the second transistor T2 and the fourth transistor T4 are shown in Figure 9A . The second transistor T2 may include a first oxide semiconductor pattern SP1, and the first oxide semiconductor pattern SP1 includes a source S2, a first channel portion CH1, and a drain D2. The source S2 and the drain D2 of the second transistor T2 may extend from the first channel portion CH1 in opposite directions. The fourth transistor T4 may include a second oxide semiconductor pattern SP2, and the second oxide semiconductor pattern SP2 includes a source S4, a second channel portion CH2, and a drain D4. The source S4 and the drain D4 of the fourth transistor T4 may extend from the second channel portion CH2 in opposite directions. The description of the first oxide semiconductor pattern SP1 and the second oxide semiconductor pattern SP2 may be applied to the oxide semiconductor patterns of the remaining transistors not shown in Figure 9A in the same manner.

[0195] A second insulating layer 20 may be provided on the first insulating layer 10 to cover the oxide semiconductor patterns SP1 and SP2. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer structure and / or a multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0196] Gate electrodes G2 and G4 may be provided on the second insulating layer 20. The gate electrodes G2 and G4 may be provided above the oxide semiconductor patterns SP1 and SP2, respectively. However, this is illustrative, and the gate electrodes G2 and G4 may be provided below the oxide semiconductor patterns SP1 and SP2, respectively.

[0197] In Figure 9A , as an example, the gate electrode G2 of the second transistor T2 and the gate electrode G4 of the fourth transistor T4 are shown. The gate electrode G2 of the second transistor T2 may be provided above the first channel portion CH1 of the first oxide semiconductor pattern SP1, and the gate electrode G4 of the fourth transistor T4 may be provided above the second channel portion CH2 of the second oxide semiconductor pattern SP2. The description of the gate electrode G2 of the second transistor T2 and the gate electrode G4 of the fourth transistor T4 may be applied to the gate electrodes of the remaining transistors not shown in Figure 9A in the same manner.

[0198] The gate electrodes G2 and G4 may include titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), and / or an alloy thereof, but are not particularly limited thereto.

[0199] The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the gate electrodes G2 and G4. The fourth insulating layer 40 may be disposed on the third insulating layer 30. Each of the third insulating layer 30 and the fourth insulating layer 40 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. In one or more embodiments, each of the third insulating layer 30 and the fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0200] A plurality of conductive patterns may be disposed on the fourth insulating layer 40. In the present embodiment, the conductive patterns disposed on the fourth insulating layer 40 may include a connection electrode CNE, a data line DLj, a first power line PL1, and a second power line PL2.

[0201] In Figure 9A As an example, a connection electrode CNE connected to the cathode CE is shown. Further, in one or more embodiments, the connection electrode CNE connected to the cathode CE may be connected to the drain D6 of the sixth transistor T6 that has been described above with reference to Figure 3 Although only the connection electrode CNE connected to the cathode CE is shown in Figure 9A A plurality of connection electrodes connected to the drains and sources of the transistors may be disposed on the second insulating layer 20.

[0202] In Figure 9A A part of the first power line PL1 is shown. The first power line PL1 may be connected to the drain D4 of the fourth transistor T4 through a contact hole penetrating the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40. In one or more embodiments, among the connection electrodes, the connection electrode connected to the drain D4 of the fourth transistor T4 may be integral with the first power line PL1. In the present embodiment, the first power line PL1 may include a structure of Ti / Al / Ti.

[0203] In Figure 9A A part of the data line DLj is shown. The data line DLj may be connected to the source S2 of the second transistor T2 through a contact hole penetrating the second insulating layer 20, the third insulating layer 30, and the fourth insulating layer 40. Among the connection electrodes, the connection electrode connected to the source S2 of the second transistor T2 may be integral with the data line DLj.

[0204] In Figure 9APart of the second power line PL2 is shown. In the present embodiment, the second power line PL2 may be disposed on the same layer as the first power line PL1 (e.g., at the same layer). In addition, the first power line PL1 and the second power line PL2 may be disposed on the same layer as the data line DLj (e.g., at the same layer).

[0205] The second power line PL2 may include the same material as the first power line PL1. According to the present embodiment, the second power line PL2 may include a Ti / Al / Ti structure. Since the second power line PL2 has a low specific resistance, the amount of noise caused by voltage drop and ripple in the second power line PL2 can be reduced. The source S1 of the first transistor T1 (referred to as the driving transistor) (refer to Figure 3 ) may be electrically connected to the second power line PL2 with reduced noise, so that the voltage level change of the source S1 of the first transistor T1 (refer to Figure 3 ) can be prevented. In addition, the light-emitting element ED may be connected between the drain D1 of the first transistor T1 (refer to Figure 3 ) and the first power line PL1, so that the voltage level of the source S1 of the first transistor T1 (refer to Figure 3 ) can be unaffected by the specific resistance of the material included in one electrode of the light-emitting element ED. Therefore, the driving current change of the light-emitting element ED can be prevented. Therefore, the display quality of the display device DD (refer to Figure 3 ) can be improved. Figure 3 ) and the first power line PL1, so that the voltage level of the source S1 of the first transistor T1 (refer to Figure 3 ) can be unaffected by the specific resistance of the material included in one electrode of the light-emitting element ED. Therefore, the driving current change of the light-emitting element ED can be prevented. Therefore, the display quality of the display device DD (refer to Figure 3 ) can be improved. Figure 1 ) can be improved.

[0206] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40, the connection electrode CNE, the data line DLj, the first power line PL1, and the second power line PL2. The fifth insulating layer 50 may cover the connection electrode CNE, the data line DLj, the first power line PL1, and the second power line PL2 disposed on the fourth insulating layer 40. In the present embodiment, the fifth insulating layer 50 may be an organic layer and may have a single-layer structure, but there is no particular limitation.

[0207] The cathode CE of the light-emitting element ED may be disposed on the fifth insulating layer 50. The cathode CE may be connected to the connection electrode CNE through a contact hole penetrating the fifth insulating layer 50. In the present embodiment, the cathode CE may have an ITO / Ag / ITO structure.

[0208] The pixel definition layer PDL may be disposed on the fifth insulating layer 50. The opening OP-PDL of the pixel definition layer PDL (hereinafter referred to as the light-emitting opening) may expose at least a part of the cathode CE. The light-emitting opening OP-PDL of the pixel definition layer PDL may define an emission region. For example, a plurality of pixels PX (refer to Figure 1 ) may be arranged on the plane of the display panel DP according to a certain rule. The region where a plurality of pixels PX (refer to Figure 1 ) are provided may be defined as a pixel region, and one pixel region may include an emission region and a non-emission region adjacent to the emission region. The non-emission region may be around the emission region (for example, may surround the emission region).

[0209] The pixel definition layer PDL may be an organic layer. For example, the pixel definition layer PDL may include general polymers (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, parylene polymers, vinyl alcohol polymers, and / or their blends.

[0210] In one or more embodiments, the pixel definition layer PDL may have the property of absorbing light. For example, the pixel definition layer PDL may be black. That is, the pixel definition layer PDL may include a black colorant. The black colorant may include black dyes and / or black pigments. The black colorant may include carbon black, metals such as chromium, and / or their oxides. The pixel definition layer PDL may correspond to a light-shielding pattern having a light-shielding property.

[0211] The intermediate layer IML may be disposed on the cathode CE. The intermediate layer IML may at least include an emission layer EML. In one or more embodiments, the intermediate layer IML may include a functional layer FNL and an emission layer EML. The functional layer FNL may control the movement of charges between the cathode CE and the anode AE. For example, the functional layer FNL may include a plurality of layers, or may include two or more layers separated from each other (for example, spaced apart) with the emission layer EML therebetween. Figure 9A An example in which the functional layer FNL includes an electron control layer ECL and a hole control layer HCL is shown.

[0212] The electron control layer ECL may be disposed on the cathode CE. The electron control layer ECL may include at least one of an electron injection layer and an electron transport layer. In one or more embodiments, the electron control layer ECL may further include a hole blocking layer.

[0213] The emission layer EML can be disposed on the electron control layer ECL. The emission layer EML can be disposed only in a region corresponding to the light-emitting opening OP-PDL. The emission layer EML can be separately formed in each of a plurality of pixels PX (refer to Figure 1 ). Although a patterned emission layer EML is shown in the present embodiment, the emission layer EML can be commonly disposed for the plurality of pixels PX. The commonly disposed emission layer EML can generate white light and / or blue light. In addition, the emission layer EML can have a multilayer structure.

[0214] The hole control layer HCL can be disposed on the emission layer EML. The hole control layer HCL can include at least one of a hole injection layer and a hole transport layer. The hole transport layer can include at least one of a hole buffer layer and an electron blocking layer.

[0215] The anode AE can be disposed on the hole control layer HCL. That is, according to the present embodiment, in the light-emitting opening OP-PDL, the emission layer EML can be disposed above the cathode CE, and the anode AE can be disposed above the emission layer EML. In the present embodiment, a plurality of anodes AE can be provided. The anode AE can be separate for each pixel PX (refer to Figure 1 ), and can be arranged in a pattern form. Each of the anodes AE can be connected to the first power line PL1 through a contact hole penetrating the pixel defining layer PDL and the fifth insulating layer 50 in a non-emitting region in the display area DA. In the present embodiment, the anode AE can be connected to the first power line PL1 by directly contacting the first power line PL1.

[0216] Because the anode AE is separate for each pixel PX (refer to Figure 1 ), a voltage drop can be reduced or prevented as compared with when the anode AE is provided as a common layer. Therefore, the anode AE can be made thin without preparing for a voltage drop, and a reduction in display efficiency can be prevented. In the present embodiment, the anode AE can include a MgAg alloy.

[0217] The display panel DP can further include a packaging layer ESL disposed on the display element layer DP-ED and sealing the display element layer DP-ED. The packaging layer ESL can include at least an inorganic layer and / or an organic layer. In one or more embodiments, the packaging layer ESL can include two inorganic layers IL1 and IL2 and / or an organic layer OL disposed therebetween. In addition, the display panel DP can further include functional layers such as an antireflection layer and / or a reflectance control layer.

[0218] Refer to Figure 9B , the display panel DPa according to the present embodiment can include a substrate layer BL, a circuit element layer DP-CLa, a display element layer DP-ED, and a packaging layer ESL. InFigure 9B Among the components shown in Figure 9A the same components as those shown in

[0219] When compared with Figure 9A the circuit element layer DP-CL in the embodiment shown in

[0220] the first connection electrode CNE1 and the data line DLj may be provided on the fourth insulating layer 40. Although only the first connection electrode CNE1 connected to the drain D4 of the fourth transistor T4 is shown in Figure 9B a plurality of first connection electrodes connected to the drains and sources of the transistors may be provided on the third insulating layer 30.

[0221] The second connection electrode CNE2 connected to the cathode CE, the first power line PL1a, and the second power line PL2a may be provided on the fifth insulating layer 50. In one or more embodiments, the second connection electrode CNE2 may be connected to the drain D6 of the sixth transistor T6 (see Figure 3 ). The first power line PL1a may be connected to the first connection electrode CNE1 connected to the drain D4 of the fourth transistor T4 through a contact hole penetrating the fifth insulating layer 50. The first power line PL1a may be electrically connected to the drain D4 of the fourth transistor T4 through the first connection electrode CNE1.

[0222] In the present embodiment, the first power line PL1a and the second power line PL2a may be provided on a layer different from the layer on which the data line DLj is provided. However, the arrangement of the data line DLj, the first power line PL1a, and the second power line PL2a is not limited to any one embodiment. For example, the first power line PL1a and the second power line PL2a may be provided on different layers. One of the first power line PL1a and the second power line PL2a may be provided on the fourth insulating layer 40, and the other of the first power line PL1a and the second power line PL2a may be provided on the fifth insulating layer 50.

[0223] Referring to Figure 10 the display panel DPb according to the present embodiment may include a substrate layer BL, a circuit element layer DP-CLb, a display element layer DP-ED, and a packaging layer ESL. Among the components shown in Figure 10 the same components as those shown in Figure 9A will be assigned the same reference numerals, and the detailed description thereof will be omitted.

[0224] When compared with Figure 9A andFigure 9B When comparing the circuit element layer DP-CL and DP-CLa in the embodiment shown, the circuit element layer DP-CLb according to the present embodiment may further include a connection conductive pattern CNP that connects the anode AE and the first power line PL1. The connection conductive pattern CNP may be disposed on the fourth insulating layer 40 and may cover the first power line PL1. Accordingly, the anode AE may be connected to the connection conductive pattern CNP through a contact hole that penetrates the fifth insulating layer 50 and the pixel defining layer PDL, and may be electrically connected to the first power line PL1 through the connection conductive pattern CNP.

[0225] In the present embodiment, the connection conductive pattern CNP may include indium tin oxide (ITO). The connection conductive pattern CNP may include the same material as the material disposed in the uppermost layer of the first power line PL1. However, the material of the connection conductive pattern CNP is not limited thereto.

[0226] According to the present embodiment, by providing the connection conductive pattern CNP that covers the first power line PL1, damage to the first power line PL1 in subsequent processes (for example, a process of forming a contact hole that penetrates the fifth insulating layer 50) can be prevented.

[0227] Referring to Figure 11 , the display panel DPc according to the present embodiment may include a substrate layer BL, a circuit element layer DP-CLc, a display element layer DP-EDc, and a packaging layer ESL. Among the components shown in Figure 11 , components that are the same as those shown in Figure 9A will be assigned the same reference numerals, and detailed descriptions thereof will be omitted.

[0228] When comparing with the anode AE in the embodiment shown in Figures 9A to 10 , the anode AEc according to the present embodiment may be commonly provided for a plurality of pixels PX (refer to Figure 1 ). The anode AEc that is commonly provided for the pixels PX (refer to Figure 1 ) may be connected to the first power line PL1c in the non-display area NDA. Although Figure 11 shows an example in which the anode AEc is connected to the first power line PL1c through a contact hole that penetrates the pixel defining layer PDLc and the fifth insulating layer 50c in the non-display area NDA, the present disclosure is not limited thereto. For example, the first power line PL1c may be disposed outside the pixel defining layer PDLc and the fifth insulating layer 50c. In this case, the anode AEc may extend along the edges of the pixel defining layer PDLc and the fifth insulating layer 50c, and may be connected to the first power line PL1c outside the pixel defining layer PDLc and the fifth insulating layer 50c.

[0229] According to this embodiment, for each of the pixels PX in the display area DA (refer to Figure 1 ), contact holes for connecting the anode AEc and the first power line PL1c may not be formed in the fifth insulating layer 50c and the pixel defining layer PDLc, so the process can be relatively simplified.

[0230] Figure 12 is a cross-sectional view of a display panel DP' according to one or more embodiments of the present disclosure. Figure 13A is according to one or more embodiments of the present disclosure Figure 12 an enlarged cross-sectional view of the area AA in Figure 13B is according to one or more embodiments of the present disclosure Figure 12 an enlarged cross-sectional view of the area BB in

[0231] Refer to Figure 12 , the display panel DP' may include a substrate layer BL and a circuit element layer DP-CL', an upper insulating layer UIL, a connection line CN, a display element layer DP-ED', and a packaging layer ESL provided on the substrate layer BL.

[0232] In Figure 12 , one transistor TR and two capacitors C1 and C2 of the pixel driver PXC are shown. The transistor TR may correspond to the transistor connected to the light-emitting element ED' through the connection line CN, that is, the connection transistor connected to the node corresponding to the cathode CE' of the light-emitting element ED' (for example, Figure 3 the fourth node N4). Specifically, the transistor TR may correspond to Figure 3 the sixth transistor T6. In one or more embodiments, other transistors constituting the pixel driver PXC may have the same structure as the transistor TR (hereinafter referred to as the connection transistor) shown in Figure 12 . However, this is illustrative, and other transistors constituting the pixel driver PXC may have a structure different from that of the connection transistor TR and are not limited to any one embodiment.

[0233] The lower conductive layer BML may be provided to overlap with the connection transistor TR and may be covered by the first insulating layer 10. At least one of an inorganic barrier layer and a buffer layer may be additionally provided between the lower conductive layer BML and the substrate layer BL.

[0234] In the present embodiment, the lower conductive layer BML may be connected to the source electrode of the connection transistor TR (or transistor) through the source electrode pattern W1. In this case, the lower conductive layer BML may be synchronized with the source electrode of the transistor TR. However, this is illustrative, and the lower conductive layer BML may be connected to the gate of the transistor TR and may be synchronized with the gate. Alternatively, the lower conductive layer BML may be connected to another electrode and may receive a constant voltage or a pulse signal independently. In another case, the lower conductive layer BML may be provided in a form isolated from another conductive pattern. The lower conductive layer BML according to one or more embodiments of the present disclosure may be provided in various forms and is not limited to any one embodiment.

[0235] The connection transistor TR may be provided on the first insulating layer 10. The connection transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be provided on the first insulating layer 10. The semiconductor pattern SP may include a source region SR, a drain region DR, and a channel region CHR that are distinguishable from each other according to the degree of conductivity.

[0236] The display panel DP' according to the present embodiment may further include a source electrode pattern W1 and a drain electrode pattern W2 that are respectively connected to the source region SR and the drain region DR. Specifically, each of the source electrode pattern W1 and the drain electrode pattern W2 may be integrally formed with one of the lines constituting the pixel driver PXC and is not limited to any one embodiment.

[0237] The second insulating layer 20 may be commonly stacked with a plurality of pixels PX (refer to Figure 1 ), and may cover the semiconductor pattern SP and the first insulating layer 10. The gate electrode GE may be provided on the second insulating layer 20. The gate electrode GE may correspond to the gate of the connection transistor TR and may be stacked with the channel region CHR in the thickness direction of the substrate layer BL (e.g., the third direction DR3).

[0238] The third insulating layer 30 may be provided on the gate electrode GE and the second insulating layer 20, and the fourth insulating layer 40 may be provided on the third insulating layer 30. The first capacitor electrode CPE1, the second capacitor electrode CPE2, and the third capacitor electrode CPE3 may be included in the plurality of conductive patterns.

[0239] The first capacitor electrode CPE1 and the second capacitor electrode CPE2 constitute the first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be separated from each other (e.g., spaced apart) and the first insulating layer 10 and the second insulating layer 20 are located therebetween.

[0240] In one or more embodiments of the present disclosure, the first capacitor electrode CPE1 and the lower conductive layer BML may have an integral shape (e.g., may be integrally formed at the same layer). Additionally, the second capacitor electrode CPE2 and the gate electrode GE may have an integral shape (e.g., may be integrally formed at the same layer).

[0241] The third capacitor electrode CPE3 may be disposed on the third insulating layer 30. The third capacitor electrode CPE3 may be separated from (e.g., spaced apart from) the second capacitor electrode CPE2 with the third insulating layer 30 therebetween, and may be superposed on the second capacitor electrode CPE2 when viewed from above in a plane (e.g., in a plan view). In other words, the second capacitor electrode CPE2 may be superposed on the third capacitor electrode CPE3 in the third direction DR3. The third capacitor electrode CPE3 and the second capacitor electrode CPE2 together may constitute the second capacitor C2.

[0242] The fourth insulating layer 40 may be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. The source electrode pattern W1 and the drain electrode pattern W2 may be disposed on the fourth insulating layer 40. The source electrode pattern W1 may be connected to the source region SR of the connection transistor TR through the first contact hole CNT1, and the source electrode pattern W1 and the source region SR of the semiconductor pattern SP may be used as the source electrode of the connection transistor TR. The drain electrode pattern W2 may be connected to the drain region DR of the connection transistor TR through the second contact hole CNT2, and the drain electrode pattern W2 and the drain region DR of the semiconductor pattern SP may be used as the drain electrode of the connection transistor TR. In one or more embodiments, the source electrode pattern W1 and the drain electrode pattern W2 may be disposed in the display panels DP, DPa, DPb, and DPc described above with reference to Figures 9A to 11 The fifth insulating layer 50 may be disposed on the source electrode pattern W1, the drain electrode pattern W2, and the fourth insulating layer 40.

[0243] The connection line CN may be disposed on the fifth insulating layer 50. The connection line CN may electrically connect the pixel driver PXC and the light-emitting element ED'. That is, the connection line CN may electrically connect the connection transistor TR and the light-emitting element ED'. The connection line CN may be a connection node connecting the pixel driver PXC and the light-emitting element ED'. That is, the connection line CN may correspond to Figure 3 the fourth node N4 shown in. However, this is illustrative, and the connection line CN may be defined as a connection node with various elements among the elements constituting the pixel driver PXC according to the design of the pixel driver PXC, as long as the connection line CN can be connected to the light-emitting element ED', and is not limited to any one embodiment.

[0244] The upper insulating layer UIL may be disposed on the connection line CN and the fifth insulating layer 50. The upper insulating layer UIL may be disposed on the fifth insulating layer 50 and may cover the connection line CN. The upper insulating layer UIL may be an organic layer. For example, the upper insulating layer UIL may include general polymers such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), and / or polystyrene (PS), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, parylene polymers, vinyl alcohol polymers, and / or blends thereof.

[0245] The upper insulating layer UIL may include an opening for exposing at least a portion of the connection line CN. The connection line CN may be electrically connected to the light-emitting element ED' through the portion exposed by the upper insulating layer UIL. That is, the connection line CN may electrically connect the connection transistor TR and the light-emitting element ED'. A detailed description thereof will be given below. In one or more embodiments, in the display panel DP' according to one or more embodiments of the present disclosure, the upper insulating layer UIL may be omitted, or a plurality of upper insulating layers UIL may be provided. However, the present disclosure is not limited to any one embodiment.

[0246] The display element layer DP-ED' may be disposed on the upper insulating layer UIL. The display element layer DP-ED' may include a pixel defining layer PDL, a light-emitting element ED', and a spacer SPR. The light-emitting element ED' may include an anode AE', an intermediate layer IML', and a cathode CE'.

[0247] In the present embodiment, the anode AE' may be disposed on the upper insulating layer UIL. The anode AE' may be a transmissive reflective electrode, a transmissive electrode, and / or a reflective electrode. According to one or more embodiments of the present disclosure, the anode AE' may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and / or a compound thereof, and / or a transparent and / or semi-transparent electrode layer formed on the reflective layer. The transparent and / or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), aluminum-doped zinc oxide (AZO), and combinations thereof. For example, the anode AE' may include a stacked structure of ITO / Ag / ITO. The anode AE' may be connected to the first power line PL1 (refer to Figure 3 ), and the first driving voltage ELVDD (refer to Figure 3 may be applied to the anode AE'.

[0248] A light-emitting opening OP-PDL for exposing at least a part of the anode AE' may be defined in the pixel definition layer PDL. A plurality of light-emitting openings OP-PDL may be provided. The plurality of light-emitting openings OP-PDL may be provided to correspond to the light-emitting elements ED' respectively. All components of the light-emitting element ED' may be provided in the light-emitting opening OP-PDL to be stacked on one another, and the light-emitting opening OP-PDL may be an area that substantially displays the light emitted by the light-emitting element ED'.

[0249] The intermediate layer IML' may be provided between the anode AE' and the cathode CE'. The intermediate layer IML' may include an emission layer EML and a functional layer FNL'. The light-emitting element ED' may include an intermediate layer IML' having various structures, and is not limited to any one embodiment. For example, the functional layer FNL' may include a plurality of layers, or may include two or more layers (e.g., see Figure 11 ) that are separated from each other (e.g., spaced apart) and the emission layer EML is located between them. Optionally, in one or more embodiments, the functional layer FNL' may be omitted. Although Figure 12 an embodiment is shown in which the emission layer EML and the functional layer FNL' have different shapes, the present disclosure is not limited thereto, and when viewed from above the plane (e.g., in a plan view), the emission layer EML and the functional layer FNL' may be provided in the same shape (e.g., may be integrally provided at the same layer).

[0250] The functional layer FNL' may be provided between the anode AE' and the cathode CE'. Specifically, the functional layer FNL' may be provided between the anode AE' and the emission layer EML, or may be provided between the cathode CE' and the emission layer EML. Optionally, the functional layer FNL' may be provided between the anode AE' and the emission layer EML and between the cathode CE' and the emission layer EML. In the present embodiment, the emission layer EML is shown as being inserted into the functional layer FNL'. However, this is illustrative, and the functional layer FNL' may include a layer provided between the emission layer EML and the anode AE' and / or a layer provided between the emission layer EML and the cathode CE', and is not limited to any one embodiment. The functional layer FNL' may include a hole control layer and an electron control layer. At least a part of the hole control layer may be provided between the anode AE' and the emission layer EML, and at least a part of the electron control layer may be provided between the emission layer EML and the cathode CE'.

[0251] The cathode CE' may be provided on the intermediate layer IML'. As described above, the cathode CE' may be connected to the connection line CN and may be electrically connected to the pixel driver PXC. That is, the cathode CE' may be electrically connected to the connection transistor TR through the connection line CN.

[0252] As described above, the connection line CN may include a driving connection portion CDP and a light-emitting connection portion CEP. The driving connection portion CDP may be a portion of the connection line CN connected to the pixel driver PXC and may be a portion substantially connected to the connection transistor TR. In the present embodiment, the driving connection portion CDP may penetrate the fifth insulating layer 50 and may be electrically connected to the drain region DR of the semiconductor pattern SP through the drain electrode pattern W2. The light-emitting connection portion CEP may be a portion of the connection line CN connected to the light-emitting element ED'. The light-emitting connection portion CEP may be a portion defined in the region exposed by the upper insulating layer UIL and connected to the cathode CE'. The tip portion TP may be defined in the light-emitting connection portion CEP.

[0253] Hereinafter, the light-emitting connection portion CEP of the connection line CN will be described in more detail with reference to Figure 12 and Figure 13A As shown in Figure 12 and Figure 13A The connection line CN may have a three-layer structure. Specifically, the connection line CN may include a first layer L1, a second layer L2, and a third layer L3 sequentially stacked in the third direction DR3. The second layer L2 may include a material different from that of the first layer L1. In addition, the second layer L2 may include a material different from that of the third layer L3. The second layer L2 may have a thickness greater than that of the first layer L1. In addition, the second layer L2 may have a thickness greater than that of the third layer L3. The second layer L2 may include a highly conductive material. In one or more embodiments, the second layer L2 may include aluminum (Al).

[0254] In one or more embodiments, the first layer L1 may include a material having an etching rate lower than that of the second layer L2. That is, the second layer L2 may be formed of a material having a high etching selectivity with respect to the first layer L1. In one or more embodiments, the first layer L1 may include titanium (Ti), and the second layer L2 may include aluminum (Al). In this case, the side surface L1_W of the first layer L1 may be defined outside the side surface L2_W of the second layer L2. That is, the light-emitting connection portion CEP of the connection line CN may have a shape in which the side surface L1_W of the first layer L1 protrudes outward from the side surface L2_W of the second layer L2. That is, the light-emitting connection portion CEP of the connection line CN may have a shape in which the side surface L2_W of the second layer L2 is recessed inward from the side surface L1_W of the first layer L1.

[0255] In addition, the third layer L3 may include a material having an etching rate lower than that of the second layer L2. That is, the second layer L2 may be formed of a material having a high etching selectivity relative to the third layer L3. In one or more embodiments, the third layer L3 may include titanium (Ti), and the second layer L2 may include aluminum (Al). In this case, the side surface L3_W of the third layer L3 may be defined outside the side surface L2_W of the second layer L2. That is, the light-emitting connection portion CEP of the connection line CN may have a shape in which the side surface L3_W of the third layer L3 protrudes outward from the side surface L2_W of the second layer L2. That is, the light-emitting connection portion CEP of the connection line CN may have an undercut shape or an overhang structure, and the tip portion TP of the light-emitting connection portion CEP may be defined by the portion of the third layer L3 that protrudes relative to the second layer L2.

[0256] The upper insulating layer UIL and the pixel defining layer PDL may expose at least a part of the tip portion TP and at least a part of the second side surface L2_W. Specifically, a first opening OP1 for exposing one side of the connection line CN may be defined in the upper insulating layer UIL, and a second opening OP2 overlapping the first opening OP1 may be defined in the pixel defining layer PDL. The planar area of the second opening OP2 may be larger than the planar area of the first opening OP1. However, the present disclosure is not limited thereto, and the planar area of the second opening OP2 may be smaller than or equal to the planar area of the first opening OP1 as long as at least a part of the tip portion TP and at least a part of the second side surface L2_W can be exposed.

[0257] An intermediate layer IML' may be provided on the pixel defining layer PDL. The intermediate layer IML' may also be provided on a partial area of the upper insulating layer UIL exposed through the second opening OP2 of the pixel defining layer PDL. In addition, the intermediate layer IML' may also be provided on a partial area of the connection line CN exposed through the first opening OP1 of the upper insulating layer UIL. As Figure 13A shown, the intermediate layer IML' may include one end IN1 provided along the upper surface of the fifth insulating layer 50 and an opposite end IN2 provided along the upper surface of the connection line CN and the upper surface of the tip portion TP. That is, when viewed in cross-section, the intermediate layer IML' may have a shape that is partially disconnected from the tip portion TP in the region where the light-emitting connection portion CEP is defined. However, when viewed from above the plane (e.g., in a plan view), the intermediate layer IML' may have an integral shape that is connected as a whole within the region defined by the separator SPR as a closed line (refer to Figure 15A ).

[0258] The cathode CE' can be disposed on the intermediate layer IML'. The cathode CE' can also be disposed on a partial area of the upper insulating layer UIL exposed through the second opening OP2 of the pixel defining layer PDL. In addition, the cathode CE' can also be disposed on a partial area of the connection line CN exposed through the first opening OP1 of the upper insulating layer UIL. As Figure 13A shown, the cathode CE' can include one end EN1 disposed along the upper surface of the fifth insulating layer 50 and an opposite end EN2 disposed along the upper surface of the connection line CN and the upper surface of the tip portion TP. That is, when viewed in cross-section, the cathode CE' can have a shape that is partially disconnected from the tip portion TP in the region defining the light-emitting connection portion CEP. However, when viewed from above the plane (e.g., in a plan view), the cathode CE' can have an integral shape that is connected as a whole within the region defined by the separator SPR as a closed curve (refer to Figure 15A ).

[0259] In one or more embodiments, one end EN1 of the cathode CE' can be disposed along the side surface L2_W of the second layer L2 and can be in contact with the side surface L2_W of the second layer L2. Specifically, due to the difference in the deposition angle between the cathode CE' and the intermediate layer IML', the cathode CE' can be formed to be in contact with the side surface L2_W of the second layer L2 exposed by the intermediate layer IML' through the tip portion TP. That is, the cathode CE' can be connected to the connection line CN without a separate patterning process for the intermediate layer IML', so that the light-emitting element ED' can be electrically connected to the pixel driver PXC through the connection line CN.

[0260] Although the opposite end IN2 of the intermediate layer IML' and the opposite end EN2 of the cathode CE' are shown as covering the side surface L3_W of the third layer L3 in this embodiment, this is illustrative, and at least a part of the side surface L3_W of the third layer L3 can be exposed by the opposite end IN2 of the intermediate layer IML' and / or the opposite end EN2 of the cathode CE'.

[0261] The display panel DP' according to this embodiment can include a separator SPR. The separator SPR can be disposed on the pixel defining layer PDL. In one or more embodiments, the cathode CE' and the intermediate layer IML' can be commonly formed by deposition through an opening mask for a plurality of pixels PX (refer to Figure 1 ). In this case, the cathode CE' and the intermediate layer IML' can be separated by the separator SPR. As described above, the separator SPR can have a closed line shape for each of the light-emitting portions, so that the cathode CE' and the intermediate layer IML' can have separate shapes for each light-emitting portion. That is, the cathode CE' and the intermediate layer IML' are separated for each adjacent pixel PX (refer toFigure 1 It may be electrically independent.

[0262] Hereinafter, the spacer SPR will be described in more detail with reference to Figure 12 and Figure 13B As shown in Figure 13B , the spacer SPR may have an inverted conical shape. That is, the angle formed by the side surface SPR_W of the spacer SPR with respect to the upper surface of the pixel defining layer PDL (hereinafter, referred to as the tilt angle) may be an obtuse angle. However, this is illustrative, and the tilt angle may be set variably as long as the spacer SPR can electrically disconnect the cathode CE' for each pixel PX (refer to Figure 1 ). In addition, the spacer SPR may have the same structure as the tip portion TP and is not limited to any one embodiment.

[0263] In one or more embodiments, the spacer SPR may include an insulating material. Specifically, the spacer SPR may include an organic insulating material. Optionally, the spacer SPR may include an inorganic insulating material. In another case, the spacer SPR may be composed of a multi-layer of organic insulating material and inorganic insulating material. In one or more embodiments, the spacer SPR may include a conductive material. That is, the type of material of the spacer SPR is not particularly limited as long as the cathode CE' can be electrically disconnected for each pixel PX (refer to Figure 1 ).

[0264] The dummy layer UP may be provided on the spacer SPR. The dummy layer UP may include a first dummy layer UP1 provided on the spacer SPR and a second dummy layer UP2 provided on the first dummy layer UP1. The first dummy layer UP1 may be formed by the same process as the intermediate layer IML' and may include the same material as the intermediate layer IML'. The second dummy layer UP2 may be formed by the same process as the cathode CE' and may include the same material as the cathode CE'. That is, the first dummy layer UP1 and the second dummy layer UP2 may be formed concurrently (e.g., simultaneously) in the processes of forming the intermediate layer IML' and the cathode CE'. In one or more embodiments, the display panel DP' may not include the dummy layer UP.

[0265] As Figure 13BAs shown, in one or more embodiments, the cathode CE' may include a first end EN1a, and the second dummy layer UP2 may include a second end EN2a. The first end EN1a may be separated (e.g., spaced apart) from the separator SPR and may be located on the pixel defining layer PDL, and the second end EN2a may be separated from the first end EN1a and may be located on the side surface SPR_W of the separator SPR. However, although in Figure 13B the first end EN1a is shown as being spaced apart from the side surface SPR_W of the separator SPR (e.g., spaced apart), the present disclosure is not limited thereto, and the first end EN1a may be in contact with the side surface SPR_W of the separator SPR as long as the first end EN1a is electrically disconnected from the second end EN2a. In addition, even if the first end EN1a and the second end EN2a are connected without being distinguished from each other, but when the portion formed along the side surface SPR_W of the separator SPR is thin such that the resistance is high, if the cathode CE' is electrically disconnected between adjacent pixels PX (refer to Figure 1 ), it can be considered that the cathode CE' is separated by the separator SPR.

[0266] According to the present disclosure, even without a separate patterning process for the cathode CE' or the intermediate layer IML', the cathode CE' and / or the intermediate layer IML' can be separated for each pixel PX (refer to Figure 1 by thinning the cathode CE' and / or the intermediate layer IML' or by preventing the cathode CE' and / or the intermediate layer IML' from being formed on the side surface SPR_W of the separator SPR. In addition, as long as the cathode CE' and / or the intermediate layer IML' can be electrically disconnected between adjacent pixels PX (refer to Figure 1 ), the shape of the separator SPR can be modified in various ways and is not limited to any one embodiment.

[0267] Figure 14 is a cross-sectional view of a display panel DP'-1 according to one or more embodiments of the present disclosure. For ease of description, a cross-sectional view of a region corresponding to Figure 14 is shown in Figure 12 . Hereinafter, components identical to those described above with reference to Figure 12 will be assigned the same reference numerals, and repeated descriptions will be omitted.

[0268] When compared with the display panel DP' shown in Figure 12 , Figure 14The display panel DP'-1 shown in [Figure] may further include a cover pattern CPP. The cover pattern CPP may be disposed on the upper insulating layer UIL. In addition, the cover pattern CPP may also be disposed on a partial area of the connection line CN exposed by the first opening OP1 of the upper insulating layer UIL. The cover pattern CPP may be disposed to overlap the connection line CN. Specifically, the cover pattern CPP may be disposed to overlap the light-emitting connection part CEP and / or the tip part TP.

[0269] In addition, when viewed in the cross-section shown in [Figure], the cover pattern CPP may have a shape that is partially disconnected from the tip part TP in the area defining the light-emitting connection part CEP. However, when viewed from above the plane (e.g., in a plan view), the cover pattern CPP may have an integral shape that is connected as a whole within the area defined by the separator SPR as a closed line (refer to [Figure]). In one or more embodiments, one end of the partially disconnected cover pattern CPP may contact the side surface L2_W of the second layer L2 of the connection line CN (refer to [Figure]), and the other end of the cover pattern CPP may be disposed on the third layer L3 of the connection line CN and may cover the tip part TP. Figure 14 In addition, when viewed in the cross-section shown in [Figure], the cover pattern CPP may have a shape that is partially disconnected from the tip part TP in the area defining the light-emitting connection part CEP. However, when viewed from above the plane (e.g., in a plan view), the cover pattern CPP may have an integral shape that is connected as a whole within the area defined by the separator SPR as a closed line (refer to [Figure]). In one or more embodiments, one end of the partially disconnected cover pattern CPP may contact the side surface L2_W of the second layer L2 of the connection line CN (refer to [Figure]), and the other end of the cover pattern CPP may be disposed on the third layer L3 of the connection line CN and may cover the tip part TP. Figure 15A In addition, when viewed in the cross-section shown in [Figure], the cover pattern CPP may have a shape that is partially disconnected from the tip part TP in the area defining the light-emitting connection part CEP. However, when viewed from above the plane (e.g., in a plan view), the cover pattern CPP may have an integral shape that is connected as a whole within the area defined by the separator SPR as a closed line (refer to [Figure]). In one or more embodiments, one end of the partially disconnected cover pattern CPP may contact the side surface L2_W of the second layer L2 of the connection line CN (refer to [Figure]), and the other end of the cover pattern CPP may be disposed on the third layer L3 of the connection line CN and may cover the tip part TP. Figure 13A In addition, when viewed in the cross-section shown in [Figure], the cover pattern CPP may have a shape that is partially disconnected from the tip part TP in the area defining the light-emitting connection part CEP. However, when viewed from above the plane (e.g., in a plan view), the cover pattern CPP may have an integral shape that is connected as a whole within the area defined by the separator SPR as a closed line (refer to [Figure]). In one or more embodiments, one end of the partially disconnected cover pattern CPP may contact the side surface L2_W of the second layer L2 of the connection line CN (refer to [Figure]), and the other end of the cover pattern CPP may be disposed on the third layer L3 of the connection line CN and may cover the tip part TP.

[0270] The cover pattern CPP may include a conductive material. Accordingly, the cathode CE' may be electrically connected to the connection line CN through the cover pattern CPP. That is, the cover pattern CPP may contact the side surface L2_W of the second layer L2 of the connection line CN (refer to [Figure]), and thus the cathode CE' may contact the cover pattern CPP and may be electrically connected to the connection line CN. The cover pattern CPP may be disposed outside the second layer L2 of the connection line CN, and the cathode CE' may be electrically connected to the second layer L2 only by connecting to the cover pattern CPP without connecting to the side surface L2_W of the second layer L2 (refer to [Figure]). Therefore, the connection between the connection line CN and the cathode CE' can be more easily performed. Figure 13A The cover pattern CPP may include a conductive material. Accordingly, the cathode CE' may be electrically connected to the connection line CN through the cover pattern CPP. That is, the cover pattern CPP may contact the side surface L2_W of the second layer L2 of the connection line CN (refer to [Figure]), and thus the cathode CE' may contact the cover pattern CPP and may be electrically connected to the connection line CN. The cover pattern CPP may be disposed outside the second layer L2 of the connection line CN, and the cathode CE' may be electrically connected to the second layer L2 only by connecting to the cover pattern CPP without connecting to the side surface L2_W of the second layer L2 (refer to [Figure]). Therefore, the connection between the connection line CN and the cathode CE' can be more easily performed. Figure 13A The cover pattern CPP may include a conductive material. Accordingly, the cathode CE' may be electrically connected to the connection line CN through the cover pattern CPP. That is, the cover pattern CPP may contact the side surface L2_W of the second layer L2 of the connection line CN (refer to [Figure]), and thus the cathode CE' may contact the cover pattern CPP and may be electrically connected to the connection line CN. The cover pattern CPP may be disposed outside the second layer L2 of the connection line CN, and the cathode CE' may be electrically connected to the second layer L2 only by connecting to the cover pattern CPP without connecting to the side surface L2_W of the second layer L2 (refer to [Figure]). Therefore, the connection between the connection line CN and the cathode CE' can be more easily performed.

[0271] In addition, the cover pattern CPP may include a material having a lower reactivity than the second layer L2 of the connection line CN. For example, the cover pattern CPP may include copper (Cu), silver (Ag), and / or a transparent conductive oxide. The side surface L2_W of the second layer L2 of the connection line CN (refer to [Figure]) may be protected by the cover pattern CPP having a lower reactivity than the second layer L2 of the connection line CN, and thus oxidation of the material included in the second layer L2 can be reduced or prevented. In addition, the phenomenon in which the silver (Ag) component included in the anode AE1' is reduced during the etching process for patterning the anode AE1' and remains as particles causing defects can be reduced or prevented. Figure 13A In addition, the cover pattern CPP may include a material having a lower reactivity than the second layer L2 of the connection line CN. For example, the cover pattern CPP may include copper (Cu), silver (Ag), and / or a transparent conductive oxide. The side surface L2_W of the second layer L2 of the connection line CN (refer to [Figure]) may be protected by the cover pattern CPP having a lower reactivity than the second layer L2 of the connection line CN, and thus oxidation of the material included in the second layer L2 can be reduced or prevented. In addition, the phenomenon in which the silver (Ag) component included in the anode AE1' is reduced during the etching process for patterning the anode AE1' and remains as particles causing defects can be reduced or prevented.

[0272] In one or more embodiments, the cover pattern CPP may be formed by the same process as that of the anode AE1' and may include the same material as the anode AE1'. However, this is illustrative, and the cover pattern CPP may be formed by a process different from that of the anode AE1' and may include a material different from that of the anode AE1'. The present disclosure is not limited to any one embodiment.

[0273] Figures 15A to 15C is an enlarged plan view of a partial area of a display panel according to one or more embodiments of the present disclosure. Figures 15A to 15C may correspond to an enlarged plan view of the display panels DP' and DP'-1 according to the embodiments described above with reference to Figures 12 to 14 The description of the embodiments. Figure 15A shows a region in which a total of four light-emitting units are arranged in two rows and two columns, Figure 15B shows Figure 15A an enlarged view of the partial area shown in Figure 15C In Figure 15A some of the components shown in Figures 15A to 15C are omitted or emphasized. Hereinafter, the present disclosure will be described with reference to

[0274] In Figure 15A light-emitting units UT11, UT12, UT21, and UT22 arranged in two rows and two columns are shown. The light-emitting portions in the first row Rk include the light-emitting portions of the light-emitting unit UT11 at the first column of the first row and the light-emitting unit UT12 at the second column of the first row, and the light-emitting portions in the second row Rk+1 include the light-emitting portions of the light-emitting unit UT21 at the first column of the second row and the light-emitting unit UT22 at the second column of the second row. In Figure 15B the light-emitting portions in the first row Rk are shown. Among the components of the display panel DP' (refer to Figure 12 ), the separator SPR, a plurality of light-emitting portions EP1, EP2, and EP3 provided in the regions divided by the separator SPR, connection lines CN1, CN2, and CN3, the anode AE', and the cathode CE' are shown in Figures 15A to 15C .

[0275] As described above, each of the light-emitting portions EP1, EP2, and EP3 may correspond to the light-emitting opening OP-PDL (refer to Figure 12 ). That is, each of the light-emitting portions EP1, EP2, and EP3 may be a region where light is emitted by the light-emitting element ED' (refer to Figure 12 ) and may correspond to a unit that constitutes an image displayed on the display panel DP' (refer to Figure 12 ). More specifically, each of the light-emitting portions EP1, EP2, and EP3 may correspond to the light-emitting opening OP-PDL (refer to Figure 12The defined region, specifically, the region defined by the lower surface of the light-emitting opening OP-PDL.

[0276] The light-emitting portions EP1, EP2, and EP3 may include a first light-emitting portion EP1, a second light-emitting portion EP2, and a third light-emitting portion EP3. The first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 may emit light of a first color, a second color, and a third color, respectively. The light of the first color, the light of the second color, and the light of the third color may be lights of different colors. For example, the first light-emitting portion EP1 may emit red light, the second light-emitting portion EP2 may emit green light, and the third light-emitting portion EP3 may emit blue light. However, the combination of colors is not limited thereto. In addition, at least two of the light-emitting portions EP1, EP2, and EP3 may emit light of the same color. For example, the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 may all emit blue light or white light.

[0277] Among the light-emitting portions EP1, EP2, and EP3, the third light-emitting portion EP3 that emits light of the third color may include two sub-light-emitting portions EP31 and EP32 that are separated from each other (e.g., spaced apart) in the second direction DR2. However, this is illustrative. Similar to the other light-emitting portions EP1 and EP2, the third light-emitting portion EP3 may be set as one pattern having an integral shape (e.g., may be integrally formed), and at least one of the other light-emitting portions EP1 and EP2 may include sub-light-emitting portions that are separated from each other (e.g., spaced apart). The present disclosure is not limited to any one embodiment.

[0278] The light-emitting portions in the first row Rk may include the light-emitting portions EP1, EP2, and EP3 that constitute the light-emitting unit UT11 at the first column of the first row and the light-emitting unit UT12 at the second column of the first row. The light-emitting portions in the second row Rk+1 may include the light-emitting portions EP1, EP2, and EP3 that constitute the light-emitting unit UT21 at the first column of the second row and the light-emitting unit UT22 at the second column of the second row. Some of the light-emitting portions EP1, EP2, and EP3 in the first row Rk and some of the light-emitting portions EP1, EP2, and EP3 in the second row Rk+1 may have a symmetric shape. For example, the first light-emitting portion EP1 and the second light-emitting portion EP2 of the light-emitting unit UT21 at the first column of the second row and the first light-emitting portion EP1 and the second light-emitting portion EP2 of the light-emitting unit UT11 at the first column of the first row may have line symmetry with respect to an axis parallel to the first direction DR1 and be arranged, and the third light-emitting portion EP3 of the light-emitting unit UT21 at the first column of the second row and the third light-emitting portion EP3 of the light-emitting unit UT11 at the first column of the first row may have line symmetry with respect to an axis parallel to the first direction DR1 and be arranged. However, this is illustrative, and the present disclosure is not limited thereto.

[0279] Hereinafter, the light-emitting unit UT11 at the first row and the first column will be described. In ​ order to facilitate the description, a plurality of cathodes CE'_1, CE'_2, and CE'_3, a plurality of pixel drivers PXC1, PXC2, and PXC3, and a plurality of connection lines CN1, CN2, and CN3 are shown. The cathodes CE'_1, CE'_2, and CE'_3 may be separated from each other by a separator SPR and may be electrically disconnected from each other. In the present embodiment, one light-emitting unit may include three light-emitting portions EP1, EP2, and EP3. Accordingly, the light-emitting unit may include three cathodes CE'_1, CE'_2, and CE'_3 (hereinafter referred to as the first cathode to the third cathode), three pixel drivers PXC1, PXC2, and PXC3, and three connection lines CN1, CN2, and CN3. However, this is illustrative, and the number and arrangement of the light-emitting units may be designed in various ways and are not limited to any one embodiment.

[0280] The first pixel driver PXC1, the second pixel driver PXC2, and the third pixel driver PXC3 are electrically connected to light-emitting elements ED' (refer to ​ ), respectively, which constitute the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3. The expression "connected" used herein includes not only physical direct contact but also electrical connection.

[0281] In addition, as shown in ​ , the region where the pixel drivers PXC1, PXC2, and PXC3 are defined on a plane may correspond to a unit in which transistors and capacitors of a pixel circuit PXC (refer to ​ ), which constitute light-emitting elements ED (refer to ​ ), for driving a pixel PX (refer to ​ ), are repeatedly arranged.

[0282] The first pixel driver PXC1, the second pixel driver PXC2, and the third pixel driver PXC3 may be sequentially arranged along a first direction DR1. The positions of the first pixel driver PXC1, the second pixel driver PXC2, and the third pixel driver PXC3 may be independently designed regardless of the positions and / or shapes of the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3.

[0283] For example, the first pixel driver PXC1, the second pixel driver PXC2, and the third pixel driver PXC3 may be disposed at positions different from the positions where the regions divided and defined by the partition SPR are provided (i.e., where the first cathode CE'_1, the second cathode CE'_2, and the third cathode CE'_3 are provided), and / or may be designed to have shapes and areas different from those of the first cathode CE'_1, the second cathode CE'_2, and the third cathode CE'_3. Optionally, the first pixel driver PXC1, the second pixel driver PXC2, and the third pixel driver PXC3 may be disposed to overlap with the positions where the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 are located, and may be designed to have a shape similar to the shape of the region divided and defined by the partition SPR (e.g., the first cathode CE'_1, the second cathode CE'_2, and the third cathode CE'_3).

[0284] In this embodiment, the first pixel driver PXC1, the second pixel driver PXC2, and the third pixel driver PXC3 are shown as rectangular shapes, the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 have areas smaller than those of the first pixel driver PXC1, the second pixel driver PXC2, and the third pixel driver PXC3, and are arranged in shapes different from those of the first pixel driver PXC1, the second pixel driver PXC2, and the third pixel driver PXC3, and the first cathode CE'_1, the second cathode CE'_2, and the third cathode CE'_3 are disposed at positions overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3, and are shown as irregular shapes.

[0285] Therefore, as ​ shown, the first pixel driver PXC1 may be disposed at a position overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2, and another adjacent light-emitting unit partially. The second pixel driver PXC2 may be disposed at a position overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2, and / or the third light-emitting portion EP3. The third pixel driver PXC3 may be disposed at a position overlapping with the third light-emitting portion EP3. However, this is illustrative, and the positions of the first pixel driver PXC1, the second pixel driver PXC2, and the third pixel driver PXC3 may be designed in various forms and arrangements independent of the light-emitting portions EP1, EP2, and EP3, and are not limited to any one embodiment.

[0286] A plurality of connection lines CN can be provided. The connection lines CN can be separated from each other (e.g., spaced apart). One connection line CN can electrically connect one of the pixel drivers PXC1, PXC2, and PXC3 and a light-emitting element corresponding to the pixel driver. Specifically, the connection line CN can correspond to the light-emitting element ED' (refer to ​ ), at which point it is connected to the pixel driver PXC (refer to ​ ), and the node (refer to ​ the fourth node N4 in

[0287] The connection line CN can include a first connection portion (or light-emitting connection portion CEP) and a second connection portion (or driving connection portion CDP). The light-emitting connection portion CEP can be provided on one side of the connection line CN, and the driving connection portion CDP can be provided on the opposite side of the connection line CN.

[0288] The driving connection portion CDP can be the portion of the connection line CN that is connected to the pixel driver PXC. In the present embodiment, the driving connection portion CDP can be connected to one electrode of the transistor that makes up the pixel driver PXC. Specifically, the driving connection portion CDP can be connected to ​ the drain D6 of the sixth transistor T6 shown in ​ . Therefore, the position of the driving connection portion CDP can correspond to the position of the transistor (refer to ​ the transistor TR in ​ the pixel driver that is physically connected to the connection line CN. The light-emitting connection portion CEP can be the portion of the connection line CN that is connected to the light-emitting element ED' (refer to ​ ). In the present embodiment, the light-emitting connection portion CEP can be connected to the cathode CE' (refer to

[0289] Each of the light-emitting units UT11, UT12, UT21, and UT22 can include a first connection line CN1, a second connection line CN2, and a third connection line CN3. The first connection line CN1 can connect the light-emitting element forming the first light-emitting portion EP1 and the first pixel driver PXC1, the second connection line CN2 can connect the light-emitting element forming the second light-emitting portion EP2 and the second pixel driver PXC2, and the third connection line CN3 can connect the light-emitting element forming the third light-emitting portion EP3 and the third pixel driver PXC3.

[0290] Specifically, the first connection line CN1, the second connection line CN2, and the third connection line CN3 can connect the first cathode CE'_1, the second cathode CE'_2, and the third cathode CE'_3 to the first pixel driver PXC1, the second pixel driver PXC2, and the third pixel driver PXC3, respectively. The first connection line CN1 can include a first driving connection portion CDP1 connected to the first pixel driver PXC1 and a first light-emitting connection portion CEP1 connected to the first cathode CE'_1. The second connection line CN2 can include a second driving connection portion CDP2 connected to the second pixel driver PXC2 and a second light-emitting connection portion CEP2 connected to the second cathode CE'_2. The third connection line CN3 can include a third driving connection portion CDP3 connected to the third pixel driver PXC3 and a third light-emitting connection portion CEP3 connected to the third cathode CE'_3.

[0291] The first driving connection portion CDP1, the second driving connection portion CDP2, and the third driving connection portion CDP3 can be aligned in the first direction DR1. As described above, the first driving connection portion CDP1, the second driving connection portion CDP2, and the third driving connection portion CDP3 can correspond to the positions of the connection transistors that make up the first pixel driver PXC1, the second pixel driver PXC2, and the third pixel driver PXC3, respectively. In one pixel, the connection transistor can be a transistor including a connection node connected to the pixel driver and the light-emitting element as one electrode and can correspond to, for example, ​ the sixth transistor T6. According to the present disclosure, the shape, position, and / or arrangement of the pixel drivers of all pixels can be simply constructed and designed regardless of the shape, size, and / or emission color of the light-emitting portion.

[0292] In the present embodiment, when viewed from above the plane (e.g., in a plan view), the first light-emitting connection portion CEP1, the second light-emitting connection portion CEP2, and the third light-emitting connection portion CEP3 can be disposed at positions not overlapping with the light-emitting portions EP1, EP2, and EP3. As will be described below, each of the light-emitting connection portions CEP1, CEP2, and CEP3 of the connection line CN can be a portion connected to the light-emitting element ED' (refer to ​ ), and a tip portion TP (refer to ​ ) is defined therein, and thus can be disposed at a position not overlapping with the light-emitting opening OP-PDL (refer to ​At the superposed positions. That is, the light-emitting connection portions CEP1, CEP2, and CEP3 can be disposed at positions separated (e.g., spaced apart) from the light-emitting portions EP1, EP2, and EP3 in the cathodes CE'_1, CE'_2, and CE'_3, and the cathodes CE'_1, CE'_2, and CE'_3 can include partial regions that protrude from the light-emitting portions EP1, EP2, and EP3 when viewed from above the plane (e.g., in a plan view) to connect to the connection lines CN1, CN2, and CN3 at the positions where the light-emitting connection portions CEP1, CEP2, and CEP3 are disposed.

[0293] For example, the first cathode CE'_1 can include a protrusion that protrudes from the first light-emitting portion EP1 at a position not superposed with the first light-emitting portion EP1 to connect to the first connection line CN1 at the position where the first light-emitting connection portion CEP1 is disposed, and the first light-emitting connection portion CEP1 can be disposed on the protrusion.

[0294] In addition, when viewed from above the plane (e.g., in a plan view), the first connection line CN1 and the first driving connection portion CDP1 where the first pixel driver PXC1 (specifically, the transistor TR (refer to ​ )) is connected can be defined at a position not superposed with the first light-emitting portion EP1. According to this embodiment, the first connection line CN1 can be disposed on the first light-emitting portion EP1, and the first cathode CE'_1 and the first pixel driver PXC1 that are separated (e.g., spaced apart) from each other can be easily connected.

[0295] In one or more embodiments, when viewed from above the plane (e.g., in a plan view), the third connection line CN3 and the third driving connection portion CDP3 where the third pixel driver PXC3 (specifically, the transistor TR (refer to ​ )) is connected can be defined at a position not superposed with the third light-emitting connection portion CEP3 and disposed at a position superposed with the third light-emitting portion EP3. According to this embodiment, the third cathode CE'_3 and the third pixel driver PXC3 can be connected through the third connection line CN3. Therefore, in the design of the third pixel driver PXC3, the restrictions according to the position or shape of the third light-emitting portion EP3 can be reduced, and thus the degree of freedom in design can be improved.

[0296] Refer back to ​, the light-emitting portions in the second row Rk+1 may include light-emitting portions that are line-symmetric and arranged with respect to an axis parallel to the first direction DR1 or the second direction DR2 with the light-emitting units UT11 and UT12 in the first row Rk. In this case, due to the shape and arrangement of the light-emitting units UT11 and UT12 in the first row Rk, the light-emitting units UT21 and UT22 in the second row Rk+1 may be substantially constituted by light-emitting portions having a form in which the light-emitting units UT11 and UT12 in the first row Rk are offset in the first direction DR1 and / or the second direction DR2. That is, the light-emitting unit UT21 at the first column of the second row may be constituted by a light-emitting portion having the same shape as the light-emitting unit UT12 at the second column of the first row, and the light-emitting unit UT22 at the second column of the second row may be constituted by a light-emitting portion having the same shape as the light-emitting unit UT11 at the first column of the first row.

[0297] Therefore, the connection lines CN-c in the light-emitting unit UT21 provided at the first column of the second row may have the same shape and arrangement as the connection lines CN1, CN2, and CN3 in the light-emitting unit UT12 provided at the second column of the first row. Similarly, the connection lines CN-d in the light-emitting unit UT22 provided at the second column of the second row may have the same shape and arrangement as the connection lines CN1, CN2, and CN3 in the light-emitting unit UT11 provided at the first column of the first row.

[0298] Referring to ​ , anodes AE' of light-emitting elements according to one or more embodiments of the present disclosure may be commonly provided for a plurality of light-emitting portions EP1, EP2, and EP3. That is, the anode AE' may be formed as an integral layer throughout the display area DA. Therefore, the layer of the anode AE' may be provided to overlap with the partition SPR. Alternatively, the anodes AE' of the light-emitting elements may be formed as separate (e.g., spaced apart) independent conductive patterns and may be electrically connected to each other through other conductive layers. Therefore, the pattern of the anode AE' may be provided not to overlap with the partition SPR.

[0299] As described above, a first driving voltage ELVDD (refer to ​ ) may be applied to the anode AE', and a common voltage may be provided to all light-emitting portions. The anode AE' may be connected to a first power line PL1 (refer to ​ ) that provides the first driving voltage ELVDD (refer to ​ ) in the non-display area NDA (refer to ​ ), or may be connected to the first power line PL1 (refer to ​ ) in the display area DA, and is not limited to any one embodiment. In the former case, the first power line PL1 (refer to ​) can be disposed in the non-display area NDA (refer to ​ ), and the anode AE' can have a shape extending into the non-display area NDA (refer to ​ ).

[0300] In ​ and ​ 's cross-sectional view, the anode AE' or AE1' is shown to overlap with the light-emitting opening OP-PDL and not to overlap with the separator SPR. However, as shown in ​ , the anode AE' of the light-emitting element can have an integral shape and can have a mesh or grid shape with openings defined in a partial area thereof. That is, as long as the same first driving voltage ELVDD (refer to ​ ) can be applied to the anode AE' of each of the plurality of light-emitting elements, the shape of the anode AE' can be set in various ways without being limited to any one embodiment.

[0301] In one or more embodiments, a plurality of openings OP-AE' can be defined in the anode AE' according to this embodiment. The opening OP-AE' can penetrate the layer of the anode AE'. The opening OP-AE' in the layer of the anode AE' can be disposed at a position not overlapping with the light-emitting portion EP and can be defined at a position overlapping with the separator SPR. The opening OP-AE' can facilitate the release of gas generated from the organic layer (e.g., the upper insulating layer UIL (refer to ​ )) disposed under the anode AE'. Therefore, the gas in the organic layer disposed under the light-emitting element can be sufficiently discharged in the process of manufacturing the display panel, and the gas discharged from the organic layer after manufacturing the display panel can be reduced. Therefore, the deterioration rate of the light-emitting element can be reduced.

[0302] According to this embodiment, a connection line can be included between the light-emitting element and the pixel driver. Therefore, even if only the shape of the cathode is changed without changing the arrangement and / or shape of the light-emitting portion, the light-emitting element can be easily connected to the pixel driver. Therefore, the degree of freedom in the design regarding the arrangement of the pixel driver can be improved, and the area or resolution of the light-emitting portion of the display panel can be easily increased.

[0303] ​ is an enlarged plan view of a partial area of a display panel according to one or more embodiments of the present disclosure. In ​ , the light-emitting units UT11, UT12, UT21, and UT22 arranged in two rows and two columns are shown. In ​ , the light-emitting portions arranged in one row are shown. In ​Among them, for ease of description, a plurality of cathodes CE'_1, CE'_2, and CE'_3, a plurality of pixel drivers PXC1, PXC2, and PXC3, a first connection electrode CNE1', a second connection electrode CNE2', a third connection electrode CNE3', and a separator SPR are shown. Among the components of the display panel, the separator SPR, a plurality of light-emitting portions EP1, EP2, and EP3 provided in the regions separated by the separator SPR, and a plurality of connection electrodes CNE1', CNE2', and CNE3' are shown in ​ and are described in ​ When describing, components that are the same as those described with reference to ​ will be assigned the same reference numerals, and descriptions thereof will be omitted. The following description will focus on the differences.

[0304] The light-emitting unit UT11 may include three cathodes CE'_1, CE'_2, and CE'_3 (hereinafter referred to as the first cathode to the third cathode), three pixel drivers PXC1, PXC2, and PXC3, and three connection electrodes CNE1', CNE2', and CNE3'. However, this is illustrative, and the number and arrangement of the light-emitting portions included in the light-emitting unit UT11 may be designed in various ways and are not limited to any one embodiment.

[0305] The light-emitting unit UT11 may include a first connection electrode CNE1', a second connection electrode CNE2', and a third connection electrode CNE3'. The first connection electrode CNE1' may electrically connect a first light-emitting element forming a first light-emitting portion EP1 and a first pixel driver PXC1, the second connection electrode CNE2' may electrically connect a second light-emitting element forming a second light-emitting portion EP2 and a second pixel driver PXC2, and the third connection electrode CNE3' may electrically connect a third light-emitting element forming a third light-emitting portion EP3 and a third pixel driver PXC3.

[0306] Specifically, the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' may electrically connect the first cathode CE'_1, the second cathode CE'_2, and the third cathode CE'_3 to the first pixel driver PXC1, the second pixel driver PXC2, and the third pixel driver PXC3 in a one-to-one correspondence.

[0307] Each of the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' may be disposed in a pixel defining layer PDL (refer to ​). The first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' may have an annular shape around the corresponding first light-emitting portion EP1, second light-emitting portion EP2, and third light-emitting portion EP3 (e.g., surrounding the first light-emitting portion EP1, second light-emitting portion EP2, and third light-emitting portion EP3). In one or more embodiments of the present disclosure, each of the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' is shown as having a closed-line annular shape, but is not limited thereto. For example, at least some of the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' may have an open-loop shape with a part disconnected.

[0308] Since the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' have an annular shape, the degree of freedom of the positions where the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' are connected to the first pixel driver PXC1, the second pixel driver PXC2, and the third pixel driver PXC3 can be improved. For example, the first connection electrode CNE1' may be connected to the first pixel driver PXC1 through the first light-emitting connection portion CEP1 (or the first connection portion), the second connection electrode CNE2' may be connected to the second pixel driver PXC2 through the second light-emitting connection portion CEP2 (or the second connection portion), and the third connection electrode CNE3' may be connected to the third pixel driver PXC3 through the connection line CN3. That is, the connection lines additionally connected to the first connection electrode CNE1' and the second connection electrode CNE2' can be omitted.

[0309] The connection line CN3 can electrically connect the third pixel driver PXC3 and the third light-emitting element constituting the third light-emitting portion EP3. The connection line CN3 may include a third light-emitting connection portion CEP3 (or the third connection portion) and a driving connection portion CDP3. The third light-emitting connection portion CEP3 may be provided on one side of the connection line CN3, and the driving connection portion CDP3 may be provided on the opposite side of the connection line CN3.

[0310] The driving connection portion CDP3 may be the portion of the connection line CN3 connected to the third pixel driver PXC3. In this embodiment, the driving connection portion CDP3 may be connected to one electrode of the transistor constituting the third pixel driver PXC3. The position of the driving connection portion CDP3 may correspond to the position of the transistor of the third pixel driver PXC3 physically connected to the connection line CN3. The third light-emitting connection portion CEP3 may be the portion of the connection line CN3 connected to the third light-emitting element. In this embodiment, the third light-emitting connection portion CEP3 may be connected to the third connection electrode CNE3'.

[0311] The first connection electrode CNE1' may include a first edge EG11 around at least a part of the first light-emitting portion EP1 (e.g., surrounding at least a part of the first light-emitting portion EP1) and a second edge EG12 around the first edge EG11 (e.g., surrounding the first edge EG11). The second connection electrode CNE2' may include a first edge EG21 around at least a part of the second light-emitting portion EP2 (e.g., surrounding at least a part of the second light-emitting portion EP2) and a second edge EG22 around the first edge EG21 (e.g., surrounding the first edge EG21). The third connection electrode CNE3' may include a first edge EG31 around at least a part of the third light-emitting portion EP3 (e.g., EP31, EP32) (e.g., surrounding at least a part of the third light-emitting portion EP3 (e.g., EP31, EP32)) and a second edge EG32 around the first edge EG31 (e.g., surrounding the first edge EG31).

[0312] The first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' may be arranged to be separated from each other (e.g., spaced apart). For example, the gaps GP1, GP2, and GP3 between the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' may overlap with the separator SPR. For example, the first edges EG11, EG21, and EG31 of the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' may not be covered by the separator SPR, and the second edges EG12, EG22, and EG32 of the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' may overlap with the separator SPR. Optionally, the second edges EG12, EG22, and EG32 of the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' may be covered by the separator SPR.

[0313] In one or more embodiments of the present disclosure, when viewed from above the plane (e.g., in a plan view), the first light-emitting connection portion CEP1, the second light-emitting connection portion CEP2, and the third light-emitting connection portion CEP3 may be provided at positions not overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3. For example, a light-emitting opening OP-PDL and a through hole OP-P separated from (e.g., spaced apart from) the light-emitting opening OP-PDL may be defined in the pixel defining layer PDL (refer to ​ )).

[0314] The through hole OP-P may include a first through hole OP-P1, a second through hole OP-P2, and a third through hole OP-P3. The first light-emitting connection part CEP1, the second light-emitting connection part CEP2, and the third light-emitting connection part CEP3 may be arranged to correspond to the first through hole OP-P1, the second through hole OP-P2, and the third through hole OP-P3, respectively. The light-emitting opening OP-PDL may include a first light-emitting opening OP-PDL1, a second light-emitting opening OP-PDL2, and a third light-emitting opening OP-PDL3. The first light-emitting part EP1, the second light-emitting part EP2, and the third light-emitting part EP3 may be defined to correspond to the first light-emitting opening OP-PDL1, the second light-emitting opening OP-PDL2, and the third light-emitting opening OP-PDL3, respectively. Accordingly, the first light-emitting connection part CEP1, the second light-emitting connection part CEP2, and the third light-emitting connection part CEP3 may be disposed at positions separated (e.g., spaced apart) from the first light-emitting part EP1, the second light-emitting part EP2, and the third light-emitting part EP3.

[0315] The first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' may be disposed on the pixel defining layer PDL (refer to ​ ). When viewed from above the plane (e.g., in a plan view), the first connection electrode CNE1' may be around the first light-emitting opening OP-PDL1 (e.g., may surround the first light-emitting opening OP-PDL1), the second connection electrode CNE2' may be around the second light-emitting opening OP-PDL2 (e.g., may surround the second light-emitting opening OP-PDL2), and the third connection electrode CNE3' may be around the third light-emitting opening OP-PDL3 (e.g., may surround the third light-emitting opening OP-PDL3).

[0316] According to one or more embodiments of the present disclosure, when viewed from above the plane (e.g., in a plan view), the connection line CN3 and the transistor TR of the third pixel driver PXC3 (refer to ​ ) at which the third driving connection part CDP3 is connected may be defined at a position not overlapping with the third light-emitting connection part CEP3 and disposed at a position overlapping with the third light-emitting part EP3. For example, the connection line CN3 may correspond to ​ the connection line CN-ad shown in, the driving connection part CDP3 may correspond to the part in contact with the intermediate connection electrode CN' shown in Figure 19 , and the third light-emitting connection part CEP3 may correspond to the part in contact with Figure 19The portion in contact with the connection electrode CNEa' shown in []. The third cathode CE'_3 and the third pixel driver PXC3 can be connected by a connection line CN3. Therefore, in the design of the third pixel driver PXC3, the restrictions according to the position and / or shape of the third light-emitting portion EP3 can be reduced, and thus the degree of freedom in design can be improved.

[0317] The first cathode CE'_1, the second cathode CE'_2, and the third cathode CE'_3 can be connected to the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3'. For example, the lower surfaces of the first cathode CE'_1, the second cathode CE'_2, and the third cathode CE'_3 can be connected to (or in contact with) the upper surfaces of the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3'. Therefore, the contact reliability (or connection stability) between the first cathode CE'_1, the second cathode CE'_2, and the third cathode CE'_3 and the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' can be further improved.

[0318] In addition, the connection regions where the first cathode CE'_1, the second cathode CE'_2, and the third cathode CE'_3 are connected to the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' can be around at least part of the first light-emitting opening OP-PDL1, the second light-emitting opening OP-PDL2, and the third light-emitting opening OP-PDL3 (for example, can surround at least part of the first light-emitting opening OP-PDL1, the second light-emitting opening OP-PDL2, and the third light-emitting opening OP-PDL3). The first cathode CE'_1, the second cathode CE'_2, and the third cathode CE'_3 and the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' can be connected in a region adjacent to the separator SPR, and the connection region can be defined as adjacent to the separator SPR. That is, the first cathode CE'_1, the second cathode CE'_2, and the third cathode CE'_3 and the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3' may not be connected at a specific point, and can be connected across a relatively wide region (for example, a region similar to the shape of the first connection electrode CNE1', the second connection electrode CNE2', and the third connection electrode CNE3'). That is, the area of the connection region can be increased, and thus the connection can be stably performed.

[0319] In Figure 16D [], a layer of the separator SPR, the light-emitting portions EP1, EP2, and EP3, and the anode AE' is shown. Refer toFigure 16D , the anode AE' of the light-emitting element ED' (refer to Figure 17 ) according to one or more embodiments of the present disclosure can be commonly provided for the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3. That is, the anode AE' can be formed as an integral layer throughout the display area DA. Therefore, the layer of the anode AE' can be provided to overlap with the separator SPR. Alternatively, the anode AE' of the light-emitting element ED' (refer to Figure 17 ) can be formed as independent conductive patterns separated (e.g., spaced apart) from each other and can be electrically connected to each other through other conductive layers. Therefore, the pattern of the anode AE' can be provided not to overlap with the separator SPR.

[0320] In one or more embodiments, a plurality of openings can be defined in the anode AE' according to the present embodiment. The openings can penetrate the layer of the anode AE'. The openings in the layer of the anode AE' can be provided at positions not overlapping with the light-emitting portions EP1, EP2, and EP3 and can be defined at positions overlapping with the separator SPR.

[0321] Figure 17 is a cross-sectional view of the display panel DP'-2 according to one or more embodiments of the present disclosure. Figure 18 is an enlarged cross-sectional view of a partial area of the display panel DP'-2 according to one or more embodiments of the present disclosure. Figure 17 shows a Figure 16A cross-sectional view of a portion corresponding to the line I-I'. Figure 18 shows Figure 17 an enlarged cross-sectional view of the area CC. In the description of Figure 17 and Figure 18 , components identical to those described with reference to Figures 12 to 16D will be assigned the same reference numerals and the description thereof will be omitted. The following description will focus on the differences.

[0322] Referring to Figure 17 and Figure 18 , the display panel DP'-2 of one or more embodiments can include a substrate layer BL, a circuit element layer DP-CL', an intermediate connection electrode CN', a connection electrode CNE', a display element layer DP-ED', a packaging layer ESL, and a sensing layer ISL. However, this is illustrative, and in one or more embodiments of the present disclosure, the display panel DP'-2 may not include the sensing layer ISL. The circuit element layer DP-CL' can include a plurality of insulating layers 10, 20, 30, 40, 50, and 60 provided on the substrate layer BL and a plurality of conductive patterns and semiconductor patterns provided between the insulating layers 10, 20, 30, 40, 50, and 60.

[0323] The intermediate connection electrode CN' may be disposed on the fifth insulating layer 50. The intermediate connection electrode CN' may electrically connect the pixel driver PXC and the light-emitting element ED'. That is, the intermediate connection electrode CN' may electrically connect the connection transistor TR and the light-emitting element ED'. The intermediate connection electrode CN' may be a connection node connecting the pixel driver PXC and the light-emitting element ED'. For example, the intermediate connection electrode CN' may correspond to Figure 3 the fourth node N4 shown in

[0324] The sixth insulating layer 60 may be disposed on the intermediate connection electrode CN'. The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and may cover at least a portion of the intermediate connection electrode CN'. The fifth insulating layer 50 and the sixth insulating layer 60 may be organic layers. For example, each of the fifth insulating layer 50 and the sixth insulating layer 60 may include a general polymer (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), a polymer derivative having a phenolic group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a parylene-based polymer, a polyvinyl alcohol-based polymer, and / or a blend thereof.

[0325] A via hole OP-60 for exposing at least a portion of the intermediate connection electrode CN' may be formed in the sixth insulating layer 60. The intermediate connection electrode CN' may be connected to the connection electrode CNE' through the portion exposed by the sixth insulating layer 60 and may be electrically connected to the light-emitting element ED'. That is, the intermediate connection electrode CN' together with the connection electrode CNE' may electrically connect the connection transistor TR and the light-emitting element ED'. In one or more embodiments, in the display panel DP'-2 according to one or more embodiments of the present disclosure, the sixth insulating layer 60 may be omitted, and / or a plurality of sixth insulating layers 60 may be provided. However, the present disclosure is not limited to any one embodiment. When the sixth insulating layer 60 is omitted, the intermediate connection electrode CN' may also be omitted.

[0326] The intermediate connection electrode CN' may include a first layer L1', a second layer L2', and a third layer L3' sequentially stacked in the third direction DR3. The second layer L2' may include a material different from that of the first layer L1'. In addition, the second layer L2' may include a material different from that of the third layer L3'. The second layer L2' may have a thickness greater than that of the first layer L1'. In addition, the second layer L2' may have a thickness greater than that of the third layer L3'. The second layer L2' may include a highly conductive material. In one or more embodiments, the second layer L2' may include aluminum (Al).

[0327] The connection electrode CNE' can be disposed on the pixel defining layer PDL. The connection electrode CNE' can electrically connect the pixel driver PXC and the light-emitting element ED'. That is, the pixel driver PXC can be electrically connected to the light-emitting element ED' through the intermediate connection electrode CN' and the connection electrode CNE'. The connection electrode CNE' can correspond to Figure 16A the first connection electrode CNE1' shown in Figure 16A . The second connection electrode CNE2' (refer to Figure 16A ) and the third connection electrode CNE3' (refer to

[0328] ) can have a structure similar to that of the connection electrode CNE'.

[0329] The connection electrode CNE' can include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO x ), and / or indium oxide (In 2 O 3 ). However, the material of the connection electrode CNE' is not limited to the foregoing examples.

[0330] The display element layer DP-ED' can be disposed on the circuit element layer DP-CL'. The display element layer DP-ED' can include a pixel defining layer PDL, a light-emitting element ED', and a separator SPR.

[0331] A through hole OP-P separated (e.g., spaced apart) from the light-emitting opening OP-PDL can be defined in the pixel defining layer PDL. A plurality of through holes OP-P can be provided. The plurality of through holes OP-P can be provided to correspond to the light-emitting elements ED' respectively. The size of the through hole OP-P defined in the pixel defining layer PDL can be larger than the size of the through hole OP-60 defined in the sixth insulating layer 60. The connection electrode CNE' can be disposed in the through hole OP-P and the through hole OP-60, and can be connected to the intermediate connection electrode CN'.

[0332] The light-emitting element ED' may include an anode AE', an intermediate layer IML', and a cathode CE'. The intermediate layer IML' may include an emission layer EML and a functional layer FNL'. The functional layer FNL' may include a first intermediate functional layer FNLa disposed between the anode AE' and the emission layer EML and a second intermediate functional layer FNLb disposed between the cathode CE' and the emission layer EML. In one or more embodiments of the present disclosure, one of the first intermediate functional layer FNLa and the second intermediate functional layer FNLb may be omitted. In the present embodiment, the emission layer EML is shown as being inserted into the functional layer FNL'. That is, the emission layer EML may be understood as being disposed between the first intermediate functional layer FNLa and the second intermediate functional layer FNLb.

[0333] The functional layer FNL' may control the movement of charges between the anode AE' and the cathode CE'. For example, the first intermediate functional layer FNLa may include a hole injection / transport material and / or an electron injection / transport material. The second intermediate functional layer FNLb may include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0334] The spacer SPR may be disposed on the pixel defining layer PDL. In addition, the spacer SPR may be disposed above a gap GP located between a connection electrode CNE' disposed on the pixel defining layer PDL and an adjacent connection electrode adjacent to the connection electrode CNE'.

[0335] In one or more embodiments, the cathode CE' and the intermediate layer IML' may be commonly formed by deposition through an opening mask for a plurality of pixels PX (refer to Figure 1 ). In this case, the cathode CE' and the intermediate layer IML' may be separated by the spacer SPR. As described above, the spacer SPR may have a closed line shape for each of the light-emitting portions, so that the cathode CE' and the intermediate layer IML' may have separate shapes for each light-emitting portion. That is, the cathode CE' and the intermediate layer IML' may be electrically independent for each adjacent pixel PX (refer to Figure 1 ). However, this is illustrative. The functional layer FNL' of the intermediate layer IML' may be formed through an opening mask, and the emission layer EML of the intermediate layer IML' may be formed through a fine metal mask. The present disclosure is not limited to any one embodiment.

[0336] Refer to Figure 17 and Figure 18, the separator SPR may have a double inverted conical shape. That is, the inclination angle formed by the first side surface SPR_W1 of the separator SPR with respect to the upper surface of the pixel defining layer PDL may be different from the inclination angle formed by the second side surface SPR_W2 of the separator SPR with respect to the upper surface of the pixel defining layer PDL. The inclination angle may be an obtuse angle. For example, referring to Figure 18 , the inclination angle formed by the first side surface SPR_W1 with respect to the upper surface of the pixel defining layer PDL may be smaller than the inclination angle formed by the second side surface SPR_W2 with respect to the upper surface of the pixel defining layer PDL. However, this is illustrative, and the inclination angle can be set in various ways as long as the separator SPR can electrically disconnect the cathode CE' for each pixel PX (refer to Figure 1 ). In addition, the separator SPR may have the same structure as the tip portion TP and is not limited to any one embodiment.

[0337] The dummy layer UP may be provided on the separator SPR. The dummy layer UP may include a first dummy layer UP1 provided on the separator SPR and a second dummy layer UP2 provided on the first dummy layer UP1. In one or more embodiments, the first dummy layer UP1 may include a first-first dummy layer UP1a and a first-second dummy layer UP1b. The first-first dummy layer UP1a may be formed by the same process as the first intermediate functional layer FNLa and may include the same material as the first intermediate functional layer FNLa. The first-second dummy layer UP1b may be formed by the same process as the second intermediate functional layer FNLb and may include the same material as the second intermediate functional layer FNLb.

[0338] The dummy layer UP may not be in contact with the connection electrode CNE' and the cathode CE'. The second dummy layer UP2 included in the dummy layer UP may not be in contact with the connection electrode CNE' and the cathode CE'. In one or more embodiments, the dummy layer UP may be formed not only on the upper surface of the separator SPR but also on a part of the side surface SPR_W. In one or more embodiments, the display panel DP'-2 may not include the dummy layer UP.

[0339] The cathode CE' may be in contact with the connection electrode CNE' through the contact area CA. The contact area CA may be provided adjacent to the separator SPR. In the contact area CA, the upper surface CNE-us of the connection electrode CNE' is in contact with the lower surface CE-bs of the cathode CE'. Since the separator SPR has an inverted conical shape and the contact area CA is provided adjacent to the separator SPR, at least a part of the contact area CA where the cathode CE' and the connection electrode CNE' are in contact may be provided under the side surface SPR_W of the separator SPR.

[0340] In one or more embodiments, at least a portion of the connection electrode CNE' may be disposed under the separator SPR. The separator SPR may be disposed over a gap GP between the connection electrode CNE' and an adjacent connection electrode adjacent to the connection electrode CNE', and a second edge EG2c of the connection electrode CNE' may be covered by the separator SPR.

[0341] A display panel DP'-2 according to one or more embodiments may include an intermediate region MA disposed between an emission region EA in which a light-emitting element ED' is disposed and a contact region CA. The intermediate region MA may be a region in which at least a portion of an intermediate layer IML' is disposed. In the intermediate region MA, a functional layer FNL' included in the intermediate layer IML' may be disposed between the connection electrode CNE' and the cathode CE'. That is, in the intermediate region MA, the connection electrode CNE' and the cathode CE' may be separated from each other (e.g., spaced apart) and the functional layer FNL' is located therebetween.

[0342] The intermediate region MA may be adjacent to the contact region CA. The functional layer FNL' disposed in the intermediate region MA may include the above-described first intermediate functional layer FNLa and second intermediate functional layer FNLb. The first intermediate functional layer FNLa may be disposed between the anode AE' and the emission layer EML in the emission region EA, and the second intermediate functional layer FNLb may be disposed between the cathode CE' and the emission layer EML in the emission region EA.

[0343] In a display panel DP'-2 according to one or more embodiments, the functional layer FNL' and the cathode CE' may be formed by different deposition processes. When compared with the deposition method for forming the functional layer FNL', a deposition method for depositing a deposition material at a low incident angle may be used to form the cathode CE'. For example, the functional layer FNL' may be formed using a thermal evaporation method, and the cathode CE' may be covered using a sputtering method. Accordingly, in the process of forming the functional layer FNL', the material for forming the functional layer FNL' may not enter below a side surface SPR_W of the separator SPR, and thus a portion of the connection electrode CNE' may be exposed. The cathode CE' may be formed closer to the separator SPR than the functional layer FNL', and may be in contact with an upper surface CNE-us of the connection electrode CNE', and the cathode CE' is exposed on the upper surface CNE-us of the connection electrode CNE'. That is, a contact region CA where the cathode CE' and the connection electrode CNE' are in contact with each other may be formed by a difference between the deposition methods in the processes of forming the functional layer FNL' and the cathode CE'.

[0344] In one or more embodiments, a connection area CNA where a connection electrode CNE' is connected to an intermediate connection electrode CN' may be provided between an emission area EA and a contact area CA. The connection area CNA may overlap with an intermediate area MA. At least a part of an intermediate layer IML' may be provided to overlap with the connection area CNA. In a display panel DP'-2 according to one or more embodiments, a functional layer FNL' included in the intermediate layer IML' may be provided to overlap with the connection area CNA.

[0345] According to one or more embodiments of the present disclosure, the connection electrode CNE' has a shape surrounding at least a part of the emission area EA where a light-emitting element ED' is provided. Accordingly, the degree of freedom in a position where the connection electrode CNE' and the light-emitting element ED' are connected and the degree of freedom in a position where the connection electrode CNE' and a pixel driver PXC are connected may be improved.

[0346] In addition, an upper surface CNE-us of the connection electrode CNE' may be in contact with a lower surface CE-bs of a cathode CE' of the light-emitting element ED' through a contact area CA defined to be adjacent to a separator SPR. Accordingly, the contact reliability between the connection electrode CNE' and the cathode CE' may be improved, and since a lower surface of the connection electrode CNE' and an upper surface of the intermediate connection electrode CN' are in contact with each other, the contact reliability may be improved. In a display panel DP'-2 according to one or more embodiments, the sizes of vias OP-P and OP-60 for connecting the connection electrode CNE' and the intermediate connection electrode CN' may be reduced or minimized by the above structure, and thus the area or resolution of a light-emitting part of the display panel DP'-2 may be easily increased.

[0347] A sensing layer ISL may sense an external input. In the present embodiment, the sensing layer ISL may be formed on a package layer ESL through a continuous process. In this case, the sensing layer ISL may be described as being directly provided on the package layer ESL. The expression "directly provided" used herein may mean that no other component is provided between the sensing layer ISL and the package layer ESL. That is, a separate bonding member may not be provided between the sensing layer ISL and the package layer ESL. However, this is illustrative, and in a display panel DP'-2 according to one or more embodiments of the present disclosure, the sensing layer ISL may be separately formed and then combined with the display panel DP'-2 through a bonding member, and is not limited to any one embodiment.

[0348] The sensing layer ISL may include a plurality of conductive layers and a plurality of insulating layers. The plurality of conductive layers may include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2, and the plurality of insulating layers may include a first sensing insulating layer 71, a second sensing insulating layer 72, and a third sensing insulating layer 73. However, this is illustrative, and the number of conductive layers and the number of insulating layers are not limited to any one embodiment.

[0349] Each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may have a single-layer structure or may have a multi-layer structure stacked in the third direction DR3. The first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may include an inorganic film. The inorganic film may include at least one of alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may include an organic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, silicone resin, polyimide resin, polyamide resin, and perylene resin.

[0350] The first sensing conductive layer MTL1 may be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A part of the second sensing conductive layer MTL2 may be connected to the first sensing conductive layer MTL1 through a contact hole CNT formed in the second sensing insulating layer 72. Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have a single-layer structure or may have a multi-layer structure stacked in the third direction DR3.

[0351] The sensing conductive layer having a single-layer structure may include a metal layer and / or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum, and / or its alloy. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and / or indium zinc tin oxide (IZTO). Optionally, the transparent conductive layer may include a conductive polymer such as PEDOT, metal nanowires, and / or graphene.

[0352] The sensing conductive layer having a multi-layer structure may include a metal layer. The metal layer may have a three-layer structure such as titanium (Ti) / aluminum (Al) / titanium (Ti), for example. Optionally, the sensing conductive layer having a multi-layer structure may include at least one metal layer and / or at least one transparent conductive layer.

[0353] In the sensing layer ISL, the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 can be configured to form sensors for sensing external inputs. The sensors can be driven by a capacitive method and can be driven by either a mutual capacitance method or a self-capacitance method. However, this is illustrative, and in addition to the capacitive method, the sensors can also be driven by a resistive method, an ultrasonic method, and / or an infrared method, without being limited to any one embodiment.

[0354] Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 can include a transparent conductive oxide and can have a metal grid shape formed of an opaque conductive material. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 can have various materials and various shapes, without being limited to any one embodiment, as long as the visibility of the image displayed by the display panel DP'-2 is not deteriorated.

[0355] Figure 19 is a cross-sectional view of a display panel DP'-3 according to one or more embodiments of the present disclosure. In the description Figure 19 when Figure 17 and Figure 18 components that are the same as those shown in

[0356] will be assigned the same reference numerals, and descriptions thereof will be omitted. Figure 19 Referring to

[0357] In one or more embodiments of the present disclosure, the connection line CN-ad can be disposed on the same layer as the anode AE' (e.g., at the same layer). For example, the connection line CN-ad can have the same material and the same layer structure as the anode AE'. In addition, the connection line CN-ad can be formed by the same process as the anode AE'. However, this is illustrative, and the present disclosure is not limited thereto. For example, the connection line CN-ad can include a material different from that of the anode AE' and can be formed by a process different from that of the anode AE'.

[0358] The pixel defining layer PDL can have a through hole OP-Pa defined therein. The through hole OP-Pa and the through hole OP-60 may not overlap with each other, but are not particularly limited thereto. For example, in one or more embodiments, the through hole OP-Pa and the through hole OP-60 may overlap with each other. The connection electrode CNEa' can be disposed in the through hole OP-Pa. The connection electrode CNEa' can be connected to the portion of the connection line CN-ad exposed through the through hole OP-Pa.

[0359] According to the present disclosure, a driving current change of a light-emitting element can be prevented. Further, in a compensation operation, an influence of a parasitic capacitance of a node connected to a cathode can be reduced or eliminated, and a pixel circuit having improved compensation stability can be provided.

[0360] According to the present disclosure, gradation can be improved, and an ability to express a changed color can be improved. According to the present disclosure, an amount of noise caused by a voltage drop and a ripple in a power line can be reduced. Accordingly, display quality of a display device can be improved.

[0361] According to the present disclosure, a display device having reduced power consumption can be provided.

[0362] Although the present disclosure has been described with reference to embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the claims and their equivalents.

Claims

1. A display device, comprising: Display panel, including pixels, Wherein, the pixels include: a light emitting element including a cathode and an anode connected to the first power line; a first transistor connected between the cathode and a second power line and configured to operate based on a potential of a first node; a second transistor connected between the first node and the data line and configured to receive a first scan signal; a third transistor connected between the first node and a reference voltage line and configured to receive a second scan signal; and The fourth transistor is connected between the first transistor and the first power line.

2. The display device according to claim 1, wherein: The second scan signal has an active level during a first initialization period, and the first scan signal has an inactive level during the first initialization period, and The second scan signal has an active level during a compensation period, and the first scan signal has an inactive level during the compensation period.

3. The display device according to claim 2, wherein: The fourth transistor is configured to receive a third scan signal, and The third scan signal has an inactive level during the first initialization period, and has an active level during the compensation period.

4. The display device according to claim 2, wherein: The fourth transistor is configured to receive the second scan signal.

5. The display device according to claim 1, wherein: The first transistor includes a first electrode connected to the cathode, a second electrode connected to the second power line, and a gate connected to the first node, and The fourth transistor includes a first electrode connected to the first power line, a second electrode connected to the first electrode of the first transistor, and a gate configured to receive a third scan signal.

6. The display device according to claim 5, wherein: The pixel also includes: a first initialization transistor connected between the second electrode of the first transistor and a first initialization voltage line and configured to receive a fourth scan signal; and The first capacitor is connected between a second node and the first node, and the second node is connected to the first transistor and the first initialization transistor.

7. The display device according to claim 6, wherein: The fourth scan signal is activated during a first initialization period and is deactivated during a data writing period during which the first scan signal is activated, and The first initialization period is located before the data writing period.

8. The display device according to claim 7, wherein: The fourth scan signal is also activated during a second initialization period after the data writing period.

9. The display device according to claim 8, wherein: The second transistor, the third transistor, and the fourth transistor are turned off during the second initialization period.

10. The display device according to claim 6, wherein: The pixel includes a plurality of pixels, and the plurality of pixels include a first light emitting element configured to emit light of a first color and a second light emitting element configured to emit light of a second color different from the first color, and Wherein, the first initialization voltage line includes a first-first initialization voltage line and a first-second initialization voltage line, the first-first initialization voltage line is connected to the first light-emitting element and is constructed to receive a first-first initialization voltage, and the first-second initialization voltage line is connected to the second light-emitting element and is constructed to receive a first-second initialization voltage different from the first-first initialization voltage.

11. The display device according to claim 6, wherein: The pixel further includes a second initialization transistor connected between the cathode of the light emitting element and a second initialization voltage line, and The first initialization voltage line and the second initialization voltage line are configured to receive different initialization voltages.

12. The display device according to claim 11, wherein: The fourth transistor is configured to receive the third scanning signal, The second initialization transistor is configured to receive the fourth scanning signal, and wherein a period during which the third scan signal is activated and a period during which the fourth scan signal is activated do not overlap with each other.

13. The display device according to claim 11, wherein: The display panel is configured to display an image during a plurality of frames, and at least one frame among the plurality of frames includes a writing frame and a holding frame, wherein the first scanning signal, the second scanning signal and the third scanning signal have an activation level in the write frame and remain in an inactive state during the hold frame, and The fourth scanning signal has an activation level in the writing frame and the holding frame.

14. The display device according to claim 11, wherein: The pixel includes a plurality of pixels, and the plurality of pixels include a first light emitting element configured to emit light of a first color and a second light emitting element configured to emit light of a second color different from the first color, and Wherein, the second initialization voltage line includes a second-first initialization voltage line and a second-second initialization voltage line, the second-first initialization voltage line is connected to the first light-emitting element and is constructed to receive a second-first initialization voltage, and the second-second initialization voltage line is connected to the second light-emitting element and is constructed to receive a second-second initialization voltage different from the second-first initialization voltage.

15. The display device according to claim 11, wherein: The second initialization transistor is configured to receive a fifth scan signal, wherein the fourth scan signal is activated during a first initialization period, and the fifth scan signal is activated during the first initialization period and the second initialization period, wherein the fourth scan signal and the fifth scan signal are deactivated during a data writing period during which the first scan signal is activated, and The first initialization period is located before the data writing period, and the second initialization period is located after the data writing period.

16. The display device according to claim 15, wherein: The fourth scan signal is also activated during the second initialization period.

17. The display device according to claim 15, wherein: The display panel is configured to display an image during a plurality of frames, and at least one frame among the plurality of frames includes a writing frame and a holding frame, wherein the fourth scanning signal has an activation level in the write frame and remains in an inactive state during the hold frame, and The fifth scanning signal has an activation level in the writing frame and the holding frame.

18. The display device according to claim 5, wherein: The pixel also includes: a first emission control transistor connected between the first electrode and the cathode of the first transistor and configured to receive an emission control signal; and The second emission control transistor is connected between the second electrode of the first transistor and the second power line and is configured to receive the emission control signal.

19. The display device according to claim 5, wherein: The pixel further includes a second capacitor connected between the second electrode of the first transistor and one of the first power line and the second power line, and The first transistor further includes a back gate connected to the second electrode of the first transistor.

20. The display device according to claim 1, wherein: Each of the first transistor, the second transistor, the third transistor, and the fourth transistor is an N-type transistor.

21. The display device according to claim 1, wherein: A first driving voltage received by the first power line is higher than a second driving voltage received by the second power line, and The reference voltage received by the reference voltage line is between the first driving voltage and the second driving voltage.

22. The display device according to claim 1, wherein: The light emitting element further comprises: an electron control layer on the cathode; an emission layer on the electron control layer; and a hole control layer, on the emission layer, Wherein, the anode is on the hole control layer.

23. The display device according to claim 1, wherein: The second power lines have a structure of Ti / Al / Ti.

24. The display device according to claim 1, wherein: The anode comprises a MgAg alloy, and Wherein, the cathode has a structure of ITO / Ag / ITO.

25. The display device according to claim 1, wherein: The second power line and the data line are at the same layer and include the same material.

26. The display device according to claim 1, wherein: The second power line is at the same layer as the first power line and includes the same material.

27. The display device according to claim 1, wherein: The anode is directly connected to the first power line.

28. The display device according to claim 1, further comprising: The connecting conductive pattern is configured to connect the anode and the first power line.

29. The display device according to claim 1, wherein: The display panel includes a display area in which the pixels are located and a non-display area around at least a portion of the display area, and The pixel includes a plurality of pixels, the anode includes a plurality of anodes, and the plurality of anodes are respectively positioned in corresponding pixels among the plurality of pixels and connected to the first power line in the display area.

30. The display device according to claim 1, wherein: The display panel includes a display area in which the pixels are located and a non-display area around at least a portion of the display area, and The pixel includes a plurality of pixels, and the anode is commonly provided in the plurality of pixels and connected to the first power line in the non-display area.

31. The display device according to claim 1, wherein: The light emitting element further comprises an intermediate layer, the intermediate layer at least comprising an emission layer, the intermediate layer being on the anode, and Wherein, the cathode is on the intermediate layer.

32. The display device according to claim 31, wherein: The display panel further includes a spacer having an obtuse tilt angle, The pixel includes a plurality of pixels, and the plurality of pixels include a first light-emitting element and a second light-emitting element, the first light-emitting element is configured to emit light of a first color, and the second light-emitting element is configured to emit light of a second color different from the first color, and The separator separates the cathode of the first light-emitting element and the cathode of the second light-emitting element from each other.

33. The display device according to claim 31, wherein: The display panel further includes a connection line configured to electrically connect the first transistor and the cathode.

34. The display device according to claim 33, wherein: The connecting line includes a first layer, a second layer on the first layer, and a third layer on the second layer, and The side surface of the third layer protrudes outward from the side surface of the second layer, and the cathode contacts the side surface of the second layer.

35. The display device according to claim 31, wherein: The display panel further includes: a pixel defining layer having an opening defined therein, the opening exposing at least a portion of the anode; a connecting electrode on the pixel defining layer and electrically connected to the first transistor and the cathode; and a spacer, on the pixel defining layer, Wherein, in a contact region adjacent to the separator, a lower surface of the cathode contacts an upper surface of the connecting electrode.

36. The display device according to claim 35, wherein: The connection electrode has a ring shape surrounding the opening.

37. The display device according to claim 35, wherein: The spacer includes a first side surface and a second side surface, the first side surface and the second side surface having different inclination angles with respect to an upper surface of the pixel defining layer.

38. The display device according to claim 35, wherein: The pixel includes a plurality of pixels, and the connection electrode includes a plurality of connection electrodes, wherein each of the plurality of connection electrodes electrically connects the first transistor and the cathode in a corresponding pixel among the plurality of pixels, and Wherein, gaps between adjacent connection electrodes among the plurality of connection electrodes overlap with the separator.

39. A display device, comprising: Display panel, including pixels, Wherein, the pixels include: a light emitting element including a cathode and an anode connected to the first power line; a driving transistor including a first electrode connected to the cathode, a second electrode connected to the second power line, and a gate connected to the first node; A switch transistor connected between the first node and the data line; an emission control transistor connected between the first electrode and the cathode of the driving transistor; a compensation transistor connected between the first electrode of the driving transistor and the first power line; and an initialization transistor connected between the cathode and an initialization voltage line, The compensation transistor and the initialization transistor are configured to receive different scan signals.

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