Pixel circuit, display panel and display device

Abstract

The invention provides a pixel circuit, a display panel and display equipment, which can be applied to the technical field of display. The pixel circuit comprises a plurality of circuit units, each circuit unit comprises a first control sub-circuit, a second control sub-circuit and a plurality of driving sub-circuits, the first control sub-circuit and the second control sub-circuit are arranged in a non-display area of the display panel, the driving sub-circuits are arranged in a display area of the display panel, the first control sub-circuit is electrically connected with the driving sub-circuits through first nodes, and the second control sub-circuit is electrically connected with the driving sub-circuits through second nodes. The second control sub-circuit is electrically connected with the plurality of driving sub-circuits through a second node; wherein the first control sub-circuit is configured to provide a gate control signal for a first node, the second control sub-circuit is configured to provide a first power supply voltage for a second node, and the driving sub-circuit is configured to drive the light-emitting element to emit light based on the first power supply voltage and a data signal from a data end under the control of the gate control signal.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and more particularly, to a pixel circuit, a display panel, and a display device. Background Art

[0002] With the continuous progress of display technologies and the diversified expansion of application scenarios, the market has an urgent need for display technologies with high resolution, high refresh rate, and low latency. From electronic devices such as smartphones, tablets to in-vehicle center control screens, head-mounted display devices, etc., end-users have put forward higher requirements for the pixel density and resolution of display panels, driving the continuous development of display technologies towards high-precision and high-refinement. Summary of the Invention

[0003] The present disclosure provides a pixel circuit, a display panel, and a display device.

[0004] One aspect of the present disclosure provides a pixel circuit, including: a plurality of circuit units, each circuit unit including a first control sub-circuit and a second control sub-circuit disposed in a non-display area of the display panel, and a plurality of driving sub-circuits disposed in a display area of the display panel. The first control sub-circuit is electrically connected to the plurality of driving sub-circuits via a first node respectively, and the second control sub-circuit is electrically connected to the plurality of driving sub-circuits via a second node respectively; wherein, the first control sub-circuit is configured to provide a gating signal to the first node, the second control sub-circuit is configured to provide a first power supply voltage to the second node, and the driving sub-circuit is configured to drive a light-emitting element to emit light based on the first power supply voltage and a data signal from a data terminal under the control of the gating signal.

[0005] Another aspect of the present disclosure provides a display panel, including the pixel circuit as described above.

[0006] Another aspect of the present disclosure provides a display device, including the display panel as described above. Brief Description of the Drawings

[0007] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:

[0008] Figure 1 Shows a schematic structural diagram of an exemplary pixel circuit;

[0009] Figure 2 Schematically shows a schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

[0010] Figure 3A Schematically shows a schematic diagram of a pixel circuit according to a specific embodiment of the present disclosure;

[0011] Figure 3BSchematically shows a schematic diagram of a driving sub - circuit according to a specific embodiment of the present disclosure;

[0012] Figure 4A Schematically shows a schematic diagram of a pixel circuit according to another specific embodiment of the present disclosure;

[0013] Figure 4B Schematically shows a schematic diagram of a driving sub - circuit according to another specific embodiment of the present disclosure;

[0014] Figure 5A Schematically shows a schematic diagram of a pixel circuit according to yet another specific embodiment of the present disclosure;

[0015] Figure 5B Schematically shows a schematic diagram of a first control sub - circuit according to a specific embodiment of the present disclosure;

[0016] Figure 6A Schematically shows a schematic diagram of a pixel circuit according to yet another specific embodiment of the present disclosure;

[0017] Figure 6B Schematically shows a schematic diagram of a second control sub - circuit according to a specific embodiment of the present disclosure;

[0018] Figure 7A Schematically shows a schematic diagram of a pixel circuit according to an embodiment of the present disclosure;

[0019] Figure 7B Schematically shows a timing diagram of the operation of a pixel circuit according to an embodiment of the present disclosure;

[0020] Figure 7C Schematically shows a schematic diagram of a pixel circuit in a reset stage according to an embodiment of the present disclosure;

[0021] Figure 7D Schematically shows a schematic diagram of a pixel circuit in a voltage compensation stage according to an embodiment of the present disclosure;

[0022] Figure 7E Schematically shows a schematic diagram of a pixel circuit in a data writing stage according to an embodiment of the present disclosure;

[0023] Figure 7F Schematically shows a schematic diagram of a pixel circuit in a light - emitting stage according to an embodiment of the present disclosure;

[0024] Figure 8 Schematically shows a schematic diagram of a display panel according to an embodiment of the present disclosure; and

[0025] Figure 9 Schematically shows a schematic diagram of a display device according to an embodiment of the present disclosure. Detailed implementation manners

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only a part rather than all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts fall within the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are denoted by the same or similar reference numerals. In the following description, some specific embodiments are for illustrative purposes only and should not be construed as any limitation to the present disclosure, but only as examples of the embodiments of the present disclosure. When it may cause confusion in the understanding of the present disclosure, conventional structures or configurations will be omitted. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual sizes and proportions, but only illustrate the content of the embodiments of the present disclosure.

[0027] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the ordinary meanings understood by those skilled in the art. The "first", "second", and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components.

[0028] In addition, in the description of the embodiments of the present disclosure, the term "electrically connected" may refer to the direct connection of two components or the connection of two components via one or more other components. In addition, these two components may be connected or coupled in a wired or wireless manner.

[0029] In the embodiments of the present disclosure, the source and drain of the switching transistor used are symmetric, so the source and drain can be interchanged. In the embodiments of the present disclosure, according to its function, one of the source and drain can be referred to as the first pole, and the other of the source and drain can be referred to as the second pole.

[0030] It should be noted that in the description of the embodiments of the present disclosure, the symbol VDD can represent both the first power supply and the first power supply voltage provided by the first power supply, and the symbol VSS can represent both the second power supply and the second power supply voltage provided by the second power supply. Similarly, the symbol CON1 can represent both the first control terminal and the first control signal provided by the first control terminal; the symbol CON2 can represent both the second control terminal and the second control signal provided by the second control terminal; the symbol CON3 can represent both the third control terminal and the third control signal provided by the third control terminal; the symbol Vdata can represent both the data terminal and the data signal provided by the data terminal, and so on. The same applies to the following embodiments and will not be repeated.

[0031] In recent years, with the increasing demand in the virtual reality (VR) display market and the expansion of application fields, there has been an urgent need for high-resolution, high-refresh-rate, and low-latency display technologies.

[0032] Among them, in order to achieve a high pixel density within a very small field of view of the VR headset to eliminate the Screen Door Effect, it is required to reduce the area of a single pixel. At the same time, due to the similar tail effect that occurs when the VR product moves at a relatively high speed or rapidly changes the viewing angle, two images are simultaneously reflected in the brain, resulting in a blurring phenomenon that affects the viewing experience. To overcome the blurring phenomenon, in related technologies, methods such as shortening the single-frame time, increasing the refresh rate, and reducing the duty cycle of light emission are adopted to reduce the blurring. However, increasing the refresh rate leads to an increase in power consumption and requires more complex timing control.

[0033] In related technologies, an optional implementation is to use a 7T1C pixel circuit as the internal compensation pixel circuit. Taking this internal compensation pixel circuit as an example, the solutions of related technologies will be described below.

[0034] Figure 1 A schematic diagram of the structure of an exemplary pixel circuit is shown.

[0035] As Figure 1 shown, the pixel circuit 100 can be a 7T1C pixel circuit. In the pixel circuit 100, transistors M1 to M2 and transistors M4 to M7 can be switching transistors, transistor M3 is a driving transistor, transistors M3 to M7 are P-type transistors, and transistors M1 and M2 are N-type transistors.

[0036] During the T1 stage when the pixel circuit 100 operates, the enable signal EM is at a high level to control transistors M5 and M6 to be turned off; the reset signal RST1 is at a high level to control transistor M1 to be turned on, so as to pull down the potential of node Q1 to the initialization signal Vinit1, thereby enabling the capacitor Cst to be reset using the initialization signal Vinit.

[0037] In the T2 stage when the pixel circuit 100 is operating, the reset signal RST1 is at a low level and the control transistor M1 is turned off; the driving signal NGate is at a high level and the control transistor M2 is turned on, the driving signal PGate is at a low level and the control transistor M4 is turned on, and the data signal Vdata charges the capacitor Cst through the transistor M4, the driving transistor M3, and the transistor M2. When Vgs of the driving transistor M3 = V(Q1) - V(Q2) = V(Q1) - Vdata = Vth, the driving transistor M3 is turned off, and at this time the voltage maintained by the capacitor Cst is V(Q1) = Vdata + Vth. At the same time, the driving signal PGate is at a low level and the control transistor M7 is turned on to reset the anode of the light-emitting element EL using the initialization signal Vinit.

[0038] In the T3 stage when the pixel circuit 100 is operating, the driving signal NGate is at a low level and the control transistor M2 is turned off, the driving signal PGate is at a high level and the control transistors M4 and M7 are turned off, the enable signal EM is at a low level and the control transistors M5 and M6 are turned on, and Vgs of the driving transistor M3 = V(Q1) - V(Q2) = Vdata + Vth - ELVDD, so the light-emitting element EL can emit light according to the potential of the data signal Vdata.

[0039] In the pixel circuit of this example, if the driving signal NGate is at a high level, the transistor M2 is turned on, and the data signal Vdata can be written into the pixel circuit 100, thereby updating the brightness of the light-emitting element EL of the pixel circuit 100. Correspondingly, the pixel row where the pixel circuit 100 is located is refreshed in the current frame. If the driving signal NGate is at a low level and the transistor M2 is always turned off, the data signal Vdata will not be written into the pixel circuit 100, the brightness of the light-emitting element EL will not change, and the brightness of the pixel row where the pixel circuit 100 is located remains unchanged in the current frame.

[0040] Therefore, by controlling the potential of the driving signal NGate, it is possible to achieve whether the pixel brightness is refreshed, thereby achieving local refreshing of the display screen.

[0041] However, this 7T1C pixel circuit includes seven TFT transistors, occupies a large area, and parasitic capacitance is easily introduced in high-density layout, resulting in signal delay, which limits the refresh rate of the pixel circuit. In addition, in the compensation stage of this circuit, it depends on the on-resistance of the transistor M2. If the threshold voltage of the transistor M2 drifts, the stored voltage of the capacitor Cst will deviate, resulting in an error in the driving current and uneven brightness of the light-emitting element EL.

[0042] In the related art, another alternative implementation is to adopt a 4T2C pixel circuit. Compared with the 7T1C pixel circuit, the transistor structure is simplified. However, the 4T2C pixel circuit relies on the voltage coupling of two capacitors to achieve voltage compensation, and a diode connection needs to be formed through a TFT transistor during the compensation stage. If the on-resistance of the switching transistor is unstable, the compensated voltage stored in the capacitor will deviate, resulting in a drift phenomenon of the gate voltage of the driving transistor.

[0043] In the related art, yet another alternative implementation is to adopt a 3T1C pixel circuit as an external compensation pixel circuit. However, the 3T1C pixel circuit itself does not have the ability of internal voltage compensation. It is necessary to regularly detect the OLED brightness through an external driving IC or an optical sensor, and then reversely adjust the data voltage to compensate for the threshold voltage drift of the TFT. However, the luminous efficiency of the OLED decreases with the use time, and the 3T1C pixel circuit cannot autonomously adjust the current to offset this effect, resulting in uneven brightness of the light-emitting elements.

[0044] In view of this, embodiments of the present disclosure provide a pixel circuit, which may include: a plurality of circuit units, each circuit unit including a first control sub-circuit and a second control sub-circuit disposed in a non-display area of the display panel, and a plurality of driving sub-circuits disposed in a display area of the display panel. The first control sub-circuit is electrically connected to the plurality of driving sub-circuits through a first node respectively, and the second control sub-circuit is electrically connected to the plurality of driving sub-circuits through a second node respectively; wherein, the first control sub-circuit is configured to provide a gating signal to the first node, the second control sub-circuit is configured to provide a first power supply voltage to the second node, and the driving sub-circuit is configured to drive a light-emitting element to emit light based on the first power supply voltage and a data signal from a data terminal under the control of the gating signal.

[0045] Figure 2 A schematic diagram of a pixel circuit according to an embodiment of the present disclosure is schematically shown.

[0046] As Figure 2 shown, the pixel circuit 200 may include a plurality of circuit units 10, and each circuit unit 10 includes a first control sub-circuit 101, a second control sub-circuit 102, and a plurality of driving sub-circuits 103. Among them, the first control sub-circuit 101 and the second control sub-circuit 102 may be disposed in a non-display area of the display panel, and the driving sub-circuit may be disposed in a display area of the display panel.

[0047] The first control sub-circuit 101 is electrically connected to the plurality of driving sub-circuits 103 through a first node N1 respectively, so that the first control sub-circuit 101 can provide a gating signal to the first node N1. Among them, the gating signal may include, for example, a scanning signal, a reset signal, etc.

[0048] The second control sub - circuit 102 is electrically connected to a plurality of driving sub - circuits 103 via a second node N2, such that the second control sub - circuit 102 can provide a first power supply voltage VDD to the second node N2.

[0049] Figure 3A FIG. schematically shows a schematic diagram of a pixel circuit according to a specific embodiment of the present disclosure.

[0050] As Figure 3A shown, the circuit unit 10 includes a first control sub - circuit 101, a second control sub - circuit 102, and a driving sub - circuit 103. Among them, the driving sub - circuit 103 can be electrically connected to a data terminal Vdata. Under the control of a gating signal GATE from the first control sub - circuit 101, the driving sub - circuit 103 can generate a driving current based on a first power supply voltage VDD from the first control sub - circuit 102 and a data signal Vdata from the data terminal Vdata, and provide the driving current to the light - emitting element to drive the light - emitting element to emit light.

[0051] At least a driving transistor can be configured in the driving sub - circuit 103. Under the control of the gating signal from the first control sub - circuit 101, the driving sub - circuit 103 can form a driving current between the source and drain of the driving transistor based on the first power supply voltage VDD and the data signal Vdata, and provide the driving current to the light - emitting element.

[0052] The light - emitting element can be any current - driven light - emitting device, such as an OLED (Organic Light - Emitting Diode), an AMOLED (Active - matrix organic light - emitting diode), etc.

[0053] Based on this, in the embodiments of the present disclosure, the first control sub - circuit and the second control sub - circuit are arranged in the non - display area of the display panel, and the first control sub - circuit and the second control sub - circuit are used to control a plurality of driving sub - circuits arranged in the display area, reducing the occupied area of the control circuit in the display area, further improving the space utilization rate of the display area, enabling the pixels to be arranged more closely, thereby reducing the pitch between individual pixels and achieving a higher pixel density. In addition, in this pixel circuit, since the control function can be uniformly completed by an external control circuit, the number of transistors used in the driving sub - circuit is reduced, and the area required for a single pixel will also be correspondingly reduced. Therefore, with this circuit, more pixels can be arranged in the same display area, thereby improving the display resolution.

[0054] Optionally, in an embodiment of the present disclosure, the driving sub - circuit includes a first transistor, a second transistor, and a first capacitor; wherein, the gate of the first transistor is electrically connected to a first node, the first pole of the first transistor is electrically connected to a data terminal, and the second pole of the first transistor is electrically connected to a third node; the gate of the second transistor is electrically connected to the third node, the drain of the second transistor is electrically connected to a second node, and the source of the second transistor is electrically connected to a fourth node; and the first pole of the first capacitor is electrically connected to the third node, and the second pole of the first capacitor is electrically connected to the fourth node.

[0055] Reference is made below Figure 3B to further illustrate the driving sub - circuit of the embodiment of the present disclosure.

[0056] Figure 3B Schematically shown is a schematic structural diagram of a driving sub - circuit according to a specific embodiment of the present disclosure.

[0057] As Figure 3B shown, the driving sub - circuit 103 may include a first transistor T1 and a second transistor T2. The first transistor T1 may be a switching transistor, and the second transistor T2 may be a driving transistor. Among them, the first transistor T1 may be a P - type transistor, and the second transistor T2 may be an N - type transistor.

[0058] The gate of the first transistor T1 is electrically connected to a first node N1, the first pole of the first transistor T1 is electrically connected to a data terminal, and the second pole of the first transistor T1 is electrically connected to a third node N3.

[0059] The gate of the second transistor T2 is electrically connected to the third node N3, the drain of the second transistor T2 is electrically connected to a second node N2, and the source of the second transistor T2 is electrically connected to a fourth node N4.

[0060] As Figure 3B shown, the driving sub - circuit may further include a first capacitor C1. Among them, the first pole of the first capacitor C1 is electrically connected to the third node N3, and the second pole of the first capacitor is electrically connected to the fourth node N4.

[0061] As Figure 3B shown, the driving sub - circuit may further include a light - emitting element LED, wherein, the first end of the light - emitting element LED is electrically connected to the fourth node N4, and the second end of the light - emitting element LED is electrically connected to a second power supply VSS.

[0062] Compared with the second power - supply voltage VSS provided by the second power supply, the first power - supply voltage VDD provided by the first power supply may be a relatively high voltage, and the second power - supply voltage VSS may be a relatively low voltage.

[0063] The light-emitting element LED can be any current-driven light-emitting device, such as an OLED (Organic Light-Emitting Diode), an AMOLED (Active-matrix organic light-emitting diode), etc. Optionally, the first end of the light-emitting element LED can be represented as the anode of the light-emitting element LED, and the second end of the light-emitting element LED can be represented as the cathode of the light-emitting element LED.

[0064] In the data writing stage, the first control sub-circuit provides a gating signal GATE to the gate of the first transistor T1 through the first node N1. When the gating signal GATE is at a high level and the first transistor T1 is turned on, the data signal Vdata of the data terminal Vdata is transmitted to the third node N3 through the first transistor T1 to change the potential of the third node N3.

[0065] When the gating signal GATE is at a low level and the first transistor T1 is turned off, the connection between the data terminal Vdata and the third node N3 is cut off to stop writing the data signal Vdata.

[0066] Since the gate-source voltage of the second transistor T2 is the potential difference between the third node N3 and the fourth node N4, when the potential of the third node N3 changes, the gate-source voltage of the second transistor T2 will also change when the potential of the fourth node N4 is relatively stable.

[0067] In the light-emitting stage, the second control sub-circuit provides a first power supply voltage VDD to the drain of the second transistor T2 through the second node N2. When the potential of the third node N3 is greater than the threshold voltage of the second transistor T2, the second transistor T2 is turned on, causing current to flow from the second node N2 through the second transistor T2 to the fourth node N4 to drive the light-emitting element LED connected to the fourth node N4 to emit light.

[0068] After the data signal Vdata is written, the first capacitor C1 can maintain the potential at the third node N3, preventing the gate-source voltage of the second transistor T2 from mutating due to external interference or signal fluctuations, so that the second transistor T2 continuously drives the light-emitting element LED to emit light with a stable current within a display cycle.

[0069] Based on this, embodiments of the present disclosure can turn on or off the first transistor by controlling the signal of the first node, thereby realizing the transmission or blocking of the data signal at the data terminal to the third node. In applications such as display circuits, this method can accurately transmit the externally input data signal to subsequent circuits, provide a basic signal for driving pixels, and realize the control of pixel display states such as brightness and color. In addition, during the operation of the circuit, a certain amount of charge is stored through the first capacitor, thereby stabilizing the voltage between the third node and the fourth node, ensuring that the pixel can accurately display according to the requirements of the data signal, and avoiding display abnormalities such as flickering and uneven brightness.

[0070] The light-emitting element LED is usually a light-emitting diode device. Since the diode device has a capacitance effect, there is usually a residual voltage after the light-emitting element LED finishes emitting light. Optionally, in order to eliminate the residual voltage, in embodiments of the present disclosure, a reset structure can be provided in the driving sub-circuit. Before the pixel circuit controls the light-emitting element LED to emit light, the reset structure can perform a reset process on the potential at the light-emitting element LED.

[0071] The following refers to Figure 4A to further illustrate the pixel circuit of another embodiment of the present disclosure.

[0072] Figure 4A A schematic diagram of a pixel circuit according to another specific embodiment of the present disclosure is schematically shown.

[0073] As Figure 4A shown, on the basis of Figure 3A the driving sub-circuit 103 is also electrically connected to the reset terminal Vinit and the first control terminal CON1 respectively.

[0074] The driving sub-circuit 103 is also configured to perform a reset process on the potential at the fourth node N4 by using the reset signal Vinit from the reset terminal Vinit under the control of the first control signal CON1 from the first control terminal CON1, so as to eliminate the potential deviation at the fourth node caused by factors such as drift of transistor characteristics and charge accumulation.

[0075] The reset signal Vinit can be a signal with a relatively low potential level with respect to the first power supply voltage VDD.

[0076] Optionally, in embodiments of the present disclosure, the driving sub-circuit further includes a third transistor and a second capacitor. Among them, the gate of the third transistor is electrically connected to the first control terminal, the first pole of the third transistor is electrically connected to the fourth node, the second pole of the third transistor is electrically connected to the reset terminal, the first pole of the second capacitor is electrically connected to the fourth node, and the second pole of the second capacitor is electrically connected to the first control terminal.

[0077] The following refers toFigure 4B A further description is given of the drive sub - circuit according to another embodiment of the present disclosure.

[0078] Figure 4B A schematic structural diagram of a drive sub - circuit according to another specific embodiment of the present disclosure is schematically shown.

[0079] As Figure 4B shown, on the basis of Figure 3B the drive sub - circuit may further include a third transistor T3, and the third transistor may be a switching transistor. Among them, the third transistor T3 may be an N - type transistor.

[0080] The gate of the third transistor T3 is electrically connected to the first control terminal CON1, the first pole of the third transistor T3 is electrically connected to the fourth node N4, and the second pole of the third transistor T3 is electrically connected to the reset terminal Vinit.

[0081] As Figure 4B shown, the drive sub - circuit may further include a second capacitor C2. Among them, the first pole of the second capacitor C2 is electrically connected to the fourth node N4, and the second pole of the second capacitor C2 is electrically connected to the first control terminal CON1.

[0082] When the first control signal CON1 input at the first control terminal CON1 is at a high level, the third transistor T3 is turned on. At this time, the reset signal Vinit at the reset terminal Vinit is transmitted to the fourth node N4 through the third transistor T3, and the potential at the fourth node N4 is quickly pulled down to the voltage value of the reset signal Vinit.

[0083] During the reset process, the second capacitor C2 interacts with the potential change at the fourth node N4. Since one end of the second capacitor C2 is connected to the fourth node N4 and the other end is connected to the first control terminal CON1, when the potential at the fourth node N4 changes, the second capacitor C2 will be charged or discharged accordingly to assist the potential at the fourth node N4 to quickly stabilize to the reset value.

[0084] After the reset is completed, the first control signal CON1 at the first control terminal changes, causing the third transistor T3 to turn off. At this time, the drive sub - circuit 103 enters the data writing stage.

[0085] Based on this, embodiments of the present disclosure control the conduction and cutoff of the third transistor through the first control signal of the first control terminal. When the first control signal turns on the third transistor, the reset signal at the reset terminal can directly act on the fourth node to reset its potential. In applications such as display circuits, the state of pixels needs to be reset at the beginning of each display cycle to ensure accurate display of the next frame of the picture. With this reset function, it can be ensured that the potential of the fourth node returns to the initial state, providing a stable and predictable starting point for subsequent data writing and pixel driving. In addition, when the potential of the fourth node fluctuates, the second capacitor can charge or discharge to balance the voltage change, reduce the amplitude of potential fluctuation, ensure the normal operation of the pixel circuit, and reduce the risk of misoperation.

[0086] Optionally, in an embodiment of the present disclosure, the first control sub-circuit is configured to provide, under the control of a second control signal from a second control terminal, either a first gating signal from a first gating terminal or a second gating signal from a second gating terminal as a gating signal to a first node.

[0087] Figure 5A A schematic diagram of a pixel circuit according to another specific embodiment of the present disclosure is schematically shown.

[0088] As Figure 5A shown, on the basis of Figure 3A the first control sub-circuit 101 is electrically connected to the second control terminal CON2, the first gating terminal GATE1, and the second gating terminal GATE2 respectively.

[0089] Under the control of a second control signal CON2 from the second control terminal CON2, either a first gating signal GATE1 from the first gating terminal GATE1 or a second gating signal GATE2 from the second gating terminal GATE2 is provided as a gating signal GATE to the first node N1.

[0090] Optionally, in an embodiment of the present disclosure, the first control sub-circuit includes a fourth transistor and a fifth transistor; wherein, the gate of the fourth transistor is electrically connected to the second control terminal, the first pole of the fourth transistor is electrically connected to the first gating terminal, and the second pole of the fourth transistor is electrically connected to the first node; and the gate of the fifth transistor is electrically connected to the second control terminal, the first pole of the fifth transistor is electrically connected to the first node, and the second pole of the fifth transistor is electrically connected to the second gating terminal.

[0091] Next, with reference to Figure 5B the first control sub-circuit of a specific embodiment of the present disclosure will be further described.

[0092] Figure 5B A schematic structural diagram of the first control sub-circuit according to a specific embodiment of the present disclosure is schematically shown.

[0093] As Figure 5B shown, the first control sub - circuit 101 may include a fourth transistor T4 and a fifth transistor T5, and the channel doping types of the fourth transistor T4 and the fifth transistor T5 are different. For example, when the fourth transistor T4 is a P - type transistor, the fifth transistor T5 may be an N - type transistor. When the fourth transistor T4 is an N - type transistor, the fifth transistor T5 may be a P - type transistor. Here, the channel doping types of the fourth transistor T4 and the fifth transistor T5 are not specifically limited.

[0094] Among them, the fourth transistor T4 and the fifth transistor T5 may be switching transistors.

[0095] The gate of the fourth transistor T4 is electrically connected to the second control terminal CON2, the first pole of the fourth transistor T4 is electrically connected to the first gating terminal GATE1, and the second pole of the fourth transistor T4 is electrically connected to the first node N1.

[0096] The gate of the fifth transistor T5 is electrically connected to the second control terminal CON2, the first pole of the fifth transistor T5 is electrically connected to the first node N1, and the second pole of the fifth transistor T5 is electrically connected to the second gating terminal GATE2.

[0097] In the case where the fourth transistor T4 is a P - type transistor and the fifth transistor T5 is an N - type transistor:

[0098] When the second control signal CON2 is at a low level, the fourth transistor T4 is turned on and the fifth transistor T5 is turned off. At this time, the first gating signal GATE1 of the first gating terminal GATE1 can be transmitted to the first node N1 through the fourth transistor T4, while the second gating signal GATE2 of the second gating terminal GATE2 cannot be transmitted to the first node N1 through the fifth transistor T5. Therefore, only the first gating signal GATE1 is provided as the gating signal GATE to the drive sub - circuit 103 through the first node N1.

[0099] When the second control signal CON2 is at a high level, the fourth transistor T4 is turned off and the fifth transistor T5 is turned on. At this time, the second gating signal GATE2 of the second gating terminal GATE2 can be transmitted to the first node N1 through the fifth transistor T5, while the first gating signal GATE1 of the first gating terminal GATE1 cannot be transmitted to the first node N1 through the fourth transistor T4. Therefore, only the second gating signal GATE2 is provided as the gating signal GATE to the drive sub - circuit 103 through the first node N1.

[0100] Optionally, in another embodiment, in the case where the fourth transistor T4 is an N - type transistor and the fifth transistor T5 is a P - type transistor:

[0101] When the second control signal CON2 is at a high level, the fourth transistor T4 is turned on and the fifth transistor T5 is turned off. At this time, the first gating signal GATE1 of the first gating terminal GATE1 can be transmitted to the first node N1 through the fourth transistor T4, while the second gating signal GATE2 of the second gating terminal GATE2 cannot be transmitted to the first node N1 through the fifth transistor T5. Therefore, only the first gating signal GATE1 is used as the gating signal GATE and provided to the driving sub-circuit 103 through the first node N1.

[0102] When the second control signal CON2 is at a low level, the fourth transistor T4 is turned off and the fifth transistor T5 is turned on. At this time, the second gating signal GATE2 of the second gating terminal GATE2 can be transmitted to the first node N1 through the fifth transistor T5, while the first gating signal GATE1 of the first gating terminal GATE1 cannot be transmitted to the first node N1 through the fourth transistor T4. Therefore, only the second gating signal GATE2 is used as the gating signal GATE and provided to the driving sub-circuit 103 through the first node N1.

[0103] Based on this, in the embodiments of the present disclosure, by changing the high and low levels of the second control signal output by the second control terminal, the on and off states of the fourth transistor and the fifth transistor can be flexibly controlled, so as to select between the first gating signal and the second gating signal, and transmit the selected gating signal to the first node, providing a suitable control signal for the driving sub-circuit to achieve different display functions and working modes. For example, in applications such as display circuits, there may be a normal display mode and a low-power display mode. Different modes require different gating signals to control the on and off states of pixels. By controlling the second control signal to switch between the two modes, the performance and power consumption of the display circuit are optimized, and the flexibility and adaptability of the display circuit are improved.

[0104] Optionally, in the embodiments of the present disclosure, the second control sub-circuit is configured to provide the first power supply voltage from the first power supply to the second node under the control of the third control signal from the third control terminal.

[0105] Figure 6A Schematically shows a schematic diagram of a pixel circuit according to another specific embodiment of the present disclosure.

[0106] As Figure 6A shown, on the basis of Figure 3A , the second control sub-circuit 102 is electrically connected to the third control terminal CON3.

[0107] The second control sub-circuit 102 is configured to provide the first power supply voltage VDD from the first power supply VDD to the second node N2 under the control of the third control signal CON3 from the third control terminal CON3.

[0108] Optionally, in an embodiment of the present disclosure, the second control sub - circuit includes a sixth transistor; wherein, the gate of the sixth transistor is electrically connected to a third control terminal, the first pole of the sixth transistor is electrically connected to a first power supply, and the second pole of the sixth transistor is electrically connected to a second node.

[0109] The following refers to Figure 6B to further illustrate the second control sub - circuit of the specific embodiment of the present disclosure.

[0110] Figure 6B Schematically shows a schematic structural diagram of the second control sub - circuit according to a specific embodiment of the present disclosure.

[0111] As Figure 6B shown, the second control sub - circuit 102 includes a sixth transistor T6, and the sixth transistor T6 can be a switching transistor. Among them, the sixth transistor T6 can be an N - type transistor.

[0112] The gate of the sixth transistor T6 is electrically connected to the third control terminal CON3, the first pole of the sixth transistor T6 is electrically connected to the first power supply VDD, and the second pole of the sixth transistor T3 is electrically connected to the second node N2.

[0113] When the third control signal CON3 is at a high level, the sixth transistor T6 is turned on, and the first power - supply voltage VDD of the first power supply VDD is transmitted to the second node N2 through the sixth transistor T6. After receiving the first power - supply voltage VDD, the second node N2 supplies the first power - supply voltage VDD to the driving sub - circuit 103, so that the driving sub - circuit 103 starts to work under the action of the first power - supply voltage VDD.

[0114] According to an embodiment of the present disclosure, by controlling the conduction and cut - off of the sixth transistor through the third control signal at the third control terminal, the second control sub - circuit can flexibly supply the first power - supply voltage to the second node, thereby controlling the working states of the driving sub - circuit and the light - emitting element, and realizing the display function of the pixel circuit. In addition, when the sixth transistor is cut off, it can effectively isolate the first power supply and the second node, prevent the signal of the second node from interfering with the first power supply, and at the same time avoid the voltage of the first power supply from affecting the potential of the second node when it is not needed.

[0115] The following combines Figure 2 、 Figures 3A - 3B 、 Figures 4A - 4B 、 Figures 5A - 5B 、 Figures 6A - 6B the circuit structures respectively shown to further illustrate the pixel circuit of the embodiment of the present disclosure.

[0116] Figure 7A Schematically shows a schematic structural diagram of the pixel circuit according to an embodiment of the present disclosure.

[0117] As Figure 7A shown, the pixel circuit 700 may include a first transistor T1 to a sixth transistor T6, a first capacitor C1, a second capacitor C2, and a light-emitting element LED. Among them, the first transistor T1 to the third transistor T3, and the fifth transistor T5 to the sixth transistor T6 may be N-type transistors, and the fourth transistor T4 may be a P-type transistor. Among them, the first transistor T1, the third transistor T3 to the sixth transistor T6 may be switching transistors, and the second transistor T2 may be a driving transistor.

[0118] The gate of the first transistor T1 is electrically connected to the first node N1, the first pole of the first transistor T1 is electrically connected to the data terminal Vdata, and the second pole of the first transistor T1 is electrically connected to the third node N3. The gate of the second transistor T2 is electrically connected to the third node N3, the drain of the second transistor T2 is electrically connected to the second node N2, and the source of the second transistor T2 is electrically connected to the fourth node N4. The gate of the third transistor T3 is electrically connected to the first control terminal CON1, the first pole of the third transistor T3 is electrically connected to the fourth node N4, and the second pole of the third transistor T3 is electrically connected to the reset terminal Vinit. The gate of the fourth transistor T4 is electrically connected to the second control terminal CON2, the first pole of the fourth transistor T4 is electrically connected to the first gating terminal GATE1, and the second pole of the fourth transistor T4 is electrically connected to the first node N1. The gate of the fifth transistor T5 is electrically connected to the second control terminal CON2, the first pole of the fifth transistor T5 is electrically connected to the first node N1, and the second pole of the fifth transistor T5 is electrically connected to the second gating terminal GATE2. The gate of the sixth transistor T6 is electrically connected to the third control terminal CON3, the first pole of the sixth transistor T6 is electrically connected to the first power supply VDD, and the second pole of the sixth transistor T3 is electrically connected to the second node N2. The first pole of the first capacitor C1 is electrically connected to the third node N3, and the second pole of the first capacitor is electrically connected to the fourth node N4. The first pole of the second capacitor C2 is electrically connected to the fourth node N4, and the second pole of the second capacitor C2 is electrically connected to the first control terminal CON1. The first end of the light-emitting element LED is electrically connected to the fourth node N4, and the second end of the light-emitting element LED is electrically connected to the second power supply VSS.

[0119] Figure 7B Schematically shows the operating timing diagram of the pixel circuit according to an embodiment of the present disclosure.

[0120] As Figure 7B shown, in the P1 stage, the pixel circuit 700 may be in the reset stage, in the P2 stage, the pixel circuit 700 may be in the voltage compensation stage, in the P3 stage, the pixel circuit 700 may be in the data writing stage, and in the P4 stage, the pixel circuit 700 may be in the light-emitting stage.

[0121] The following combines with Figures 7C - 7FThe circuit structures shown respectively are used to further illustrate each working stage of the pixel circuit according to the embodiments of the present disclosure.

[0122] Figure 7C FIG. schematically shows a pixel circuit according to an embodiment of the present disclosure in a reset stage.

[0123] Figure 7D FIG. schematically shows a pixel circuit according to an embodiment of the present disclosure in a voltage compensation stage.

[0124] Figure 7E FIG. schematically shows a pixel circuit according to an embodiment of the present disclosure in a data writing stage.

[0125] Figure 7F FIG. schematically shows a pixel circuit according to an embodiment of the present disclosure in a light emitting stage.

[0126] In stage P1, as Figure 7C shown, the second control signal CON2 is at a low level to control the fourth transistor T4 to conduct, so as to transfer the first gate signal GATE1 to the first node N1; the first gate signal GATE1 is at a high level to control the first transistor T1 to conduct, so that the third node N3 is disconnected from the data terminal Vdata, and the potential at the third node N3 is pulled down to the reference signal Vref, thereby the potential at the third node N3 can be reset by using the reference signal Vref at the data terminal; the first control signal CON1 is at a high level to control the third transistor T3 to conduct, so that the fourth node N4 is connected to the reset terminal Vinit, and the potential at the fourth node N4 is pulled down to the reset signal Vinit, thereby the potential at the fourth node N4 can be reset by using the reset signal Vinit.

[0127] Preferably, in stage P1, the data terminal can be configured to input the reference signal Vref to avoid the data signal Vdata interfering with the reset of the third node N3.

[0128] Preferably, in stage P1, the third node N3 of the driving sub-circuit 103 is reset row by row by using the first gate signal GATE1 to reduce the instantaneous current peak, thereby reducing the power consumption.

[0129] Preferably, in stage P1, the first gate signal GATE1 can also be configured as a global pulse signal, so that the third nodes N3 of multiple driving sub-circuits 103 in the pixel circuit are reset simultaneously to reduce the reset occupation time of the third node N3.

[0130] In stage P2, as Figure 7DAs shown, the second control signal CON2 remains low to control the fourth transistor T4 to conduct continuously, so as to supply the first gating signal GATE1 to the gate of the first transistor T1 through the first node N1; the first gating signal GATE1 is high to control the first transistor T1 to conduct, so that the potential at the third node N3 is maintained at the reference signal Vref; the third control signal CON3 is high to control the sixth transistor T6 to conduct, so as to supply the first power supply voltage VDD to the first pole of the second transistor T2 through the second node N2, and control the second transistor T2 to conduct when the potential at the third node N3 is greater than the threshold voltage of the second transistor T2, so that current flows from the second node N2 through the second transistor T2 to the fourth node N4. At this time, the potential at the fourth node N4 is V N4 = V ref - V th t2 , where V th_t2 is the threshold voltage of the second transistor T2, and the voltage maintained by the first capacitor C1 is V C1 = V ref -(V ref - V th_t2 ) = V th_t2 , thus realizing the voltage compensation for the fourth node N4.

[0131] In the P3 stage, as Figure 7E shown, the second control signal CON2 is high to control the fourth transistor T4 to cut off and the fifth transistor T5 to conduct, so as to supply the second gating signal GATE2 to the gate of the first transistor T1 through the first node N1; the second gating signal GATE2 is high to control the first transistor T1 to conduct, so as to write the data signal Vdata at the data terminal into the third node N3 through the first transistor T1 to change the potential at the third node N3. At this time, the potential at the third node N3 is V N3 = Vdata, which is greater than the potential at the fourth node N4, that is, Vref - Vth_t2, so that the second transistor T2 conducts, and current begins to flow from the second node N2 through the second transistor T2 to the fourth node N4. At this time, through the coupling effect of the first capacitor C1 and the second capacitor C2, the potential of the fourth node N4 is changed. Among them, the potential change of the fourth node N4 is: V N4 = V ref - V th_t2 +(V data - V ref )×C1 / (C1 + C2). As the potential of the fourth node N4 changes, the gate-source voltage Vgs of the second transistor T2 also changes accordingly: V gs = V N3 - V N4 =(V data-V ref )×C2 / (C1 + C2)+V th_t2 。

[0132] In the P4 stage, as Figure 7F shown, the second control signal CON2 is at a high level to turn off the fourth transistor T4 and turn on the fifth transistor T5, so as to provide the second gating signal GATE2 to the gate of the first transistor T1 through the first node N1; the second gating signal GATE2 is at a low level to turn off the first transistor T1, so that the data signal Vdata stops being written; the third control signal CON3 is at a high level to turn on the sixth transistor T6, so as to provide the first power supply voltage VDD to the first pole of the second transistor T2 through the second node N2. At this time, the second transistor T2 is turned on, so that the current flows from the second node N2 through the second transistor T2 to the fourth node N4 to drive the light-emitting element LED connected to the fourth node N4 to emit light. Based on the source-follower effect of the second transistor T2, in order to maintain the gate-source voltage Vgs of the second transistor T2 unchanged to ensure the stability of the light-emitting current, when the potential of the fourth node N4 changes, the potential of the third node N3 will jump with the potential of the fourth node N4. At this time, the current I d = k×(V gs -V th_t2 ) 2 = I d = k×[(V data -V ref )×C2 / (C1 + C2)] 2 , where k is a correlation coefficient such as TFTW / L, mobility, etc. Therefore, in the P4 stage, the pixel circuit 1100 can control the light-emitting brightness of the light-emitting element LED based on the written data signal V data to realize image display.

[0133] Based on this, in the embodiments of the present disclosure, the fourth transistor T4 to the sixth transistor T6 are disposed outside the non-display area, reducing the number of transistors included in the display area, so that the driving sub-circuit located in the display area forms a 3T2C structure, reducing the occupied area of the control circuit on the display area, further improving the space utilization rate of the display area, enabling the pixels to be arranged more closely, reducing the number of transistors used in the driving sub-circuit, and correspondingly reducing the area required for a single pixel.

[0134] In an embodiment of the present disclosure, the sixth transistor T6 is disposed outside the non-display area. The second gating signal from the non-display area is used to control the conduction of the sixth transistor T6, and the first power supply VDD is connected to the second node N2 of the pixel circuit row by row, reducing the bus load and noise interference (such as crosstalk). In addition, by controlling the conduction time of the sixth transistor T6, the emission duration of the light-emitting element LED can be precisely adjusted, and the motion blur can be reduced in cooperation with the high refresh rate.

[0135] In an embodiment of the present disclosure, data signals multiplex the same data line in different stages to input different function signals to the first node N1, so as to avoid setting separate data lines for different functions, reducing the number of pins and wiring complexity within the pixel, and releasing space for high pixel density layout. In addition, by switching the conduction states of the fourth transistor T4 and the fifth transistor T5 through the second control terminal CON2, signal interference in different stages is ensured to be avoided, improving the operation reliability.

[0136] In an embodiment of the present disclosure, the second transistor T2 can be used as a source follower. Its gate voltage determines the source voltage, and it has the characteristics of high input impedance and low output impedance, which can stably drive the current of the light-emitting element LED.

[0137] In an embodiment of the present disclosure, the first capacitor C1 is used to store the gate-source voltage difference of the second transistor T2, and directly couple the threshold voltage deviation of the second transistor T2 into Vgs to eliminate the influence of TFT manufacturing differences on the emission current and improve the display uniformity. The second capacitor C2 is used to store the potential of the reset signal Vinit during the reset stage, and stabilize the potential at the fourth node N4 through the coupling effect during the emission stage to reduce the influence of power supply fluctuations.

[0138] Preferably, in the pixel circuit of the embodiment of the present disclosure, the first transistor T1 to the sixth transistor T6 can all be configured as any one or more of a low-temperature polysilicon thin-film transistor, a low-temperature polysilicon oxide thin-film transistor, and an oxide thin-film transistor.

[0139] Preferably, for the driving sub-circuit 103 of the embodiment of the present disclosure, the first transistor T1 and the second transistor T2 can be configured as low-temperature polysilicon thin-film transistors to improve the compensation ability of the threshold voltage of the transistors. During the display process, through this configuration, the display non-uniformity problem caused by the threshold voltage difference can be reduced. At the same time, through this configuration, the bottleneck of the anode layout in the layout design can also be reduced, which is beneficial to achieving a more compact pixel layout, thereby increasing the pixel density (PPI). The third transistor can be configured as an oxide thin-film transistor. Based on its low leakage characteristics, it can ensure that the third node N3 remains stable during the non-active period, avoiding flicker.

[0140] In the pixel circuit 10 of the first embodiment of the present disclosure, the first transistor T1 to the third transistor T3, and the fifth transistor T5 to the sixth transistor T6 may be configured as N-type transistors, and the fourth transistor T4 may be configured as a P-type transistor.

[0141] Preferably, in the pixel circuit 10 of the second embodiment of the present disclosure, the first transistor T1 to the third transistor T3, and the fifth transistor T5 to the sixth transistor T6 may be configured as P-type transistors, and the fourth transistor T4 may be configured as an N-type transistor.

[0142] Preferably, in the pixel circuit 10 of the third embodiment of the present disclosure, the first transistor T1 to the fourth transistor T4, and the sixth transistor T6 may be configured as P-type transistors, and the fifth transistor T5 may be configured as an N-type transistor.

[0143] Preferably, in the pixel circuit 10 of the fourth embodiment of the present disclosure, the first transistor T1 to the fourth transistor T4, and the sixth transistor T6 may be configured as N-type transistors, and the fifth transistor T5 may be configured as a P-type transistor.

[0144] According to the embodiments of the present disclosure, for the transistor types of the first transistor T1 to the sixth transistor T6, the logic levels of the corresponding gate signals may be configured, and the first transistor T1 to the sixth transistor T6 may be controlled to be turned on and off through the gate signals, so as to achieve precise control of the pixel circuit. Precise control of the data writing stage, reset stage, voltage compensation stage, and light emitting stage of the pixel circuit.

[0145] Figure 8 Schematically shows a schematic diagram of a display panel according to an embodiment of the present disclosure.

[0146] As Figure 8 shown, the display panel 800 may include a display area 810 and a non-display area 820. A plurality of pixel circuits 811 may be provided in the display area 810, and the pixel circuit 811 may be any one of the pixel circuits 200 and 700 described above, which is not limited herein.

[0147] Figure 9 Schematically shows a schematic diagram of a display device according to an embodiment of the present disclosure.

[0148] As Figure 9 shown, the display device 900 may include a display panel 910. A plurality of pixel circuits may be provided in the display area of the display panel 910, and the pixel circuit may be any one of the pixel circuits 200 and 700 described above, which is not limited herein.

[0149] Those skilled in the art will appreciate that the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.

[0150] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A pixel circuit, comprising: A plurality of circuit units, the circuit units comprising a first control subcircuit and a second control subcircuit disposed in a non-display area of ​​a display panel, and a plurality of driving subcircuits disposed in a display area of ​​the display panel, the first control subcircuit being electrically connected to the plurality of driving subcircuits via a first node, respectively, and the second control subcircuit being electrically connected to the plurality of driving subcircuits via a second node, respectively; Among them, the first control subcircuit is configured to provide a gating signal to the first node, the second control subcircuit is configured to provide a first power supply voltage to the second node, and the driving subcircuit is configured to drive the light-emitting element to emit light based on the first power supply voltage and the data signal from the data terminal under the control of the gating signal.

2. The pixel circuit according to claim 1, wherein: The driving subcircuit includes a first transistor, a second transistor and a first capacitor; The gate of the first transistor is electrically connected to the first node, the first electrode of the first transistor is electrically connected to the data terminal, and the second electrode of the first transistor is electrically connected to the third node; a gate of the second transistor is electrically connected to the third node, a drain of the second transistor is electrically connected to the second node, and a source of the second transistor is electrically connected to a fourth node; and A first electrode of the first capacitor is electrically connected to the third node, and a second electrode of the first capacitor is electrically connected to the fourth node.

3. The pixel circuit according to claim 2, wherein: The driving subcircuit is also electrically connected to the reset terminal and the first control terminal respectively; The driving sub-circuit is further configured to reset the potential at the fourth node using a reset signal from the reset terminal under the control of the first control signal from the first control terminal.

4. The pixel circuit according to claim 3, wherein: The driving subcircuit also includes a third transistor and a second capacitor; wherein the gate of the third transistor is electrically connected to the first control terminal, the first electrode of the third transistor is electrically connected to the fourth node, and the second electrode of the third transistor is electrically connected to the reset terminal; and A first electrode of the second capacitor is electrically connected to the fourth node, and a second electrode of the second capacitor is electrically connected to the first control terminal.

5. The pixel circuit according to any one of claims 2 to 4, wherein: A first terminal of the light emitting element is electrically connected to the fourth node, and a second terminal of the light emitting element is electrically connected to a second power source.

6. The pixel circuit according to claim 1, wherein: The first control subcircuit is configured to provide a first gating signal from a first gating terminal or a second gating signal from a second gating terminal as the gating signal to the first node under the control of a second control signal from a second control terminal.

7. The pixel circuit according to claim 6, wherein: The first control subcircuit includes a fourth transistor and a fifth transistor; wherein the gate of the fourth transistor is electrically connected to the second control terminal, the first electrode of the fourth transistor is electrically connected to the first gate terminal, and the second electrode of the fourth transistor is electrically connected to the first node; and A gate of the fifth transistor is electrically connected to the second control terminal, a first electrode of the fifth transistor is electrically connected to the first node, and a second electrode of the fifth transistor is electrically connected to the second gate terminal.

8. The pixel circuit according to claim 7, wherein: A channel doping type of the fourth transistor is different from a channel doping type of the fifth transistor.

9. The pixel circuit according to claim 1, wherein: The second control subcircuit is configured to provide a first power supply voltage from a first power supply to the second node under the control of a third control signal from a third control terminal.

10. The pixel circuit according to claim 9, wherein: The second control subcircuit includes a sixth transistor; The gate of the sixth transistor is electrically connected to the third control terminal, the first electrode of the sixth transistor is electrically connected to the first power supply, and the second electrode of the sixth transistor is electrically connected to the second node.

11. A display panel comprising the pixel circuit according to any one of claims 1 to 10.

12. A display device comprising the display panel according to claim 11.

Images