Memory controller, control method, and memory device

Abstract

The invention discloses a memory controller, a control method, and a memory device. A memory controller connectable to a memory including a plurality of bank groups, each bank group including a plurality of banks, the memory controller holding a plurality of access requests to the memory, generating a read or write command from each of the plurality of access requests such that banks in different bank groups are set as destinations of adjacent read or write commands, and issuing a page control command for an access request selected from the plurality of access requests, wherein a page control command for an access request for which an open or closed state of a page of a plurality of memory banks set as a destination satisfies a predetermined condition is preferentially issued.

Description

Technical Field

[0001] The present disclosure relates to a memory controller, a control method, and a memory device. Background Art

[0002] Generally, DRAM is used as a main storage device in a computer system. As the functions and performance of computer systems have improved, the requirements for DRAM performance have increased, and various techniques for memory controllers have been proposed to more effectively achieve performance.

[0003] Some DRAMs are configured to include a plurality of bank groups, each bank group including a plurality of banks, and the data transfer speed is increased by independently performing a prefetch operation between the bank groups. In one of such DRAMs, when a read command or a write command is issued to the banks in the same bank group in a consecutive manner, the interval between the commands needs to satisfy a timing constraint for ensuring the completion of the prefetch of the previous command. For this reason, a gap appears on the data bus, resulting in a reduction in memory use efficiency. Hereinafter, read commands and write commands are collectively referred to as "read or write commands". In Japanese Patent Publication No. 2021-157295, the reduction in memory use efficiency is suppressed by a memory controller issuing adjacent read or write commands obtained by dividing one memory access request to the banks in different bank groups.

[0004] Japanese Patent Publication No. 2021-157295 does not mention the page control performed when adjacent read or write commands obtained by dividing one memory access request are issued to the banks in different bank groups. Even in a configuration where adjacent read or write commands are issued to the banks in different bank groups, if an interval appears between the page control commands of the plurality of banks that are the access destinations of the adjacent read or write commands, a redundant gap appears between the commands, and the memory use efficiency is reduced. According to one aspect of the present disclosure, such a problem is solved. Summary of the Invention

[0005] According to one aspect of the present disclosure, there is provided a memory controller that can be connected to a memory including a plurality of bank groups, each bank group including a plurality of banks. The memory controller includes: a holding circuit configured to hold a plurality of access requests to the memory; a read and write control circuit configured to generate a read or write command from each of the plurality of access requests such that banks in different bank groups are set as destinations of adjacent read or write commands; and a page control circuit configured to issue a page control command for an access request selected from the plurality of access requests, wherein the page control circuit preferentially issues a page control command for an access request for which the open or closed state of pages of a plurality of banks set as destinations satisfies a predetermined condition.

[0006] According to one aspect of the present invention, there is provided a control method for a memory controller that can be connected to a memory including a plurality of bank groups, each bank group including a plurality of banks. The control method includes: holding a plurality of access requests to the memory in a holding circuit; performing read and write control to generate a read or write command from each of the plurality of access requests such that banks in different bank groups are set as destinations of adjacent read or write commands; and performing page control to issue a page control command for an access request selected from the plurality of access requests, wherein in the page control, a page control command for an access request for which the open or closed state of pages of a plurality of banks set as destinations satisfies a predetermined condition is preferentially issued.

[0007] According to one aspect of the present disclosure, there is provided a memory device including: a memory including a plurality of bank groups, each bank group including a plurality of banks; and a controller that can be connected to the memory, wherein the controller includes: a holding circuit configured to hold a plurality of access requests to the memory; a read and write control circuit configured to generate a read or write command from each of the plurality of access requests such that banks in different bank groups are set as destinations of adjacent read or write commands; and a page control circuit configured to issue a page control command for an access request selected from the plurality of access requests, wherein the page control circuit preferentially issues a page control command for an access request for which the open or closed state of pages of a plurality of banks set as destinations satisfies a predetermined condition.

[0008] More features of various embodiments will become apparent from the following description of exemplary embodiments with reference to the accompanying drawings. Description of the Drawings

[0009] Figure 1 is a block diagram showing a configuration example of a memory controller according to the first embodiment.

[0010] Figure 2A is a diagram showing an exemplary data configuration of entries in an access hold circuit.

[0011] Figure 2B is a diagram showing an exemplary data configuration of entry control signals.

[0012] Figure 3 is a diagram showing a memory map according to the first embodiment.

[0013] Figure 4 is a block diagram showing a configuration example of a page control circuit according to the first embodiment.

[0014] Figure 5 is a flowchart showing a generation process of an ACT command issuance request according to the first embodiment.

[0015] Figure 6 is a flowchart showing a generation process of a PRE command issuance request according to the first embodiment.

[0016] Figure 7 is a block diagram showing a configuration example of a memory controller according to the second embodiment.

[0017] Figure 8 is a block diagram showing a configuration example of a read and write control circuit according to the second embodiment.

[0018] Figure 9 is a flowchart showing a determination process of a priority access type according to the second embodiment. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments are not intended to limit the scope of the claims. In the embodiments, multiple features are described, but embodiments that require all such features are not limited, and multiple such features can be appropriately combined. Additionally, in the drawings, the same or similar configurations are given the same reference numerals, and redundant descriptions thereof are omitted.

[0020] First Embodiment

[0021] Figure 1FIG. is a block diagram showing a configuration example of a memory controller 100 according to a first embodiment. The memory controller 100 is connected to a DRAM 110 and a bus master 120, selects any appropriate memory access request from a plurality of memory access requests, and issues a command. The DRAM 110 is a memory including a plurality of bank groups, each bank group including a plurality of banks, and in the present embodiment, the following description will be given: The DRAM 110 is configured to have four bank groups, each bank group including four banks. However, in the present disclosure, the number of bank groups and the number of banks in each bank group are not limited, and it is sufficient that the number of bank groups is two or more and the number of banks in each bank group is one or more. The bus master 120 sends a memory access request including address information (in the case of a write command, write data is also included) to the memory controller 100. The memory controller 100 generates a DRAM command including a read or write command and a page control command based on the memory access request received from the bus master 120, and sends the generated DRAM command to the DRAM 110. In addition, the memory controller 100 sends data to / receives data from the DRAM 110 based on the sent DRAM command.

[0022] Next, the configuration of the memory controller 100 will be described. The access hold circuit 101 is a buffer for holding a plurality of memory access requests from the bus master 120. The access hold circuit 101 according to the present embodiment can hold m pieces (m≥2) of entry data. In this example, a description will be given with m = 4, but the present disclosure does not limit the value of m. Figure 2A FIG. is a diagram showing an exemplary data configuration of the entry data 200 held in the access hold circuit 101. At most, Figure 2A the m pieces of entry data 200 shown in FIG. can be held in the access hold circuit 101. As shown in Figure 2A FIG., the entry data 200 has fields for access type, target bank group, target bank, target page, target column, and the remaining number of read or write commands. The access hold circuit 101 converts the memory access request received from the bus master 120 corresponding to the fields of the entry data 200 and holds the resulting data. The information stored in the fields is as follows.

[0023] (a) Access type field

[0024] The access type of the memory access request stored as an entry.

[0025] WRITE: The memory access request is a request to write (data)

[0026] READ: The memory access request is a request to read (data)

[0027] (b) Target bank group field

[0028] Bank group address accessed according to the memory access request stored as an entry.

[0029] (c) Target bank field

[0030] Bank address accessed according to the memory access request stored as an entry.

[0031] (d) Target page field

[0032] Page address accessed according to the memory access request stored as an entry.

[0033] (e) Target column field

[0034] Starting column address accessed according to the memory access request stored as an entry.

[0035] (f) Remaining read or write command count field

[0036] The number of remaining DRAM read or write commands to be executed according to the memory access request stored as an entry.

[0037] The access holding circuit 101 holds the entry data while maintaining the order of receiving the memory access requests from the bus master. When a memory access request is newly stored in the access holding circuit 101, the access holding circuit 101 stores the corresponding entry data sequentially from the top entry. In addition, when an entry data is deleted, the access holding circuit 101 moves the entry data of the memory access information received later than the deleted entry data to the top side. Then, the access holding circuit 101 stores the new memory access request from the bus master 120 as an entry after the last stored memory access request. In this way, the entries are held in the access holding circuit 101 and arranged in the order in which the entries are held. On the other hand, when the read and write control circuit 102 and the page control circuit 103 read the memory access request from the access holding circuit 101, the memory access request can be read from any entry.

[0038] Next, the entry control signal input to the access holding circuit 101 will be described. Figure 2BFIG. is a diagram showing an exemplary data configuration of an entry control signal 210. The entry control signal 210 includes an entry number field, a delete field, and an update field. When “1” is set in the delete field of the entry control signal 210, the access holding circuit 101 deletes the entry indicated by the data in the entry number field. When “1” is set in the update field, the access holding circuit 101 updates the target bank group field and the target column field of the entry indicated by the data in the entry number field to the bank group address and the top column address of the next read or write command. Further, at this time, the access holding circuit 101 updates the remaining read or write command count field to a value obtained by subtracting one from the value of the remaining read or write command count field.

[0039] Based on Figure 3 the memory map 300 and the address information of the entry shown in FIG., the bank group address and the top column address of the read or write command are calculated. The memory map 300 according to the present embodiment assumes a case where the DRAM data has a 32-bit width and the burst length of the read or write command is 16. Further, it is assumed that the data width of the memory access request is 8 bits / address, and thus the four addresses represented by the lower 2 bits (addr(0) and addr(1)) of the memory access request address are not assigned to the DRAM address. To achieve a burst length of 16 with a 32-bit width, 32 addresses (column addresses (0) to (3)) are accessed in a single read or write access. The bank group address (1) is assigned to the bit immediately above the column address (3), and thus, in adjacent read or write commands, the first bit of the bank group address is switched. Therefore, the read or write commands are issued to different bank groups. Note that the present disclosure does not depend on Figure 3 the memory map 300 shown in FIG., and any memory map in which adjacent read or write commands correspond to different bank group addresses can be used.

[0040] The read and write control circuit 102 can refer to all memory access requests stored in the access holding circuit 101. The read and write control circuit 102 selects any appropriate memory access request from the memory access requests stored in the access holding circuit 101 for which the page to be accessed is open. Based on the target bank group field, the target bank field, and the target page field of the entry data 200 and the bank state generated by the bank state management circuit 104, it is determined whether the page to be accessed according to the memory access request is open. The read and write control circuit 102 generates a read or write command from the selected memory access request and outputs the command to the command selector 105.

[0041] Next, the process of the read and write control circuit 102 generating an entry control signal will be described. When the last read or write command executed for a memory access request is issued, the processing of the memory access request is completed. In this case, the read and write control circuit 102 generates an entry control signal (where the delete field is set to "1") from the access hold circuit 101 to indicate deleting the entry corresponding to the memory access request. On the other hand, in the case where a read or write instruction that is not the last read or write command in the memory access request is issued, the read and write control circuit 102 generates an entry control signal to update the entry in the access hold circuit 101 corresponding to the memory access request. Note that in the case where the last read or write command is issued, the corresponding entry is deleted, so there is no need to update the entry. Additionally, it can be determined whether the issued read command or write command is the last command based on whether the remaining read or write command count field of the entry data 200 is "1".

[0042] The page control circuit 103 can refer to all memory access requests stored in the access hold circuit 101. The page control circuit 103 generates page control commands such as an activate command and a precharge command based on the memory access requests held in the access hold circuit 101 and the bank state output by the bank state management circuit 104. The generated page control commands are output to the command selector 105. Hereinafter, the activate command is referred to as the "ACT command", and the precharge command is referred to as the "PRE command".

[0043] The bank state management circuit 104 updates the bank state based on the command issue status input from the command selector 105. The command issue status consists of the command type (read or write) issued to the DRAM 110 through the command selector 105 and the bank group, bank, and page to which the command is issued. The bank state includes information indicating whether each page in the banks constituting the DRAM 110 is open and the address of the open page.

[0044] The command selector 105 selects one command from the read or write commands input from the read and write control circuit 102 and the ACT command and PRE command input from the page control circuit 103, and issues the command to the DRAM 110. Note that commands such as a refresh command can also be selected simultaneously, which is not described in this embodiment. In addition, the command selector 105 generates information about the command issue status from the command type of the command issued to the DRAM 110 and the bank group, bank, and page to which the command is issued, and outputs the information to the bank state management circuit 104.

[0045] Figure 4FIG. is a block diagram showing a configuration example of a page control circuit 103 according to the first embodiment. The page control circuit 103 includes an ACT command issue request generation circuit (hereinafter, ACT request generation circuit 401) and an ACT command issue request selection circuit (hereinafter, ACT request selection circuit 402). In addition, the page control circuit 103 includes a PRE command issue request generation circuit (hereinafter, PRE request generation circuit 403) and a PRE command issue request selection circuit (hereinafter, PRE request selection circuit 404).

[0046] The ACT request generation circuit 401 and the ACT request selection circuit 402 preferentially issue a page control command (ACT command) for a memory access request whose open or closed state of pages of a plurality of banks set as destinations satisfies a predetermined condition. For each memory access request among the memory access requests held in the access hold circuit 101, the ACT request generation circuit 401 generates an ACT command issue request based on the bank state provided from the bank state management circuit 104. In addition, the ACT request generation circuit 401 determines whether the generated ACT command issue request is to be preferentially selected by the ACT request selection circuit 402 based on the state of the bank set as the destination of the memory access request, and generates a priority ACT flag indicating the determination result. Figure 5 FIG. is a flowchart showing the generation process of the ACT command issue request according to the present embodiment. The operation of the ACT request generation circuit 401 will be described in more detail below with reference to Figure 5 the flowchart in. For each cycle of memory access, the generation process of the ACT command issue request is executed for each memory access request among the memory access requests held in the access hold circuit 101.

[0047] The ACT request generation circuit 401 specifies the access destination bank of the memory access request based on the target bank group and target bank of the memory access request, the remaining number of read or write commands, and the number n of banks sequentially accessed according to the memory access request (step S500). In the memory mapping 300 ( Figure 3 ) of the present embodiment, since the memory access request alternately accesses two banks belonging to different bank groups, n = 2. Therefore, for example, if the target bank group is "0", the target bank is "0", and the remaining number of read or write commands is two or more, the two banks represented by (bank group address, bank address)-that is, (0, 0) and (2, 0) are the access destination banks. Note that in the present embodiment, n = 2, but it is not limited thereto. That is, n does not limit the number of bank groups and the number of banks in each bank group, and it is sufficient that n is 2 or more and less than or equal to the number of bank groups and is a power of 2.

[0048] Next, the ACT request generation circuit 401 determines whether the n access destination memory banks include a memory bank in the all - page - closed state (step S501). If it is determined that there is no access destination memory bank in the all - page - closed state (No in step S501), the ACT request generation circuit 401 does not generate an ACT command issue request (step S502). On the other hand, if it is determined that there is an access destination memory bank in the all - page - closed state (Yes in step S501), the ACT request generation circuit 401 determines whether the access destination memory banks include a memory bank with the target page open (step S503).

[0049] If it is determined that the access destination memory banks do not include an access destination memory bank with the target page open (No in step S503), the ACT request generation circuit 401 generates an ACT command issue request for the access destination memory bank in the all - page - closed state (step S504). In this case, since the access destination memory banks do not include a memory bank with the target page open, even if the issue of the ACT command is delayed, no redundant gap appears between read or write commands. Therefore, the ACT request generation circuit 401 invalidates the priority ACT flag associated with the generated ACT command issue request so that the ACT request selection circuit 402 does not need to prioritize the notification of this ACT command (step S504). On the other hand, if it is determined that there is an access destination memory bank with the target page open (Yes in step S503), the ACT request generation circuit 401 generates an ACT command issue request for the access destination memory bank in the all - page - closed state (step S505). In this case, the access destination memory banks include a memory bank in a state where the ACT command can be issued (all - page - closed memory bank) and a memory bank in a state where the ACT command does not need to be issued (memory bank with the target page open). The ACT request generation circuit 401 generates an ACT command issue request for the memory bank in a state where the ACT command can be issued. In addition, in this way, if the access destination memory banks include a memory bank with the target page open and a memory bank with the target page not open, and the issue of the ACT command for the memory bank with the target page not open is delayed, a redundant gap appears between read or write commands. For this reason, the ACT request generation circuit 401 validates the priority ACT flag associated with the generated ACT command issue request so that the ACT request selection circuit 402 prioritizes the notification of the issue of the ACT command (step S505).

[0050] Note that when generating a request to issue an ACT command in steps S504 and S505, there may be multiple accessed destination memory banks in a state where all pages are closed. In such a case, the ACT request generation circuit 401 generates a request to issue an ACT command for the memory bank that is accessed first among the multiple accessed destination memory banks. The memory bank that is accessed first can be determined, for example, based on the target memory bank group and the target memory bank of the entry data 200. More specifically, when the number of memory access request addresses increases sequentially, the memory bank that is accessed first is determined based on the change order of the accessed destination memory banks indicated by the target memory bank group and the target memory bank of the entry data 200. In the present embodiment, for example, n = 2, and the memory bank group address (1) is used to alternately access the memory bank groups. Therefore, for example, when the target memory bank group of the entry data 200 is "10" and the target memory bank is "11", the memory bank that is accessed first is specified in the following order of (1) and (2).

[0051] (1) Memory bank "11" of memory bank group "10"

[0052] (2) Memory bank "11" of memory bank group "00"

[0053] The ACT request selection circuit 402 selects one request to issue an ACT command from the requests to issue ACT commands generated by the ACT request generation circuit 401, and outputs the selected request to issue an ACT command as an ACT command to the command selector 105. When multiple requests to issue ACT commands are generated simultaneously, the ACT request selection circuit 402 preferentially selects a request to issue an ACT command for which the priority ACT flag is valid. If there are multiple requests to issue ACT commands for which the priority ACT flag is valid, the ACT request selection circuit 402 selects, from the multiple requests to issue ACT commands, a request to issue an ACT command for the memory access request that was first held in the access hold circuit 101. As described above, the entries are held in the access hold circuit 101 in the order in which they are held by entry, and the memory access request that was first held can be easily determined.

[0054] Using the above ACT command issuing control performed by the ACT request generation circuit 401 and the ACT request selection circuit 402, the ACT command for a memory access request is issued in a centralized manner. For example, when the number of memory banks accessed sequentially according to the memory access request is two, there is a need to issue two ACT commands to two different memory bank groups. Using the above ACT command issuing control, issuing an ACT command to another memory bank group is blocked between the issuance of the first ACT command and the second ACT command in response to the memory access request. Therefore, the occurrence of redundant gaps caused by the interval between the first ACT command and the second ACT command can be suppressed, and the memory usage efficiency is improved.

[0055] In addition, the PRE request generation circuit 403 and the PRE request selection circuit 404 preferentially issue a page control command (PRE command) for a memory access request whose open or closed state of pages of multiple destination memory banks satisfies a predetermined condition. The PRE request generation circuit 403 generates a PRE command issuance request for each memory access request in the memory access requests held in the access holding circuit 101 based on the memory bank state provided from the memory bank state management circuit 104. In addition, the PRE request generation circuit 403 determines whether the generated PRE command issuance request is preferentially selected by the PRE request selection circuit 404 based on the memory bank state of the destination of the memory access request, and generates a priority PRE flag indicating the determination result. Figure 6 is a flowchart showing the generation process of the PRE command issuance request according to the present embodiment. The operation of the PRE request generation circuit 403 will be described in detail below with reference to Figure 6 the flowchart in. Note that for each cycle of memory access, the generation process of the PRE command issuance request is executed for each memory access request in the memory access requests held in the access holding circuit 101.

[0056] The PRE request generation circuit 403 specifies the access destination memory bank of the memory access request based on the target memory bank group and target memory bank of the memory access request, the remaining number of read or write commands, and the number n of memory banks accessed sequentially according to the memory access request (step S600). The method for specifying the access destination memory bank is the same as the above generation process of the ACT command issuance request ( Figure 5 ).

[0057] The PRE request generation circuit 403 determines whether the access destination memory bank includes a memory bank in which a page other than the target page is open (step S601). If it is determined that there is no access destination memory bank in which a page other than the target page is open (No in step S601), the PRE request generation circuit 403 does not generate a request to issue a PRE command (step S602). If it is determined that there is an access destination memory bank in which a page other than the target page is open (Yes in step S602), the PRE request generation circuit 403 determines whether there is an access destination memory bank in a state where all pages are closed or whether there is an access destination memory bank in a state where the target page is open (step S603).

[0058] If it is determined that there is no access destination memory bank in which all pages are closed and there is no access destination memory bank in which the target page is open (No in step S603), the PRE request generation circuit 403 generates a request to issue a PRE command. In this case, even when the issuance of the PRE command is delayed, no redundant gap appears between read or write commands. For this reason, in order to execute the issuance of the PRE command without the need for notification to be prioritized by the PRE request selection circuit 404, the priority PRE flag related to the PRE command issuance request is invalidated (step S604). On the other hand, if there is an access destination memory bank in a state where all pages are closed, or there is an access destination memory bank in a state where the target page is open (Yes in step S603), the PRE request generation circuit 403 generates a request to issue a PRE command (step S605). In this case, the access destination memory bank includes a memory bank for which a PRE command needs to be issued (a memory bank in which a page other than the target page is open) and a memory bank for which a PRE command does not need to be issued (a memory bank in which all pages are closed and a memory bank in which the target page is open). The PRE request generation circuit 403 generates a request to issue a PRE command for the memory bank for which a PRE command needs to be issued. Further, in the case where the access destination memory bank includes a memory bank that requires a PRE command and a memory bank that does not require a PRE command in this way, and the issuance of the PRE command for the memory bank that requires a PRE command is delayed, a redundant gap appears between read or write commands. For this reason, the PRE request generation circuit 403 enables the priority PRE flag related to the PRE command issuance request to notify the PRE request selection circuit 404 that the PRE command issuance request is prioritized (step S605).

[0059] Note that when a request to issue a PRE command is generated in steps S604 and S605, and a page other than the target page is open in multiple memory banks among the access destination memory banks, a request to issue a PRE command for the memory bank that is accessed first among these memory banks is generated. The descriptions of steps S504 and S505 apply to the memory bank that is accessed first.

[0060] The PRE request selection circuit 404 selects one PRE command issue request from the PRE command issue requests generated by the PRE request generation circuit 403, and outputs the selected request as a PRE command to the command selector 105. When multiple PRE command issue requests are generated simultaneously, the PRE request selection circuit 404 preferentially selects the PRE command issue request for which the priority PRE flag is valid. If there are multiple PRE command issue requests for which the priority PRE flag is valid, the PRE request selection circuit 404 selects, among the multiple PRE command issue requests, the PRE command issue request for the memory access request that was stored in the access hold circuit 101 first.

[0061] Using the above PRE command issue control performed by the PRE request generation circuit 403 and the PRE request selection circuit 404, the PRE commands required to issue an ACT command for one memory access request are issued in a centralized manner. For example, when the number of memory banks accessed sequentially according to a memory access request is two, it is necessary to put the two memory banks into the closed state. Using the above PRE command issue control, the PRE commands for putting the two memory banks into the closed state are issued in a centralized manner. Therefore, the first ACT command and the second ACT command can be continuously issued for a memory access request, and the occurrence of redundant gaps caused by the intervals between these ACT commands can be suppressed, and the memory usage efficiency is improved.

[0062] As described above, according to the first embodiment, in the case where adjacent read or write commands obtained by dividing one memory access request are issued to memory banks in different memory bank groups, the page control of the memory banks that are the access destinations of the read or write commands is performed in a centralized manner. For this reason, a decrease in memory usage efficiency can be suppressed.

[0063] Second Embodiment

[0064] The second embodiment solves the problem of a decrease in memory usage efficiency caused by selecting a memory access request for a memory bank group that is performing prefetching and thus suspending the issue of read or write commands. Figure 7 is a block diagram showing a configuration example of the memory controller 100a according to the second embodiment. Compared with the first embodiment / ( Figure 1Components similar to the components of ( ) are given the same reference numerals. The read and write control circuit 102a according to the second embodiment uses the command issuance state input from the command selector 105 to determine whether prefetching is being performed in each bank group, and operates so as not to select a memory access request that needs to wait for the completion of prefetching. Therefore, a situation where a memory access request to a bank group in which prefetching is being performed is selected is avoided, and a decrease in memory usage efficiency is prevented.

[0065] Figure 8 is a block diagram showing a configuration example of the read and write control circuit 102a according to the second embodiment. The read and write control circuit 102a includes a page open determination circuit 801, a priority access type determination circuit 802, a bank group prefetch determination circuit (hereinafter, prefetch determination circuit 803), a memory access request selection circuit 804, and timers 805 to 808. The timers 805 to 808 correspond to bank groups 0 to 3 of the DRAM 110.

[0066] The page open determination circuit 801 determines, based on the bank state, whether the target page is open in the target bank of the target bank group for each memory access request among the memory access requests stored in the access hold circuit 101. Then, the page open determination circuit 801 outputs only the memory access requests for which the target page is open among the memory access requests stored in the access hold circuit 101 to the priority access type determination circuit 802, and masks the other memory access requests.

[0067] The priority access type determination circuit 802 determines whether the access type of each memory access request among the memory access requests output by the page open determination circuit 801 is a priority access type. The priority access type is generated by the priority access type determination circuit 802 based on the memory access requests stored in the access hold circuit 101 and the bank state, and indicates whether a read command or a write command is to be issued preferentially. The priority access type determination circuit 802 outputs only the memory access requests corresponding to the priority access type to the prefetch determination circuit 803, and masks the other memory access requests.

[0068] Figure 9 is a flowchart showing an example of the determination process of the priority access type executed by the priority access type determination circuit 802. The priority access type determination circuit 802 determines the priority access type according to this flowchart for each cycle. In addition, when there is no memory access request in the access hold circuit 101, the priority access type is set to "read".

[0069] In steps S901 to S903, the priority access type determination circuit 802 determines whether the access hold circuit 101 holds a memory access request for a read or write operation. If there is no memory access request for a read or write operation (No in step S901), the priority access type determination circuit 802 sets the priority access type to "read" (step S912). Further, in the case where the access hold circuit 101 holds only a memory access request for a read operation (Yes in steps S901 and S902), the priority access type determination circuit 802 also sets the priority access type to "read" (step S912). On the other hand, when the access hold circuit 101 holds only a memory access request for a write operation (Yes in step S903), the priority access type determination circuit 802 sets the priority access type to "write" (step S911).

[0070] If the access hold circuit 101 holds memory access requests for both read and write operations (No in step S903), the priority access type determination circuit 802 determines whether the current priority access type is "read" or "write" (step S904). Note that the current priority access type is the access type (read or write) determined to be the priority in the previous cycle. If the current priority access type is "read" (Yes in step S904), a determination is made as to whether there is a memory access request indicating the same as the indication of the priority access type (here, "read") and for which the target page has been opened (step S905). On the other hand, if the priority access type is "write" (No in step S904), a determination is made as to whether there is a memory access request indicating the same as the indication of the priority access type (here, "write") and for which the target page has been opened (step S906). If there is such a memory access request (Yes in step S905 or step S906), the priority access type is not changed (steps S907 and S909). On the other hand, if there is no such memory access request (No in step S905 or S906), the priority access type is changed (steps S908 and S910). In this way, the priority access type is determined.

[0071] If the command issue status output from the command selector 105 indicates the issue of a read or write command to bank group 0, the timer 805 sets a time period during which a read or write command cannot be issued to the same bank group due to the prefetch operation. During a time period other than the set time, the value of the timer 805 decreases with time, and the timer 805 stops at 0. The timers 806 to 808 operate in a similar manner with respect to their corresponding bank groups 1 to 3, respectively.

[0072] For each memory access request in the memory access requests output by the priority access type determination circuit 802, the prefetch determination circuit 803 determines whether it is necessary to wait for the completion of the prefetch of the target bank group. Whether it is necessary to wait for the completion of the prefetch of the target bank group is determined based on whether the values of the timers 805 to 808 corresponding to the target bank group of the memory access request are other than 0. The prefetch determination circuit 803 outputs only the memory access requests that do not need to wait for the completion of the prefetch of the target bank group to the memory access request selection circuit 804, and masks the memory access requests that need to wait for the completion of the prefetch of the target bank group.

[0073] The memory access request selection circuit 804 selects any suitable memory access request from the memory access requests output by the prefetch determination circuit 803. Then, a read command or a write command for the selected memory access request is generated and output to the command selector 105.

[0074] As described above, according to the second embodiment, it is possible to suppress a decrease in memory usage efficiency by not selecting memory access requests that need to wait for the completion of the prefetch of the bank group.

[0075] As described above, by using the memory controller according to the present disclosure, in the case of issuing adjacent read or write commands from one memory access request to banks of different bank groups, page control of the destination banks of the read or write commands is performed in a centralized manner. For this reason, a decrease in the memory usage efficiency of the DRAM is prevented. In addition, the memory controller according to the present disclosure can be used in various memory controllers that are connected to the DRAM, select any suitable memory access request from a plurality of memory access requests, and issue commands.

[0076] Some embodiments of the present disclosure are not limited to the above embodiments, and various changes and modifications can be made within the spirit and scope of the present disclosure. Therefore, in order to inform the public of the scope of the present disclosure, the following claims are proposed.

[0077] Other embodiments

[0078] One or more embodiments of the present invention can also be implemented by a computer of a system or device that reads and executes computer-executable instructions (e.g., one or more programs) recorded on a storage medium (which may also be more fully referred to as a "non-transitory computer-readable storage medium") to perform the functions of one or more of the above-described embodiments and / or includes one or more circuits (e.g., an application specific integrated circuit (ASIC)) for performing the functions of one or more of the above-described embodiments, and can be implemented by a method executed by a computer of the system or device, for example, by reading and executing computer-executable instructions from the storage medium to perform the functions of one or more of the above-described embodiments and / or controlling one or more circuits to perform the functions of one or more of the above-described embodiments. The computer may include one or more processors (e.g., a central processing unit (CPU), a microprocessing unit (MPU)), and may include a network of separate computers or separate processors to read and execute the computer-executable instructions. The computer-executable instructions may be provided to the computer, for example, from a network or a storage medium. The storage medium may include, for example, one or more of a hard disk, a random access memory (RAM), a read only memory (ROM), a storage device of a distributed computing system, an optical disk (such as a compact disk (CD), a digital versatile disk (DVD) or a Blu-ray disk (BD) TM ), a flash device, a memory card, etc.

[0079] Other embodiments

[0080] Embodiments of the present invention can also be implemented by the following method, that is, by providing software (program) that performs the functions of the above-described embodiments to a system or device through a network or various storage media, and the method by which a computer or a central processing unit (CPU), a microprocessing unit (MPU) of the system or device reads and executes the program.

[0081] Although the present disclosure has been described with reference to exemplary embodiments, it is to be understood that some embodiments are not limited to the disclosed exemplary embodiments. The scope of the appended claims should be given the broadest interpretation to encompass all such modifications as well as equivalent structures and functions.

Claims

1. A memory controller, the memory controller being connectable to a memory including a plurality of memory bank groups, each memory bank group including a plurality of memory banks, the memory controller comprising: a holding circuit configured to hold a plurality of access requests to the memory; a read and write control circuit configured to generate a read or write command from each of the plurality of access requests such that memory banks in different memory bank groups are set as destinations of adjacent read or write commands; as well as a page control circuit configured to issue a page control command for an access request selected from the plurality of access requests, wherein The page control circuit preferentially issues a page control command for an access request for which an open or closed state of pages of a plurality of memory banks set as destinations satisfies a predetermined condition.

2. The memory controller according to claim 1, wherein The page control circuit preferentially issues a page control command for an access request including, as a destination, a memory bank in a state where the page control command can be issued and a memory bank in a state where the page control command does not need to be issued.

3. The memory controller according to claim 2, wherein The page control command is an activation command. The memory bank in the state where the page control command can be issued is a memory bank with all pages closed, and The memory bank in the state where the page control command does not need to be issued is a memory bank opened from the target page of the read or write command generated from the access request.

4. The memory controller according to claim 1, wherein The page control circuit preferentially issues a page control command for an access request including a memory bank in a state where the page control command needs to be issued and a memory bank in a state where the page control command does not need to be issued as a destination.

5. The memory controller according to claim 4, wherein The page control command is a precharge command, The memory bank in the state where the page control command needs to be issued is a memory bank with a page opened that is different from the target page of the read or write command generated from the access request, and The memory bank in a state where the page control command does not need to be issued is a memory bank in which a page different from the target page is not opened.

6. The memory controller according to claim 1, wherein In a case where there are a plurality of page control commands generated from one access request in which the states of a plurality of destination memory banks satisfy the predetermined condition, the page control circuit preferentially issues the page control command to a memory bank that is accessed first among the plurality of memory banks.

7. The memory controller according to claim 1, wherein In a case where there are two or more access requests whose states of a plurality of destination memory banks satisfy the predetermined condition, the page control circuit preferentially issues a page control command generated from an access request first held in the holding circuit among the plurality of access requests.

8. The memory controller according to claim 1, wherein The read and write control circuit generates a read or write command for an access request selected from remaining access requests obtained by removing access requests including a memory bank group for which prefetching is being performed as a destination from the plurality of access requests.

9. The memory controller according to claim 1, wherein The read and write control circuit determines whether a read command or a write command is issued preferentially based on access types of the plurality of access requests and states of destination memory banks of the plurality of access requests.

10. A method for controlling a memory controller, wherein the memory controller is connectable to a memory including a plurality of memory bank groups, each memory bank group including a plurality of memory banks, the method comprising: holding a plurality of access requests to the memory in a holding circuit; performing read and write control to generate a read or write command from each of the plurality of access requests so that memory banks in different memory bank groups are set as destinations of adjacent read or write commands; as well as performing page control to issue a page control command for an access request selected from the plurality of access requests, wherein In the page control, a page control command for an access request for which an open or closed state of pages of a plurality of memory banks set as destinations satisfies a predetermined condition is preferentially issued.

11. A memory device comprising: A memory, wherein the memory includes a plurality of memory bank groups, each memory bank group includes a plurality of memory banks; as well as a controller, the controller being connectable to the memory, wherein the controller comprises: a holding circuit configured to hold a plurality of access requests to the memory; a read and write control circuit configured to generate a read or write command from each of the plurality of access requests such that memory banks in different memory bank groups are set as destinations of adjacent read or write commands; and a page control circuit configured to issue a page control command for an access request selected from the plurality of access requests, wherein The page control circuit preferentially issues a page control command for an access request for which an open or closed state of pages of a plurality of memory banks set as destinations satisfies a predetermined condition.

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