Smooth RTT transitions

Abstract

The invention relates to smoothing RTT transitions. Systems and methods are provided for performing a "smooth RTT transition" to avoid undesired fluctuations in termination resistance RTT values (e.g., undesired values during skew). In one embodiment, an RTT control signal (e.g., RTTPARK, RTTWR, RTTNOMWR, RTTNOMRD) is converted from a binary code to a unary code, and a resistive driver is enabled / disabled based on the unary code to provide a corresponding termination resistance of the RTT control signal. There is no undesired value that occurs during a transition of the termination resistance from one value to another. Thus, noise on a transmission line (e.g., connecting a memory device to a host device) caused by undesired fluctuations is reduced / avoided.

Description

Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 609,083, filed on December 12, 2023, which is hereby incorporated by reference in its entirety. Field of the Invention

[0003] This disclosure generally relates to the field of semiconductor memory devices. More specifically, embodiments of this disclosure relate to transitions of the termination resistance (RTT) in memory devices. Background Art

[0004] An impedance (ZQ) calibration signal can be used in a memory device to tune an output driver and on-die termination (ODT) values by adjusting the pull-up and pull-down resistors of the memory device over changes in process, voltage, and temperature (PVT) values. The ODT can be dynamically changed by using an RTT control signal (e.g., RTT_WR). Separate RTTs can be allowed for various operations. For example, the RTT control signal can include RTT_WR, RTT_NOM_WR, RTT_NOM_RD, and RTT-PARK for WR, NT_WR, NT_RD, and other states, respectively. The RTT control signal can have different RTT values corresponding to different settings of the driver circuit. Since the RTT changes in combination with the command input, a transition occurs between RTT_PARK and other RTTs (e.g., RTT_WR, RTT_NOM_WR, RTT_NOM_RD). However, an undesired fluctuation of the RTT value (e.g., an unexpected value during skew) may occur when transitioning from one value of the RTT to another value, which can cause noise (e.g., on the transmission line connecting the memory device to the host device).

[0005] Summary of the Invention

[0006] An embodiment of this disclosure provides an apparatus, including: an I / O pin coupled to an output driver, the termination resistance of the output driver being adjustable; and a termination resistance control circuit configured to transition the termination resistance from a first value to a second value by: converting a second control signal corresponding to the second value into a unary code; and applying the second control signal of the unary code to the transition of the termination resistance from the first value to the second value.

[0007] ​Another embodiment of the present disclosure provides a method, which includes: receiving a control signal corresponding to a terminal resistance value; converting the control signal into a unary code; and adjusting one or more driver circuits based on the unary code to generate the terminal resistance value, wherein the one or more driver circuits are connected to the I / O pins of a device.

[0008] Yet another embodiment of the present disclosure provides a terminal resistance control circuit, which includes: a decoder configured to receive a plurality of control signals and convert the plurality of control signals into corresponding unary codes; a plurality of selection devices configured to select a specific control signal from the plurality of control signals based on a selection signal and output the unary code of the specific control signal, wherein the specific control signal corresponds to a specific terminal resistance value; and an output driver, the terminal resistance of which is adjustable, wherein the output driver is configured to provide the specific terminal resistance value based on the unary code. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Aspects of the present disclosure may be better understood after reading the following detailed description and with reference to the drawings, in which:

[0010] Figure 1 is a simplified block diagram showing certain features of a memory device according to an embodiment of the present disclosure;

[0011] Figure 2 is a plot showing the transition of RTT according to an embodiment of the present disclosure;

[0012] Figure 3 shows according to an embodiment of the present disclosure Figure 1 a block diagram of an embodiment of a part of the RTT control circuit of a memory device; and

[0013] Figure 4 is a flowchart of a method for implementing Figure 3 the RTT control circuit according to an embodiment of the present disclosure to obtain an RTT value. DETAILED DESCRIPTION

[0014] One or more specific embodiments will be described below. To provide a brief description of these embodiments, not all features of actual implementations will be described in this specification. It should be understood that in the development of any such actual implementation, as in any engineering or design project, many implementation-specific decisions must be made to achieve the specific goals of the developer, such as consistency with system-related and enterprise-related constraints, which may vary from one implementation to another. In addition, it should be understood that such development efforts may be complex and time-consuming, yet will be routine for those of ordinary skill in the art who will benefit from the present disclosure in the design, construction, and manufacture.

[0015] As previously mentioned, the undesirable fluctuations in the RTT value that may occur during a transition from one value of the RTT to another value (e.g., unexpected values during skew) can cause noise (e.g., on the transmission line connecting the memory device to the host device). Thus, it is desirable to avoid the undesirable fluctuations in the RTT value during a transition of the RTT value.

[0016] The present disclosure herein provides systems and methods for performing a "smooth RTT transition" to avoid undesirable fluctuations in the termination resistance (RTT) value (e.g., unexpected values during skew). The RTT control signals (e.g., RTT_PARK, RTT_WR, RTT_NOM_WR, RTT_NOM_RD) can be converted from binary code to unary code, and the driver circuits can be enabled / disabled based on the unary code to provide the corresponding RTT value of the RTT control signal. There may be no undesirable RTT values during a transition of the RTT from a first value to a second value. Thus, the noise on the transmission line (e.g., connecting the memory device to the host device) caused by the undesirable fluctuations can be reduced / avoided.

[0017] Turning now to the figures, Figure 1 is a simplified block diagram showing certain features of the memory device 10. Specifically, Figure 1 the block diagram is a functional block diagram showing certain functionality of the memory device 10. According to one embodiment, the memory device 10 can be a double data rate type five synchronous dynamic random access memory (DDR5 SDRAM) device. Compared with previous generations of DDR SDRAM, the various features of DDR5 SDRAM result in reduced power consumption, more bandwidth, and more storage capacity.

[0018] The memory device 10 can include a plurality of memory bank groups 12. The memory bank groups 12 can be, for example, DDR5 SDRAM memory bank groups. The memory bank groups 12 can be provided on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMM). Each DIMM can include several SDRAM memory chips (e.g., x8 or x16 memory chips), as will be appreciated. Each SDRAM memory chip can include one or more memory bank groups 12. For DDR5, the memory bank groups 12 can be further arranged to form bank group clusters. For example, for an 8-gigabit (Gb) DDR5 SDRAM, the memory chip can include 16 memory bank groups 12, arranged in 8 bank group clusters, each bank group cluster including 2 memory bank groups. For a 16-Gb DDR5 SDRAM, the memory chip can, for example, include 32 memory bank groups 12, arranged in 8 bank group clusters, each bank group cluster including 4 memory bank groups. Depending on the application and design of the overall system, various other configurations, organizations, and sizes of the memory bank groups 12 on the memory device 10 can be utilized.

[0019] The memory device 10 may include a command interface 14 and an input / output (I / O) interface 16 configured to exchange (e.g., receive and transmit) signals with an external device. The command interface 14 is configured to receive a number of signals (e.g., signal 15) from an external device such as a processor or a controller (not shown). The processor or controller may provide various signals 15 to the memory device 10 to facilitate the transfer and reception of data to be written to or read from the memory device 10.

[0020] As will be appreciated, the command interface 14 may include several circuits, such as a clock input circuit 18 and a command / address input circuit 20, to ensure, for example, proper handling of the signal 15. The command interface 14 may receive one or more clock signals from an external device. Generally, a double data rate (DDR) memory utilizes a differential pair of system clock signals, herein referred to as a true clock signal (Clk_t) and a complementary clock signal (Clk_c). The positive clock edge of DDR refers to the point where the rising true clock signal Clk_t crosses the falling complementary clock signal Clk_c, while the negative clock edge indicates the transition of the falling true clock signal Clk_t and the rising of the complementary clock signal Clk_c. Commands (e.g., read commands, write commands, etc.) are typically input on the positive edge of the clock signal, and data is transmitted or received on both the positive and negative clock edges.

[0021] The clock input circuit 18 receives the true clock signal (Clk_t) and the complementary clock signal (Clk_c) and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator 30, such as a delay locked loop (DLL) circuit. The internal clock generator 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase-controlled internal clock signal LCLK is supplied to, for example, the I / O interface 16 and is used as a timing signal for determining the output timing of the read data.

[0022] The internal clock signal CLK may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For example, the internal clock signal CLK may be provided to a command decoder 32. The command decoder 32 may receive command signals from a command bus 34 and may decode the command signals to provide various internal commands. For example, the command decoder 32 may provide command signals to the internal clock generator 30 via a bus 36 to coordinate the generation of the phase-controlled internal clock signal LCLK. The command decoder 32 may also provide command signals to the I / O interface 16 via a bus 37 to facilitate the reception and transmission of I / O signals. The phase-controlled internal clock signal LCLK may be used to time data, for example, through the I / O interface 16.

[0023] In addition, the command decoder 32 can decode commands received from the command bus 34, such as read commands, write commands, mode register set commands, activation commands, etc., and provide access to a specific memory bank 12 corresponding to the command via the bus path 40. As will be appreciated, the memory device 10 can include various other decoders, such as a row decoder and a column decoder, to facilitate access to the memory bank 12. In one embodiment, each memory bank 12 includes a bank control block 22 that provides the necessary decoding (e.g., row decoder and column decoder) and other features such as timing control and data control to facilitate the execution of commands to and from the memory bank 12. A group of memory banks 12 can be included in the memory chip 23, and the memory device 10 can include one or more memory chips.

[0024] The memory device 10 performs operations such as read commands and write commands based on command / address signals received from an external device such as a processor. In one embodiment, the command / address bus can be a 14-bit bus for accommodating command / address signals (CA<13:0>). The command / address signals are clocked into the command interface 14 using clock signals (Clk_t and Clk_c). The command / address input circuit 20 in the command interface 14 can be configured to receive and transmit commands, for example, through the command decoder 32, to provide access to the memory bank 12. Additionally, the command interface 14 can receive a chip select signal (CS_n). The chip select signal CS_n enables the memory device 10 to process commands on the incoming command / address signals CA<13:0> for the memory chip selected by the chip select signal CS_n. Thus, access to a specific bank 12 within the memory device 10 is facilitated by the information encoded on the chip select signal CS_n and the command / address signals CA<13:0>.

[0025] In addition, the command interface 14 can be configured to receive several other command signals. For example, a command / address on-die termination (CA_ODT) signal can be provided to facilitate proper impedance matching within the memory device 10. A reset command (RESET_n) can be used to, for example, reset the command interface 14, status register, state machine, and the like during power-up. The command interface 14 can also receive a command / address inversion (CAI) signal, which can be provided to invert the state of the command / address signals CA<13:0> on the command / address bus, for example, depending on the command / address routing of a particular memory device 10. A mirror (MIR) signal can also be provided to facilitate the mirroring function. Based on the configuration of multiple memory devices in a particular application, the MIR signal can be used to multiplex signals such that they can be swapped for certain routing of signals to the memory device 10. Various signals can also be provided to facilitate testing of the memory device 10, such as a test enable (TEN) signal. For example, the TEN signal can be used to place the memory device 10 in a test mode for connectivity testing.

[0026] The command interface 14 can also be used to provide an alert signal (ALERT_n) to the system processor or controller for certain detectable errors. For example, the alert signal (ALERT_n) can be transmitted from the memory device 10 in the event of a detected cyclic redundancy check (CRC) error. Other alert signals can also be generated. In addition, the bus and pin used to transmit the alert signal (ALERT_n) from the memory device 10 can be used as input pins during certain operations, such as the connectivity test mode performed using the TEN signal as described above.

[0027] Using the commands and timing signals discussed above, data can be sent to and from the memory device 10 by transmitting and receiving data signals 44 via the I / O interface 16. More specifically, data can be sent to or retrieved from the memory bank group 12 via a data bus 46 that includes multiple bidirectional data buses. Data I / O signals, commonly referred to as DQ signals, are typically transmitted and received in one or more bidirectional data buses. For certain memory devices, such as DDR5 SDRAM memory devices, the I / O signals can be divided into upper and lower bytes. For example, for a x16 memory device, the I / O signals can be divided into upper and lower I / O signals (e.g., DQ<15:8> and DQ<7:0>) corresponding to the upper and lower bytes of the data signals, respectively.

[0028] To allow for higher data rates within the memory device 10, certain memory devices, such as DDR memory devices, may utilize a data strobe signal, commonly referred to as the DQS signal. The DQS signal is driven by an external processor or controller that transmits data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For a read command, the DQS signal is effectively an additional data output (DQ) signal with a predetermined pattern. For a write command, the DQS signal is used as a clock signal to capture the corresponding input data. As with the clock signals (Clk_t and Clk_c), a data strobe (DQS) signal may be provided as a differential pair (DQS_t and DQS_c) of data strobe signals to provide differential pair signaling during reads and writes. For certain memory devices, such as DDR5 SDRAM memory devices, the differential pair of DQS signals may be split into an upper data strobe signal and a lower data strobe signal (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c), which correspond to the upper and lower bytes of data, respectively, sent to and from the memory device 10.

[0029] The impedance (ZQ) calibration signal can also be provided to the memory device 10 through the I / O interface 16. The ZQ calibration signal can be provided to a reference pin and is used to tune the output driver and on-die termination (ODT) values by adjusting the pull-up and pull-down resistors of the memory device 10 across process, voltage, and temperature (PVT) value changes. Since the PVT characteristics may affect the ZQ resistor value, the ZQ calibration signal can be provided to the ZQ reference pin for adjusting the resistance to calibrate the input impedance to a known value. As should be understood, a precision resistor is typically coupled between the ZQ pin on the memory device 10 and GND / VSS external to the memory device 10. This resistor serves as a reference for adjusting the drive strength of the internal ODT and data I / O pins (DQ pins). According to various embodiments of the present disclosure, the effective termination resistance (RTT) of the ODT can be adjusted by adjusting the output impedance of one or more driver circuits in the RTT control circuit 50. The ODT can be dynamically changed by using an RTT control signal (e.g., RTT_WR). Separate RTTs can be allowed for various operations. For example, the RTT control signal can include RTT_WR, RTT_NOM_WR, RTT_NOM_RD, and RTT-PARK for WR, NT_WR, NT_RD, and other states, respectively. The RTT control signal can have different values corresponding to different settings of the driver circuits in the RTT control circuit 50, which can be defined by mode register bits, as described in detail herein. Since the RTT changes in conjunction with the command input, a transition occurs between RTT_PARK and other RTTs (e.g., RTT_WR, RTT_NOM_WR, RTT_NOM_RD), and the transition timing is tADC. To reduce / avoid noise on the transmission line (e.g., connecting the memory device 10 to the host device) caused by undesired fluctuations in the RTT value (e.g., unexpected values during skew) that may occur when transitioning from one value of the RTT to another value, it is desirable to constrain the RTT value within a range between the start value and the end value of the transition during the transition, as described in detail herein.

[0030] In addition, a loopback signal (LOOPBACK) can be provided to the memory device 10 through the I / O interface 16. The loopback signal can be used during testing, debugging phases, or training phases to set the memory device 10 into a mode in which the signal is looped back through the memory device 10. For example, the loopback signal can be used to set the memory device 10 to test the data input of the memory device 10. The loopback can include both data and strobe or may include only the data pins. This is generally intended to monitor the data captured by the memory device 10 at the I / O interface 16.

[0031] As will be appreciated, various other components such as a power supply circuit (for receiving external VDD and VSS signals), a mode register (for defining various modes of programmable operations and configurations), a read / write amplifier (for amplifying signals during read / write operations), a temperature sensor (for sensing the temperature of the memory device 10), etc. may also be incorporated into the memory device 10. Thus, it should be understood that only the Figure 1 block diagram is provided to highlight certain functional features of the memory device 10 to assist in the subsequent detailed description.

[0032] In some embodiments, the memory device 10 may be disposed within a host device (physically integrated into the host device or otherwise connected to the host device) or otherwise coupled to the host device. The host device may include any one of a desktop computer, a laptop computer, a pager, a cellular phone, a personal organizer, a portable audio player, a control circuit, a camera, etc. The host device may also be a network node, such as a router, a server, or a client (e.g., one of the types of computers previously described). The host device may be some other kind of electronic device, such as a copier, a scanner, a printer, a game console, a television, a set-top box video distribution or recording system, a cable box, a personal digital media player, a factory automation system, an automotive computer system, or a medical device. (The terms used to describe these various examples of systems, such as many other terms used herein, may share some referents and thus should not be interpreted solely by the other items listed.)

[0033] The host device may thus be a processor-based device that may include a processor, such as a microprocessor, that controls system functions and processing of requests in the host. Additionally, any host processor may include multiple processors that share system control. The host processor may be directly or indirectly coupled to additional system elements of the host such that the host processor controls the operation of the host by executing instructions that may be stored within or external to the host.

[0034] As discussed above, data can be written to and read from the memory device 10 by a host, for example, such that the memory device 10 acts as a volatile memory, such as a double data rate DRAM (e.g., DDR5 SDRAM). In some embodiments, the host may also include separate non-volatile memories, such as read only memory (ROM), PC-RAM, silicon-oxide-nitride-oxide-silicon (SONOS) memory, metal-oxide-nitride-oxide-silicon (MONOS) memory, polysilicon floating gate-based memory, and / or other types of flash memory of various architectures (e.g., NAND memory, NOR memory, etc.), as well as other types of memory devices (e.g., storage devices), such as solid state drives (SSD), multimedia media cards (MMC), secure digital (SD) cards, compact flash (CF) cards, or any other suitable device. Additionally, it should be understood that the host may include one or more external interfaces, such as universal serial bus (USB), peripheral component interconnect (PCI), PCI express (PCI-E), small computer system interface (SCSI), IEEE 1394 (FireWire), or any other suitable interface, as well as one or more input devices for allowing a user to input data into the host, such as buttons, switch elements, keyboards, light pens, styli, mice, and / or voice recognition systems. The host may optionally also include an output device, such as a display coupled to a processor, and a network interface device for interfacing with a network, such as the Internet, such as a network interface card (NIC). As will be appreciated, depending on the application of the host, the host may include many other components.

[0035] As discussed above, undesirable fluctuations in the RTT may cause noise on the transmission line connecting the memory device 10 to the host device. Thus, when transitioning from one value of the RTT to another value, the RTT value during the transition can be constrained to a value between the start value and the end value of the transition to avoid undesirable fluctuations in the RTT value (e.g., unexpected values during skew). The RTT control signal can have different values corresponding to different settings of the driver circuit in the RTT control circuit 50. An embodiment of the RTT control signal defined by mode register bits is shown in Table 1.

[0036] Table 1

[0037]

[0038]

[0039] As shown in Table 1, the value for each RTT control signal can be defined by three digits corresponding to eight values of a mode register (e.g., MR34, MR35). For example, RTT_PARK is defined by MR34:OP[2:0], RTT_WR is defined by MR34:OP[5:3], RTT_NOM_WR is defined by MR35:OP[2:0], and RTT_NOM_RD is defined by MR35:OP[5:3]. Each RTT control signal can have eight RTT values corresponding to eight binary codes of the three corresponding digits. For example, when the binary code is 000, the corresponding RTT control signal is off; when the binary code is 001, the corresponding RTT value is 240 ohms (Ω); when the binary code is 010, the corresponding RTT value is 120 Ω; when the binary code is 011, the corresponding RTT value is 80 Ω; when the binary code is 100, the corresponding RTT value is 60 Ω; when the binary code is 101, the corresponding RTT value is 48 Ω; when the binary code is 110, the corresponding RTT value is 40 Ω; when the binary code is 111, the corresponding RTT value is 34 Ω. As previously mentioned, to reduce / avoid noise on the transmission line (e.g., connecting the memory device 10 to the host) caused by the undesired fluctuations (e.g., high impedance (HiZ)) of the RTT value that may occur when transitioning from one value of the RTT to another value, the RTT during the transition can be constrained to a value between the start value and the end value of the transition, as Figure 2 shown in. For example, when transitioning the RTT from the value corresponding to the binary code 100 to the value corresponding to the binary code 001, the RTT value changes from 60 Ω to 240 Ω. The RTT value during the transition can be in the range of 60 Ω to 240 Ω (e.g., ≥60 Ω and ≤240 Ω) to reduce / avoid noise on the transmission line (e.g., connecting the memory device 10 to the host) caused by the undesired fluctuations of the RTT.

[0040] Figure 2 is a drawing showing an embodiment of an RTT transition 60 from the value of RA to the value of RB. For example, the transition can start at time t0 when the value of the RTT is RA and end at time t3 when the RTT value is RB. The duration between t3 and t0 is the RTT transition time. In Figure 2In it, Rt corresponds to the terminal resistance during the transition from RA to RB, and it can have a value within the range of RA to RB (e.g., RA ≤ Rt ≤ RB). For example, during the transition from RA to RB, the RTT value can increase from RA to Rt during the time period from t0 to t1, and then increase from Rt to RB during the time period from t2 to t3. The above transition can be called a "smooth RTT transition" because there is no undesired fluctuation in the RTT value (e.g., Rt < RA or Rt > RB). Therefore, during the RTT transition time of the "smooth RTT transition", the RTT will not have a value less than RA or greater than RB. The RTT control circuit 50 can be designed to perform a "smooth RTT transition" so that the RTT value during the transition can be constrained to a value between the start RTT value and the end RTT value of the transition.

[0041] Figure 3An embodiment of a portion of the RTT control circuit 50 of the memory device 10 that can be used to perform a "smooth RTT transition" is shown. As shown, the RTT control circuit 50 can include a decoder 100 to receive mode register bits for the RTT control signals from the corresponding mode registers 70 (e.g., MR34, MR35). For example, bit 72 can correspond to MR34OP0, bit 74 can correspond to MR34OP3, bit 76 can correspond to MR35OP0, bit 78 can correspond to MR35OP3, bit 80 can correspond to MR34OP1, bit 82 can correspond to MR34OP4, bit 84 can correspond to MR35OP1, bit 86 can correspond to MR35OP4, bit 88 can correspond to MR34OP2, bit 90 can correspond to MR34OP5, bit 92 can correspond to MR35OP2, and bit 94 can correspond to MR35OP5. As previously discussed, the values of the RTT control signals (e.g., RTT_PARK, RTT_WR, RTT_NOM_WR, RTT_NOM_RD) can be defined by the binary codes of three corresponding mode register bits. For example, RTT_PARK is defined by MR34:OP[2:0], RTT_WR is defined by MR34:OP[5:3], RTT_NOM_WR is defined by MR35:OP[2:0], and RTT_NOM_RD is defined by MR35:OP[5:3]. Each RTT control signal can have eight values corresponding to eight binary codes of three corresponding digits (e.g., HiZ, 240Ω, 120Ω, 80Ω, 60Ω, 48Ω, 40Ω, 34Ω), as shown in Table 102. For example, when the binary code is 000, the corresponding RTT control signal is off (HiZ); when the binary code is 001, the corresponding RTT value is 240Ω; when the binary code is 010, the corresponding RTT value is 120Ω; when the binary code is 011, the corresponding RTT value is 80Ω; when the binary code is 100, the corresponding RTT value is 60Ω; when the binary code is 101, the corresponding RTT value is 48Ω; when the binary code is 110, the corresponding RTT value is 40Ω; when the binary code is 111, the corresponding RTT value is 34Ω.

[0042] The decoder 100 can be used to convert a three-digit binary code into a corresponding seven-digit unary code to represent eight values corresponding to eight three-digit binary codes (e.g., HiZ, 240Ω, 120Ω, 80Ω, 60Ω, 48Ω, 40Ω, 34Ω), as shown in Table 104. For example, when the three-digit binary code is 000, the corresponding seven-digit unary code is 00000000, and the corresponding RTT control signal is off (HiZ); when the three-digit binary code is 001, the corresponding seven-digit unary code is 0000001, and the corresponding RTT value is 240Ω; when the three-digit binary code is 010, the corresponding seven-digit unary code is 0000011, and the corresponding RTT value is 120Ω; when the three-digit binary code is 011, the corresponding seven-digit unary code is 0000111, and the corresponding RTT value is 80Ω; when the three-digit binary code is 100, the corresponding seven-digit unary code is 0001111, and the corresponding RTT value is 60Ω; when the three-digit binary code is 101, the corresponding seven-digit unary code is 0011111, and the corresponding RTT value is 48Ω; when the three-digit binary code is 110, the corresponding seven-digit unary code is 0111111, and the corresponding RTT value is 40Ω; when the three-digit binary code is 111, the corresponding seven-digit unary code is 1111111, and the corresponding RTT value is 34Ω.

[0043] The decoder 100 can output the seven - bit binary code of each RTT control signal (e.g., RTT_PARK, RTT_WR, RTT_NOM_WR, RTT_NOM_RD) to a selection device (e.g., a multiplexer) for selecting the RTT control signal. In some embodiments, each digit of the seven - bit binary code can be transmitted to a corresponding selection device (e.g., a multiplexer), and the corresponding selection device can receive a selection signal to select the RTT control signal. For example, the first right - most digit of the seven - bit binary code can be transmitted to the selection device 110, the second right - most digit of the seven - bit binary code can be transmitted to the selection device 112, the third right - most digit of the seven - bit binary code can be transmitted to the selection device 114, the fourth right - most digit of the seven - bit binary code can be transmitted to the selection device 116, the fifth right - most digit of the seven - bit binary code can be transmitted to the selection device 118, the sixth right - most digit of the seven - bit binary code can be transmitted to the selection device 120, and the seventh right - most digit of the seven - bit binary code can be transmitted to the selection device 122. Each of the selection devices 110, 112, 114, 116, 118, 120, and 122 can receive a selection signal 124 to select the corresponding digit for the RTT control signal (e.g., RTT_PARK, RTT_WR, RTT_NOM_WR, RTT_NOM_RD), and can transmit the selected digit through outputs 130, 132, 134, 136, 138, 140, and 142 respectively. The selection signal is generated from the WR, WR_NT, and RD_NT commands. Each output of the selection devices 110, 112, 114, 116, 118, 120, and 122 can be used to enable (e.g., when having a value of "1") or disable (e.g., when having a value of "0") the corresponding driver unit 150 of the output driver 151. Each driver unit 150 can include a pre - pre - driver 152 to drive a pre - driver 154, and the pre - driver can be used to drive a resistance driver 156 to obtain a resistance (e.g., 240Ω).

[0044] In some embodiments, the resistance driver 156 may have a drivability of 240 Ω, and the driver units 150 of the output driver 151 may be electrically coupled in parallel to obtain a termination resistance (RTT). The output driver 151 may be electrically coupled to a DQ pad (e.g., a data I / O pin) 160. Thus, when no driver unit 150 is enabled (e.g., corresponding to the one-hot code 0000000), the RTT may have a HiZ state (RTT off); when only one driver unit 150 is enabled (e.g., corresponding to the one-hot code 0000001), the RTT may have a resistance of 240 Ω; when only two driver units 150 are enabled (e.g., corresponding to the one-hot code 0000011), the RTT may have a resistance of 120 Ω (240 Ω / 2); when only three driver units 150 are enabled (e.g., corresponding to the one-hot code 0000111), the RTT may have a resistance of 80 Ω (240 Ω / 3); when only four driver units 150 are enabled (e.g., corresponding to the one-hot code 0001111), the RTT may have a resistance of 60 Ω (240 Ω / 4); when only five driver units 150 are enabled (e.g., corresponding to the one-hot code 0011111), the RTT may have a resistance of 48 Ω (240 Ω / 5); when only six driver units 150 are enabled (e.g., corresponding to the one-hot code 0111111), the RTT may have a resistance of 40 Ω (240 Ω / 6); and when all seven driver units 150 are enabled (e.g., corresponding to the one-hot code 1111111), the RTT may have a resistance of 34 Ω (240 Ω / 7). Thus, the RTT may have 8 values corresponding to the eight one-hot codes in Table 104. Since each one-hot code represents the number of enabled resistance drivers 156, the transition of the RTT from one value to another may involve enabling / disabling a certain number (e.g., 1, 2, 3, 4, 5, 6, 7) of resistance drivers 156. Further, during the transition from one RTT value to another, a certain number of resistance drivers 156 are all enabled or all disabled, such that the RTT may only have a resistance value between the start value and the end value of the transition. Thus, no unexpected value may occur for the RTT value during the transition from one value to another, and the transition of the RTT between values may be a "smooth RTT transition".

[0045] Figure 4A flowchart showing a method 200 for implementing an RTT control circuit 50 to provide an RTT value based on RTT control signals. At block 202, the RTT control circuit 50 may receive a plurality of RTT control signals (e.g., RTT_PARK, RTT_WR, RTT_NOM_WR, RTT_NOM_RD), and the values of the plurality of RTT control signals may be stored in one or more mode registers (e.g., MR34, MR35). At block 204, the RTT control signals may be converted to a one-hot code by a decoder 100. At block 206, an RTT control signal may be selected based on a selection signal 124 by a selection device (e.g., selection devices 110, 112, 114, 116, 118, 120, and 122). At block 208, the corresponding one-hot code of the selected RTT control signal may be transmitted (e.g., via outputs 130, 132, 134, 136, 138, 140, and 142) to a plurality of driver units 150 of an output driver 151. At block 210, one or more driver units 150 may be enabled / disabled based on the corresponding one-hot code to obtain an RTT value corresponding to the one-hot code of the selected RTT control signal. Although the above description of method 200 is described as being performed in a particular order, it should be understood that method 200 may be performed in any suitable order.

[0046] Accordingly, the technical effects of the present disclosure include methods and systems for performing a "smooth RTT transition" to avoid undesired fluctuations in the RTT value (e.g., unexpected values during skew). Although Figure 3 seven selection devices are used in the embodiments shown in Figure 3 other numbers of selection devices may be used in other embodiments. Additionally, in the embodiments shown in Figure 3 the values of all RTT control signals (e.g., RTT_PARK, RTT_WR, RTT_NOM_WR, RTT_NOM_RD) may first be converted from binary code to one-hot code, and then the RTT control signal may be selected. In some embodiments, the RTT control signal may first be selected (e.g., by a selection device), and the corresponding value of the selected RTT control signal may be converted from binary code to one-hot code. Figure 3 the embodiments shown in

[0047] may be beneficial for controlling tADC timing because all RTT control signals are ready (e.g., converted from binary code to one-hot code) when the selection signal 124 is received.

[0047] It should be understood that logically equivalent circuitry may be used to implement the systems and methods described above. For example, a logical exclusive OR gate may be replaced by a logically equivalent combination of a NOT gate, an AND gate, a NAND gate, an OR gate, a NOR gate, or the like.

[0048] While the present disclosure may admit of various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the present disclosure is not intended to be limited to the particular forms disclosed. On the contrary, the present disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present disclosure as defined by the appended claims.

[0049] The technologies presented and claimed herein are referenced and applied to substantial objects and specific instances of a practical nature, which substantially improve the technical field in an arguable manner and are thus not abstract, intangible, or purely theoretical. Additionally, if any claim appended to the end of this specification contains one or more elements expressed as "means for [performing][function]..." or "step for [performing][function]...", then such elements are intended to be construed under 35 U.S.C. 112(f). However, for any claim item containing elements specified in any other manner, it is not intended that such elements be construed in accordance with 35 U.S.C. 112(f).

Claims

1. A device comprising: an I / O pin coupled to an output driver, wherein a termination resistance of the output driver is adjustable; as well as A terminal resistance control circuit is configured to change the terminal resistance from a first value to a second value by: converting a second control signal corresponding to the second value into a unary code; and The second control signal of the unary code is applied to the transition of the terminal resistance from the first value to the second value. 2 . The apparatus of claim 1 , wherein the second control signal comprises at least one of RTT_PARK, RTT_WR, RTT_NOM_WR, or RTT_NOM_RD.

3. The apparatus of claim 1, wherein the terminal resistance is configured to have a predefined value during the transition. The apparatus of claim 1 , wherein the second control signal is converted from a binary code to the unary code.

5. The apparatus of claim 4, wherein the binary code of the second control signal is stored in a mode register. 6 . The apparatus of claim 1 , wherein the termination resistance control circuit comprises a decoder configured to convert the second value into the unary code.

7. The apparatus of claim 1, wherein the output driver comprises a plurality of driver units coupled in parallel, and wherein the termination resistance is adjusted by enabling or disabling one or more driver units of the plurality of driver units.

8. The apparatus of claim 1, wherein the terminal resistance control circuit comprises one or more selection devices to select the second control signal from a plurality of control signals.

9. A method comprising: receiving a control signal corresponding to a terminal resistance value; Converting the control signal into a unary code; as well as One or more driver circuits are adjusted based on the unary code to produce the terminal resistance value, wherein the one or more driver circuits are connected to an I / O pin of a device.

10. The method according to claim 9, wherein the control signal is a binary code. The method of claim 10 , wherein the binary code is stored in a mode register.

12. The method according to claim 9, comprising: The control signal is selected from a plurality of control signals.

13. The method of claim 9, wherein the control signal comprises at least one of RTT_PARK, RTT_WR, RTT_NOM_WR, or RTT_NOM_RD. The method according to claim 13 , wherein the terminal resistance value is within a predefined range.

15. The method of claim 9, wherein the one or more driver circuits are coupled in parallel.

16. A terminal resistance control circuit, comprising: a decoder configured to receive a plurality of control signals and convert the plurality of control signals into respective unary codes; a plurality of selection devices configured to select a specific control signal from among the plurality of control signals based on a selection signal and output a unary code of the specific control signal, wherein the specific control signal corresponds to a specific terminal resistance value; as well as An output driver having a terminal resistance that is adjustable, wherein the output driver is configured to provide the specific terminal resistance value based on the unary code. 17 . The terminal resistance control circuit according to claim 16 , wherein the decoder is configured to convert the plurality of control signals from corresponding binary codes into the corresponding unary codes. 18 . The terminal resistance control circuit according to claim 16 , wherein the output driver comprises one or more driver units that are enabled or disabled based on the unary code.

19. The terminal resistance control circuit according to claim 16, wherein the specific terminal resistance value is within a predefined range. 20 . The terminal resistance control circuit according to claim 16 , wherein the plurality of control signals include at least one of RTT_PARK, RTT_WR, RTT_NOM_WR, or RTT_NOM_RD.

Images