Structure for improving single particle burning resistance of silicon carbide junction terminal and preparation method thereof

Abstract

The invention provides a structure for improving single particle burning resistance of a silicon carbide junction terminal and a preparation method. The device structurally comprises an N + substrate, an N-type buffer layer, an N-type drift region, a current expansion layer, a P-type well region, an expansion P-type well region, a transition region P-type well region, a P-type field limiting ring, a P-type source region, an N-type source region, an expansion N-type source region, a polycrystalline silicon gate, an oxide, a source trench, a source, a drain and a passivation layer. An expanded P-type well region, an expanded N-type source region and a source trench are introduced at a source contact position of a junction termination transition region. The source trench can improve hole distribution at the source contact position, and hole current is prevented from being gathered locally and massively. And the expanded N-type source region can reduce the potential barrier between the P-type well region of the transition region and the expanded N-type source region by using the voltage drop of the equivalent resistance of the transition region, so that the hole concentration is reduced, and a strong electric field is prevented from being formed at the contact part of source electrode metal and SiC. Meanwhile, in order to ensure voltage resistance, an expanded P-type well region is introduced below the source trench.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor devices, and in particular relates to a structure and a preparation method for improving the single particle burnout resistance of a silicon carbide junction terminal. Background Art

[0002] With the development of the times, the semiconductor industry is facing many challenges such as reducing power consumption, improving performance and reliability. Although traditional silicon-based semiconductor materials have developed relatively maturely and have occupied a dominant position in the field of power devices, it is difficult for their performance to make a significant breakthrough, and their physical properties are already close to the limit. Silicon carbide (SiC), as a third-generation semiconductor material, has a larger bandgap, higher critical breakdown electric field, higher thermal conductivity, and faster saturation drift speed than silicon. With its excellent physical properties, silicon carbide power devices are widely used in modern new energy, aerospace and other fields.

[0003] Silicon carbide MOSFET is the most common silicon carbide power device today, but in aerospace applications, the reliability issues caused by radiation cannot be ignored, especially the device failure caused by single particle effects. At present, some studies have designed cellular structures to improve the device's ability to resist single particle burnout, but single particle effects also exist at the device junction terminal.

[0004] The single particle effects caused by heavy ions in silicon carbide MOSFET devices are mainly divided into single particle burnout effect and single particle gate penetration effect. When heavy ions bombard the junction terminal region of the device, a large number of electron-hole pairs will be generated on their path. At this time, a large number of holes will flow into the source contact of the transition region. In a short period of time, a large number of holes will gather near the source contact, forming a strong electric field and a large current, causing the local temperature to rise rapidly, causing the junction terminal region of the device to burn. Therefore, improving the single particle burnout resistance of the device junction terminal structure is of great significance to maintaining the reliable operation of the entire aerospace system. Summary of the invention

[0005] The present invention proposes a structure and a preparation method for enhancing the single-event burnout resistance of a silicon carbide junction terminal. In the junction terminal transition region, source trenches are etched, and extended N-type source regions are formed by implantation below the left and right of the trenches, and extended P-type well regions are implanted below the extended N-type source regions. When a single particle is incident near the source contact in the junction terminal transition region, the electron-hole pairs generated by ionization will be separated under the action of the electric field, and a large number of holes will rush into the source contact in the junction terminal transition region, locally inducing an avalanche effect to generate a large current and a high voltage, thereby causing thermal failure of the junction terminal structure. After introducing the source trenches, the hole distribution at the source contact can be improved, avoiding the local large accumulation of hole current, thereby reducing the contact temperature between the metal and SiC. The extended N-type source region can utilize the voltage drop of the equivalent resistance in the transition region to reduce the potential barrier between the P-type well region and the extended N-type source region in the transition region, enabling the electrons in the extended N-type source region to be injected into the P-type well region in the transition region, thereby reducing the hole concentration and avoiding the formation of a strong electric field at the contact between the source metal and SiC. Due to the introduction of the source trenches, the breakdown voltage of the transition region will decrease, and the deeper the trench, the more obvious the decrease. To ensure the breakdown voltage, extended P-type well regions are introduced below the trenches.

[0006] To achieve the above-mentioned invention purpose, the technical solution of the present invention is as follows:

[0007] A structure for enhancing the single-event burnout resistance of a silicon carbide junction terminal, including an N+ substrate 15, a drain metal 16 below the N+ substrate 15, an N-type buffer layer 14 is provided above the N+ substrate 15, an N-type drift region 13 is located above the N-type buffer layer 14, and the drain metal 16 forms an ohmic contact with the N+ substrate 15;

[0008] In the cell region, a current spreading layer 12 is provided above the N-type drift region 13, and there are two P-type well regions 10, left and right, inside it. The left P-type well region 10 contains an N-type source region 2 and a P-type source region 1, and the right P-type well region 10 contains an N-type source region 2, and the transition region P-type well region 6 is on the right of the N-type source region 2;

[0009] In the transition region, the source contact in the transition region P-type well region 6 is a source trench 8, the extended N-type source regions 7 are below the left and right of the source trench 8, and there are two extended P-type well regions 11, left and right, below the transition region P-type well region 6 and aligned with the center of the source trench 8; the source trench 8, the extended N-type source regions 7, the transition region P-type well region 6, and the extended P-type well regions 11 together form a single-event effect reinforcement structure, and 30 identical P-type field limiting rings 9 are provided in the junction terminal region, and the P-type field limiting rings 9 are located on the right of the transition region P-type well region 6;

[0010] Above the entire structure is the source metal 5, above which is the passivation layer 17. Inside the source metal 5 and above the P-type well region 6 is the oxide 4. Inside the oxide 4 is the polysilicon gate 3, and the polysilicon gate 3 is symmetric about the centers of the two P-type well regions 10 and the N-type source region 2. The source metal 5 forms ohmic contacts with the P-type source region 1, the N-type source region 2, the extended N-type source region 7, and the P-type field limiting ring 9.

[0011] As a preferred embodiment, the P-type well region 10, the N-type source region 7, the P-type source region 1, the transition P-type well region 6, and the current spreading layer 12 are formed by ion implantation.

[0012] As a preferred embodiment, the extended P-type well region 11 and the extended N-type source region 7 are both formed by ion implantation.

[0013] As a preferred embodiment, the source trench 8 is formed by etching.

[0014] As a preferred embodiment, the materials used for the P-type source region 1, the N-type source region 2, the transition P-type well region 6, the extended N-type source region 7, the P-type field limiting ring 9, the P-type well region 10, the extended P-type well region 11, the current spreading layer 12, the N-type drift region 13, the N-type buffer layer 14, and the N+ substrate 15 are all silicon carbide.

[0015] The second object of the present invention is to provide a method for manufacturing the structure for enhancing the single-event burnout resistance of the silicon carbide junction terminal, including the following steps:

[0016] The first step: epitaxial growth, an N-type buffer layer and an N-type drift region are epitaxially grown on the N+ substrate.

[0017] The second step: implant aluminum ions to form the current spreading layer.

[0018] The third step: implant aluminum ions to form the P-type well region and the extended P-type well region.

[0019] The fourth step: through a self-alignment process, form the N-type source region and the extended N-type source region.

[0020] The fifth step: implant aluminum ions to form the P-type source region, the transition P-type well region, and the field limiting ring.

[0021] The sixth step: dry oxidation to form the gate oxide layer, and then anneal in a nitric oxide atmosphere.

[0022] The seventh step: deposit and etch polysilicon.

[0023] The eighth step: form the field oxide layer.

[0024] The ninth step: etch to form the source trench.

[0025] Step 10: Etch the source contact holes, deposit the source ohmic contact metal and anneal; etch the gate contact holes, deposit or evaporate the metal to form the source and the gate;

[0026] Step 11: Deposit the passivation layer;

[0027] Step 12: Deposit the metal on the back side and alloy the drain metal.

[0028] The beneficial effects of the present invention are as follows:

[0029] The etched source trenches change the hole current flow path caused by the single event effect, effectively alleviating the accumulation of hole current at the source contact in the junction termination transition region. The extended N-type source region can recombine part of the holes. The combined effect makes the source contact in the junction termination transition region have lower thermal power and a larger energy dissipation area under the single event effect compared with the traditional structure, significantly reducing the contact temperature between the metal and SiC and enhancing the single event burnout resistance of the junction termination structure. In addition, the extended P-type well region ensures the breakdown voltage level of the junction termination transition region. Description of the Drawings

[0030] Figure 1 It is a schematic structural diagram of a structure for enhancing the single event burnout resistance of a silicon carbide junction termination in the present invention;

[0031] Figure 2 It is a schematic diagram of epitaxially growing an N-type buffer layer and an N-type drift region on an N+ substrate in the present invention;

[0032] Figure 3 It is a schematic diagram of forming a current spreading layer by implanting Al ions in the N-type drift region in the present invention;

[0033] Figure 4 It is a schematic diagram of forming a P-type well region and an extended P-type well region by implanting Al ions in the present invention;

[0034] Figure 5 It is a schematic diagram of forming an N-type source region and an extended N-type source region by implanting N ions through a self-alignment process in the present invention;

[0035] Figure 6 It is a schematic diagram of forming a P-type source region, a transition region P-type well region, and a field limiting ring by implanting Al ions in the present invention;

[0036] Figure 7 It is a schematic diagram of forming gate oxide by dry oxidation in the present invention;

[0037] Figure 8 It is a schematic diagram of depositing and etching polysilicon in the present invention;

[0038] Figure 9 It is a schematic diagram of forming field oxide in the present invention;

[0039] Figure 10 Schematic diagram of etching field oxide in the present invention;

[0040] Figure 11 Schematic diagram of etching source contact holes, depositing source ohmic contact metal and annealing in the present invention;

[0041] Figure 12 Schematic diagram of depositing a passivation layer in the present invention;

[0042] Figure 13 Schematic diagram of depositing drain metal and alloying in the present invention;

[0043] Among them, 1 is a P-type source region, 2 is an N-type source region, 3 is a polysilicon gate, 4 is an oxide, 5 is a source metal, 6 is a transition region P-type well region, 7 is an extended N-type source region, 8 is a source trench, 9 is a P-type field limiting ring, 10 is a P-type well region, 11 is an extended P-type well region, 12 is a current spreading layer, 13 is an N-type drift region, 14 is an N-type buffer layer, 15 is an N+ substrate, 16 is a drain metal, and 17 is a passivation layer. Specific embodiments

[0044] The following illustrates the implementation manners of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] As Figure 1 shown, a structure for improving the single-event burnout resistance of a silicon carbide junction terminal is provided, including an N+ substrate 15, a drain metal 16 below the N+ substrate 15. An N-type buffer layer 14 is provided above the N+ substrate 15, an N-type drift region 13 is located above the N-type buffer layer 14, and the drain metal 16 forms an ohmic contact with the N+ substrate 15;

[0046] In the cell region, a current spreading layer 12 is provided above the N-type drift region 13. There are two P-type well regions 10, left and right, inside it. The left P-type well region 10 contains an N-type source region 2 and a P-type source region 1, while the right P-type well region 10 contains an N-type source region 2, and a transition region P-type well region 6 is on the right side of the N-type source region 2;

[0047] In the transition region, at the source contact inside the transition region P-type well region 6 is the source trench 8. At the lower left and lower right of the source trench 8 are the extended N-type source regions 7. Aligned with the center of the source trench 8 below the transition region P-type well region 6 are two extended P-type well regions 11 on the left and right; the source trench 8, the extended N-type source regions 7, the transition region P-type well region 6, and the extended P-type well regions 11 together form a single-event effect hardening structure. There are 30 identical P-type field limiting rings 9 in the junction termination region, and the P-type field limiting rings 9 are located on the right side of the transition region P-type well region 6;

[0048] Above the entire structure is the source metal 5, above the source metal 5 is the passivation layer 17. Inside the source metal 5 and above the P-type well region 6 is the oxide 4. Inside the oxide 4 is the polysilicon gate 3, and the polysilicon gate 3 is symmetric about the centers of the two P-type well regions 10 and the N-type source region 2; the source metal 5 forms ohmic contacts with the P-type source region 1, the N-type source region 2, the extended N-type source regions 7, and the P-type field limiting rings 9.

[0049] Furthermore, the P-type well region 10, the N-type source region 7, the P-type source region 1, the transition region P-type well region 6, and the current spreading layer 12 are formed by ion implantation process.

[0050] Furthermore, the extended P-type well regions 11 and the extended N-type source regions 7 are both formed by ion implantation.

[0051] Furthermore, the source trench 8 is formed by etching.

[0052] Furthermore, the materials used for the P-type source region 1, the N-type source region 2, the transition region P-type well region 6, the extended N-type source regions 7, the P-type field limiting rings 9, the P-type well region 10, the extended P-type well regions 11, the current spreading layer 12, the N-type drift region 13, the N-type buffer layer 14, and the N+ substrate 15 are all silicon carbide.

[0053] The etched source trench changes the hole conduction path caused by the single-event effect, effectively alleviating the accumulation of holes at the source contact in the transition region. The extended N-type source regions can recombine part of the holes. The combined effect makes the source contact in the junction termination transition region have lower thermal power and a larger energy dissipation area under the single-event effect compared with the traditional structure, significantly reducing the internal temperature and enhancing the single-event burnout resistance ability of the junction termination structure. In addition, the extended P-type well regions effectively protect the hardening structure and prevent it from suffering from electrical breakdown under high-voltage applications.

[0054] As Figures 2 - 13 shown, this embodiment provides a preparation method for a structure for enhancing the single-event burnout resistance ability of a silicon carbide junction termination, including the following steps:

[0055] The first step: epitaxial growth, an N-type buffer layer and an N-type drift region are epitaxially grown on the N+ substrate, as Figure 2 shown;

[0056] Step 2: Inject aluminum ions to form a current expansion layer, as Figure 3 shown;

[0057] Step 3: Inject aluminum ions to form a P-type well region and an extended P-type well region, as Figure 4 shown;

[0058] Step 4: Through a self-alignment process, form an N-type source region and an extended N-type source region, as Figure 5 shown;

[0059] Step 5: Inject aluminum ions to form a P-type source region, a transition region P-type well region, and a field limiting ring, as Figure 6 shown;

[0060] Step 6: Form a gate oxide layer by dry oxidation, and then anneal it in a nitric oxide atmosphere, as Figure 7 shown;

[0061] Step 7: Deposit and etch polysilicon, as Figure 8 shown;

[0062] Step 8: Form a field oxide layer, as Figure 9 shown;

[0063] Step 9: Etch to form a source trench, as Figure 10 shown;

[0064] Step 10: Etch a source contact hole, deposit a source ohmic contact metal and anneal it; etch a gate contact hole, deposit or evaporate a metal to form a source and a gate, as Figure 11 shown;

[0065] Step 11: Deposit a passivation layer, as Figure 12 shown;

[0066] Step 12: Deposit a metal on the back, and alloy the drain metal, as Figure 13 shown.

[0067] The above embodiments only illustrate the principles and effects of the present invention, rather than limiting the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A structure for improving the single-particle burnout resistance of silicon carbide junction terminations, characterized in that: Including N + Substrate (15), N + The drain metal (16) below the substrate (15), N + An N-type buffer layer (14) is provided above the substrate (15), an N-type drift region (13) is located above the N-type buffer layer (14), and a drain metal (16) is connected to the N-type + The substrate (15) forms an ohmic contact; In the cell region, a current extension layer (12) is provided above the N-type drift region (13), and inside the current extension layer (12) are two left and right P-type well regions (10), wherein the left P-type well region (10) includes an N-type source region (2) and a P-type source region (1), and the right P-type well region (10) includes an N-type source region (2), and to the right of the N-type source region (2) is a transition region P-type well region (6); In the transition region, the source contact point inside the transition region P-type well region (6) is a source trench (8), the lower left and lower right of the source trench (8) are extended N-type source regions (7), and two left and right extended P-type well regions (11) are aligned with the center of the source trench (8) below the transition region P-type well region (6); the source trench (8), the extended N-type source region (7), the transition region P-type well region (6) and the extended P-type well region (11) together constitute an anti-single-particle effect reinforcement structure, and 30 identical P-type field limiting rings (9) are provided in the junction terminal region, and the P-type field limiting ring (9) is located on the right side of the transition region P-type well region (6); A source metal (5) is located above the entire structure, a passivation layer (17) is located above the source metal (5), an oxide (4) is located inside the source metal (5) and above the P-type well region (6), a polysilicon gate (3) is located inside the oxide (4), and the polysilicon gate (3) is symmetrical about the center of the two P-type well regions (10) and the N-type source region (2); the source metal (5) and the P-type source region (1), the N-type source region (2), the extended N-type source region (7), and the P-type field limiting ring (9) all form ohmic contacts.

2. A structure for improving the single particle burnout resistance of silicon carbide junction termination according to claim 1, characterized in that: The P-type well region (10), the N-type source region (7), the P-type source region (1), the transition region P-type well region (6), and the current extension layer (12) are formed by an ion implantation process.

3. The structure for improving the single particle burnout resistance of silicon carbide junction termination according to claim 1, characterized in that: The extended P-type well region (11) and the extended N-type source region (7) are both formed by ion implantation.

4. The structure for improving the single particle burnout resistance of silicon carbide junction termination according to claim 1, characterized in that: The source trench (8) is formed by etching.

5. The structure for improving the single particle burnout resistance of silicon carbide junction termination according to claim 1, characterized in that: P-type source region (1), N-type source region (2), transition region P-type well region (6), extended N-type source region (7), P-type field limiting ring (9), P-type well region (10), extended P-type well region (11), current spreading layer (12), N-type drift region (13), N-type buffer layer (14), N + The material used for the substrate (15) is silicon carbide.

6. The method for preparing a structure for improving the single particle burnout resistance of a silicon carbide junction terminal according to any one of claims 1 to 5, characterized in that The following steps are involved: Step 1: Epitaxial growth, N + Epitaxially generating an N-type buffer layer and an N-type drift region on the substrate; Step 2: Inject aluminum ions to form a current spreading layer; Step 3: inject aluminum ions to form a P-type well region and expand the P-type well region; Step 4: Form an N-type source region and expand the N-type source region through a self-alignment process; Step 5: inject aluminum ions to form a P-type source region, a transition region P-type well region, and a field limiting ring; Step 6: Dry oxygen oxidation to form a gate oxide layer, followed by annealing in a nitric oxide atmosphere; Step 7: depositing and etching polysilicon; Step 8: forming a field oxide layer; Step 9: Etching to form a source trench; Step 10: Etch the source contact hole, deposit the source ohmic contact metal and anneal; Etch the gate contact hole, deposit or evaporate metal, and form the source and gate; Step 11: Deposit a passivation layer; Step 12: Deposit metal on the back and alloy the drain metal.

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