Protection circuit and semiconductor device including same

Abstract

The invention provides a protection circuit and a semiconductor device including the same, which can protect a protection object from being affected by application of a power supply voltage with opposite polarity. A protection circuit is formed on a semiconductor substrate having a three-well structure including a substrate region, a partition wall region, and a well region in at least a portion thereof, and protects a protected circuit from being affected by application of a power supply voltage having a polarity opposite to that of a steady state, the protected circuit including a noise generation source, and between a VDD and a GND terminal. And a ground terminal connected to the GND terminal via a protection circuit. The protection circuit has first and second protection transistors (hereinafter Tr), the first protection transistor (Tr) including a source and a back gate connected to a node of the first circuit, and the second protection transistor (Tr) including a source and a back gate connected to a node connected to the second circuit in a state of not being connected to the first circuit. A partition wall region within the substrate region or the substrate region is connected to a drain electrode that protects Tr formed in a well region within the partition wall region.

Description

Technical Field

[0001] The present invention relates to a protection circuit and a semiconductor device including the protection circuit. Background Art

[0002] A power supply device (such as a secondary battery, etc.) that supplies power to a semiconductor device may apply a power supply voltage with a polarity opposite to the polarity applied in the stable state (hereinafter, simply referred to as "opposite polarity") due to reverse connection of a connector or noise, etc. A general semiconductor device is configured to include a parasitic diode that is forward-biased with respect to the power supply voltage of the opposite polarity. Therefore, if a power supply voltage of the opposite polarity is applied to a semiconductor device that does not consider the application of a power supply voltage of the opposite polarity, an excessive forward current flows through the parasitic diode, and the elements constituting the semiconductor device may be damaged. From the viewpoint of preventing damage to the elements caused by the application of such a power supply voltage of the opposite polarity, a technique for protecting an integrated circuit has been disclosed (for example, refer to Patent Document 1).

[0003] The protection circuit to which the technique disclosed in Patent Document 1 is applied has a negative-positive-negative (NPN) bipolar transistor, and the NPN bipolar transistor includes: a base connected to a VCC terminal that supplies a power supply voltage VCC (≠0V) via a resistor; a collector connected to an internal circuit to be protected (hereinafter referred to as "protection target" or "protected circuit"); and an emitter connected to a ground (GND) terminal that supplies a power supply voltage of 0V.

[0004] In a state where a power supply voltage of the opposite polarity is not applied, that is, in a stable state where the power supply voltage VCC is a positive voltage (VCC>0), if the power supply voltage VCC is sufficiently higher than the forward voltage Vf of the base-emitter diode of the NPN bipolar transistor, the current driving force increases, and the collector-emitter voltage can be regarded as approximately 0V. Therefore, in a stable state, the internal circuit can be regarded as directly connected to the GND terminal.

[0005] On the other hand, in a state where a power supply voltage of the opposite polarity is applied, that is, in a power supply reverse connection state where the power supply voltage VCC is a negative voltage (VCC<0), the base voltage follows the power supply voltage VCC, and no base current flows. Therefore, the NPN bipolar transistor included in the protection circuit becomes a cut-off state, and the collector current is cut off. By cutting off the collector current, when the internal circuit is directly connected to the GND terminal, the excessive forward current flowing through the parasitic diode, which is the cause of element damage, can be cut off, and further, the protection target can be protected from damage to the elements caused by the application of a power supply voltage of the opposite polarity.

[0006] [Prior Art Documents]

[0007] [Patent Document]

[0008] [Patent Document 1] Japanese Patent Laid-Open No. 10-289956 Summary of the Invention

[0009] [Problems to be Solved by the Invention]

[0010] However, in existing protection circuits and semiconductor devices including such protection circuits that apply the technology disclosed in Patent Document 1, there is room for improvement in terms of possible adverse effects on the protected object depending on the circuit structure of the protected object. For example, when the circuit to be protected is a circuit in which an analog circuit that processes a DC voltage or a continuous signal and a digital circuit that processes a switching power supply, a charge pump, or a discrete signal that has a large current flowing during a switching operation are mixed in an internal circuit, in a steady state, a change in the collector voltage is generated due to the current flowing from the digital circuit or a direct current to direct current (DCDC) converter to an NPN bipolar transistor. The change in the collector voltage becomes noise in the analog circuit and has an adverse effect on the signal processing of the analog circuit.

[0011] In order to reduce the noise in the analog circuit, the NPN bipolar transistor included in the protection circuit can be changed to an NPN bipolar transistor having a higher current driving force. However, the larger the current driving force, the larger the area of the bipolar transistor tends to be. Therefore, the application of an NPN bipolar transistor having a high current driving force results in an increase in the area of the protection circuit and thus the cost.

[0012] The present invention has been made in view of the above circumstances, and an object thereof is to provide a protection circuit and a semiconductor device including the protection circuit, the protection circuit being capable of suppressing an increase in cost and adverse effects on a protected object, and protecting the protected object from a power supply voltage having an opposite polarity applied thereto.

[0013] [Technical Means for Solving the Problems]

[0014] The protection circuit according to an embodiment of the present invention is formed on a semiconductor substrate having a triple-well structure including a substrate region of a first conductivity type, an isolation wall region, and a well region of the first conductivity type in at least a part thereof, and protects a circuit to be protected from the influence of a power supply voltage having a polarity opposite to that in a steady state. The isolation wall region is formed in the substrate region and includes a semiconductor region of a second conductivity type in at least a part thereof. The well region of the first conductivity type is formed inside the region surrounded by the isolation wall region. The protection circuit is characterized in that the circuit to be protected includes a noise generation source and has a first circuit and a second circuit. The first circuit is connected to the second power supply terminal via the protection circuit between a first power supply terminal and the second power supply terminal. The second circuit is connected in parallel with the first circuit via the protection circuit between the first power supply terminal and the second power supply terminal. On the other hand, the protection circuit has a first protection transistor and a second protection transistor. The first protection transistor includes a drain connected to the second power supply terminal, a gate supplied with a first control voltage, and a source and a back gate connected to the first circuit. The second protection transistor includes a drain connected to the drain of the first protection transistor, a gate supplied with a second control voltage, and a source and a back gate that are not connected to the connection point of the source and the back gate of the first protection transistor and the first circuit and are connected to the second circuit. At least one of the first protection transistor and the second protection transistor is formed in the well region, and the drain of the protection transistor formed in the well region is connected to any one of the semiconductor region and the substrate region included in the isolation wall region surrounding the well region. The semiconductor device according to an embodiment of the present invention includes the protection circuit.

[0015] [Effects of the Invention]

[0016] According to the present invention, an increase in cost and an adverse influence on an object to be protected can be suppressed, and the object to be protected can be protected from the influence of a power supply voltage having an opposite polarity. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a circuit diagram of a semiconductor device including a protection circuit according to an embodiment of the present invention.

[0018] Figure 2A is a circuit diagram of a current source showing a first configuration example of a load of a step-down circuit in the semiconductor device according to the present embodiment, Figure 2B is a circuit diagram showing a first configuration example of a current source as a load, Figure 2C is a circuit diagram showing a second configuration example of a current source as a load.

[0019] Figure 3Cross-sectional view of the protection circuit included in the semiconductor device of the first embodiment.

[0020] Figure 4 Cross-sectional view of the protection circuit included in the semiconductor device of the second embodiment.

[0021] Figure 5 Cross-sectional view showing a first modification of the semiconductor device of the first embodiment.

[0022] Figure 6 Cross-sectional view showing a second modification of the semiconductor device of the first embodiment.

[0023] Figure 7 Cross-sectional view showing a third modification of the semiconductor device of the first embodiment.

[0024] Figure 8A Circuit diagram showing a second configuration example of the load in the semiconductor device of the present embodiment, Figure 8B Circuit diagram showing a third configuration example of the load in the semiconductor device of the present embodiment, Figure 8C Circuit diagram showing a fourth configuration example of the load in the semiconductor device of the present embodiment.

[0025] Figure 9A Circuit diagram showing a second configuration example of the step-down circuit in the semiconductor device of the present embodiment, Figure 9B Partial circuit diagram of a third configuration example of the step-down circuit.

[0026] Figure 10A Circuit diagram showing a first configuration example of the current source in the second configuration example of the step-down circuit in the semiconductor device of the present embodiment, Figure 10B Circuit diagram showing a second configuration example of this current source.

[0027] Figure 11 Circuit diagram showing a modification example of the protection circuit and semiconductor device of the present embodiment.

[0028] [Description of symbols]

[0029] 1: VDD terminal

[0030] 2: GND terminal

[0031] 10A, 10B, 10C, 10D, 10E, 10F: Semiconductor device

[0032] 11: Analog circuit (second circuit)

[0033] 12: Digital circuit (first circuit)

[0034] 15, 25, 35: Step-down circuit (gate voltage control circuit)

[0035] 15i: Input terminal

[0036] 15o, 25o: Output terminals (of the step-down circuit)

[0037] 16, 31, 51: Depletion-type NMOS transistors

[0038] 17: Load

[0039] 20A, 20B, 20C, 20D, 20E, 20F: Protection circuits

[0040] 21: NMOS transistor (second protection transistor)

[0041] 22: NMOS transistor (first protection transistor)

[0042] 32, 52: Current mirror circuits

[0043] 33, 53, 171, 251: Current sources

[0044] 50: Semiconductor substrate

[0045] 173, 250: I / V conversion circuits

[0046] 173a, 252: Resistance elements

[0047] 173b: Zener diode

[0048] 173c: Transistor circuit

[0049] 173c_1: MOS transistor

[0050] 321, 322: NMOS transistors

[0051] 510: Substrate region

[0052] 531, 532: Isolation wall regions

[0053] 541, 542: Well regions

[0054] 521, 522: PMOS transistors

[0055] 551, 552: Insulating layers

[0056] 561, 562: Parasitic diodes (isolation wall regions)

[0057] 561a, 562a: Nwell

[0058] 561b, 561c: Trenches

[0059] 571, 572: Connection terminals

[0060] B: Back gate

[0061] D: Drain

[0062] G: Gate

[0063] S: Source

[0064] I1, I2, I3, I4: Constant current

[0065] N1, N2, N3, N4, N5, N6: Node

[0066] X, Y, Z: Axis Detailed implementation manners

[0067] Hereinafter, examples of a protected object, i.e., a protected circuit, protected by a protection circuit according to an embodiment of the present invention, in which a circuit including a noise generation source and a circuit that may be affected by noise coexist, will be listed, and the protection circuit according to the embodiment of the present invention and a semiconductor device including the protection circuit will be described with reference to the drawings.

[0068] [First Embodiment]

[0069] Figure 1 is a circuit diagram of a semiconductor device 10A including a protection circuit 20A, which is an example of a semiconductor device including a protection circuit according to the first embodiment. In addition, Figure 2A is a circuit diagram showing a current source 171 as a first configuration example of a load 17, Figure 2B and Figure 2C are circuit diagrams showing the first configuration example and the second configuration example of the current source 171, respectively.

[0070] With reference to Figure 1 , the protection circuit 20A and the semiconductor device 10A will be described. The semiconductor device 10A includes an analog circuit 11, a digital circuit 12, a protection circuit 20A, and a step-down circuit 15. The analog circuit 11, the digital circuit 12, the protection circuit 20A, and the step-down circuit 15 constitute a semiconductor integrated circuit formed on a semiconductor substrate.

[0071] Here, the digital circuit 12 as the first circuit processes a switching power supply, a charge pump, or a discrete signal that flows a large current during a switching operation. Therefore, generally, the current variation or the maximum value during operation is larger than that of the analog circuit 11. Therefore, in the description of the present embodiment, the digital circuit 12 includes a noise generation source.

[0072] In addition, the analog circuit 11, which is the second circuit, is a circuit that can be affected by noise. Without any noise countermeasures implemented, the analog circuit 11 is affected by the noise generated by the noise source. However, as will be described later, in the semiconductor device 10A configured to suppress the influence of the noise generated by the noise source, the analog circuit 11 can operate stably. Furthermore, the analog circuit 11 and the digital circuit 12 are the protected circuits of the protection circuit 20A, which are the objects to be protected from the influence of the power supply voltage with a polarity opposite to the steady state.

[0073] The analog circuit 11, the digital circuit 12, and the step-down circuit 15 each have a first end and a second end. The first end is connected to the VDD terminal 1 that supplies the voltage VDD, which is an example of the power supply voltage, and the second end is connected to the GND terminal 2 that supplies the voltage GND, which is another example of the power supply voltage, without passing through the protection circuit 20A. The second ends of the analog circuit 11, the digital circuit 12, and the step-down circuit 15 are respectively connected to the protection circuit 20A and are connected to the GND terminal 2 via the protection circuit 20A. Here, the connection point of each first end of the analog circuit 11, the digital circuit 12, and the step-down circuit 15 with the VDD terminal 1 is referred to as the node N1.

[0074] The step-down circuit 15, which is a gate voltage control circuit, has, for example, a depletion-type N-channel metal oxide semiconductor (NMOS) transistor 16, a load 17, and an output terminal 15o connected to the connection point of the depletion-type NMOS transistor 16 and the load 17. The other end, i.e., the second end, of the load 17 opposite to the first end connected to the depletion-type NMOS transistor 16 and the output terminal 15o is connected to the second end of the analog circuit 11. Here, the connection point of the load 17 and the analog circuit 11 is referred to as the node N2. The step-down circuit 15 having the depletion-type NMOS transistor 16 is a so-called source follower that also has an input terminal 15i connected to the gate of the depletion-type NMOS transistor 16.

[0075] Here, with reference to Figures 2A to 2C , a configuration example of the load 17 will be described. For example, as shown in Figure 2A , the load 17 is a current source 171 that supplies a constant current I1 along the direction from the node N5 to the node N2. The current source 171 is configured, for example, to have a depletion-type NMOS transistor 31 with its gate and source connected (refer to Figure 2B ), or is configured to have a current source 33 that supplies a constant current I2 to the drain of the NMOS transistor 322 and a current mirror circuit 32 (refer to Figure 2C ).

[0076] The current mirror circuit 32 is configured to include, for example, an NMOS transistor 321 and an NMOS transistor 322. The NMOS transistor 322 includes a gate connected to the gate of the NMOS transistor 321 and its own drain. The current mirror circuit 32 causes a constant current I1 (= mI2) that replicates the constant current I2 at a specified mirror ratio m (where m is an arbitrary positive number) to flow to the drain of the NMOS transistor 321.

[0077] Return Figure 1 , the protection circuit 20A will be described. The protection circuit 20A includes an NMOS transistor 21 and an NMOS transistor 22. The NMOS transistor 21 is connected between the analog circuit 11 and the GND terminal 2, and the NMOS transistor 22 is connected between the digital circuit 12 and the GND terminal 2.

[0078] The NMOS transistor 21, which is the second protection transistor, includes, for example, a source and a back gate connected to the node N2 in addition to a drain and a gate. The node N2 is a node that serves as a reference with respect to the analog circuit 11.

[0079] The NMOS transistor 22, which is the first protection transistor, includes, for example, a drain connected to the drain of the NMOS transistor 21, a gate connected to the gate of the NMOS transistor 21, and a source and a back gate connected to the node N3. The node N3 is a node that serves as a reference with respect to the digital circuit 12.

[0080] The drain of the NMOS transistor 21 is connected to the drain of the NMOS transistor 22. Here, the connection point of the drain of the NMOS transistor 21 and the drain of the NMOS transistor 22 is referred to as the node N4. The node N4 is connected to the GND terminal 2. The connection point of the gates of the NMOS transistor 21 and the NMOS transistor 22, i.e., the node N5, is connected to the output terminal 15o of the step-down circuit 15.

[0081] Figure 3 is a cross-sectional view of the protection circuit 20A.

[0082] The protection circuit 20A is formed as a semiconductor integrated circuit on a semiconductor substrate 50. The semiconductor substrate 50 has a so-called triple-well structure in at least a part thereof. For example, the semiconductor substrate 50 in the semiconductor device 10A has a triple-well structure including a P-type substrate region 510 as the first conductivity type, an N-type well region as the second conductivity type, i.e., an isolation wall region (in the figure, denoted as "Nwell (N Buried Layer, NBL)") 531, an isolation wall region 532, and P-type well regions 541 and 542 as the first conductivity type.

[0083] The isolation wall regions 531 and 532 are formed in the substrate region 510. The well region 541 is formed inside the region surrounded by the isolation wall region 531. The well region 542 is formed inside the region surrounded by the isolation wall region 532. NMOS transistors 21 and 22 are respectively formed in the well region 541 and the well region 542. The gate G of the NMOS transistor 21 is provided via the well region 541 and the insulating layer 551. The gate G of the NMOS transistor 22 is provided via the well region 542 and the insulating layer 552.

[0084] Here, the impurity concentrations of the isolation wall regions 531 and 532, and the drains D and sources S of the NMOS transistors 21 and 22 are formed to be high (N+) with respect to the N-type semiconductor region (not shown) in the N-type semiconductor region. The back gates B of the NMOS transistors 21 and 22 are formed to be high (P+) with respect to the substrate region 510, the well region 541, and the well region 542.

[0085] The drain D of the NMOS transistor 21 is connected to the isolation wall region 531. The drain D of the NMOS transistor 22 is connected to the isolation wall region 532. The connection point of the drain D of the NMOS transistor 21 and the isolation wall region 531 and the connection point of the drain D of the NMOS transistor 22 and the isolation wall region 532 are connected to form a node N4.

[0086] Next, the operations of the protection circuit 20A and the semiconductor device 10A will be described. In addition, when describing the operations of the protection circuit 20A and the semiconductor device 10A, the following is assumed: The analog circuit 11 and the digital circuit 12 are circuits in which a reverse current flows through a parasitic diode in a state where the protection circuit 20A is not connected and a negative voltage is applied to the VDD terminal 1, that is, in a state where a power supply voltage having a polarity opposite to the stable state is applied.

[0087] First, in a state where a positive voltage is applied to the VDD terminal 1, that is, in a stable state, the current flowing inside the analog circuit 11 flows in the direction from the node N1 toward the node N2, and the current flowing inside the digital circuit 12 flows in the direction from the node N1 toward the node N3. The step-down circuit 15 supplies the gate voltage Vg of the NMOS transistor 22 as the first control voltage and the gate voltage Vg of the NMOS transistor 21 as the second control voltage to the gates of the NMOS transistors 21 and 22.

[0088] When using Figure 1When controlling the NMOS transistor 21 and the NMOS transistor 22 by means of the step-down circuit 15 of the illustrated source follower, it is only necessary to appropriately set the bias voltage Vbias, which is the gate voltage of the depletion-type NMOS transistor 16 serving as the step-down transistor, that is, the voltage input to the input terminal 15i, so that the voltage of the node N5 serving as each gate voltage Vg is higher than the threshold voltage Vth1 of the NMOS transistor 21 and the threshold voltage Vth2 of the NMOS transistor 22.

[0089] When the NMOS transistor 21 and the NMOS transistor 22 are turned on (ON) and in a state where current flows from their respective sources (node N2 and node N3) to the drain (node N4), the bias voltage Vbias, the gate / source voltage Vgs of the depletion-type NMOS transistor 16, and the threshold voltage Vth_sf of the depletion-type NMOS transistor 16 are used, and the gate voltages Vg respectively satisfy the following formulas (1) and (2)

[0090] Vg = Vbias - Vgs ≒ Vbias - Vth_sf > Vth1 ··· (1)

[0091] Vg = Vbias - Vgs ≒ Vbias - Vth_sf > Vth2 ··· (2)

[0092] Set the bias voltage Vbias in such a way that the relationships shown are satisfied.

[0093] When a depletion-type transistor is applied to the step-down transistor, the threshold voltage Vth_sf is negative, so the gate voltage Vg can be set to be equal to or higher than the bias voltage Vbias (Vg ≧ Vbias). That is, by applying a depletion-type transistor such as the depletion-type NMOS transistor 16 to the step-down transistor, it is easy to turn on the NMOS transistor 21 and the NMOS transistor 22.

[0094] In addition, for the stable operation of the analog circuit 11 and the digital circuit 12, it is ideal for the nodes N2 and N3 to operate at a voltage close to the voltage GND. In the above case, the NMOS transistor 21 and the NMOS transistor 22 serving as protection transistors operate in the resistance region where the drain / source voltage is close to 0V. Therefore, the current flowing from the VDD terminal 1 to the node N2 flows to the GND terminal 2 via the on-resistance of the NMOS transistor 21. The current flowing from the VDD terminal 1 to the node N3 flows to the GND terminal 2 via the on-resistance of the NMOS transistor 22.

[0095] Here, when the NMOS transistor 21 and the NMOS transistor 22 operate in a resistance region where the drain / source voltage is close to 0V, the voltage Vint_gnd1_ope of the node N2 can be expressed by Equation (3) using the resistance value Ron21 of the on-resistance of the NMOS transistor 21 and the current value Iope_gnd1 of the current flowing from the node N2 toward the node N4. In addition, the voltage Vint_gnd2_ope of the node N3 can be expressed by Equation (4) using the resistance value Ron22 of the on-resistance of the NMOS transistor 22 and the current value Iope_gnd2 of the current flowing from the node N3 toward the node N4.

[0096] Vint_gnd1_ope = Ron21 × Iope_gnd1 ··· (3)

[0097] Vint_gnd2_ope = Ron22 × Iope_gnd2 ··· (4)

[0098] As Figure 1 and Figure 3 illustrated in the protection circuit 20A, when the NMOS transistor 22 is separated from the NMOS transistor 21 through the well region 542 formed in the isolation wall region 532, the current from the digital circuit 12 flows into the NMOS transistor 22 via the node N3. The variation in the current from the digital circuit 12 is converted into a voltage variation at the source S through the on-resistance (resistance value Ron22) of the NMOS transistor 22.

[0099] At this time, the voltage of the well region 542 serving as the back gate B of the NMOS transistor 22 also varies. Here, when the direction from the well region 542 toward the substrate region 510 is defined as the positive direction, the voltage variation of the well region 542 propagates to the isolation wall region 532 through the parasitic diode 561 forward-biased between the well region 542 and the isolation wall region 532. However, since the parasitic diode 562 between the isolation wall region 532 and the substrate region 510 forming the junction surface is reverse-biased, the propagation of the voltage variation of the well region 542, that is, the noise, to the substrate region 510 is cut off.

[0100] Next, in a state where a negative voltage is applied to the VDD terminal 1, that is, when a power supply voltage with a polarity opposite to the stable state is applied, in the analog circuit 11, a reverse current flows from the node N2 toward the node N1 via the parasitic diode. In the digital circuit 12, a reverse current flows from the node N3 toward the node N1 via the parasitic diode. At this time, the gate voltages Vg of the NMOS transistors 21 and 22, the voltage Vint_gnd1_ope of the node N2, and the voltage Vint_gnd2_ope of the node N3 decrease following the voltage of the VDD terminal 1. As a result, the gate-source voltage of the NMOS transistor 21 becomes lower than the threshold voltage Vth1 and turns off (OFF). The gate-source voltage of the NMOS transistor 22 becomes lower than the threshold voltage Vth2 and turns off.

[0101] Focusing on the cross-sectional structure, in a state where a negative voltage is applied to the VDD terminal 1, the voltages of the well region 541, the well region 542, and the substrate region 510 become lower than the voltage GND of the GND terminal 2 and lower than the voltages of the isolation wall regions 531 and 532. Therefore, the parasitic diodes (not shown) between the well region 541 and the isolation wall region 531, the parasitic diodes (not shown) between the isolation wall region 531 and the substrate region 510, the parasitic diode 561 between the well region 542 and the isolation wall region 532, and the parasitic diode 562 between the isolation wall region 532 and the substrate region 510 are all in a reverse-biased state. In short, in a state where a negative voltage is applied to the VDD terminal 1, the parasitic diodes formed in the triple-well structure including the well region 541, the well region 542, the isolation wall regions 531 and 532, and the substrate region 510 are all reverse-biased, so the reverse current is cut off.

[0102] As described above, according to the protection circuit 20A and the semiconductor device 10A, since the protection circuit 20A has the NMOS transistors 21 and 22, the analog circuit 11 and the digital circuit 12 can be protected from the influence of a power supply voltage with an opposite polarity.

[0103] If described in more detail, by satisfying at least one of forming the NMOS transistor 21 in the well region 541 within the isolation wall region 531 and forming the NMOS transistor 22 in the well region 542 within the isolation wall region 532, the nodes N2 and N3 are physically and electrically separated by the isolation wall regions 531 and 532. Therefore, the semiconductor device 10A can suppress the adverse effects of noise from the noise source and suppress the increase in cost. That is, according to the protection circuit 20A and the semiconductor device 10A, the propagation of the voltage variation shown in the formula (4) from the digital circuit 12 to other circuits such as the analog circuit 11 can be cut off.

[0104] Further, in a state where a negative voltage is applied to the VDD terminal 1, parasitic diodes formed in the triple-well structure including the well region 541, the well region 542, the isolation wall region 531, the isolation wall region 532, and the substrate region 510 are all reverse-biased, so that reverse current can be cut off.

[0105] Furthermore, in the protection circuit 20A and the semiconductor device 10A, as can be understood from the above-described formulas (3) and (4), by adjusting the resistance values of the on-resistances of the NMOS transistors 21 and 22 to appropriate values, the voltage drops from the node N2 to the node N4 and from the node N3 to the node N4 can be adjusted separately. That is, in the protection circuit 20A and the semiconductor device 10A, the degree of freedom in circuit design of the protection circuit 20A and the semiconductor device 10A can be increased. In addition, the adjustment of the resistance values of the on-resistances of the NMOS transistors 21 and 22 can be appropriately selected, for example, from several methods such as changing the aspect ratios of the NMOS transistors 21 and 22.

[0106] [Second Embodiment]

[0107] The protection circuit of the second embodiment of the present invention and the semiconductor device including the protection circuit are different from the protection circuit of the first embodiment and the semiconductor device including the protection circuit in that the drain of the formed protection transistor is connected to the substrate region and the isolation wall region is not connected to any terminal, that is, it is floating, but there is no substantial difference in other aspects. In other words, the protection circuit of the second embodiment and the semiconductor device including the protection circuit have no substantial difference in circuit structure from the protection circuit of the first embodiment and the semiconductor device including the protection circuit, and the connection relationship between the protection transistor and the semiconductor substrate is different. Therefore, in the present embodiment, the description will be centered on the above-described differences, and redundant descriptions for aspects that are not substantially different will be omitted.

[0108] Figure 4 FIG. is a cross-sectional view of a semiconductor device 10B including a protection circuit 20B, which is an example of a semiconductor device including the protection circuit of the second embodiment.

[0109] The semiconductor device 10B is different from the semiconductor device 10A in that it includes the protection circuit 20B with respect to the protection circuit 20A, but there is no substantial difference in other aspects. In addition, the protection circuit 20B is different from the protection circuit 20A in the connection destination of the drain D of the NMOS transistor 21 formed in the well region 541, the connection destination of the drain D of the NMOS transistor 22 formed in the well region 542, and the fact that the isolation wall regions 531 and 532 are floating, but there is no substantial difference in other aspects.

[0110] In the protection circuit 20B, the drain D of the NMOS transistor 21 is connected to the connection terminal 571 electrically connected to the substrate region 510. The drain D of the NMOS transistor 22 is connected to the connection terminal 572 electrically connected to the substrate region 510. The connection terminal 571 and the connection terminal 572 are regions where the impurity concentration is formed to be high (P+) with respect to the substrate region 510, the well region 541, and the well region 542 within the substrate region 510. On the other hand, the isolation wall regions 531 and 532 are in a state of not being connected to any terminal, that is, floating.

[0111] Next, the operations of the protection circuit 20B and the semiconductor device 10B will be described. In addition, when describing the operations of the protection circuit 20B and the semiconductor device 10B, it is premised that there is no circuit based on the voltage of the substrate region 510, and the content that is substantially the same as the operations of the protection circuit 20A and the semiconductor device 10A is omitted.

[0112] If it is premised that there is no circuit based on the voltage of the substrate region 510 within the semiconductor device 10B, in the protection circuit 20B and the semiconductor device 10B, the well regions 541 and 542 are connected to the GND terminal 2 via the NMOS transistor 21 and the NMOS transistor 22. In addition, the substrate region 510 (more specifically, the connection terminal 571 and the connection terminal 572) is connected to the GND terminal 2, and the isolation wall regions 531 and 532 are floating.

[0113] The protection circuit 20B and the semiconductor device 10B connected in this way can turn on the NMOS transistor 21 and the NMOS transistor 22 to ensure a current path in the steady state, similarly to the protection circuit 20A and the semiconductor device 10A. On the other hand, when a power supply voltage with a polarity opposite to the steady state is applied, the parasitic diodes (not shown) between the well regions 541 and 542 and the isolation wall regions 531 and 532 or the parasitic diodes (not shown) between the isolation wall regions 531 and 532 and the substrate region 510 are in a reverse-biased state. Therefore, similarly to the protection circuit 20A and the semiconductor device 10A, the reverse-biased parasitic diodes cut off the reverse current.

[0114] As described above, according to the protection circuit 20B and the semiconductor device 10B, the same effects as those of the protection circuit 20A and the semiconductor device 10A can be obtained. That is, the analog circuit 11 and the digital circuit 12 can be protected from the influence of a power supply voltage with an opposite polarity. The degree of freedom in circuit design in the protection circuit 20B and the semiconductor device 10B can be improved.

[0115] Furthermore, according to the protection circuit 20B and the semiconductor device 10B, the substrate area 510 can be stably used because the substrate area 510 is connected to the GND terminal 2. In addition, when an integrated circuit (IC) including the protection circuit 20B is enclosed in a package having a solder surface on the back, the operability of the electrical connection test between the package and the IC or between the package and the mounting substrate can be improved.

[0116] The present invention is not limited to the above-described embodiments as it is, and can be implemented in various forms other than the above-described embodiments in the implementation stage, and various omissions, additions, substitutions, or changes can be made without departing from the gist of the invention.

[0117] The protection circuit of this embodiment and the semiconductor device including the protection circuit, for example, the isolation wall region 531 and the isolation wall region 532 in the protection circuit 20A and the semiconductor device 10A are connected to the drain of the NMOS transistor 21 and the drain of the NMOS transistor 22, that is, the node N4, respectively, but the present invention is not limited thereto. It is also possible to configure such that one of the isolation wall region 531 and the isolation wall region 532 in the protection circuit 20A and the semiconductor device 10A is set to float, and the other of the isolation wall region 531 and the isolation wall region 532 is connected to the node N4.

[0118] The connection terminals 571 and 572 in the protection circuit 20B and the semiconductor device 10B do not necessarily need to be both formed, and at least one of them may be formed. That is, as long as one of the connection terminals 571 and 572 is connected to the GND terminal 2, the other of the connection terminals 571 and 572 may be omitted. In addition, as described later Figures 5 to 11 As shown, deformation is also possible.

[0119] Figure 5 , Figure 6 and Figure 7 The semiconductor devices of the first embodiment are cross-sectional views of a semiconductor device 10C, a semiconductor device 10D, and a semiconductor device 10E, which are first and second variations of the semiconductor device of the first embodiment. Figure 7 The X-axis, Y-axis, and Z-axis shown are three axes in a three-dimensional orthogonal coordinate system. In this embodiment, the X-axis direction, the Y-axis direction, and the Z-axis direction correspond to the horizontal direction, the vertical direction, and the depth direction, respectively.

[0120] The protection circuit and the semiconductor device of the present embodiment may be, for example, a protection circuit 20A and a semiconductor device 10A in which the isolation wall region 532 and the well region 542 are omitted (see Figure 5 ) of the protection circuit 20C and the semiconductor device 10C, the isolation wall region 531 and the well region 541 may be omitted (seeFigure 6 ) The protection circuit 20D and the semiconductor device 10D. Since the protection circuit 20C and the semiconductor device 10C or the protection circuit 20D and the semiconductor device 10D function in the same manner as the protection circuit 20A and the semiconductor device 10A, the same effects as those of the protection circuit 20A and the semiconductor device 10A can be obtained.

[0121] Furthermore, the protection circuit and the semiconductor device of the present embodiment can omit the isolation wall region 532 and the well region 542 with respect to the protection circuit 20B and the semiconductor device 10B, and can also omit the isolation wall region 531 and the well region 541. The protection circuit and the semiconductor device that omit the isolation wall region 532 and the well region 542 or the isolation wall region 531 and the well region 541 with respect to the protection circuit 20B and the semiconductor device 10B can also obtain the same effects as those of the protection circuit 20B and the semiconductor device 10B.

[0122] The protection circuit and the semiconductor device of the present embodiment can also be configured to include the isolation wall region 561 and the isolation wall region 562 instead of the isolation wall region 531 and the isolation wall region 532 with respect to the protection circuit 20A and the semiconductor device 10A or with respect to the protection circuit 20B and the semiconductor device 10B. The isolation wall region 561 and the isolation wall region 562 are the same as the isolation wall region 531 and the isolation wall region 532 in that they respectively include Nwell 561a and Nwell 562a, but are different in that a region containing an insulator is further included in a part of the isolation wall region 561 and the isolation wall region 562.

[0123] The isolation wall region 561 includes, in a part thereof, a region containing an N-type semiconductor such as Nwell 561a formed with a predetermined width in the depth direction along the lateral direction, that is, at substantially the same depth. Nwell 561a is bonded to the trench 561b and the trench 561c as insulators at both ends thereof. The trench 561b and the trench 561c are formed of an air region, for example, as an example of an insulator, that is, only formed as a groove, but may also be formed of an oxide such as SiO 2 etc. The isolation wall region 562 is configured in the same manner as the isolation wall region 561.

[0124] In addition, Figure 7The illustrated isolation wall regions 561 and 562 are examples in which the Nwell 561a is uniformly formed at substantially the same depth, but the position or size of the Nwell 561a is not limited to the illustrated locations. In the isolation wall regions 561 and 562, the Nwell 561a and Nwell 562a only need to be included in at least a part of any one of the first part, which is the region on the side with a smaller X, the second part, which is the region on the side with a larger X, and the third part, which is the region extending in the lateral direction, in the region extending in the depth direction. That is, any one of the first region, the second region, and the third region may be formed to include the Nwell 561a and the insulator. In addition, regarding the isolation wall regions 561 and 562, for example, one of the first region and the second region may be formed by the Nwell 561a and Nwell 562a, and the other of the first region and the second region and the third region may be formed by the insulator.

[0125] Although Figure 7 the N-type semiconductor regions included in the illustrated isolation wall region 561 and isolation wall region 562 are floating, they may also be connected to the node N4.

[0126] In addition, the step-down circuit 15 is an example having a current source 171 as an example of the load 17, but it may also be configured to have a current / voltage (I / V) conversion circuit 173 that converts current to voltage instead of the current source 171 (refer to Figures 8A to 8C ).

[0127] Figures 8A to 8C They are circuit diagrams showing second to fourth configuration examples of the load 17, respectively.

[0128] In the above embodiment, as an example of the I / V conversion circuit 173, the load 17 may apply a resistance element 173a (second configuration example: refer to Figure 8A ), may also apply a Zener diode 173b (third configuration example: refer to Figure 8B ), and may also apply a transistor circuit 173c including at least one diode-connected MOS transistor 173c_1 (fourth configuration example: refer to Figure 8C ). In addition, the transistor circuit 173c is not limited to the case including one diode-connected MOS transistor 173c_1, and may also be configured to serially connect a plurality of diode-connected MOS transistors including the MOS transistor 173c_1.

[0129] The semiconductor devices 10A to 10E include the step-down circuit 15 and may also include a step-down circuit 25 (refer to Figure 9A and Figure 9B) to replace the step-down circuit 15.

[0130] Figure 9A is a circuit diagram of the step-down circuit 25 having a current source 251, Figure 9B is a partial circuit diagram of the step-down circuit 25 having a resistance element 252 to replace the current source 251. In addition, Figure 10A is a circuit diagram showing a first configuration example of the current source 251, Figure 10B is a circuit diagram showing a second configuration example of the current source 251.

[0131] In the above-described embodiment, as Figure 9A illustrated, the step-down circuit 25 has a current source 251 to replace the depletion-type NMOS transistor 16 with respect to the step-down circuit 15, has an I / V conversion circuit 250 to replace the load 17, and also has an output terminal 25o corresponding to the output terminal 15o. As Figure 9B partially illustrated, the step-down circuit 25 may have a resistance element 252 to replace the current source 251.

[0132] The current source 251 is configured, for example, to have a depletion-type NMOS transistor 51 with its gate and source connected (refer to Figure 10A ), or is configured to have a current source 53 that supplies a constant current I4 to the drain of a P-type metal oxide semiconductor (PMOS) transistor 522 and a current mirror circuit 52 (refer to Figure 10B ).

[0133] The current mirror circuit 52 is configured, for example, to have a PMOS transistor 521 and a PMOS transistor 522. The PMOS transistor 521 includes a gate connected to its own drain, and the PMOS transistor 522 includes a gate connected to the gate and drain of the PMOS transistor 521. The current mirror circuit 52 causes a constant current I3 (= kI4) obtained by replicating the constant current I4 at a specified mirror ratio k (k is an arbitrary positive number) to flow to the drain of the PMOS transistor 521.

[0134] Similar to the I / V conversion circuit 173, the I / V conversion circuit 250 can be constituted by applying a resistance element, a Zener diode, a diode-connected MOS transistor, or a transistor circuit formed by connecting a plurality of diode-connected MOS transistors in series.

[0135] The protection circuits 20A to 20E are examples that do not include the step-down circuit 15 or the step-down circuit 25, but the protection circuits 20A to 20E are not limited to the above examples. The protection circuits 20A to 20E and the protection circuit 20F described later (refer to Figure 11) may also include a step-down circuit 15, a step-down circuit 25, or a step-down circuit 35 described later (see Figure 11 ).

[0136] The protection circuits 20A to 20E are examples in which the NMOS transistor 21 and the NMOS transistor 22 include a common gate, but the gates of the NMOS transistor 21 and the NMOS transistor 22 may not be common. That is, the gates of the NMOS transistor 21 and the NMOS transistor 22 can be independent. When the gates of the NMOS transistor 21 and the NMOS transistor 22 are independent, as long as the step-down circuit 15 and the step-down circuit 25 are combined to form a step-down circuit, an independent gate voltage can be supplied.

[0137] Figure 11 is a partial circuit diagram of a protection circuit and a semiconductor device including the protection circuit according to this embodiment, that is, the protection circuit 20F and the semiconductor device 10F. In addition, in Figure 11 , from the viewpoints of clarity and simplicity, the illustration of the analog circuit 11 and the digital circuit 12 connected in the same way as Figure 1 is omitted.

[0138] The semiconductor device 10F is different from the semiconductor device 10A in terms of including the protection circuit 20F instead of the protection circuit 20A and including the step-down circuit 35 instead of the step-down circuit 15, but is substantially the same in other aspects. The protection circuit 20F is different from the protection circuit 20A in that different (independent) nodes N5 and N6 are formed at the gates of the NMOS transistor 21 and the NMOS transistor 22, respectively, but is substantially the same in other aspects. The step-down circuit 35 as a gate voltage control circuit is a step-down circuit capable of outputting two independent voltages. As Figure 11 illustrates, it has one step-down circuit 15 and one step-down circuit 25.

[0139] In addition, Figure 11 The illustrated step-down circuit 35 is an example in which the step-down circuit 25 for supplying voltage to the gate of the NMOS transistor 22 is connected between the node N1 and the node N2, but is not limited thereto. The step-down circuit 25 for supplying voltage to the gate of the NMOS transistor 22 may be connected to the node N3 instead of the node N2. In addition, Figure 11 The illustrated step-down circuit 35 is an example having one step-down circuit 15 and one step-down circuit 25, but is not limited thereto. The step-down circuit 35 may have two step-down circuits 15 or two step-down circuits 25.

[0140] In addition, the protection circuits 20A to 20F and the semiconductor devices 10A to 10F have been described by taking the case where the first conductivity type and the second conductivity type are P-type and N-type respectively and VDD is a positive voltage in the stable state as an example. However, the conductivity type (P-type and N-type) of the semiconductor substrate 50, the polarities of the polar components such as the NMOS transistor 21 and the NMOS transistor 22, and the polarities of the power supply voltage (positive and negative) can be changed to be used as the protection circuit and the semiconductor device of the present embodiment.

[0141] These embodiments or their modifications are included in the scope or gist of the invention and are included in the invention described in the claims and its equivalents.

Claims

1. A protection circuit, formed on a semiconductor substrate having a triple-well structure including a substrate region of a first conductivity type, an isolation wall region, and a well region of the first conductivity type in at least a portion thereof, and protecting a protected circuit from a power supply voltage having a polarity opposite to that in a stable state, wherein the isolation wall region is formed on the substrate region and includes a semiconductor region of a second conductivity type in at least a portion thereof, and the well region of the first conductivity type is formed inside the well region surrounded by the isolation wall region, wherein the protection circuit is characterized in that: The protected circuit includes a noise generating source and has a first circuit and a second circuit, wherein the first circuit is between a first power supply terminal and a second power supply terminal and is connected to the second power supply terminal via the protection circuit, and the second circuit is between the first power supply terminal and the second power supply terminal and is connected in parallel to the first circuit via the protection circuit, and on the other hand, The protection circuit comprises a first protection transistor and a second protection transistor. The first protection transistor includes a drain connected to the second power supply terminal, a gate receiving a first control voltage, and a source and a back gate connected to the first circuit. The second protection transistor includes a drain connected to the drain of the first protection transistor, a gate receiving a second control voltage, and a source and a back gate that are not connected to a connection point between the source and the back gate of the first protection transistor and the first circuit and are connected to the second circuit. At least one of the first protection transistor and the second protection transistor is formed in the well region, A drain of the protection transistor formed in the well region is connected to any one of the semiconductor region and the substrate region included in the isolation wall region surrounding the well region.

2. The protection circuit according to claim 1, wherein: The drain of the protection transistor formed in the well region is connected to the substrate region and further connected to the second power supply terminal. The isolation wall region surrounding the well region where the protection transistor is formed is floating and is not connected to any terminal.

3. The protection circuit according to claim 1, wherein: A drain of the protection transistor formed in the well region is connected to the isolation wall region surrounding the well region, and further connected to the second power supply terminal.

4. The protection circuit according to any one of claims 1 to 3, wherein: The protection circuit has a common node formed by connecting a gate of the second protection transistor and a gate of the first protection transistor.

5. The protection circuit according to claim 4 further includes a gate voltage control circuit, which has an output terminal that outputs a specified voltage as the first control voltage and the second control voltage, and is connected between the first power supply terminal and the source and back gate of the second protection transistor and the connection point of the second circuit.

6. The protection circuit according to any one of claims 1 to 3, further comprising a gate voltage control circuit connected between the first power supply terminal and a connection point between the source and back gate of the second protection transistor and the second circuit, The gate voltage control circuit has a first output terminal that outputs the first control voltage and a second output terminal that outputs the second control voltage.

7. The protection circuit according to any one of claims 1 to 3, further comprising a gate voltage control circuit, wherein the gate voltage control circuit outputs the first control voltage and the second control voltage. The gate voltage control circuit has a first output terminal and a second output terminal. The first output terminal is provided between the first power supply terminal and a connection point between the source and back gate of the first protection transistor and the first circuit, and outputs the first control voltage. The second output terminal is provided between the first power supply terminal and a connection point between the source and back gate of the second protection transistor and the second circuit, and outputs the second control voltage.

8. A semiconductor device, characterized in that: The invention comprises a semiconductor integrated circuit formed on a semiconductor substrate having a triple-well structure including a substrate region of a first conductivity type, a partition wall region of a second conductivity type, and a well region of the first conductivity type in at least a portion thereof, wherein the partition wall region of the second conductivity type is formed in the substrate region, and the well region of the first conductivity type is formed inside the well region surrounded by the partition wall region. The semiconductor integrated circuit includes a protection circuit that protects a connected protected circuit from being affected by application of a power supply voltage having a polarity opposite to that in a stable state, The protected circuit includes a noise generating source and has a first circuit and a second circuit, wherein the first circuit is between a first power supply terminal and a second power supply terminal and is connected to the second power supply terminal via the protection circuit, and the second circuit is between the first power supply terminal and the second power supply terminal and is connected in parallel to the first circuit via the protection circuit, and on the other hand, The protection circuit comprises a first protection transistor and a second protection transistor. The first protection transistor includes a drain connected to the second power supply terminal, a gate receiving a first control voltage, and a source and a back gate connected to the first circuit. The second protection transistor includes a drain connected to the drain of the first protection transistor, a gate receiving a second control voltage, and a source and a back gate that are not connected to a connection point between the source and the back gate of the first protection transistor and the first circuit and are connected to the second circuit. At least one of the first protection transistor and the second protection transistor is formed in the well region, A drain of the protection transistor formed in the well region is connected to any one of the isolation wall region surrounding the well region and the substrate region.

9. The semiconductor device according to claim 8, wherein: The semiconductor integrated circuit further includes a gate voltage control circuit connected between the first power supply terminal and a connection point between the source and back gate of the second protection transistor and the second circuit. The gate voltage control circuit includes an output terminal that outputs at least one of the first control voltage and the second control voltage.

10. The semiconductor device according to claim 8, wherein The semiconductor integrated circuit further includes a gate voltage control circuit, the gate voltage control circuit outputting the first control voltage and the second control voltage. The gate voltage control circuit has a first output terminal and a second output terminal. The first output terminal is provided between the first power supply terminal and a connection point between the source and back gate of the first protection transistor and the first circuit, and outputs the first control voltage. The second output terminal is provided between the first power supply terminal and a connection point between the source and back gate of the second protection transistor and the second circuit, and outputs the second control voltage.

Images