Anti-quantum cryptography algorithm FPGA structure and anti-quantum cryptography operation method

Abstract

The invention provides an FPGA structure of an anti-quantum cryptography algorithm and an anti-quantum cryptography operation method.The FPGA structure comprises a data flow detection logic module, a control logic module, a storage module and an algorithm logic module, the storage module comprises a read-only storage unit and 2n + 2 access units, and the algorithm logic module comprises n + 1 parallel butterfly logic operation units, n is an integer greater than or equal to 1. A parallelism degree control signal is determined through a data flow detection logic module, so that the control logic module performs data access control based on the parallelism degree control signal, butterfly operation of input data to be processed is realized, an FPGA structure can dynamically adjust the parallelism degree according to the flow of the input data, and when the data volume is relatively large, the data access control is realized. When the data volume is small, the parallelism is increased, namely, the number of the butterfly logic operation units is increased, when the data volume is small, the parallelism is reduced, namely, the number of the butterfly logic operation units is reduced, and therefore efficient utilization of resources is achieved.

Description

Technical Field

[0001] The present invention relates to the field of cryptographic application technology, and in particular to an FPGA structure of an anti-quantum cryptographic algorithm and an anti-quantum cryptographic operation method. Background Art

[0002] In modern cryptography, post-quantum cryptography (PQC) algorithms are gradually becoming a hot topic of research. The ML-KEM algorithm is a public key encryption scheme based on lattice theory. In order to meet the requirements of high efficiency and low latency, it is usually necessary to implement acceleration on hardware. NTT (Number Theoretic Transform) is a key step in the ML-KEM algorithm, which is used to accelerate polynomial multiplication.

[0003] However, the traditional NTT algorithm has performance bottlenecks in hardware implementation. According to the derivation of the algorithm principle, the performance limitations of the NTT algorithm are mainly due to the following reasons: the loop algorithm process in the NTT algorithm is too long, resulting in the loop stage taking up too much algorithm operation time, resulting in poor operation performance; the butterfly operation recursive stage in the NTT algorithm requires modular operation for each operation in turn, but on the one hand, there are few dedicated modular operation resources, and on the other hand, the modular operation delay is long, resulting in resource and performance bottlenecks. The traditional FPGA implementation method is often a fixed parallelism and fixed resource configuration method, which cannot adjust the hardware parallelism and operation resource utilization in real time according to the data flow, resulting in waste of resources in low-load scenarios and limited operation in high-load scenarios. It does not have flexible adaptation capabilities and dynamic optimization potential. Summary of the invention

[0004] The purpose of the present invention is to provide an FPGA structure of a quantum-resistant cryptographic algorithm and a quantum-resistant cryptographic operation method to address the deficiencies in the above-mentioned prior art, so as to determine the parallelism control signal through a data flow detection logic module, so that the control logic module performs data access control based on the parallelism control signal, that is, determines the number of butterfly logic operation units that need to perform butterfly operation, thereby realizing butterfly operation on the input data to be processed.

[0005] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0006] In a first aspect, an embodiment of the present application provides an FPGA structure of an anti-quantum cryptographic algorithm, the FPGA structure comprising: a data flow detection logic module, a control logic module, a storage module and an algorithm logic module, the storage module comprising: a read-only storage unit, 2n+2 access units, the algorithm logic module comprising: parallel n+1 butterfly logic operation units, n is an integer greater than or equal to 1;

[0007] The input end of the data traffic detection logic module is used to perform traffic detection on the input data to be processed, and obtain a parallelism control signal; the first output end of the data traffic detection logic module is connected to the control logic module to output the parallelism control signal to the control logic module; the second output end of the data traffic detection logic module is further connected to the 2n + 2 access units to store the input data;

[0008] The control logic module is connected to the read-only storage unit and the 2n + 2 access units to perform data access control based on the parallelism control signal; the read-only storage unit is connected to the first input end of the n + 1 butterfly logic operation units, the 2n + 2 access units are connected to the input end of each of the 2n + 2 first selectors, and the output ends of every two of the 2n + 2 first selectors are respectively connected to the second input end and the third input end of a butterfly logic operation unit; the output ends of the n + 1 butterfly logic operation units are connected to the input end of each of the 2n + 2 second selectors, and the output end of each second selector is connected to an access unit;

[0009] The control logic module is further connected to the control interfaces of the n + 1 butterfly logic operation units to control the target butterfly logic operation unit to perform butterfly operations based on the parallelism control signal.

[0010] In an alternative embodiment, the data traffic detection logic module includes: a data statistics logic circuit, a comparison and control logic circuit, and a parallelism operation logic circuit. The input end of the data statistics logic circuit is used to perform data statistics on the input data to be processed to obtain average data; the output end of the data statistics logic circuit is connected to the input end of the comparison and control logic circuit and the first input end of the parallelism operation logic circuit, so that the comparison and control logic circuit generates an operation control signal based on the average data;

[0011] The output end of the comparison and control logic circuit is further connected to the second input end of the parallelism operation logic circuit, so that the comparison and control logic circuit performs parallelism operation according to the operation control signal and the average data to obtain the parallelism control signal.

[0012] In an alternative embodiment, the data statistics logic circuit includes: a counter and an averaging logic circuit. The input end of the counter is the input end of the data statistics logic circuit, the output end of the counter is connected to the input end of the averaging logic circuit, and the output end of the averaging logic circuit is the output end of the data statistics logic circuit.

[0013] In an alternative embodiment, the comparison and control logic circuit includes: a comparator, a register, and a state machine logic unit. The input end of the comparator is the input end of the comparison and control logic circuit, and the input end of the comparator is also connected to the output end of the register; the input end of the comparator is connected to the input end of the state machine logic unit, and the output end of the state machine logic unit is the output end of the comparison and control logic circuit.

[0014] In an alternative embodiment, the input end of the data traffic detection logic module is further connected to the 2n + 2 access units.

[0015] In an alternative embodiment, each butterfly logic operation unit includes: a multiplier, a modular multiplication operator, an adder, a subtractor, a first modulo operator, and a second modulo operator; wherein, the two input ends of the multiplier are respectively connected to the first input end and the second input end of each butterfly logic operation unit, the output interface of the multiplier is connected to the input end of the modular multiplication operator, the output end of the modular multiplication operator is respectively connected to the first input end of the adder and the first input end of the subtractor, and the second input ends of the adder and the subtractor are both connected to the third input end of each butterfly logic operation unit;

[0016] The output end of the adder and the output end of the subtractor are respectively connected to the input ends of the first modulo operator and the second modulo operator, and the output ends of the first modulo operator and the second modulo operator are respectively connected to the output end of each butterfly logic operation unit.

[0017] In an alternative embodiment, each butterfly logic operation unit further includes: three input buffer units, an intermediate buffer unit, and two output buffer units. The two input ends of the multiplier are respectively connected to the first input end and the second input end of each butterfly logic operation unit through two input buffer units, and the third input end of each butterfly logic operation unit is connected to the second input ends of the adder and the subtractor through other input buffer units;

[0018] The output end of the modular multiplication operator is respectively connected to the first input end of the adder and the first input end of the subtractor through the intermediate buffer unit;

[0019] The output ends of the first modulo operator and the second modulo operator are respectively connected to the output end of each butterfly logic operation unit through the two output buffer units.

[0020] In a second aspect, an embodiment of the present application further provides a quantum-resistant cryptographic operation method based on an FPGA structure, which is applied to the FPGA structure described in any one of the above first aspects. The method includes:

[0021] Use the data traffic detection module in the FPGA structure to perform traffic detection on the input data of the current round, obtain the parallelism control signal of the current round, and store the input data of the current round into multiple target access units corresponding to the current round in 2n + 2 access units in the FPGA structure; the multiple target access units corresponding to the current round are the multiple target access units indicated by the parallelism control signal of the current round.

[0022] Use the control logic module in the FPGA structure to control the multiple target butterfly logic operation units of the current round to respectively read the input data from the corresponding multiple target access units according to the parallelism control signal of the current round.

[0023] Use the multiple target butterfly logic operation units to perform parallel butterfly operations on the input data of the current round, and store their respective butterfly logic operation data as the butterfly operation data of the current round into the target access units corresponding to the current round, where the multiple target butterfly logic operation units of the current round are the multiple butterfly logic operation units indicated by the parallelism control signal of the current round.

[0024] In an alternative embodiment, before using the data traffic detection module in the FPGA structure to perform traffic detection on the input data of the current round and obtain the parallelism control signal of the current round, the method further includes:

[0025] If the current round is the first round, use the data traffic detection module to use the externally input data as the input data of the current round.

[0026] If the current round is not the first round, use the data traffic detection module to read the butterfly operation data of the previous round from the multiple target access units corresponding to the previous round as the input data of the current round.

[0027] In an alternative embodiment, using the multiple target butterfly logic operation units to perform parallel butterfly operations on the input data of the current round includes:

[0028] Use the multiple target butterfly logic operation units to respectively determine the target storage addresses corresponding to the multiple target butterfly logic operation units from the read-only storage units in the storage module in the FPGA structure according to the identifiers of the multiple target butterfly logic operation units and the current round.

[0029] Use the multiple target butterfly logic operation units to respectively obtain the corresponding butterfly operation control parameters from the corresponding target storage addresses.

[0030] The multiple target butterfly logic operation units perform parallel butterfly operations on the input data of the current round by using the corresponding butterfly operation control parameters.

[0031] The beneficial effects of this application are:

[0032] The embodiment of this application provides an FPGA structure for an anti-quantum cryptographic algorithm and an anti-quantum cryptographic operation method. The FPGA structure includes: a data traffic detection logic module, a control logic module, a storage module, and an algorithm logic module. The storage module includes: a read-only storage unit, 2n + 2 access units. The algorithm logic module includes: n + 1 parallel butterfly logic operation units, where n is an integer greater than or equal to 1. The input end of the data traffic detection logic module is used to perform traffic detection on the input data to be processed to obtain a parallelism control signal; the first output end of the data traffic detection logic module is connected to the control logic module to output the parallelism control signal to the control logic module; the second output end of the data traffic detection logic module is also connected to 2n + 2 access units to store the input data. The control logic module is connected to the read-only storage unit and 2n + 2 access units to perform data access control based on the parallelism control signal; the read-only storage unit is connected to the first input ends of n + 1 butterfly logic operation units, 2n + 2 access units are connected to the input ends of each of 2n + 2 first selectors, and the output ends of every two of the 2n + 2 first selectors are respectively connected to the second input end and the third input end of a butterfly logic operation unit; the output ends of n + 1 butterfly logic operation units are connected to the input ends of each of 2n + 2 second selectors, and the output end of each second selector is connected to an access unit. The control logic module is also connected to the control interfaces of n + 1 butterfly logic operation units to control the target butterfly logic operation units to perform butterfly operations based on the parallelism control signal.

[0033] The FPGA structure provided by this application realizes the determination of the parallelism control signal through the data traffic detection logic module, so that the control logic module performs data access control based on the parallelism control signal, that is, determines the number of butterfly logic operation units that need to perform butterfly operations, thereby realizing the butterfly operation on the input data to be processed. In addition, this FPGA structure can dynamically adjust the parallelism according to the traffic of the input data, that is, obtain the parallelism control signal. When the data volume is large, increase the parallelism, that is, increase the number of butterfly logic operation units to perform butterfly operations. When the data volume is small, decrease the parallelism, that is, reduce the number of butterfly logic operation units to perform butterfly operations, thereby reducing power consumption and realizing the efficient use of resources. Description of the Drawings

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0035] Figure 1 Schematic diagram of an FPGA structure for an anti - quantum cryptographic algorithm provided by an embodiment of the present application;

[0036] Figure 2 Schematic diagram of a data traffic detection logic module provided by an embodiment of the present application;

[0037] Figure 3 Schematic diagram of a butterfly logic operation unit provided by an embodiment of the present application;

[0038] Figure 4 Schematic diagram of a flow for an anti - quantum cryptographic operation method based on an FPGA structure provided by an embodiment of the present application;

[0039] Figure 5 Schematic diagram of a flow for another anti - quantum cryptographic operation method based on an FPGA structure provided by an embodiment of the present application;

[0040] Figure 6 Schematic diagram of obtaining control parameters for butterfly operations provided by an embodiment of the present application;

[0041] Figure 7 Schematic diagram of read - write logic of an access unit provided by an embodiment of the present application. Detailed implementation manners

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention.

[0043] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0044] In the description of the present application, it should be noted that if terms such as "upper", "lower", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the products of this application are customarily placed during use, it is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0045] In addition, terms such as "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0046] It should be noted that, without conflict, the features in the embodiments of the present application can be combined with each other.

[0047] To better understand the solutions provided in the following embodiments of the present application, here, the technical terms involved in the following embodiments of the present application are first explained.

[0048] FPGA (Field-Programmable Gate Array): Field Programmable Gate Array, an integrated circuit that can be programmed.

[0049] NTT (Number Theoretic Transform): In mathematics and computer science, this is an algorithm similar to the Fourier transform, mainly used for fast multiplication calculation of polynomials. It plays a key role in modern cryptography, especially in implementing fast and secure large integer multiplication operations, such as in certain forms of encryption and hash algorithms.

[0050] PQC (Post-Quantum Cryptography): Refers to cryptographic methods that remain secure after the emergence of quantum computers. Such cryptographic technologies aim to develop encryption algorithms based on mathematical problems that are difficult to solve by quantum computers to resist the potential threats of future quantum computers to current encryption technologies, such as encryption technologies based on lattices, codes, or multivariate polynomials.

[0051] ML-KEM: A post-quantum cryptographic algorithm that enhances the security of key transmission and storage by encapsulating keys at multiple levels. Each level of encapsulation uses a different key, increasing the difficulty of cracking and ensuring more secure and reliable key management in scenarios with high security requirements.

[0052] Butterfly Operation: A basic computational unit used in the Fast Fourier Transform (FFT) and the Discrete Number Theoretic Transform (NTT) to achieve efficient transformation of signals and data. It recursively decomposes and recombines data through specific combinations and calculations of data points, significantly reducing the complexity of the entire transformation process.

[0053] To improve algorithm performance and reduce hardware resource consumption, this application provides an FPGA architecture for an anti-quantum cryptographic algorithm. The FPGA architecture includes: a data traffic detection logic module, a control logic module, a storage module, and an algorithm logic module. The storage module includes: a read-only storage unit and 2n + 2 access units. The algorithm logic module includes: n + 1 parallel butterfly logic operation units, where n is an integer greater than or equal to 1. The data traffic detection logic module dynamically adjusts the parallelism based on the received input data. When the data volume is large, the parallelism is increased, i.e., the number of butterfly logic operation units is increased for butterfly operations. When the data volume is small, the parallelism is decreased, i.e., the number of butterfly logic operation units is decreased for butterfly operations, thereby reducing power consumption and achieving efficient utilization of resources.

[0054] The following uses multiple examples in combination with the accompanying drawings to illustrate the FPGA architecture of the anti-quantum cryptographic algorithm provided by this application. Figure 1 It is a schematic diagram of an FPGA architecture for an anti-quantum cryptographic algorithm provided by an embodiment of this application, as Figure 1 shown. The FPGA architecture includes: a data traffic detection logic module, a control logic module, a storage module, and an algorithm logic module. The storage module includes: a read-only storage unit and 2n + 2 access units. The algorithm logic module includes: n + 1 parallel butterfly logic operation units, where n is an integer greater than or equal to 1.

[0055] The input end of the data traffic detection logic module is used to detect the traffic of the input data to be processed and obtain a parallelism control signal. The first output end of the data traffic detection logic module is connected to the control logic module to output the parallelism control signal to the control logic module. The second output end of the data traffic detection logic module is also connected to 2n + 2 access units to store the input data.

[0056] In this embodiment, the read-only storage unit in the storage module is used to store some fixed data, such as constants, coefficients, etc. required in the algorithm. These data will not change during the entire operation process. For example, the read-only storage unit stores the butterfly operation control parameters required for the butterfly operation of n + 1 butterfly logic operation units, that is, the rotation factors. The 2n + 2 access units in the storage module are used to temporarily store input data and intermediate operation results. Data storage and reading can be performed according to the parallelism control signal.

[0057] The input end of the data flow detection logic module receives the input data to be processed and performs flow detection on it. The purpose of flow detection is to determine the parallelism of the input data, that is, how many data can be processed simultaneously, so as to obtain the parallelism control signal. The first output end of the data flow detection logic module sends the parallelism control signal to the control logic module, so that the control logic module can control the storage module and the algorithm logic module according to the parallelism control signal. The second output end of the data flow detection logic module stores the input data into the 2n + 2 access units, so that the butterfly logic operation unit can obtain the input data from the access units.

[0058] The control logic module is connected to the read-only storage unit and the 2n + 2 access units to perform data access control based on the parallelism control signal; the read-only storage unit is connected to the first input ends of n + 1 butterfly logic operation units, the 2n + 2 access units are connected to the input ends of each of the 2n + 2 first selectors, and the output ends of every two of the 2n + 2 first selectors are respectively connected to the second input end and the third input end of a butterfly logic operation unit; the output ends of the n + 1 butterfly logic operation units are connected to the input ends of each of the 2n + 2 second selectors, and the output end of each second selector is connected to an access unit.

[0059] Among them, the butterfly logic operation unit is a common operation structure, which is often used in signal processing and cryptographic algorithms, and it can efficiently complete specific mathematical operations. In the quantum-resistant cryptographic algorithm, these butterfly logic operation units work in parallel, which improves the operation speed of the algorithm. Since each butterfly logic operation unit corresponds to two access units, in the FPGA structure, if the number of butterfly logic operation units is n + 1, then the number of access units is 2n + 2.

[0060] The control logic module is also connected to the control interfaces of the n + 1 butterfly logic operation units to control the target butterfly logic operation unit to perform butterfly operations based on the parallelism control signal.

[0061] Specifically, the control logic module is connected to the read-only storage unit and 2n + 2 access units. It determines the number of butterfly logic operation units according to the parallelism control signal, specifically which access units the butterfly logic operation units read input data from, and after the butterfly operation, to which access units the operation results are stored, so as to achieve effective control of data access.

[0062] The number of the first selectors corresponds to the number of access units. Each first selector has 2n + 2 input terminals for obtaining input data from 2n + 2 access units, but each first selector has only one output terminal. The control logic module controls each first selector to select the input data of one access unit according to the parallelism control signal, and sends the selected input data to the connected butterfly logic operation unit through the output terminal. Since the second input terminal Y and the third input terminal X of each butterfly logic operation unit are respectively connected to two first selectors, each butterfly logic operation unit can receive two input data sent by the two selectors after selecting the input data of 2n + 2 access units. The first input terminal Z of each butterfly logic operation unit is also connected to the read-only storage unit for obtaining the butterfly operation control parameters, so that each butterfly logic operation unit can perform the butterfly operation according to the two received input data and the butterfly operation control parameters to obtain the operation result.

[0063] The output terminal of each butterfly logic operation unit is connected to the input terminal of each of the 2n + 2 second selectors. Each second selector can receive the operation result of each butterfly logic operation unit. The output terminal of each second selector is connected to an access unit, so that the control logic module can store the operation result of each butterfly logic operation unit to the corresponding access unit based on the parallelism control signal. For example, the access units corresponding to the butterfly logic operation unit 0 are the access unit RAM0 and the access unit RAM1. After the butterfly logic operation unit 0 performs the butterfly operation, obtains the operation result and sends it to each second selector, the control logic module can control the second selector 0 to store the operation result to the access unit RAM0 connected to the second selector 0 based on the parallelism control signal.

[0064] Optionally, the input terminal of the data flow detection logic module is also connected to 2n + 2 access units.

[0065] Among them, the parallelism control signal includes the value of the parallelism and the number of rounds of performing the butterfly operation. The data flow detection logic module obtains the data for the next round of butterfly operation from 2n + 2 access units to perform flow detection on the data for the next round of butterfly operation, obtains the parallelism control signal for the next round, and then sends the parallelism control signal for the next round to the control logic module, so that the control logic module performs data access control based on the parallelism control signal for the next round.

[0066] In summary, the embodiment of the present application provides an FPGA structure for an anti-quantum cryptographic algorithm. The FPGA structure includes: a data traffic detection logic module, a control logic module, a storage module, and an algorithm logic module. The storage module includes: a read-only storage unit, 2n + 2 access units. The algorithm logic module includes: n + 1 parallel butterfly logic operation units, where n is an integer greater than or equal to 1. The input end of the data traffic detection logic module is used to perform traffic detection on the input data to be processed to obtain a parallelism control signal. The first output end of the data traffic detection logic module is connected to the control logic module to output the parallelism control signal to the control logic module. The second output end of the data traffic detection logic module is also connected to 2n + 2 access units to store the input data. The control logic module is connected to the read-only storage unit and 2n + 2 access units to perform data access control based on the parallelism control signal. The read-only storage unit is connected to the first input ends of n + 1 butterfly logic operation units. The 2n + 2 access units are connected to the input ends of each of the 2n + 2 first selectors. The output ends of every two of the 2n + 2 first selectors are respectively connected to the second input end and the third input end of a butterfly logic operation unit. The output ends of n + 1 butterfly logic operation units are connected to the input ends of each of the 2n + 2 second selectors. The output end of each second selector is connected to an access unit. The control logic module is also connected to the control interfaces of n + 1 butterfly logic operation units to control the target butterfly logic operation unit to perform butterfly operations based on the parallelism control signal.

[0067] The FPGA structure provided by the present application realizes the determination of the parallelism control signal through the data traffic detection logic module, so that the control logic module performs data access control based on the parallelism control signal, that is, determines the number of butterfly logic operation units that need to perform butterfly operations, thereby realizing the butterfly operations on the input data to be processed. In addition, the FPGA structure can dynamically adjust the parallelism according to the traffic of the input data, that is, obtain the parallelism control signal. When the data volume is large, the parallelism is increased, that is, the number of butterfly logic operation units is increased to perform butterfly operations. When the data volume is small, the parallelism is reduced, that is, the number of butterfly logic operation units is reduced to perform butterfly operations, thereby reducing power consumption and realizing the efficient utilization of resources.

[0068] The embodiment of the present application also provides another possible implementation manner of the FPGA structure for an anti-quantum cryptographic algorithm. Figure 2 It is a schematic diagram of a data traffic detection logic module provided by the embodiment of the present application, as Figure 2As shown in the figure, the data traffic detection logic module includes: a data statistics logic circuit, a comparison and control logic circuit, and a parallelism operation logic circuit. The input end of the data statistics logic circuit is used to perform data statistics on the input data to be processed, and obtain the average data. The output end of the data statistics logic circuit is connected to the input end of the comparison and control logic circuit and the first input end of the parallelism operation logic circuit, so that the comparison and control logic circuit generates an operation control signal based on the average data.

[0069] The output end of the comparison and control logic circuit is also connected to the second input end of the parallelism operation logic circuit, so that the comparison and control logic circuit performs parallelism operation according to the operation control signal and the average data, and obtains a parallelism control signal.

[0070] In this embodiment, the core of the data traffic detection logic module is to perform statistics and processing on the input data to be processed within the time window ΔT, and then obtain the parallelism control signal to achieve dynamic optimization of the hardware resources. This module consists of three parts: a data statistics logic circuit, a comparison and control logic circuit, and a parallelism operation logic circuit. Each part cooperates with each other to complete the analysis of the input data and the determination of the parallelism control signal.

[0071] Optionally, the data statistics logic circuit includes: a counter and an averaging logic circuit. The input end of the counter is the input end of the data statistics logic circuit. The output end of the counter is connected to the input end of the averaging logic circuit. The output end of the averaging logic circuit is the output end of the data statistics logic circuit.

[0072] Among them, the counter accumulates the input data Data_in to be processed within the time window ΔT, and inputs the accumulated result into the averaging logic circuit for averaging calculation to obtain the average data Data avg .

[0073] Specifically, the calculation formula of the average data Data avg is:

[0074]

[0075] Optionally, the comparison and control logic circuit includes: a comparator, a register, and a state machine logic unit. The input end of the comparator is the input end of the comparison and control logic circuit. The input end of the comparator is also connected to the output end of the register. The input end of the comparator is connected to the input end of the state machine logic unit. The output end of the state machine logic unit is the output end of the comparison and control logic circuit.

[0076] Among them, the register stores a preset high-load threshold Threshold H , a low-load threshold Threshold L , and the upper and lower limits of parallelism Pmin and P max and other parameters, input the average data Data avg and the high load threshold Threshold H , the low load threshold Threshold L , as well as the upper and lower limits of parallelism P min and P max and other parameters into the comparator circuit to obtain a comparison output signal, and input the comparison output signal into the state machine logic unit FSM. The state machine logic unit FSM selects a state according to the comparison output signal and generates an operation control signal.

[0077] Specifically, the calculated average data Data avg and the high load threshold Threshold H , the low load threshold Threshold L have the following comparison results:

[0078] If Data avg > Threshold H , then determine that the comparison output signal, i.e., the parallelism P = P max .

[0079] If Data avg < Threshold L , then determine that the comparison output signal, i.e., the parallelism P = P min .

[0080] If Threshold L ≤ Data avg ≤ Threshold H , then calculate the comparison output signal, i.e., the intermediate value P, through linear mapping:

[0081]

[0082] The data flow detection module internally adopts a state machine logic unit (FSM) control structure, transfers between different states according to the comparison result of Data avg and the threshold, and outputs the corresponding parallelism control signal to achieve closed-loop regulation.

[0083] Specifically, different states are defined as follows:

[0084] LOW state: indicates that the current load is low, and the state machine logic unit FSM outputs P min parallelism control signal;

[0085] MID state: indicates that the load is in the medium range, and the state machine logic unit FSM calculates the appropriate parallelism P value according to the formula;

[0086] HIGH state: indicates a relatively high load, and the state machine logic unit FSM outputs P max Parallelism control signal.

[0087] The state transition conditions are as follows:

[0088] At the end of each time window ΔT cycle, the state machine logic unit FSM updates the state according to the average data Data avg Update state:

[0089] If Data avg > Threshold H : Transition to or remain in the HIGH state;

[0090] If Data avg < Threshold L : Transition to or remain in the LOW state;

[0091] If Threshold L ≤ Data avg ≤ Threshold H : Transition to or remain in the MID state and calculate the intermediate parallelism value.

[0092] Through the control association of this state machine logic unit FSM, when the external load changes, the parallelism configuration is dynamically updated in the next time window ΔT cycle, realizing an adaptive response to the change of data traffic.

[0093] Among them, the parallelism operation logic circuit, based on the operation control signal, calls basic arithmetic units such as addition, subtraction, and multiplication, and calculates the final parallelism control signal, that is, the parallelism P value according to the average data Data avg This P value is transmitted to the enable control line of the butterfly logic operation unit and the address generation circuit in the form of hardwiring or Boolean logic to adjust the access strategy of the storage module.

[0094] The data traffic detection logic module provided by the embodiment of the present application can dynamically adjust the parallelism control signal according to the input data, that is, the parallel number of the butterfly logic operation unit and the allocation method of storage resources. In a high-load scenario, that is, when the data volume is large, the parallelism is increased to improve the operation speed. In a low-load scenario, that is, when the data volume is small, the parallelism is reduced to reduce power consumption, thereby realizing the adaptive and efficient utilization of operation resources.

[0095] The embodiment of the present application also provides another possible implementation manner of the FPGA structure of the anti-quantum cryptographic algorithm, Figure 3 which is a schematic diagram of a butterfly logic operation unit provided by the embodiment of the present application, as Figure 3As shown in the figure, each butterfly logic operation unit includes: a multiplier, a modular multiplication arithmetic unit, an adder, a subtractor, a first modular arithmetic unit, and a second modular arithmetic unit; wherein, the two input terminals of the multiplier are respectively connected to the first input terminal and the second input terminal of each butterfly logic operation unit, the output interface of the multiplier is connected to the input terminal of the modular multiplication arithmetic unit, the output terminal of the modular multiplication arithmetic unit is respectively connected to the first input terminal of the adder and the first input terminal of the subtractor, and the second input terminal of the adder and the second input terminal of the subtractor are both connected to the third input terminal of each butterfly logic operation unit.

[0096] The output terminal of the adder and the output terminal of the subtractor are respectively connected to the input terminals of the first modular arithmetic unit and the second modular arithmetic unit, and the output terminals of the first modular arithmetic unit and the second modular arithmetic unit are respectively connected to the output terminal of each butterfly logic operation unit.

[0097] In this embodiment, the butterfly logic operation unit is the basic unit for implementing specific mathematical operations and plays an important role in the anti-quantum cryptography algorithm. This unit is mainly composed of a multiplier, a modular multiplication arithmetic unit, an adder, a subtractor, a first modular arithmetic unit, and a second modular arithmetic unit. Through the collaborative work of these components, specific operation tasks are completed.

[0098] The multiplier is used to perform a multiplication operation on two input data. In the butterfly logic operation unit, it receives the data from the first input terminal and the second input terminal of the butterfly logic operation unit, multiplies these two data, and transmits the result of the multiplication operation to the modular multiplication arithmetic unit. The modular multiplication arithmetic unit receives the output result of the multiplier and performs a modular multiplication operation on it. Modular multiplication is very important in cryptography and is often used to process the multiplication and modulo operation of large integers to ensure that the operation result is within a specific modulo space, and then the result of the modular multiplication operation is used as an input to the adder and the subtractor.

[0099] The adder and the subtractor respectively perform addition and subtraction operations on the output result of the modular multiplication arithmetic unit and the data from the third input terminal of the butterfly logic operation unit, and then respectively transmit the results of the addition and subtraction operations to the modular arithmetic unit.

[0100] The first modular arithmetic unit and the second modular arithmetic unit respectively perform modular operations on the output results of the adder and the subtractor to ensure that the final output result is within a specific modulo space, and use the result after the modular operation as the final output of the butterfly logic operation unit.

[0101] Among them, the first input terminal of each butterfly logic operation unit receives the butterfly operation control parameter ζ sent by the read-only storage unit k , where the second input terminal of each butterfly logic operation unit receives the input data transmitted by an access unit where The third input terminal of each butterfly logic operation unit receives the input data transmitted by another access unit Among them,

[0102] It is completed by a multiplier The operation is performed to obtain the result of the multiplication operation. The modular multiplication unit receives the output result of the multiplier and performs a modular multiplication operation on it to obtain the result of the modular multiplication operation. The addition operation is completed by an adder The operation is performed to obtain the result of the addition operation. The subtraction operation is completed by a subtractor The result of the subtraction operation is obtained.

[0103] The modular operation is completed by a first modular operation unit to obtain an output value of the butterfly logic operation unit. The modular operation is completed by a second modular operation unit to obtain another output value of the butterfly logic operation unit. The operation result of the butterfly logic operation unit includes two output values.

[0104] Optionally, each butterfly logic operation unit further includes: three input buffer units, an intermediate buffer unit, and two output buffer units. Two input terminals of the multiplier are respectively connected to the first input terminal and the second input terminal of each butterfly logic operation unit through two input buffer units. The third input terminal of each butterfly logic operation unit is connected to the second input terminal of the adder and the second input terminal of the subtractor through other input buffer units.

[0105] The output terminal of the modular multiplication unit is respectively connected to the first input terminal of the adder and the first input terminal of the subtractor through the intermediate buffer unit.

[0106] The output terminals of the first modular operation unit and the second modular operation unit are respectively connected to the output terminal of each butterfly logic operation unit through two output buffer units.

[0107] Specifically, continue to refer to Figure 3 , the main function of the buffer unit is to temporarily store data, and its purpose is to coordinate the data transfer speed between different modules to avoid data loss or operation errors caused by speed mismatches. Adding buffer units in the butterfly logic operation unit can improve the stability and efficiency of data processing.

[0108] Among them, the two input buffer units are respectively arranged between the two input terminals of the multiplier and the first and second input terminals of the butterfly logic operation unit; the other input buffer unit is arranged between the third input terminal of the butterfly logic operation unit and the second input terminals of the adder and the subtractor. The control logic module calls the storage module and reads in the butterfly operation control parameter ζ k , the input data and the input data and store them in three input buffer units respectively, which can ensure that the input data is transmitted to the corresponding arithmetic modules (multiplier, adder, and subtractor) at an appropriate time, preventing data conflicts or losses during transmission.

[0109] The intermediate buffer unit is located between the output end of the modular multiplication calculator and the first input ends of the adder and subtractor, and is used to temporarily store the output result of the modular multiplication calculator. Since the modular multiplication operation may be relatively complex and time-consuming, the intermediate buffer unit can save the operation result and wait until the adder and subtractor are ready to receive the data before transmitting it, thus ensuring the orderly flow of data and the accuracy of the operation.

[0110] Two output buffer units are respectively connected to the output ends of the first modular calculator and the second modular calculator, and are used to temporarily store the final result after the modular operation. In this way, the butterfly logic operation unit can stably output the processed data to the access unit, avoiding affecting the operation of the current unit due to the processing speed of the access unit.

[0111] The butterfly logic operation unit provided by the embodiment of the present application can more efficiently and stably complete the butterfly operation task through the collaborative work of the multiplier, modular multiplication calculator, adder, subtractor, first modular calculator, and second modular calculator.

[0112] The embodiment of the present application also provides a quantum-resistant cryptographic operation method based on the FPGA structure, which is applied to the FPGA structure. Figure 4 is a schematic flowchart of a quantum-resistant cryptographic operation method based on the FPGA structure provided by the embodiment of the present application, as Figure 4 shown, the method includes:

[0113] S101. Use the data traffic detection module in the FPGA structure to perform traffic detection on the input data of the current round, obtain the parallelism control signal of the current round, and store the input data of the current round in multiple target access units corresponding to the current round in 2n + 2 access units in the FPGA structure.

[0114] Among them, the multiple target access units corresponding to the current round are the multiple target access units indicated by the parallelism control signal of the current round.

[0115] S102. Use the control logic module in the FPGA structure to control the multiple target butterfly logic operation units of the current round to respectively read the input data from the corresponding multiple target access units according to the parallelism control signal of the current round.

[0116] S103. Use multiple target butterfly logic operation units to perform parallel butterfly operations on the input data of the current round, and store the respective butterfly logic operation data as the butterfly operation data of the current round into the target access units corresponding to the current round.

[0117] Among them, the multiple target butterfly logic operation units of the current round are the multiple butterfly logic operation units indicated by the parallelism control signal of the current round.

[0118] In this embodiment, use the data traffic detection module in the FPGA structure to perform traffic detection on the input data of the current round, and obtain the parallelism control signal of the current round.

[0119] Specifically, the calculator in the data traffic detection module accumulates the input data of the current round within the time window ΔT, inputs the accumulated result into the averaging logic circuit for averaging calculation to obtain the average data. Then, the comparator circuit compares the average data with the high load threshold and the low load threshold to obtain a comparison output signal. The state machine logic unit FSM selects a state according to the comparison output signal and generates an operation control signal. Finally, use the parallelism operation logic circuit. Based on the operation control signal, call basic arithmetic units such as addition, subtraction, and multiplication, and calculate the parallelism control signal of the current round according to the average data.

[0120] According to the parallelism control signal, determine the multiple target butterfly logic operation units that need to be parallel in the current round, and further determine the multiple target access units corresponding to the multiple target butterfly logic operation units. Then, store the input data of the current round into the multiple target access units in the FPGA structure.

[0121] Use the control logic module in the FPGA structure to control the multiple target butterfly logic operation units of the current round according to the parallelism control signal of the current round. The control logic module will determine that the multiple target butterfly logic operation units participate in the operation of the current round according to the parallelism control signal, and control the multiple target butterfly logic operation units to read the input data from the corresponding multiple target access units respectively. This precise control ensures that each target butterfly logic operation unit can obtain the correct data and prepares for the subsequent operation.

[0122] Multiple target butterfly logic operation units simultaneously perform parallel butterfly operations on the input data of the current round. Since these target butterfly logic operation units work in parallel, the operation speed can be greatly improved. Each target butterfly logic operation unit performs specific mathematical operations on the input data to obtain its own butterfly logic operation data. The butterfly logic operation data obtained by each target butterfly logic operation unit is used as the butterfly operation data of the current round and stored in the target access unit corresponding to the current round. In this way, the operation results are properly saved and can be used for subsequent rounds of operations or final output.

[0123] It should be noted that, let be defined as the polynomial coefficient ring of modulus q and dimension n - 1. In the known ML-KEM algorithm, q = 3329 and n = 256.

[0124] Suppose there exists a polynomial

[0125]

[0126] where, f i is the polynomial array coefficient value, and the NTT transform operation formula is:

[0127]

[0128] where, ζ is the value of the rotation factor, which is the n-th primitive root of unity modulo q and satisfies ζ n mod q ≡ 1. Thus, the butterfly logic operation data of each target butterfly logic operation unit is obtained.

[0129] The embodiment of the present application also provides a possible implementation manner of a quantum-resistant cryptographic operation method based on the FPGA structure. Before using the data traffic detection module in the FPGA structure to detect the traffic of the input data of the current round and obtain the parallelism control signal of the current round, the method further includes:

[0130] If the current round is the first round, the data traffic detection module uses the external input data as the input data of the current round.

[0131] If the current round is not the first round, the data traffic detection module reads the butterfly operation data of the previous round from the multiple target access units corresponding to the previous round and uses it as the input data of the current round.

[0132] In this embodiment, if the current round is the first round, the data traffic detection module is used to obtain the externally input data and perform the butterfly operation in the first round. The current round is the first round. If the current round is not the first round, for example, the second round, the data traffic detection module reads the butterfly operation data in the first round from multiple target access units corresponding to the first round as the input data for the current round, that is, the input data for the second round, and performs the butterfly operation in the second round.

[0133] It should be noted that after the butterfly operation in one round is completed, the data traffic detection module performs data detection based on the output data of this round to determine the parallelism control signal, that is, to determine the number of butterfly logic operation units in parallel in the next round.

[0134] During parallel execution, if the data traffic decreases midway, the data traffic detection module can issue an instruction to perform clock gating or directly idle some butterfly operation units, thereby reducing power consumption. In a high-load scenario, the control logic module and the data traffic detection module work together to enable more butterfly unit resources in real time and improve the throughput and parallelism of the operation by quickly switching the read / write address mapping of the access unit RAM.

[0135] The embodiment of the present application also provides a possible implementation manner of a quantum-resistant cryptographic operation method based on the FPGA structure. Figure 5 It is a schematic flowchart of another quantum-resistant cryptographic operation method based on the FPGA structure provided by the embodiment of the present application. Figure 6 It is a schematic diagram of obtaining butterfly operation control parameters provided by the embodiment of the present application. Figure 7 It is a schematic diagram of the read / write logic of the access unit provided by the embodiment of the present application. As Figure 5 shown, multiple target butterfly logic operation units perform parallel butterfly operations on the input data of the current round, including:

[0136] S201: Use multiple target butterfly logic operation units to respectively determine the target storage addresses corresponding to the multiple target butterfly logic operation units from the read-only storage units in the storage module in the FPGA structure according to the identifiers of the multiple target butterfly logic operation units and the current round.

[0137] S202: Use multiple target butterfly logic operation units to respectively obtain the corresponding butterfly operation control parameters from the corresponding target storage addresses.

[0138] S203: Use multiple target butterfly logic operation units to perform parallel butterfly operations on the input data of the current round by using the corresponding butterfly operation control parameters.

[0139] In this embodiment, the read-only storage unit ROM allocates the butterfly operation control parameters, i.e., initializes the rotation factor ζ, according to the current butterfly operation round number and the target storage address. k For the parameters, the FPGA internally calls the butterfly operation control parameters by means of table lookup. The operation formula of the butterfly operation control parameter ζ k is as follows:

[0140] ζ k = ζ BitRev(k) mod q

[0141] where q = 3329, k ∈ [1:127], and BitRev(k) is the bit-reversal function operation.

[0142] As Figure 6 shown, a butterfly operation unit with dynamic parallelism is called. Taking the 8x parallelism as an example, the dimension k of the NTT operation is 128. Therefore, seven rounds of butterfly operations are required to complete a single NTT operation, and 8 butterfly logic operation units are needed. The read logic design steps of the rotation factor are as follows:

[0143] Step 1: The 8 butterfly logic operation units in the first round read the rotation factor ζ at address 1 1 and complete 128 butterfly operations in parallel.

[0144] Step 2: The 8 butterfly logic operation units in the second round read the rotation factor ζ at address 2 2 complete the first 64 butterfly operations, read the rotation factor ζ at address 3 3 and complete the last 64 butterfly operations.

[0145] Step 3: The 8 butterfly logic operation units in the third round read the rotation factor ζ at address 4 4 complete the first 32 butterfly operations, read the rotation factor ζ at address 5 5 complete up to 64 butterfly operations, read the rotation factor ζ at address 6 6 complete up to 96 butterfly operations, read the rotation factor ζ at address 7 7 and complete up to 128 butterfly operations.

[0146] Step 4: Similarly, according to the above operation rule, seven rounds of butterfly operations are completed.

[0147] It should be noted that taking the 8x parallelism butterfly logic operation unit as an example, the initialization design of the access unit RAM is as Figure 7As shown in the figure, when performing the first round of butterfly operations, the butterfly logic operation unit sequentially performs parallel access to the initialized coefficient values according to the address order through the access unit RAM. The even access unit RAMs (RAM0, RAM2... RAM14) correspond to the F[j] array, and the odd access unit RAMs (RAM1, RAM3... RAM15) correspond to the F[j + l] array. During the first round of butterfly operations, l = 128.

[0148] The control logic module reads the polynomial coefficient values in the corresponding address space from the RAM according to the call logic and timing of the NTT operation and sends them to the butterfly logic operation unit. After the operation is completed, the intermediate values are written into the corresponding address space in the access unit RAM. The steps for designing the read / write logic of the access unit RAM are as follows:

[0149] Step 1: Initialize the storage space of the access unit RAM. The initialized data is stored in buffer A and waits for the control logic module to read the data for the first round of butterfly operations.

[0150] Step 2: After the first round of butterfly operations is completed, the control logic module places the data in buffer B according to the data call address for the next round of butterfly operations and waits for the data to be read for the next round of butterfly operations.

[0151] Step 3: Buffer A and buffer B sequentially complete the data read / write operations. Among them, in odd rounds, buffer A is the data read area and buffer B is the write area. In even rounds, buffer A is the data write area and buffer B is the data read area.

[0152] In the method provided by this application, multiple target butterfly logic operation units can obtain the required control parameters from the read-only storage unit according to their own identifiers and the current round, and use these parameters to perform efficient parallel butterfly operations on the input data. This method ensures the accuracy and efficiency of the operation, enabling the FPGA structure to better handle the complex operation requirements in the post-quantum cryptography algorithm.

[0153] The above are only the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. An FPGA structure for quantum cryptographic algorithms, characterized in that: The FPGA structure includes: a data flow detection logic module, a control logic module, a storage module and an algorithm logic module, the storage module includes: a read-only storage unit, 2n+2 access units, the algorithm logic module includes: parallel n+1 butterfly logic operation units, n is an integer greater than or equal to 1; The input end of the data flow detection logic module is used to perform flow detection on the input data to be processed to obtain a parallelism control signal; the first output end of the data flow detection logic module is connected to the control logic module to output the parallelism control signal to the control logic module; the second output end of the data flow detection logic module is also connected to the 2n+2 access units to store the input data; The control logic module is connected to the read-only storage unit and the 2n+2 access units to perform data access control based on the parallelism control signal; the read-only storage unit is connected to the first input end of the n+1 butterfly logic operation units, the 2n+2 access units are connected to the input end of each first selector in the 2n+2 first selectors, and the output ends of every two first selectors in the 2n+2 first selectors are respectively connected to the second input end and the third input end of a butterfly logic operation unit; the output end of the n+1 butterfly logic operation unit is connected to the input end of each second selector in the 2n+2 second selectors, and the output end of each second selector is connected to an access unit; The control logic module is also connected to the control interfaces of the n+1 butterfly logic operation units to control the target butterfly logic operation unit to perform butterfly operation based on the parallelism control signal.

2. The FPGA structure according to claim 1, characterized in that: The data flow detection logic module includes: a data statistics logic circuit, a comparison and control logic circuit, and a parallelism operation logic circuit. The input end of the data statistics logic circuit is used to perform data statistics on the input data to be processed to obtain average data; the output end of the data statistics logic circuit is connected to the input end of the comparison and control logic circuit and the first input end of the parallelism operation logic circuit, so that the comparison and control logic circuit generates an operation control signal based on the average data; The output end of the comparison and control logic circuit is also connected to the second input end of the parallelism operation logic circuit, so that the comparison and control logic circuit performs parallelism operation according to the operation control signal and the average data to obtain the parallelism control signal.

3. The FPGA structure according to claim 2, characterized in that: The data statistics logic circuit includes: a counter and an averaging logic circuit. The input end of the counter is the input end of the data statistics logic circuit, the output end of the counter is connected to the input end of the averaging logic circuit, and the output end of the averaging logic circuit is the output end of the data statistics logic circuit.

4. The FPGA structure according to claim 2, characterized in that: The comparison and control logic circuit includes: a comparator, a register and a state machine logic unit, the input end of the comparator is the input end of the comparison and control logic circuit, and the input end of the comparator is also connected to the output end of the register; the input end of the comparator is connected to the input end of the state machine logic unit, and the output end of the state machine logic unit is the output end of the comparison and control logic circuit.

5. The FPGA structure according to claim 1, characterized in that: The input end of the data flow detection logic module is also connected to the 2n+2 access units.

6. The FPGA structure according to claim 1, characterized in that: Each butterfly logic operation unit includes: a multiplier, a modular multiplication operator, an adder, a subtractor, a first modular operator and a second modular operator; wherein the two input ends of the multiplier are respectively connected to the first input end and the second input end of each butterfly logic operation unit, the output interface of the multiplier is connected to the input end of the modular multiplication operator, the output end of the modular multiplication operator is respectively connected to the first input end of the adder and the first input end of the subtractor, and the second input end of the adder and the second input end of the subtractor are both connected to the third input end of each butterfly logic operation unit; The output end of the adder and the output end of the subtractor are respectively connected to the input ends of the first modulus operator and the second modulus operator, and the output ends of the first modulus operator and the second modulus operator are respectively connected to the output end of each butterfly logic operation unit.

7. The FPGA structure according to claim 6, characterized in that: Each butterfly logic operation unit further includes: three input buffer units, an intermediate buffer unit and two output buffer units, the two input ends of the multiplier are connected to the first input end and the second input end of each butterfly logic operation unit through the two input buffer units respectively, and the third input end of each butterfly logic operation unit is connected to the second input end of the adder and the second input end of the subtractor through other input buffer units; The output end of the modular multiplication operator is connected to the first input end of the adder and the first input end of the subtractor respectively through the intermediate buffer unit; The output ends of the first modulo operator and the second modulo operator are connected to the output end of each butterfly logic operation unit through the two output buffer units respectively.

8. A quantum cryptographic calculation method based on FPGA structure, characterized in that: Applied to the FPGA structure described in any one of claims 1 to 7, the method comprises: A data flow detection module in the FPGA structure is used to perform flow detection on the input data of the current round to obtain a parallelism control signal of the current round, and the input data of the current round is stored in a plurality of target access units corresponding to the current round in the 2n+2 access units in the FPGA structure; the plurality of target access units corresponding to the current round are the plurality of target access units indicated by the parallelism control signal of the current round; Using the control logic module in the FPGA structure to control the multiple target butterfly logic operation units of the current round to read the input data from the corresponding multiple target access units respectively according to the parallelism control signal of the current round; The multiple target butterfly logic operation units are used to perform parallel butterfly operations on the input data of the current round, and the respective butterfly logic operation data are stored as the butterfly operation data of the current round in the target access unit corresponding to the current round, wherein the multiple target butterfly logic operation units of the current round are the multiple butterfly logic operation units indicated by the parallelism control signal of the current round.

9. The method according to claim 8, characterized in that Before the data flow detection module in the FPGA structure is used to perform flow detection on the input data of the current round to obtain the parallelism control signal of the current round, the method further includes: If the current round is the first round, the data flow detection module is used to take the external input data as the input data of the current round; If the current round is not the first round, the data flow detection module is used to read the butterfly operation data of the previous round from a plurality of target access units corresponding to the previous round as input data of the current round.

10. The method according to claim 8, characterized in that The using the multiple target butterfly logic operation units to perform parallel butterfly operations on the input data of the current round includes: Using the multiple target butterfly logic operation units, according to the identifiers of the multiple target butterfly logic operation units and the current round, respectively determine the target storage addresses corresponding to the multiple target butterfly logic operation units from the read-only storage units in the storage module in the FPGA structure; Using the plurality of target butterfly logic operation units to respectively obtain corresponding butterfly operation control parameters from corresponding target storage addresses; The plurality of target butterfly logic operation units are used to use the corresponding butterfly operation control parameters to perform parallel butterfly operations on the input data of the current round.

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