A data transmission method and device, electronic equipment and storage medium

Abstract

The embodiment of the application provides a data transmission method and device, electronic equipment and storage medium, the method comprises: obtaining the delay time of receiving the data packet sent by the SPI slave, the delay time at least comprises the sum of delay time of different stages; according to the delay time and preset clock cycle, the adjustment strategy corresponding to the delay time is determined;According to the adjustment strategy, the data packet sent by the SPI slave is received, in the embodiment of the application, the time consumed by the SPI slave for sending the data packet to the SPI host is obtained, and the preset clock cycle is compared, so that the adjustment strategy is determined, and then the SPI host receives the data packet sent by the SPI slave according to the adjustment strategy, the delay time in the data transmission process is compensated, and the data transmission efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a data transmission method, device, electronic device and storage medium. Background Art

[0002] SPI is a synchronous serial interface technology, a high-speed, full-duplex, synchronous communication bus. Unlike I2C, the SPI protocol does not restrict the SPI clock frequency. Currently, most SPI interfaces operate at speeds exceeding 10 Mbps. However, there are situations where higher throughput is required, requiring an SPI interface capable of supporting higher frequencies. The maximum achievable SPI clock frequency is affected by the clock frequency, device capabilities, and communication length. These factors can be summarized as the signal transmission delay between the master and slave SPI interfaces (circuit transmission time and device data preparation time) during the actual transmission process.

[0003] The Master SPI sends and receives data on the two clock edges within the same cycle, while the Slave SPI receives and sends data using the same CLK scheme. However, as the SPI CLK frequency increases, the signal transmission delay accounts for an increasingly higher proportion of an SCLK cycle, so the impact of signal transmission delay also becomes increasingly significant. When the frequency exceeds a certain level, it can even cause the Master SPI to fail to receive the MISO data sent by the Slave on the previously specified CLK edge. However, this method can resolve the problem of data not being correctly received due to propagation delay, but it requires the Master SPI to have at least two SPI interfaces. This cannot be achieved if the Master SPI only has one SPI interface. Therefore, how to improve data transmission efficiency while saving costs is an urgent problem that needs to be solved. Summary of the Invention

[0004] Some embodiments of the present application aim to provide a data transmission method, apparatus, electronic device, and storage medium. Through the technical solutions of the embodiments of the present application, a delay time of receiving a data packet sent by an SPI slave is obtained, wherein the delay time includes at least the sum of delay times in different stages; an adjustment strategy corresponding to the delay time is determined based on the delay time and a preset clock cycle; and a data packet sent by the SPI slave is received according to the adjustment strategy. In the embodiments of the present application, the time required for the SPI slave to send the data packet to the SPI host is obtained and compared with the preset clock cycle to determine the adjustment strategy. Then, according to the adjustment strategy, the SPI host receives the data packet sent by the SPI slave, compensates for the delay time during the data transmission process, and improves the data transmission efficiency.

[0005] In a first aspect, some embodiments of the present application provide a data transmission method, applied to an SPI host, comprising:

[0006] Obtaining a delay time for receiving a data packet sent by an SPI slave, wherein the delay time at least includes the sum of delay times at different stages;

[0007] Determining an adjustment strategy corresponding to the delay time according to the delay time and a preset clock cycle;

[0008] According to the adjustment strategy, a data packet sent by the SPI slave is received.

[0009] Some embodiments of the present application determine an adjustment strategy by obtaining the time required for an SPI slave to send a data packet to an SPI master and comparing it with a preset clock cycle. Then, based on the adjustment strategy, the SPI master receives the data packet sent by the SPI slave and compensates for the delay time during the data transmission process, thereby improving data transmission efficiency.

[0010] Optionally, the delay time includes at least a first delay time, a second delay time and a third delay time;

[0011] The first delay time is obtained by sending a data packet from the host SPI chip to the SPI slave general output port;

[0012] The second delay time is determined according to the preparation time of the SPI slave machine to prepare to send a data packet;

[0013] The third delay time is obtained by sending the data packet from the SPI slave universal output port to the SPI master.

[0014] Some embodiments of the present application obtain the delay time by acquiring the delay time of each stage of sending from the SPI slave to the SPI master.

[0015] Optionally, determining an adjustment strategy corresponding to the delay time according to the delay time and a preset clock period includes:

[0016] If the delay time is less than half of the preset clock cycle, determining a first adjustment strategy, wherein the first adjustment strategy includes receiving a data packet sent by the SPI slave at a falling edge of the current clock cycle;

[0017] If the delay time is greater than or equal to half of the preset clock cycle, a second adjustment strategy is determined, where the second adjustment strategy includes receiving a data packet sent by the SPI slave at a falling edge of a next clock cycle.

[0018] In some embodiments of the present application, when the delay time is greater than or equal to half of the preset clock cycle, a second adjustment strategy is determined, and the second adjustment strategy includes receiving the data packet sent by the SPI slave at the falling edge of the next clock cycle. In this way, the data packet can be received in the shortest time, thereby improving data transmission efficiency.

[0019] Optionally, the method further includes:

[0020] According to the preset clock cycle, at the moment of the rising edge of the preset clock cycle, a data packet is sent to the SPI slave.

[0021] Optionally, sending a data packet to the SPI slave at a rising edge of the preset clock cycle according to the preset clock cycle includes:

[0022] Obtaining a fourth delay time, where the fourth delay time at least includes a master preparation time and a time consumed by the master to transmit data to the slave;

[0023] According to the fourth delay time, a data packet is sent to the SPI slave at a rising edge of a preset clock cycle.

[0024] In some embodiments of the present application, the SPI master simultaneously sends a clock signal and a data packet to the slave SPI, thereby reducing time delay and improving the accuracy of data transmission.

[0025] In a second aspect, some embodiments of the present application provide a data transmission device, applied to an SPI host, comprising:

[0026] An acquisition module is used to acquire a delay time of receiving a data packet sent by an SPI slave, wherein the delay time at least includes the sum of delay times at different stages;

[0027] A determination module, configured to determine an adjustment strategy corresponding to the delay time according to the delay time and a preset clock cycle;

[0028] A receiving module is used to receive the data packet sent by the SPI slave according to the adjustment strategy.

[0029] Some embodiments of the present application determine an adjustment strategy by obtaining the time required for an SPI slave to send a data packet to an SPI master and comparing it with a preset clock cycle. Then, based on the adjustment strategy, the SPI master receives the data packet sent by the SPI slave and compensates for the delay time during the data transmission process, thereby improving data transmission efficiency.

[0030] Optionally, the delay time includes at least a first delay time, a second delay time and a third delay time;

[0031] The first delay time is obtained by sending a data packet from the host SPI chip to the SPI slave general output port;

[0032] The second delay time is determined according to the preparation time of the SPI slave machine to prepare to send a data packet;

[0033] The third delay time is obtained by sending the data packet from the SPI slave universal output port to the SPI master.

[0034] Some embodiments of the present application obtain the delay time by acquiring the delay time of each stage of sending from the SPI slave to the SPI master.

[0035] Optionally, the determining module is used to:

[0036] If the delay time is less than half of the preset clock cycle, determining a first adjustment strategy, wherein the first adjustment strategy includes receiving a data packet sent by the SPI slave at a falling edge of the current clock cycle;

[0037] If the delay time is greater than or equal to half of the preset clock cycle, a second adjustment strategy is determined, where the second adjustment strategy includes receiving a data packet sent by the SPI slave at a falling edge of a next clock cycle.

[0038] In some embodiments of the present application, when the delay time is greater than or equal to half of the preset clock cycle, a second adjustment strategy is determined, and the second adjustment strategy includes receiving the data packet sent by the SPI slave at the falling edge of the next clock cycle. In this way, the data packet can be received in the shortest time, thereby improving data transmission efficiency.

[0039] Optionally, the receiving module is used to:

[0040] According to the preset clock cycle, at the moment of the rising edge of the preset clock cycle, a data packet is sent to the SPI slave.

[0041] Optionally, the receiving module is used to:

[0042] Obtaining a fourth delay time, where the fourth delay time at least includes a master preparation time and a time consumed by the master to transmit data to the slave;

[0043] According to the fourth delay time, a data packet is sent to the SPI slave at a rising edge of a preset clock cycle.

[0044] In some embodiments of the present application, the SPI master simultaneously sends a clock signal and a data packet to the slave SPI, thereby reducing time delay and improving the accuracy of data transmission.

[0045] In a third aspect, some embodiments of the present application provide an electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the program, the data transmission method as described in any embodiment of the first aspect can be implemented.

[0046] In a fourth aspect, some embodiments of the present application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the data transmission method as described in any embodiment of the first aspect.

[0047] In a fifth aspect, some embodiments of the present application provide a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, it can implement the data transmission method as described in any embodiment of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of some embodiments of the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0049] Figure 1 A flowchart of a data transmission method provided in an embodiment of the present application;

[0050] Figure 2 A schematic diagram of the structure of a data transmission system provided in an embodiment of the present application;

[0051] Figure 3 A data transmission timing diagram provided in an embodiment of the present application;

[0052] Figure 4 A schematic diagram of another data transmission timing provided in an embodiment of the present application;

[0053] Figure 5 A schematic diagram of the structure of a data transmission device provided in an embodiment of the present application;

[0054] Figure 6 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The technical solutions in some embodiments of the present application will be described below in conjunction with the drawings in some embodiments of the present application.

[0056] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0057] SPI is a synchronous serial interface technology, a high-speed, full-duplex, synchronous communication bus. Unlike I2C, the SPI protocol does not restrict the SPI clock frequency. Currently, most SPI interfaces operate at speeds exceeding 10 Mbps. However, there are situations where higher throughput is required, requiring an SPI interface capable of supporting higher frequencies. The maximum achievable SPI clock frequency is affected by the clock frequency, device capabilities, and communication length. These factors can be summarized as the signal transmission delay between the master and slave SPI interfaces (circuit transmission time and device data preparation time) during the actual transmission process.

[0058] The Master SPI sends and receives data on the two clock change edges in the same cycle, and the Slave SPI receives and sends data according to the same CLK scheme. However, as the SPI CLK frequency increases, the proportion of signal transmission delay in an SCLK cycle becomes increasingly higher, so the impact of signal transmission delay also becomes increasingly greater. When the frequency exceeds a certain level, it may even cause the Master SPI to fail to receive the MISO data sent by the Slave at the previously specified CLK transition edge. However, this method can solve the problem of data failure caused by propagation delay, but this requires the Master SPI to have at least two sets of SPI interfaces. If the Master SPI has only one SPI interface, this cannot be achieved. Therefore, how to improve data transmission efficiency while saving costs is currently an urgent problem to be solved. In view of this, some embodiments of the present application provide a data transmission method, the method comprising obtaining a delay time for receiving a data packet sent by an SPI slave, the delay time comprising at least the sum of delay times at different stages; determining an adjustment strategy corresponding to the delay time based on the delay time and a preset clock cycle; and receiving a data packet sent by the SPI slave according to the adjustment strategy. In the embodiments of the present application, the time required for the SPI slave to send the data packet to the SPI master is obtained and compared with the preset clock cycle to determine the adjustment strategy. Then, according to the adjustment strategy, the SPI master receives the data packet sent by the SPI slave, compensates for the delay time during the data transmission process, and improves data transmission efficiency.

[0059] like Figure 1As shown, an embodiment of the present application provides a data transmission method, the method comprising:

[0060] S101, obtaining a delay time for receiving a data packet sent by an SPI slave, where the delay time at least includes the sum of delay times at different stages;

[0061] Specifically, if Figure 2 As shown, the data transmission system includes an SPI host and an SPI slave, and the SPI interface of the SPI host is connected to the SPI interface of the SPI slave;

[0062] The SPI interface generally includes the following four interface signals:

[0063] MISO: MASTERSPI input, SLAVE SPI output;

[0064] MOSI: MASTERSPI output, SLAVE SPI input;

[0065] CS: chip select signal from MASTER to SLAVE;

[0066] SCLK: CLK signal output by MASTER to SLAVE, SCLK: SPI clock;

[0067] GPIO: General Purpose Input Output;

[0068] SPI: Serial Peripheral interface;

[0069] Mode0 is working mode 0;

[0070] MISO: Master In Slave Out (master input slave output);

[0071] MOSI: Master Out Slave In (master output slave input);

[0072] CS: chip select signal;

[0073] SS: slave select signal, Slave select;

[0074] SCLK: SERIAL CLOCK serial shift clock input pin;

[0075] The SPI host obtains the delay time of receiving the data packet sent by the SPI slave, where the delay time at least includes the sum of delay times in different stages, for example, the sum of the first delay time, the second delay time, and the third delay time.

[0076] S102, determining an adjustment strategy corresponding to the delay time according to the delay time and a preset clock cycle;

[0077] Specifically, the SPI host is pre-set with a clock cycle, and then compares the acquired delay time with the preset time period. According to the comparison result, an adjustment strategy corresponding to the delay time is determined, wherein the adjustment strategy at least includes that when a data packet cannot be received at the falling edge of the current clock, a data packet can be received at the falling edge of one or more future clock cycles.

[0078] S103: Receive a data packet sent by the SPI slave according to the adjustment strategy.

[0079] The SPI host adjusts the policy according to which, for example, if the data packet cannot be received at the falling edge of the current clock cycle, the data packet may be received at the falling edge of the next clock cycle, or at the falling edges of the next few clock cycles.

[0080] Some embodiments of the present application determine an adjustment strategy by obtaining the time required for an SPI slave to send a data packet to an SPI master and comparing it with a preset clock cycle. Then, based on the adjustment strategy, the SPI master receives the data packet sent by the SPI slave and compensates for the delay time during the data transmission process, thereby improving data transmission efficiency.

[0081] Another embodiment of the present application further supplements the data transmission method provided in the above embodiment.

[0082] Optionally, the delay time includes at least a first delay time, a second delay time and a third delay time;

[0083] The first delay time is obtained by sending the data packet from the host SPI chip to the SPI slave general output port;

[0084] The second delay time is determined according to the preparation time of the SPI slave to prepare to send a data packet;

[0085] The third delay time is obtained by sending the data packet from the SPI slave general output port to the SPI master.

[0086] Some embodiments of the present application obtain the delay time by acquiring the delay time of each stage of sending from the SPI slave to the SPI master.

[0087] Optionally, determining an adjustment strategy corresponding to the delay time according to the delay time and a preset clock period includes:

[0088] If the delay time is less than half of the preset clock cycle, determining a first adjustment strategy, the first adjustment strategy including receiving a data packet sent by the SPI slave at a falling edge of the current clock cycle;

[0089] If the delay time is greater than or equal to half of the preset clock cycle, a second adjustment strategy is determined, and the second adjustment strategy includes receiving a data packet sent by the SPI slave at a falling edge of the next clock cycle.

[0090] In some embodiments of the present application, when the delay time is greater than or equal to half of the preset clock cycle, a second adjustment strategy is determined. The second adjustment strategy includes receiving a data packet sent by the SPI slave at the falling edge of the next clock cycle. In this way, the data packet can be received in the shortest time, thereby improving data transmission efficiency.

[0091] The data flow from SLAVE to Master (MISO):

[0092] 1) The MasterSPI generates a certain frequency of SCLK according to the relevant configuration and outputs it to the corresponding GPIO port, and then sends it to the corresponding SlaveSPI SCLK interface. After receiving SCLK, communication begins. The delay here is called Tpro_dly_clk (clock delay during transmission), which is the first delay time;

[0093] 2) After receiving the rising edge of CLK at the SLAVESPI end, the delay for preparing to output the MISO signal is Tslv_ready (slave master preparation time), which is the second delay time;

[0094] 3) The MISO on the SLAVE end is sent to the corresponding GPIO port (general purpose input and output) and then sent to the MISO interface of the MasterSPI through corresponding processing. The delay is called Tpro_dly_miso, which is the time required for the slave to output MISO and the host to input MISO, that is, the third delay time.

[0095] It can be seen that the total delay of this path, that is, the delay time, is: Tall_dly=Tpro_dly_clk+Tpro_dly_miso+Tslv_ready.

[0096] If the total delay Tall_dly is less than half of the SCLK cycle (i.e. the host input arrives before the falling edge of the host's SCLK), then the Master can still receive the i_miso data without any special processing. However, as the frequency increases, the total delay in one SCLK cycle becomes larger and larger, so it is very likely that the i_miso data packet will arrive after the falling edge of SCLK, and the data will not be collected. See the timing diagram for details. Figure 4 shown.

[0097] Note: The solid arrows indicate the time when the Master / SLAVE SPI sends, and the dotted arrows indicate the time when the Master / SLAVE SPI receives.

[0098] In the embodiment of the present application, the timing of the first data stream, sent by the Master and received by the Slave, is fully satisfied in most cases. This is because the propagation delay from the Master's SCLK to the Slave end is almost the same as the path from the Master's MOSI to the Slave end, so the two signals arrive at the Slave end at similar times, so the Slave end can always sample the MOSI signal. However, in the second data stream, sent by the Slave and received by the Master, if the SCLK frequency is relatively high, it is difficult for the Master end to sample the MOSI signal at the agreed clock edge without special processing.

[0099] The scheme for compensating for propagation delay provided in the embodiments of the present application modifies the SPI-related controls on the master side to perform delay compensation without adding ports. The specific scheme is to connect the SCLK output by the MasterSPI SCLK through the GPIO PAD back to the SPI inside the Master side, and then use this CLK to sample the MISO signal sent by the SlaveSPI. This can offset most of the transmission delay from the Master SPI to the Slave side. This is because the time delay of the GPIO output PAD accounts for a large proportion of the transmission delay of the entire path and is also much larger than the time delay of the input PAD.

[0100] Optionally, the method further includes:

[0101] According to the preset clock cycle, at the moment of the rising edge of the preset clock cycle, a data packet is sent to the SPI slave.

[0102] Optionally, according to a preset clock cycle, at the moment of a rising edge of the preset clock cycle, sending a data packet to the SPI slave includes:

[0103] Obtaining a fourth delay time, where the fourth delay time at least includes a master preparation time and a time consumed by the master to transmit data to the slave;

[0104] According to the fourth delay time, a data packet is sent to the SPI slave at the rising edge of the preset clock cycle.

[0105] When the master SPI communicates with the slave SPI, the master SPI sends data to the slave on one SCLK edge and receives data from the slave on the other edge of the same cycle. The slave SPI also sends data on the same CLK edge and receives data on the other edge of the same cycle. The actual SPI data transmission takes into account the circuit transmission time and the device data preparation time. The specific data transmission and reception communication process is as follows (taking CLK Mode 0 as an example):

[0106] MasterSPI preparation: first output the CS chip select signal to GPIO, and select the corresponding slave SPI.

[0107] Data flow sent by Master and received by SLAVE (MOSI):

[0108] like Figure 3 The figure shows the process flow of MOSI (SPI master) sending data packets to SPI slaves: Note: The solid arrows indicate the time when Master / SLAVE SPI sends, and the dotted arrows indicate the time when Master / SLAVE SPI receives.

[0109] MasterSPI generates SCLK of a certain frequency according to the relevant configuration, and outputs it to the corresponding GPIO port, and then sends it to the corresponding SLAVESPI SCLK interface. After receiving SCLK, communication begins, and the host sends SCLK to the slave end. At this time, the time consumed by transmitting SCLK is Tpro_dly_clk (the delay of the clock during the transmission process);

[0110] MasterSPI prepares data and sends it to MASTERSPIMOSI port a certain time after the rising edge of SCLK. The time consumed is Tmas_ready (master preparation time).

[0111] The master's internal MOSI is then sent to the corresponding GPIO, and then to the slave's input port MOSI. Let this time be Tpad. At this time, the total delay of MOSI from the host to the slave is Tpro_dly_mosi = Tmas_ready + Tpad; (the time required for the master's output MOSI to the slave's input MOSI)

[0112] And collect MOSI data on the falling edge of SCLK at the SLAVE end, thus completing the communication between Master and SLAVE.

[0113] Without increasing the number of used ports, the SPI control on the master side can be modified to compensate for the delay and thus improve the SPI transmission rate. That is, the CLK output by the PAD is used to sample the MISO signal sent by the slave, thus compensating for most of the delay in the path from the master SPI to the slave SPI.

[0114] In some embodiments of the present application, the SPI master simultaneously sends a clock signal and a data packet to the slave SPI, thereby reducing time delay and improving the accuracy of data transmission.

[0115] It should be noted that each implementable method in this embodiment can be implemented separately, or can be implemented in combination in any combination without conflict, and this application does not limit it.

[0116] Another embodiment of the present application provides a data transmission device for executing the data transmission method provided in the above embodiment.

[0117] like Figure 5 FIG. 1 is a schematic diagram of the structure of a data transmission device provided in an embodiment of the present application. The data transmission device includes, and is applied to an SPI host, wherein:

[0118] The acquisition module 501 is used to obtain the delay time of receiving the data packet sent by the SPI slave, and the delay time at least includes the sum of the delay times of different stages;

[0119] The determination module 502 is configured to determine an adjustment strategy corresponding to the delay time according to the delay time and a preset clock cycle;

[0120] The receiving module 503 is configured to receive data packets sent by the SPI slave according to the adjustment strategy.

[0121] Regarding the device in this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method and will not be elaborated here.

[0122] Some embodiments of the present application determine an adjustment strategy by obtaining the time required for an SPI slave to send a data packet to an SPI master and comparing it with a preset clock cycle. Then, based on the adjustment strategy, the SPI master receives the data packet sent by the SPI slave and compensates for the delay time during the data transmission process, thereby improving data transmission efficiency.

[0123] Another embodiment of the present application further supplements the data transmission device provided in the above embodiment.

[0124] Optionally, the delay time includes at least a first delay time, a second delay time and a third delay time;

[0125] The first delay time is obtained by sending the data packet from the host SPI chip to the SPI slave general output port;

[0126] The second delay time is determined according to the preparation time of the SPI slave to prepare to send a data packet;

[0127] The third delay time is obtained by sending the data packet from the SPI slave general output port to the SPI master.

[0128] Some embodiments of the present application obtain the delay time by acquiring the delay time of each stage of sending from the SPI slave to the SPI master.

[0129] Optionally, the determination module is configured to:

[0130] If the delay time is less than half of the preset clock cycle, determining a first adjustment strategy, the first adjustment strategy including receiving a data packet sent by the SPI slave at a falling edge of the current clock cycle;

[0131] If the delay time is greater than or equal to half of the preset clock cycle, a second adjustment strategy is determined, and the second adjustment strategy includes receiving a data packet sent by the SPI slave at a falling edge of the next clock cycle.

[0132] In some embodiments of the present application, when the delay time is greater than or equal to half of the preset clock cycle, a second adjustment strategy is determined. The second adjustment strategy includes receiving a data packet sent by the SPI slave at the falling edge of the next clock cycle. In this way, the data packet can be received in the shortest time, thereby improving data transmission efficiency.

[0133] Optionally, the receiving module is configured to:

[0134] According to the preset clock cycle, at the moment of the rising edge of the preset clock cycle, a data packet is sent to the SPI slave.

[0135] Optionally, the receiving module is configured to:

[0136] Obtaining a fourth delay time, where the fourth delay time at least includes a master preparation time and a time consumed by the master to transmit data to the slave;

[0137] According to the fourth delay time, a data packet is sent to the SPI slave at the rising edge of the preset clock cycle.

[0138] In some embodiments of the present application, the SPI master simultaneously sends a clock signal and a data packet to the SPI slave, reducing time delays and improving data transmission accuracy. Regarding the device of this embodiment, the specific manner in which each module performs operations has been described in detail in the embodiments of the method and will not be elaborated on here.

[0139] It should be noted that each implementable method in this embodiment can be implemented separately, or can be implemented in combination in any combination without conflict, and this application does not limit it.

[0140] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the operation of the method corresponding to any embodiment of the data transmission method provided in the above embodiments can be implemented.

[0141] An embodiment of the present application further provides a computer program product, which includes a computer program, wherein when the computer program is executed by a processor, it can implement the operations corresponding to any embodiment of the data transmission method provided in the above embodiments.

[0142] like Figure 6 As shown, some embodiments of the present application provide an electronic device 600, which includes: a memory 610, a processor 620, and a computer program stored in the memory 610 and executable on the processor 620, wherein the processor 620 can implement a method of any embodiment included in the above-mentioned data transmission method when reading the program from the memory 610 through the bus 630 and executing the program.

[0143] Processor 620 can process digital signals and can include various computing architectures, such as a complex instruction set computer architecture, a reduced instruction set computer architecture, or an architecture that implements a combination of multiple instruction sets. In some examples, processor 620 can be a microprocessor.

[0144] The memory 610 can be used to store instructions executed by the processor 620 or data related to the execution of instructions. These instructions and / or data may include code for implementing some or all functions of one or more modules described in the embodiments of this application. The processor 620 of the embodiment of the present disclosure can be used to execute the instructions in the memory 610 to implement the method shown above. The memory 610 includes dynamic random access memory, static random access memory, flash memory, optical storage, or other memory known to those skilled in the art.

[0145] The above are merely examples of the present application and are not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application. It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined or explained in subsequent figures.

[0146] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

[0147] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

Claims

1. A data transmission method, characterized in that: Applied to an SPI host, the method includes: Obtaining a delay time for receiving a data packet sent by an SPI slave, the delay time including at least the sum of delay times at different stages, and the delay time including at least a first delay time, a second delay time, and a third delay time; the first delay time is obtained by sending the data packet from the host SPI chip to the SPI slave general output port; the second delay time is determined based on the preparation time for the SPI slave to prepare to send the data packet; and the third delay time is obtained by sending the data packet from the SPI slave general output port to the SPI host; Determining an adjustment strategy corresponding to the delay time based on the delay time and a preset clock cycle; the adjustment strategy at least includes receiving the data packet at a falling edge of one or more future clock cycles if the data packet cannot be received at a falling edge of the current clock; According to the adjustment strategy, receiving a data packet sent by the SPI slave; The step of determining an adjustment strategy corresponding to the delay time according to the delay time and the preset clock period includes: If the delay time is less than half of the preset clock cycle, determining a first adjustment strategy, wherein the first adjustment strategy includes receiving a data packet sent by the SPI slave at a falling edge of the current clock cycle; If the delay time is greater than or equal to half of the preset clock cycle, a second adjustment strategy is determined, where the second adjustment strategy includes receiving a data packet sent by the SPI slave at a falling edge of a next clock cycle.

2. The data transmission method according to claim 1, wherein: The method further comprises: According to the preset clock cycle, at the moment of the rising edge of the preset clock cycle, a data packet is sent to the SPI slave.

3. The data transmission method according to claim 1, wherein: The step of sending a data packet to the SPI slave at a rising edge of the preset clock cycle according to the preset clock cycle includes: Obtaining a fourth delay time, where the fourth delay time at least includes a master preparation time and a time consumed by the master to transmit data to the slave; According to the fourth delay time, a data packet is sent to the SPI slave at a rising edge of a preset clock cycle.

4. A data transmission device, characterized in that: Applied to an SPI host, the device comprises: An acquisition module is configured to acquire a delay time for receiving a data packet sent by an SPI slave, wherein the delay time includes at least the sum of delay times at different stages; the delay time includes at least a first delay time, a second delay time, and a third delay time; the first delay time is obtained by sending the data packet from the host SPI chip to the SPI slave's universal output port; the second delay time is determined based on the preparation time for the SPI slave to prepare to send the data packet; and the third delay time is obtained by sending the data packet from the SPI slave's universal output port to the SPI host; a determination module, configured to determine an adjustment strategy corresponding to the delay time based on the delay time and a preset clock cycle; the adjustment strategy at least including receiving a data packet at a falling edge of one or more future clock cycles if a data packet cannot be received at a falling edge of a current clock; A receiving module, configured to receive a data packet sent by the SPI slave according to the adjustment strategy; The determining module is used for: If the delay time is less than half of the preset clock cycle, determining a first adjustment strategy, wherein the first adjustment strategy includes receiving a data packet sent by the SPI slave at a falling edge of the current clock cycle; If the delay time is greater than or equal to half of the preset clock cycle, a second adjustment strategy is determined, where the second adjustment strategy includes receiving a data packet sent by the SPI slave at a falling edge of a next clock cycle.

5. An electronic device, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor can implement the data transmission method according to any one of claims 1 to 3 when executing the program.

6. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the program is executed by a processor, the data transmission method according to any one of claims 1 to 3 can be implemented.

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