MOS varactor based on two-dimensional material and preparation method thereof

Abstract

The invention discloses an MOS varactor based on a two-dimensional material. The MOS varactor comprises a substrate; the channel layer is a two-dimensional transition metal chalcogenide thin film; the grid electrode is of a multi-finger structure formed by mutually connecting a plurality of strip-shaped grid electrode fingers; two sides of each gate finger are respectively provided with a source electrode and a drain electrode, and the source electrode and the drain electrode are in short circuit; and the gate dielectric layer is arranged between the channel layer and the gate. The MOS varactor based on the two-dimensional material shows remarkable advantages in high-frequency tuning and capacitance-variable application, the MOS varactor has stable capacitance characteristics under the high-frequency condition due to the optimized device structure and material selection, meanwhile, the dual targets of a high Q value and a large capacitance-variable ratio are achieved, the capacitance characteristics are relatively stable under the high-frequency condition, and the MOS varactor is suitable for high-frequency tuning and capacitance-variable application. These characteristics make it suitable for high frequency tuning and capacitance varying applications.

Description

Technical Field

[0001] The present invention belongs to the technical field of MOS varactors, and relates to a MOS varactor based on two-dimensional materials and a preparation method thereof. Background Art

[0002] Metal-oxide-semiconductor (MOS) varactors are widely used in the radio frequency field. They are devices that adjust capacitance by changing the reverse bias voltage, and their principle is to utilize the depletion layer capacitance of semiconductors and the gate dielectric capacitance. The two key indicators for measuring the performance of MOS varactors are the quality factor (Q value) and the capacitance ratio. Among them, the quality factor (Q value) reflects the loss level of the device in high-frequency applications. The higher the Q value, the smaller the energy loss and the higher the efficiency of the device during operation; the capacitance ratio reflects the capacitance adjustment ability of the device. The larger the capacitance ratio, the wider the tuning range that the device can achieve, and it can better meet the application requirements of wide frequency bands. Traditional MOS varactors are usually based on silicon materials and have many limitations in high-frequency applications, mainly reflected in the following aspects: First, due to the relatively large capacitance of silicon materials (ε Si = 11.9), it restricts the further improvement of the capacitance ratio of silicon-based MOS varactors; Second, the Q value of MOS varactors is mainly determined by the mobility and contact resistance of the channel material. When the silicon-based material reduces the channel thickness to increase the capacitance ratio, the mobility will decrease, thereby reducing the Q value; Third, due to the relatively slow switching speed of silicon-based MOS varactors, the loss in high-frequency applications is relatively high, making it difficult to meet the requirements of modern high-frequency power electronic systems for high efficiency and high power density. Summary of the Invention

[0003] Object of the Invention: The object of the present invention is to provide a MOS varactor based on two-dimensional materials and a preparation method thereof, so as to solve the problems of narrow capacitance tuning range, low Q value, and high power consumption of existing MOS varactors under high-frequency applications.

[0004] Technical Solution: A MOS varactor based on two-dimensional materials of the present invention includes: a substrate; a channel layer, where the channel layer is a two-dimensional transition metal chalcogenide thin film; a gate, where the gate is composed of a plurality of finger-shaped gate fingers connected to each other to form a multi-finger structure. Source electrodes and drain electrodes are respectively arranged on both sides of each gate finger, and the source electrode and the drain electrode are short-circuited; a gate dielectric layer is arranged between the channel layer and the gate.

[0005] Further, the two-dimensional transition metal chalcogenide thin film is a molybdenum disulfide thin film.

[0006] Further, the length of the channel layer corresponding to each gate finger is 1 μm, and the width is 10 μm.

[0007] Further, the gate dielectric layer is a hafnium dioxide thin film, and the thickness of the hafnium dioxide thin film is 6-10 nm.

[0008] Further, the source and drain are an antimony / gold laminated metal thin film deposited by electron beam evaporation, and the total thickness of the antimony / gold laminated metal thin film is 40-200 nm.

[0009] Further, the gate is a titanium / gold laminated metal thin film deposited by electron beam evaporation, and the total thickness of the titanium / gold laminated metal thin film is 40-200 nm.

[0010] The present invention provides a method for preparing a MOS varactor based on two-dimensional materials, comprising the following steps:

[0011] S1. Prepare a single-layer two-dimensional transition metal chalcogenide thin film on a sapphire substrate by chemical vapor deposition;

[0012] S2. Wet-transfer the two-dimensional transition metal chalcogenide thin film onto a substrate of intrinsic silicon;

[0013] S3. Pattern-expose the channel and source-drain regions by electron beam lithography, short-circuit the source and drain electrodes, and deposit an antimony / gold laminated metal thin film by electron beam evaporation as the source electrode and the drain electrode;

[0014] S4. Deposit a hafnium dioxide thin film by atomic layer deposition, and deposit a titanium / gold laminated metal thin film by electron beam evaporation as the gate electrode.

[0015] Further, the specific steps of step S1 are as follows:

[0016] S11. Place sulfur powder in a quartz crucible, heat it to 170 °C, and simultaneously introduce argon at a flow rate of 100 sccm to promote the transport of sulfur;

[0017] S12. Use a molybdenum sheet as the molybdenum source, heat it to 650 °C, introduce it into another gas stream in the growth chamber, which contains 5-10 sccm of oxygen and 50 sccm of argon, and then deposit it onto the substrate in the third temperature zone together with the sulfur vapor, with a growth temperature of 950 °C.

[0018] Further, the specific steps of step S2 are as follows:

[0019] S21. Spin-coat polymethyl methacrylate on the original substrate with the two-dimensional transition metal chalcogenide thin film and bake it at 150 °C to form a molybdenum disulfide / polymethyl methacrylate thin film. After soaking it in a potassium hydroxide solution to separate the MoS2 / PMMA thin film from the original substrate, paste it onto the intrinsic silicon substrate;

[0020] S22. Perform annealing treatment in a vacuum environment;

[0021] S23. Immerse in acetone to dissolve polymethyl methacrylate and dry with nitrogen.

[0022] Beneficial effects: Compared with the prior art, the present invention has the following remarkable advantages: 1. By utilizing the characteristics of low interface states of two-dimensional materials, the equivalent series resistance can be significantly reduced, thereby achieving a high Q value; at the same time, the regulation of the channel carrier concentration by the gate voltage is made more efficient to achieve a high varactor ratio.

[0023] 2. Adopt a multi-finger device structure to increase the effective area of the MOS varactor. The short channel can improve the Q value and reduce parasitic effects; the large width can increase the effective area and improve the varactor ratio.

[0024] 3. Use hafnium dioxide (HfO 2 ) as the gate dielectric. Its high dielectric constant can effectively reduce the leakage current of the device, improve the Q value, and further enhance the device performance. Description of the Drawings

[0025] Figure 1 Cross-sectional schematic diagram of a MOS varactor device structure based on MoS 2 for a single gate finger.

[0026] Figure 2 Cross-sectional schematic diagram of a MOS varactor device based on MoS 2 with a multi-finger structure.

[0027] Figure 3 Bright-field (left) and dark-field (right) optical pictures of a MOS varactor device based on MoS 2 with 14 interleaved fingers.

[0028] Figure 4 Equivalent circuit diagram of a MOS varactor device based on MoS 2 .

[0029] Figure 5 Capacitance-voltage curve of a MOS varactor based on MoS 2 .

[0030] Figure 6 Q-value-voltage curve of a MOS varactor based on MoS 2 .

[0031] Figure 7 Conductance-voltage curve of a MOS varactor based on MoS 2 .

[0032] Figure 8 Cross-sectional schematic diagram of a MOS varactor device based on MoS 2Phase angle-voltage curve of the MOS varactor. Detailed implementation mode

[0033] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0034] In this embodiment, molybdenum disulfide (MoS 2 ) is taken as an example to prepare a MOS varactor with low interface states. By utilizing its characteristics of low interface states and low dielectric constant, high Q value and large varactor ratio are achieved. The device structure is as Figure 1-2 shown, including: a substrate 1; a channel layer 2, and the channel layer 2 is a two-dimensional transition metal chalcogenide thin film. In this embodiment, MoS 2 thin film is used. It also includes a gate. In this embodiment, the gate is a titanium / gold (Ti / Au) stacked metal thin film deposited by electron beam evaporation. The total thickness of the Ti / Au stacked metal thin film is 40-200 nm. In this embodiment, Ti and Au are 20 nm and 80 nm respectively, and the gate is composed of multiple finger-shaped gate fingers 3 to form a multi-finger structure. As Figure 3 shown, it is a bright-field (left) and dark-field (right) optical picture of a MOS varactor device based on MoS 2 with 14 finger insertions. The length of the channel layer 2 corresponding to each gate finger is 1 μm, and the width is 10 μm. If the number of finger insertions is 14, the width is 14*10 = 140 μm, and the channel length is still 1 μm. The design of the multi-finger device structure can increase the effective area of the MOS varactor. The short channel can improve the Q value and reduce parasitic effects, and the large width can increase the effective area and improve the varactor ratio. The MOS varactor also includes a gate dielectric layer 4 disposed between the channel layer 2 and the gate 3. In this embodiment, the gate dielectric layer uses a hafnium dioxide (HfO 2 ) thin film with a thickness of 8 nm. Using the high-k material HfO 2 as the gate dielectric, its high dielectric constant can effectively reduce the leakage current of the device and improve the Q value, further enhancing the device performance. The MOS varactor also includes a source electrode 6 and a drain electrode 5 disposed at both ends of the gate dielectric 4 layer. The source electrode 6 and the drain electrode 5 are short-circuited. In this embodiment, the source electrode 6 and the drain electrode 5 are antimony / gold (Sb / Au) stacked metal thin films deposited by electron beam evaporation. The total thickness of the Sb / Au stacked metal thin film is 40-200 nm. In this embodiment, Sb and Au are 20 nm and 30 nm respectively.

[0035] Specifically, the MoS 2 thin film has a natural atomic layer thickness and can still maintain a high carrier mobility under the single-layer condition, enabling the MoS 2 -based MOS varactor to exhibit low loss and high Q value in high-frequency applications. MoS 2It has a small dielectric constant and a small capacitance when depleted. By adjusting the gate voltage, a large varactor ratio can be achieved, thus providing a wider capacitance tuning range. MoS 2 The device has a fast switching speed and can achieve fast switching under high-frequency conditions, thus significantly reducing power consumption.

[0036] The MOS varactor shorts the source and drain of the MOS field-effect transistor and forms a two-terminal device together with the gate. The capacitance utilized is the capacitance between the gate and the source. MoS 2 The magnitude of the capacitance is controlled by the voltage V g between the gate and the substrate. We selected the high-k dielectric HfO 2 as the gate dielectric layer, and MoS 2 as the channel material to fabricate the MOS varactor. The total capacitance (C total ) is composed of the gate dielectric capacitance and the MoS 2 capacitance in series.

[0037] The equivalent circuit is as Figure 4 shown. The working principle of the MOS varactor is based on the regulation of the carrier concentration in the n-type MoS 2 channel by the gate voltage, thereby changing the total capacitance value of the device:

[0038]

[0039] Depletion region: When the gate voltage is less than the threshold voltage (V g <V th ), the MoS 2 channel is in the depletion state, the electron concentration in the channel is low, the dielectric constant increases, and the total capacitance value is low after being connected in series with .

[0040] Accumulation region: When the gate voltage is greater than the threshold voltage (V g >V th ), a high-concentration electron layer is formed in the MoS 2 channel. Due to the low dielectric constant characteristic of MoS2, is significantly reduced, and the total capacitance value is high after being connected in series with .

[0041] This embodiment demonstrates the specific processing flow of the device of the present invention, including the following steps:

[0042] S1. Preparation of the MoS 2 thin film: Use a three-zone chemical vapor deposition (CVD) device to prepare a large-area and high-quality single-layer MoS on the c-plane sapphire substrate 2Thin film. Sulfur (S) powder was placed in a quartz crucible and heated to 170 °C, while argon was introduced at a flow rate of 100 sccm to facilitate the transport of sulfur. A molybdenum (Mo) sheet, as the molybdenum source, was heated to 650 °C and introduced into another gas stream in the growth chamber. This gas stream contained 5 - 10 sccm of oxygen (O 2 , used to promote the oxidation of molybdenum) and 50 sccm of argon, and was then deposited onto the substrate in the third temperature zone together with S vapor at a growth temperature of 950 °C.

[0043] S2, MoS 2 Transfer of the MoS thin film: First, a polymethyl methacrylate (PMMA) thin film was spin-coated on the original substrate with the transition metal chalcogenide thin film and baked at 150 °C to ensure good adhesion between the PMMA and the thin film. Then, it was immersed in a potassium hydroxide solution to separate the thin film from the original substrate. After the MoS 2 / PMMA thin film detached from the original substrate, it was pasted onto an intrinsic silicon substrate. The transferred MoS 2 / PMMA thin film was annealed in a vacuum environment at an annealing temperature of 140 °C for a duration of 10 minutes. The purpose of vacuum annealing was to remove the residual stress and impurities in the PMMA thin film and ensure good adhesion between the MoS 2 thin film and the intrinsic silicon substrate. Finally, it was immersed in acetone to dissolve the PMMA and dried with nitrogen.

[0044] S3. Device design and fabrication: Electron beam lithography was used to pattern the channel and source-drain regions. The length of the channel region was defined as 1 μm and the width as 10 μm. The source and drain electrodes were shorted, and an Sb / Au stacked metal was deposited as the source and drain electrodes by electron beam evaporation, with the thicknesses of the metal thin films being 20 nm and 30 nm respectively.

[0045] S4. 8 nm of HfO was deposited by atomic layer deposition (ALD), and a Ti / Au stacked metal was deposited as the gate electrode by electron beam evaporation, with the thicknesses of the metal thin films being 20 nm and 80 nm respectively. 2 Device testing and analysis

[0046] The MOS varactor was tested using an LCR digital bridge device, including capacitance-voltage test, Q-value-voltage test, conductance-voltage test, and phase angle-voltage test. The test curves are shown in the attached figures. The LCR digital bridge controlled the magnitude of the AC signal to be 30 mV, the scanning speed was slow, and the DC signal scanning range was from -3.5 V to 0.5 V.

[0047]

[0048] Figure 5 ​shows the capacitance-voltage curves of the MOS varactor at different frequencies. 21 frequencies are selected for testing in the frequency range from 50 kHz to 2 MHz. When the gate voltage is scanned from negative to positive, the MOS varactor undergoes a transition from the depletion region to the accumulation region: when operating in the depletion region, the electrons in the MoS 2 channel are depleted, and the capacitance is mainly determined by the gate oxide capacitance and the MoS 2 channel capacitance together, and the capacitance value is at the minimum; when operating in the accumulation region, a high-concentration electron layer is formed in the MoS 2 channel, and the capacitance is mainly determined by the gate oxide capacitance. At different frequencies, the shapes of the capacitance-voltage curves are basically the same, indicating that the device has good frequency response characteristics within the tested frequency range. The varactor ratio of the MOS varactor is 2.4.

[0049] Figure 6 is the Q-value-voltage curve of the MOS varactor based on MoS 2 . The capacitance-voltage curve of the MOS varactor is shown. 21 frequencies are selected for testing in the frequency range from 50 kHz to 2 MHz. In the accumulation region, the device achieves a Q value as high as 52, indicating its low loss and high performance.

[0050] Figure 7 is the conductance-voltage curve of the MOS varactor based on MoS 2 . 26 frequencies are selected for testing in the frequency range from 400 Hz to 2 MHz. In the varactor region, the conductance reaches the maximum value, indicating that the device has a high carrier concentration and low impedance in this region; the device has good frequency response characteristics in the frequency range from 400 Hz to 2 MHz, but there is a certain loss at high frequencies.

[0051] Figure 8 is the phase angle-voltage curve of the MOS varactor based on MoS 2 . 21 frequencies are selected for testing in the frequency range from 50 kHz to 2 MHz. The phase angle is the phase difference between the voltage and the current, which is used to describe the impedance characteristics of the device: the MOS varactor exhibits excellent capacitance characteristics when operating in the accumulation region and the depletion region, and the phase angle basically remains below -80°, proving that it mainly exhibits capacitance characteristics in these operating regions.

[0052] In summary, a MOS varactor based on two-dimensional transition metal chalcogenides provided by the present invention, compared with the traditional silicon-based MOS varactor, significantly improves the Q value and varactor ratio of the MOS varactor by introducing two-dimensional material high-k dielectrics and optimizing the device structure. Specifically, by utilizing the atomic-level thickness and high mobility characteristics of two-dimensional materials, low interface states and high Q values are achieved. MoS 2The low dielectric constant can obtain a smaller capacitance in the depletion state, thereby achieving a larger varactor ratio. At the same time, HfO with a high dielectric constant is selected as the gate dielectric, which significantly reduces the leakage current of the device and further improves the overall performance of the device. The use of a multi-finger device structure and a short-channel design not only increases the effective area of the MOS varactor, improves the capacitance tuning range, but also effectively reduces the parasitic effect and further optimizes the high-frequency performance. The MOS varactor based on two-dimensional materials designed in the present invention exhibits significant advantages in high-frequency tuning and varactor applications. Its optimized device structure and material selection enable it to have stable capacitance characteristics under high-frequency conditions, while achieving the dual goals of high Q value and large varactor ratio. The capacitance characteristics are relatively stable under high-frequency conditions. These characteristics make it suitable for high-frequency tuning and varactor applications. 2 As the gate dielectric, it significantly reduces the leakage current of the device and further improves the overall performance of the device. By adopting a multi-finger device structure and a short-channel design, not only the effective area of the MOS varactor is increased, the capacitance tuning range is improved, but also the parasitic effect is effectively reduced, and the high-frequency performance is further optimized. The MOS varactor based on two-dimensional materials designed in the present invention shows significant advantages in high-frequency tuning and varactor applications. Its optimized device structure and material selection make it have stable capacitance characteristics under high-frequency conditions, and at the same time achieve the dual goals of high Q value and large varactor ratio. The capacitance characteristics are relatively stable under high-frequency conditions. These characteristics make it suitable for high-frequency tuning and varactor applications.

Claims

1. A MOS varactor based on two-dimensional materials, characterized in that: include: substrate; A channel layer, wherein the channel layer is a two-dimensional transition metal chalcogenide film; A gate, wherein the gate is composed of a plurality of gate fingers in the form of finger strips connected to each other to form a multi-finger structure, a source electrode and a drain electrode are respectively arranged on both sides of each gate finger, and the source electrode and the drain electrode are short-circuited; The gate dielectric layer is disposed between the channel layer and the gate.

2. The MOS varactor based on two-dimensional materials according to claim 1, characterized in that: The two-dimensional transition metal chalcogenide film is a molybdenum disulfide film.

3. The MOS varactor based on two-dimensional materials according to claim 2, characterized in that: The channel layer corresponding to each gate finger has a length of 1 μm and a width of 10 μm.

4. The MOS varactor based on two-dimensional materials according to claim 1, characterized in that: The gate dielectric layer is a hafnium dioxide film, and the thickness of the hafnium dioxide film is 6-10 nm.

5. The MOS varactor based on two-dimensional materials according to claim 1, characterized in that: The source and drain are antimony / gold stacked metal films deposited by electron beam evaporation, and the total thickness of the antimony / gold stacked metal films is 40-200 nm.

6. The MOS varactor based on two-dimensional materials according to claim 1, characterized in that: The grid is a titanium / gold laminated metal film deposited by electron beam evaporation, and the total thickness of the titanium / gold laminated metal film is 40-200nm.

7. A method for preparing a MOS varactor based on two-dimensional materials according to any one of claims 1 to 6, characterized in that: The following steps are involved: S1. Prepare a single-layer two-dimensional transition metal chalcogenide film on a sapphire substrate using chemical vapor deposition; S2, wet-transferring the two-dimensional transition metal chalcogenide thin film onto an intrinsic silicon substrate; S3, patterning the channel and source / drain regions by electron beam exposure, short-circuiting the source and drain electrodes, and depositing antimony / gold stacked metal films by electron beam evaporation as source and drain electrodes; S4. A hafnium dioxide film is deposited by atomic layer deposition, and a titanium / gold stacked metal film is evaporated by electron beam evaporation as a gate electrode.

8. The method for preparing a MOS varactor of a two-dimensional material according to claim 7, characterized in that: The specific steps of step S1 are: S11, placing sulfur powder in a quartz crucible, heating to 170° C., and simultaneously introducing argon gas at a flow rate of 100 sccm to promote the transfer of sulfur; S12. The molybdenum sheet is used as a molybdenum source, heated to 650°C, and introduced into another gas flow in the growth chamber, which contains 5-10sccm of oxygen and 50sccm of argon. It is then deposited onto the substrate in the third temperature zone together with sulfur vapor at a growth temperature of 950°C.

9. The method for preparing a MOS varactor of a two-dimensional material according to claim 7, characterized in that: The specific steps of step S2 are: S21, spin coating polymethyl methacrylate on the original substrate with the two-dimensional transition metal chalcogenide film and baking at 150° C. to form a molybdenum disulfide / polymethyl methacrylate film, soaking the MoS2 / PMMA film in a potassium hydroxide solution to separate it from the original substrate, and then pasting it on an intrinsic silicon substrate; S22, performing annealing treatment in a vacuum environment; S23, immersed in acetone to dissolve polymethyl methacrylate and dried with nitrogen.

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