Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprises a substrate and a multi-channel heterojunction layer, the substrate and the multi-channel heterojunction layer are stacked, the multi-channel heterojunction layer is provided with a first heterojunction layer,..., an mth heterojunction layer,... and an nth heterojunction layer in the direction away from the substrate, and each heterojunction layer comprises a channel layer and a barrier layer; the anode and the cathode are located at the two ends of the multi-channel heterojunction layer, the anode comprises at least one set of anode fingers, the set of anode fingers comprises n anode fingers of the first anode finger,..., the mth anode finger,... and the nth anode finger which are different in length, and the mth anode finger partially penetrates through the multi-channel heterojunction layer to the corresponding mth heterojunction layer. According to the semiconductor structure, the plurality of anode fingers independently control the plurality of channels of the semiconductor structure, so that the phenomenon of electric field concentration occurring on a Schottky interface where anode metal and a semiconductor are in contact under the condition that the semiconductor structure is subjected to relatively large reverse bias voltage is avoided, electric field peaks are avoided, and the breakdown voltage of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] The junction barrier Schottky (JBS) diode, as a type of enhanced Schottky diode, has become a research hotspot. The outstanding advantage of the junction barrier Schottky diode is that it has the on-state and fast switching characteristics of a Schottky barrier diode, as well as the off-state and low leakage current characteristics of a PIN diode.

[0003] Compared with a junction barrier Schottky diode having a single two-dimensional electron gas (2DEG) channel, a junction barrier Schottky diode having a multi-2DEG channel structure can have a higher electron mobility and a lower sheet resistance of the material, thereby further reducing the series resistance. However, when a junction barrier Schottky diode having a multi-2DEG channel structure is subjected to a relatively large reverse bias, an electric field concentration phenomenon will occur at the Schottky interface between the anode metal and the semiconductor, generating an electric field spike, resulting in premature breakdown of the device. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof to solve the technical problem of premature breakdown of a device caused by electric field concentration at the anode metal of a multi-channel junction barrier Schottky diode in the prior art.

[0005] According to one aspect of the present disclosure, an embodiment of the present disclosure provides a semiconductor structure, characterized by comprising:

[0006] A substrate and a multi-channel heterojunction layer stacked thereon, wherein in the direction away from the substrate, the multi-channel heterojunction layer is the 1st, …, the mth, …, the nth heterojunction layer, 1 ≤ m ≤ n, n ≥ 2, and m and n are both integers. Each heterojunction layer includes a channel layer and a barrier layer;

[0007] An anode and a cathode located at both ends of the multi-channel heterojunction layer. The anode includes at least one set of anode fingers. The set of anode fingers includes n anode fingers of different lengths, namely the 1st, …, the mth, …, the nth anode fingers, 1 ≤ m ≤ n, n ≥ 2, and m and n are both integers. The mth anode finger partially penetrates the multi-channel heterojunction layer into the corresponding mth heterojunction layer.

[0008] As an optional embodiment, the bottom surface of the mth anode finger is located in the channel layer of the corresponding mth heterojunction layer, at the interface between the channel layer and the barrier layer, or in the barrier layer.

[0009] As an alternative embodiment, the width of the m-th anode finger is less than that of the (m - 1)-th anode finger, where 2 ≤ m ≤ n, and both m and n are integers.

[0010] As an alternative embodiment, the set of anode fingers are electrically connected.

[0011] As an alternative embodiment, multiple first anode fingers are electrically connected,..., multiple m-th anode fingers are electrically connected,..., and multiple n-th anode fingers are electrically connected.

[0012] As an alternative embodiment, the semiconductor structure further includes:

[0013] A plurality of first P-type regions spaced apart from each other at one end of the multi-channel heterojunction layer, the first P-type regions extending from the surface of the multi-channel heterojunction layer on the side away from the substrate towards the substrate, and the bottom surface of at least one of the first P-type regions is located in the channel layer of the first layer of heterojunction.

[0014] As an alternative embodiment, at least one of the first P-type regions is included between two adjacent sets of the anode fingers.

[0015] As an alternative embodiment, one of the first P-type regions is included between at least two adjacent anode fingers in the set of anode fingers.

[0016] As an alternative embodiment, along the direction from the anode towards the cathode, the length of each of the first P-type regions increases uniformly or stepwise in the direction away from the substrate.

[0017] As an alternative embodiment, along the direction from one anode finger towards another anode finger, the length of each of the first P-type regions increases uniformly or stepwise in the direction away from the substrate.

[0018] As an alternative embodiment, the semiconductor structure further includes a second P-type layer located on the multi-channel heterojunction layer and the plurality of first P-type regions, and the second P-type layer is connected to the plurality of first P-type regions.

[0019] As an alternative embodiment, along the direction from the anode towards the cathode, the length of the second P-type layer is greater than or equal to the length of the first P-type region.

[0020] According to another aspect of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which is characterized by including the following steps:

[0021] S1. Grow a multi-channel heterojunction layer on a substrate, where the multi-channel heterojunction layer has the first,..., the m-th,..., the n-th layer of heterojunction in the direction away from the substrate, 1 ≤ m ≤ n, n ≥ 2, and both m and n are integers, and each layer of the heterojunction includes a channel layer and a barrier layer;

[0022] S2. Etch both ends of the multi-channel heterojunction layer to form an anode region and a cathode region. The anode region includes at least one set of anode finger grooves. The set of anode finger grooves includes the 1st, …, the mth, …, the nth anode finger grooves with different lengths, where 1 ≤ m ≤ n, n ≥ 2, and both m and n are integers. The mth anode finger groove at least partially penetrates the multi-channel heterojunction layer into the corresponding mth layer of heterojunction;

[0023] S3. Set an anode in the anode region and a cathode in the cathode region. The 1st, …, the mth, …, the nth anode fingers are in the 1st, …, the mth, …, the nth anode finger grooves. The mth anode finger partially penetrates the multi-channel heterojunction layer into the corresponding mth layer of heterojunction.

[0024] As an optional embodiment, the bottom surface of the mth anode finger groove is located in the channel layer of the corresponding mth layer of heterojunction, at the interface between the channel layer and the barrier layer, or in the barrier layer.

[0025] As an optional embodiment, the width of the mth anode finger groove is less than the width of the (m - 1)th anode finger groove, where 2 ≤ m ≤ n and both m and n are integers.

[0026] As an optional embodiment, after step S1, it further includes:

[0027] S11. Set a plurality of spaced-apart first P-type regions at one end of the multi-channel heterojunction layer. The first P-type regions extend from the surface of the multi-channel heterojunction layer away from the substrate towards the substrate. The bottom surface of at least one of the first P-type regions is located in the channel layer of the 1st layer of heterojunction.

[0028] As an optional embodiment, after step S11, it further includes:

[0029] S12. Continuously epitaxially grow a healed second P-type layer on the first P-type regions.

[0030] The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate and a multi-channel heterojunction layer arranged in a stacked manner. In the direction away from the substrate, the multi-channel heterojunction layer includes the 1st, …, the mth, …, the nth heterojunctions. Each heterojunction includes a channel layer and a barrier layer; an anode and a cathode, located at both ends of the multi-channel heterojunction layer. The anode includes at least one set of anode fingers. One set of anode fingers includes n anode fingers with different lengths, namely the 1st, …, the mth, …, the nth anode fingers. The mth anode finger partially penetrates the multi-channel heterojunction layer into the corresponding mth heterojunction. The present disclosure independently controls multiple channels of the semiconductor structure through multiple anode fingers, thereby avoiding the electric field concentration phenomenon occurring at the Schottky interface between the anode metal and the semiconductor when the semiconductor structure is under a large reverse bias, avoiding the generation of electric field spikes, and improving the breakdown voltage of the semiconductor structure. The multiple anode fingers designed in the present disclosure are located on the same side of the multi-channel heterojunction layer, eliminating the need to etch steps to form multiple anodes for independently controlling multiple channels, and effectively reducing the space occupied by the anode region without sacrificing the channel length while achieving independent control of multiple channels. Description of the Drawings

[0031] Figure 1 The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0032] Figures 2a to 2c The figure shows a side view of a semiconductor structure provided by some embodiments of the present disclosure.

[0033] Figure 3 The figure shows a side view of a semiconductor structure provided by some embodiments of the present disclosure.

[0034] Figures 4a to 4b The figure shows a side view of a semiconductor structure provided by some embodiments of the present disclosure.

[0035] Figure 5 The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0036] Figures 6a to 6b The figure shows a side view of a semiconductor structure provided by some embodiments of the present disclosure.

[0037] Figures 7a to 7b The figure shows a cross-sectional view of the first P-type region of a semiconductor structure provided by an embodiment of the present disclosure.

[0038] Figures 8a to 8b The figure shows a side view of a semiconductor structure provided by an embodiment of the present disclosure.

[0039] Figure 9 The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.

[0040] Figure 10The figure shows a flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

[0041] Figures 11 to 18 The figure shows a schematic diagram of an intermediate structure corresponding to a semiconductor structure provided by an embodiment of the present disclosure during the manufacturing process. Detailed implementation manners

[0042] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0043] To solve the technical problem of premature breakdown of a device caused by electric field concentration at the anode metal of a multi-channel junction barrier Schottky diode in the prior art, the present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate and a multi-channel heterojunction layer stacked thereon. In the direction away from the substrate, the multi-channel heterojunction layer includes the first, …, the m-th, …, the n-th heterojunctions. Each heterojunction includes a channel layer and a barrier layer; an anode and a cathode located at both ends of the multi-channel heterojunction layer. The anode includes at least one set of anode fingers. One set of anode fingers includes n anode fingers of the first, …, the m-th, …, the n-th anode fingers with different lengths. The m-th anode finger partially penetrates the multi-channel heterojunction layer into the corresponding m-th heterojunction. The present disclosure independently controls multiple channels of the semiconductor structure through multiple anode fingers, thereby avoiding the electric field concentration phenomenon occurring at the Schottky interface between the anode metal and the semiconductor when the semiconductor structure is under a large reverse bias, avoiding the generation of electric field spikes, and improving the breakdown voltage of the semiconductor structure. The multiple anode fingers designed in the present disclosure are located on the same side of the multi-channel heterojunction layer, without the need to etch steps to form multiple anodes for independently controlling multiple channels, and without sacrificing the channel length, it is possible to effectively reduce the space occupied by the anode region while realizing the independent control of multiple channels.

[0044] Next, in combination with Figures 1 to 18 Further, a semiconductor structure and a manufacturing method thereof mentioned in the present disclosure are illustrated by examples.

[0045] Figure 1 The figure shows a schematic diagram of the structure of a semiconductor structure provided by an embodiment of the present disclosure. As Figure 1As shown, the semiconductor structure includes a substrate 10 and a multi-channel heterojunction layer 20 arranged in a stacked manner. In the direction away from the substrate 10, the multi-channel heterojunction layer 20 is the 1st, …, the mth, …, the nth heterojunction layer, where 1 ≤ m ≤ n, n ≥ 2, and both m and n are integers. Each heterojunction layer includes a channel layer 21 and a barrier layer 22; an anode 41 and a cathode 42 are located at both ends of the multi-channel heterojunction layer 20. The anode 41 includes at least one set of anode fingers. One set of anode fingers includes n anode fingers of the 1st, …, the mth, …, the nth anode fingers with different lengths, where 1 ≤ m ≤ n, n ≥ 2, and both m and n are integers. The mth anode finger partially penetrates the multi-channel heterojunction layer 20 into the corresponding mth heterojunction layer.

[0046] In this embodiment, the multi-channel heterojunction layer 20 may only include two heterojunction layers, namely the 1st heterojunction layer and the 2nd heterojunction layer arranged in a stacked manner in the direction away from the substrate 10. In other embodiments, the multi-channel heterojunction layer 20 may include three or more heterojunction layers, namely the 1st heterojunction layer, the 2nd heterojunction layer, …, the nth heterojunction layer arranged in a stacked manner in the direction away from the substrate 10, where n ≥ 3. Each heterojunction layer includes a channel layer 21 and a barrier layer 22, and the bandgap width of the material of the barrier layer 22 is greater than that of the material of the channel layer 21. The material of the channel layer 21 and the material of the barrier layer 22 may include group III nitride materials, and a two-dimensional electron gas may be formed at the interface between the channel layer 21 and the barrier layer 22. In an alternative solution, the channel layer 21 is a GaN layer and the barrier layer 22 is an AlGaN layer. In other alternative solutions, the material combination of the channel layer 21 and the barrier layer 22 may also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN. The materials of the multi-layer heterojunction layers may be the same or different, and the present disclosure does not make specific limitations.

[0047] Figures 2a to 2c The figure shows a side view of a semiconductor structure provided by some embodiments of the present disclosure. In this embodiment, the mth anode finger partially penetrates the multi-channel heterojunction layer 20 into the corresponding mth heterojunction layer, and the bottom surface of the mth anode finger is located in the channel layer 21 of the corresponding mth heterojunction layer (as shown in Figure 2a ), at the interface between the channel layer 21 and the barrier layer 22 (as shown in Figure 2b ), or in the barrier layer 22 (as shown in Figure 2c ). By designing the anode fingers at different depths in the multi-channel heterojunction layer 20, the control ability of the anode fingers over the corresponding channels can be adjusted.

[0048] Figure 3 The figure shows a side view of a semiconductor structure provided by some embodiments of the present disclosure. In one embodiment, as shown in Figure 3As shown, the width of the m-th anode finger is smaller than that of the (m - 1)-th anode finger, where 2 ≤ m ≤ n and both m and n are integers. That is, the width of the anode finger corresponding to the heterojunction farther away from the substrate 10 is smaller. A larger anode finger width can provide greater control ability. Under the condition of the same anode finger width, the anode control ability of the heterojunction farther away from the substrate 10 is greater. Therefore, the width of the anode finger corresponding to the heterojunction farther away from the substrate 10 can be reduced, and the use of anode material can be decreased.

[0049] Figures 4a to 4b The figure shows a side view of a semiconductor structure provided by some embodiments of the present disclosure. In this embodiment, all anode fingers can be electrically connected, such as Figure 1 shown; in one embodiment, a group of anode fingers are electrically connected, and different groups of anode fingers are not electrically connected, such as Figure 4a shown; in another embodiment, multiple first anode fingers are electrically connected,..., multiple m-th anode fingers are electrically connected,..., and multiple n-th anode fingers are electrically connected. Different electrical connection methods of the anode fingers can achieve common control or independent control of different channels of the semiconductor structure.

[0050] Figure 5 The figure shows a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. Figures 6a to 6b The figure shows a side view of a semiconductor structure provided by some embodiments of the present disclosure. In one embodiment, as Figure 5 shown, the semiconductor structure further includes: a plurality of spaced first P-type regions 31 located at one end of the multi-channel heterojunction layer 20. The first P-type regions 31 extend from the surface of the multi-channel heterojunction layer 20 away from the substrate 10 towards the substrate 10, and the bottom surface of at least one first P-type region 31 is located in the channel layer 21 of the first layer heterojunction. As Figure 6a shown, at least one first P-type region 31 is included between adjacent two groups of anode fingers; as Figure 6b shown, one first P-type region 31 is included between at least two adjacent anode fingers in a group of anode fingers. By forming a lateral PN junction between the first P-type region 31 and the two-dimensional electron gas in the heterojunction, when reverse-biased, the depletion region of the PN junction expands to pinch off the current channel, effectively shielding the Schottky junction with a low barrier height, suppressing the Schottky barrier lowering effect and controlling the reverse leakage current, thereby increasing the breakdown voltage and maintaining a low turn-on voltage. At the same time, multiple stacked heterojunctions are used to form multiple parallel two-dimensional electron gas paths between the anode 41 and the cathode 42 to compensate for the depletion of the two-dimensional electron gas by the first P-type region 31 and ensure the forward current of the diode.

[0051] Figures 7a to 7b The figure shows a cross-sectional view of the first P-type region of a semiconductor structure provided by an embodiment of the present disclosure. Figures 8a to 8bThe following is a side view of a semiconductor structure provided by an embodiment of the present disclosure. In one embodiment, the contact interface between the channel layer 21 and the barrier layer 22 in each heterojunction layer has a two-dimensional electron gas, and the lengths of the first P-type regions 31 at different two-dimensional electron gases in the direction from the anode 41 to the cathode 42 and / or in the direction from one anode finger to another anode finger are different. Specifically, in the direction from the anode 41 to the cathode 42, the length of each first P-type region 31 increases uniformly (as shown in Figure 7a shown) or increases stepwise (as shown in Figure 7b shown) in the direction away from the substrate 10, and / or, in the direction from one anode finger to another anode finger, the length of each first P-type region 31 increases uniformly (as shown in Figure 8a shown) or increases stepwise (as shown in Figure 8b shown) in the direction away from the substrate 10. By changing the length of the first P-type region 31, on the one hand, the channel shape can be changed to increase the electron movement path, thereby reducing the on-state resistance, and on the other hand, the depletion layer width can be changed to reduce the peak electric field, thereby increasing the breakdown voltage.

[0052] Figure 9 The following is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. In one embodiment, as shown in Figure 9 shown, the P-type epitaxial layer 30 further includes a second P-type layer 32 located on the multi-channel heterojunction layer 20 and a plurality of first P-type regions 31, and the second P-type layer 32 is connected to the plurality of first P-type regions 31. In the direction from the anode 41 to the cathode 42, the length of the second P-type layer 32 is greater than or equal to the length of the first P-type region 31. The first P-type region 31 and the second P-type layer 32 can cooperate to redistribute the surface electric field of the heterojunction structure between the anode 41 and the cathode 42, improve the electric field distribution at the edge of the anode 41, prevent avalanche breakdown, and further increase the breakdown voltage of the device and reduce the reverse leakage current.

[0053] According to another aspect of the present disclosure, Figure 10 The following is a flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, Figures 11 to 18 The following is a schematic diagram of an intermediate structure corresponding to the semiconductor structure during manufacturing provided by an embodiment of the present disclosure. As shown in Figure 10 shown, the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure includes the following steps:

[0054] Step S1: Grow a multi-channel heterojunction layer on the substrate. In the direction away from the substrate, the multi-channel heterojunction layer is the 1st, …, the mth, …, the nth heterojunction layer, 1 ≤ m ≤ n, n ≥ 2, and both m and n are integers. Each heterojunction layer includes a channel layer and a barrier layer.

[0055] Specifically, as shown in Figure 11As shown, a multi-channel heterojunction layer 20 is grown on a substrate 10. In the direction away from the substrate 10, the multi-channel heterojunction layer 20 has the 1st, …, the mth, …, the nth heterojunctions, where 1 ≤ m ≤ n, n ≥ 2, and both m and n are integers. Each heterojunction includes a channel layer 21 and a barrier layer 22. The material of the substrate 10 includes any one or a combination of Si, Al 2 O 3 , GaN, SiC or AlN. The method for growing the multi-channel heterojunction layer 20 on the substrate 10 can be in-situ growth, or can be obtained by atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), metal-organic chemical vapor deposition (MOCVD) or a combination thereof.

[0056] Step S11: A plurality of first P-type regions are arranged at one end of the multi-channel heterojunction layer at intervals. The first P-type regions extend from the surface of the multi-channel heterojunction layer away from the substrate towards the substrate, and the bottom surface of at least one first P-type region is located in the channel layer of the 1st heterojunction.

[0057] Specifically, as Figure 12 shown, a plurality of first P-type regions 31 are arranged at one end of the multi-channel heterojunction layer 20 at intervals. The first P-type regions 31 extend from the surface of the multi-channel heterojunction layer 20 away from the substrate 10 towards the substrate 10, and the bottom surface of at least one first P-type region 31 is located in the channel layer 21 of the 1st heterojunction. By forming a lateral PN junction between the first P-type region 31 and the two-dimensional electron gas in the heterojunction, when reverse-biased, the depletion region of the PN junction widens to pinch off the current channel, effectively shielding the Schottky junction with a low barrier height, which can suppress the Schottky barrier lowering effect and control the reverse leakage current, thereby increasing the breakdown voltage and maintaining a low turn-on voltage.

[0058] Step S12: A healed second P-type layer is continuously epitaxially formed on the first P-type region.

[0059] Specifically, as Figure 13As shown, a healed second P-type layer 32 is continuously epitaxially formed on the first P-type region 31. The first P-type region 31 and the second P-type layer 32 can cooperate to redistribute the surface electric field of the heterojunction structure between the anode 41 and the cathode 42, improve the electric field distribution at the edge of the anode 41, prevent avalanche breakdown, further increase the breakdown voltage of the device and reduce the reverse leakage current.

[0060] Step S2: Etch both ends of the multi-channel heterojunction layer 20 to form an anode region and a cathode region. The anode region includes at least one set of anode finger grooves. One set of anode finger grooves includes the 1st, …, the mth, …, the nth anode finger grooves with different lengths, where 1 ≤ m ≤ n, n ≥ 2, and both m and n are integers. The mth anode finger groove at least partially penetrates the multi-channel heterojunction layer into the corresponding mth layer of the heterojunction.

[0061] Specifically, as Figure 14 shown, etch both ends of the multi-channel heterojunction layer 20 to form an anode region and a cathode region. The anode region includes at least one set of anode finger grooves 401. One set of anode finger grooves 401 includes the 1st, …, the mth, …, the nth anode finger grooves 401 with different lengths, where 1 ≤ m ≤ n, n ≥ 2, and both m and n are integers. The mth anode finger groove 401 at least partially penetrates the multi-channel heterojunction layer 20 into the corresponding mth layer of the heterojunction.

[0062] In one embodiment, the bottom surface of the mth anode finger groove 401 is located in the channel layer 21 of the corresponding mth layer of the heterojunction (as Figure 15 shown), at the interface between the channel layer 21 and the barrier layer 22 (as Figure 16 shown), or in the barrier layer 22 (as Figure 17 shown). By designing the anode fingers at different depths in the multi-channel heterojunction layer 20, the control ability of the anode fingers on the corresponding channels can be regulated.

[0063] In one embodiment, as Figure 18 shown, the width of the mth anode finger groove 401 is smaller than the width of the (m - 1)th anode finger groove 401, where 2 ≤ m ≤ n, and both m and n are integers.

[0064] Step S3: Set an anode in the anode region and a cathode in the cathode region. The 1st, …, the mth, …, the nth anode finger grooves are the 1st, …, the mth, …, the nth anode fingers, and the mth anode finger partially penetrates the multi-channel heterojunction layer into the corresponding mth layer of the heterojunction.

[0065] Specifically, set an anode 41 in the anode region and a cathode 42 in the cathode region. The 1st, …, the mth, …, the nth anode finger grooves 401 are the 1st, …, the mth, …, the nth anode fingers, and the mth anode finger partially penetrates the multi-channel heterojunction layer 20 into the corresponding mth layer of the heterojunction, forming as Figure 9The semiconductor structure shown.

[0066] The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate and a multi-channel heterojunction layer arranged in a stacked manner. In the direction away from the substrate, the multi-channel heterojunction layer has the 1st, …, the mth, …, the nth heterojunction layers. Each heterojunction layer includes a channel layer and a barrier layer; an anode and a cathode, located at both ends of the multi-channel heterojunction layer. The anode includes at least one set of anode fingers. One set of anode fingers includes n anode fingers of the 1st, …, the mth, …, the nth anode fingers with different lengths. The mth anode finger partially penetrates the multi-channel heterojunction layer into the corresponding mth heterojunction layer. The present disclosure independently controls multiple channels of the semiconductor structure through multiple anode fingers, thereby avoiding the electric field concentration phenomenon occurring at the Schottky interface between the anode metal and the semiconductor when the semiconductor structure is under a large reverse bias, avoiding the generation of electric field spikes, and improving the breakdown voltage of the semiconductor structure. The multiple anode fingers designed in the present disclosure are located on the same side of the multi-channel heterojunction layer, without the need to etch steps to form multiple anodes for independently controlling multiple channels, and can effectively reduce the space occupied by the anode region without sacrificing the channel length while realizing the independent control of multiple channels.

[0067] It should be understood that the term "including" and its variants used in the present disclosure are open-ended, that is, "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0068] The above are only the preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, etc. made within the spirit and principle of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, comprising: a substrate (10) and a multi-channel heterojunction layer (20) arranged in a stacked manner, wherein in the direction away from the substrate (10), the multi-channel heterojunction layer (20) is the 1st, …, the mth, …, the nth heterojunction layer, 1 ≤ m ≤ n, n ≥ 2, both m and n are integers, and each heterojunction layer comprises a channel layer (21) and a barrier layer (22); an anode (41) and a cathode (42), located at two ends of the multi-channel heterojunction layer (20), the anode (41) comprises at least one set of anode fingers, and the set of anode fingers comprises n anode fingers of the 1st, …, the mth, …, the nth anode fingers with different lengths, 1 ≤ m ≤ n, n ≥ 2, both m and n are integers, and the mth anode finger partially penetrates through the multi-channel heterojunction layer (20) into the corresponding mth heterojunction layer.

2. The semiconductor structure according to claim 1, characterized in that, the bottom surface of the mth anode finger is located in the channel layer (21) of the corresponding mth heterojunction layer, at the interface between the channel layer (21) and the barrier layer (22), or in the barrier layer (22).

3. The semiconductor structure according to claim 1, characterized in that, the width of the mth anode finger is smaller than the width of the (m - 1)th anode finger, 2 ≤ m ≤ n, both m and n are integers.

4. The semiconductor structure according to claim 1, characterized in that, the set of anode fingers is electrically connected.

5. The semiconductor structure according to claim 1, characterized in that, a plurality of the 1st anode fingers are electrically connected, …, a plurality of the mth anode fingers are electrically connected, …, a plurality of the nth anode fingers are electrically connected.

6. The semiconductor structure according to claim 1, characterized in that, the semiconductor structure further comprises: a plurality of first P-type regions (31) arranged at intervals at one end of the multi-channel heterojunction layer (20), the first P-type regions (31) extend from the surface on the side of the multi-channel heterojunction layer (20) away from the substrate (10) towards the substrate (10), and the bottom surface of at least one first P-type region (31) is located in the channel layer (21) of the 1st heterojunction layer.

7. The semiconductor structure according to claim 6, characterized in that, at least one first P-type region (31) is included between two adjacent sets of the anode fingers.

8. The semiconductor structure according to claim 6, characterized in that, one first P-type region (31) is included between at least two adjacent anode fingers in the set of anode fingers.

9. The semiconductor structure according to claim 6, characterized in that, along the direction from the anode (41) to the cathode (42), the length of each first P-type region (31) increases uniformly or stepwise in the direction away from the substrate (10).

10. The semiconductor structure according to claim 6, characterized in that, along the direction from one anode finger to another anode finger, the length of each first P-type region (31) increases uniformly or stepwise in the direction away from the substrate (10).

11. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure further includes a second P-type layer (32) located on the multi-channel heterojunction layer (20) and the plurality of first P-type regions (31), and the second P-type layer (32) is connected to the plurality of first P-type regions (31).

12. The semiconductor structure according to claim 11, wherein, along the direction from the anode (41) to the cathode (42), the length of the second P-type layer (32) is greater than or equal to the length of the first P-type region (31).

13. A manufacturing method of a semiconductor structure, wherein, it includes the following steps: S1. Grow a multi-channel heterojunction layer (20) on a substrate (10). In the direction away from the substrate (10), the multi-channel heterojunction layer (20) is the 1st, …, the mth, …, the nth layer of heterojunctions, 1 ≤ m ≤ n, n ≥ 2, m and n are both integers. Each layer of the heterojunction includes a channel layer (21) and a barrier layer (22); S2. Etch both ends of the multi-channel heterojunction layer (20) to form an anode region and a cathode region. The anode region includes at least one group of anode finger grooves (401). The group of anode finger grooves (401) includes the 1st, …, the mth, …, the nth anode finger grooves (401) with different lengths, 1 ≤ m ≤ n, n ≥ 2, m and n are both integers. The mth anode finger groove (401) at least partially penetrates through the multi-channel heterojunction layer (20) into the corresponding mth layer of heterojunction; S3. Set an anode (41) in the anode region and a cathode (42) in the cathode region. The 1st, …, the mth, …, the nth anode fingers are in the 1st, …, the mth, …, the nth anode finger grooves (401), and the mth anode finger partially penetrates through the multi-channel heterojunction layer (20) into the corresponding mth layer of heterojunction.

14. The manufacturing method of the semiconductor structure according to claim 13, wherein, the bottom surface of the mth anode finger groove (401) is located in the channel layer (21) of the corresponding mth layer of heterojunction, at the interface between the channel layer (21) and the barrier layer (22), or in the barrier layer (22).

15. The manufacturing method of the semiconductor structure according to claim 13, wherein, the width of the mth anode finger groove (401) is smaller than the width of the (m - 1)th anode finger groove (401), 2 ≤ m ≤ n, m and n are both integers.

16. The manufacturing method of the semiconductor structure according to claim 13, wherein, after the step S1, it further includes: S11. Set a plurality of first P-type regions (31) with intervals at one end of the multi-channel heterojunction layer (20). The first P-type regions (31) extend from the surface of the multi-channel heterojunction layer (20) away from the substrate (10) towards the substrate (10), and the bottom surface of at least one first P-type region (31) is located in the channel layer (21) of the 1st layer of heterojunction.

17. The manufacturing method of the semiconductor structure according to claim 16, wherein, after the step S11, it further includes: S12. On the first P-type region (31), continue epitaxial growth to form a healed second P-type layer (32).

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