IGBT device integrated with mos-controlled floating schottky diode and method of fabrication

Abstract

The present application relates to power semiconductor technology, and in particular to an IGBT device integrated with MOS-controlled floating Schottky diodes and a preparation method. Compared with the previous Floating P-body IGBT structure, the IGBT proposed in the present application embeds two series-connected floating Schottky diodes (P-type Schottky diode and N-type Schottky diode) in the emitter end. When the device is in forward conduction, the potential of the floating P-type region is less than the sum of the turn-on voltages of the two floating Schottky diodes, which further enhances carrier injection and optimizes carrier distribution, thereby enhancing the conductance modulation effect of the device, thereby reducing the on-state loss of the device. When the device is in short-circuit resistance, the voltage across the collector and emitter of the device is large, at this time the potential of the floating P-type region is greater than the sum of the turn-on voltages of the two floating Schottky diodes, the holes in the device body will disappear through the floating metal to reduce the saturation current of the device, and improve the short-circuit resistance of the device.

Description

Technical Field

[0001] This invention relates to power semiconductor technology, specifically to an IGBT device and its fabrication method that integrates a MOS-controlled floating Schottky diode. Background Technology

[0002] With the continuous advancement of science and technology and the increasing reliance on electricity, achieving efficient power transmission, conversion, and control has become a key focus of society. Power semiconductors, as core components in power transmission, conversion, and control, are widely used in computers, network communications, consumer electronics, and industrial control, serving as a crucial foundation for energy conservation and emission reduction. In automotive electronics, power semiconductor chips are used to control high-power currents, particularly in the main drive control of electric vehicles, placing higher demands on the efficiency, reliability, and robustness of power semiconductors and driving the advancement of modern automobiles. Furthermore, in the aerospace field, power semiconductors play a vital role in ensuring the stability and reliability of aerospace transportation vehicles, requiring further improvements in device reliability.

[0003] IGBTs, as bipolar power semiconductor devices, are key components for efficient power transmission, conversion, and control, often referred to as the "CPU" of power electronics technology. They are widely used in consumer electronics, industrial control circuits, intelligent transportation, and aerospace. As gate-controlled bipolar devices, IGBTs utilize two types of charge carriers during conduction, with minority carriers also participating in conductivity modulation, further reducing the on-resistance in the drift region and effectively lowering conduction losses. To further reduce conduction losses, IGBT technology needs further development. Trench-gate floating P-body IGBTs have been proposed; however, the introduction of a trench gate enhances the short-channel effect, increasing the saturation current during conduction and making the device prone to thermal breakdown. Simultaneously, when the device is in a short-circuit state, the voltage and current it withstands are large, resulting in very high power consumption and a high risk of thermal breakdown. Therefore, improving the short-circuit withstand capability of devices while maintaining low conduction losses has become a key focus for both academia and industry. Based on this, the present invention proposes an IGBT structure with integrated MOS gate-controlled floating Schottky diode. By integrating the MOS gate-controlled floating Schottky diode, the carrier injection efficiency can be controlled, and a conduction path can be provided for hole current. This helps to further reduce the saturation current of the device and improve the short-circuit withstand capability of the device. Summary of the Invention

[0004] To address the above problems, this invention proposes an IGBT device with an integrated MOS-controlled floating Schottky diode.

[0005] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0006] An IGBT device structure integrating a MOS-controlled floating Schottky diode includes a collector metal 1, a P-type collector region 2, an N-type buffer layer 3, an N-type drift region 4, a floating P-type region 5, an N-type blocking region 6, a P-body 7, a P+ emitter region 8, an N+ emitter region 9, a trench gate oxide layer 10, a gate polysilicon layer 11, an emitter metal 12, a floating metal 13, a P+ emitter contact region 14, an N+ emitter contact region 15, a gate oxide layer isolation region 16, and a floating metal oxide layer isolation region 17.

[0007] The current collector metal 1 is located below the P-type current collector region 2; the P-type current collector region 2 is located between the current collector metal 1 and the N-type buffer layer 3; the N-type buffer layer 3 is located below the N-type drift region 4; the N-type drift region 4 is located below the floating P-type region 5; and the N-type blocking region 6 is located below the P-body 7.

[0008] The bottom of the trench gate oxide layer 10 is placed in the floating P-type region 5; the inner surface of the trench gate oxide layer 10 surrounds the gate polysilicon 11, and the trench gate oxide layer 10 penetrates the entire P-body 7 and N-type blocking region 6, dividing the P-body 7 and N-type blocking region 6 into left and right parts.

[0009] To the left of the trench gate oxide layer 10, above the P-body 7, are the P+ emitter region 8 and the N+ emitter region 9. The right surface of the P+ emitter region 8 is in contact with the N+ emitter region 9. Above the P+ emitter region 8 and the N+ emitter region 9 is the emitter metal 12. The lower surface of the emitter metal 12 is in contact with the P+ emitter region 8 and the N+ emitter region 9. The N-type drift region 4 is in contact with part of the lower surface of the N-type blocking region 6 on the left side of the trench gate oxide layer 10. The right surface of the N+ emitter region 9 is in contact with the trench gate oxide layer 10.

[0010] To the right of the trench gate oxide layer 10, above the P-body 7 are the N+ emitter contact region 15 and the P+ emitter contact region 14. The left surface of the P+ emitter contact region 14 contacts the N+ emitter contact region 15, and the lower surface of the P+ emitter contact region 14 contacts the P-body 7. The right surfaces of both the P+ emitter contact region 14 and the P-body 7 are in contact with the empty metal oxide isolation region 17. Below the P-body 7 and the floating metal oxide isolation region 17 is... The right surface of the N-type blocking region 6 and the floating metal oxide isolation region 17 is in contact with the floating metal 13; the floating P-type region 5 is located below the N-type blocking region 6, the left surface of the floating P-type region 5 is in contact with the N-type drift region 4, the upper surface of the floating P-type region 5 is in contact with the floating metal 13, the lower surface of the emitter metal 12 is in contact with the N+ emitter contact region 15 and the P+ emitter contact region 14, and the left surface of the N+ emitter contact region 15 is in contact with the gate oxide layer 10;

[0011] The trench gate oxide layer 10 is located below the gate oxide isolation region 16, and the outer surface of the trench gate oxide layer 10 is in contact with the floating P-type region 5, the N-type blocking region 6, the P-body 7, the N+ emitter region 9, and the N+ emitter contact region 15; the upper surface of the gate polysilicon 11 is in contact with the gate oxide isolation region 16; the emitter metal 12 is located at the top of the device, and the right surface of the emitter metal 12 is in contact with the floating metal oxide isolation region 17; the gate oxide isolation region 16 is located in the emitter metal 12, and the lower surface of the gate oxide isolation region 16 is in contact with the trench gate oxide layer 10 and the gate polysilicon 11.

[0012] As a preferred embodiment, the floating metal 13 forms a Schottky contact diode with the floating P-type region 5 and the N-type blocking region 6, wherein it forms an N-type Schottky diode with the N-type blocking region 6 and a P-type Schottky diode with the floating P-type region 5.

[0013] As a preferred method, the metal of the floating metal 13 is Al, Pt, Ni, AlSiCu or a metal composite, and its work function is adjusted by using different metals according to actual needs.

[0014] As a preferred embodiment, the anodes of the P-type Schottky diode and the N-type Schottky diode are shorted together by the floating metal 13.

[0015] As a preferred embodiment, the doping concentration of the floating P-type region 5 is 5 × 10⁻⁶. 16 cm -3 ~1×10 18 cm -3 between.

[0016] As a preferred embodiment, the doping concentration of the N-type blocking region 6 is 5 × 10⁻⁶. 16 cm-3 ~1×10 18 cm -3 between.

[0017] A second objective of this invention is to provide a method for fabricating the device, comprising the following steps:

[0018] (a) First, a floating P-type region 5 is formed by photolithography and P-type ion implantation and annealing; next, an N-type barrier region 6 is formed by N-type ion implantation and annealing; finally, a P-body 7 is formed by P-type ion implantation and annealing.

[0019] (b) A gate communication is formed by photolithography and etching; then, a trench gate oxide layer 10 is formed by high-temperature oxidation; next, the gate polysilicon 11 is filled by chemical deposition, and chemical mechanical polishing (CMP) is performed after deposition.

[0020] (c) The P+ emitter region 8 and the P+ emitter contact region 14 are formed by photolithography and P-type ion implantation and annealing; then, the N+ emitter region 9 and the N+ emitter contact region 15 are formed by photolithography and N-type ion implantation and annealing.

[0021] (d) A floating metal trench is formed by photolithography and etching, followed by physical deposition of metal to form floating metal 13, and finally chemical mechanical polishing (CMP) is performed.

[0022] (e) An oxide isolation layer is formed by chemical vapor deposition, followed by photolithography and etching to form the gate oxide isolation region 16;

[0023] (f) The emitter metal 12 is formed by physical deposition and then annealed to make the metal more closely contact the silicon surface;

[0024] (g) A trench is formed by photolithography and etching of silicon, and then filled with silicon dioxide. After chemical mechanical polishing (CMP), a floating metal oxide layer isolation region 17 is formed.

[0025] (h) The wafer is thinned to the required thickness using the TAIKO process or conventional thinning. Next, N-type ion implantation and annealing are performed to form an N-type buffer layer 3. Then, P-type ion implantation and annealing are performed to form a P-type collector region 2. Finally, back-side metal sputtering is performed to form the collector metal 1.

[0026] The beneficial effects of this invention are as follows: Compared to the previous floating P-body IGBT structure, the IGBT proposed in this invention embeds two series-connected floating Schottky diodes (P-type Schottky diode and N-type Schottky diode) controlled by a MOS at the emitter terminal. When the device is in forward conduction, the potential of the floating P-type region is less than the sum of the turn-on voltages of the two floating Schottky diodes, which further enhances carrier injection and optimizes carrier distribution, thereby enhancing the conductivity modulation effect of the device and reducing the conduction loss. When the device is in short-circuit withstand mode, the voltage across the collector and emitter terminals is relatively large. At this time, the potential of the floating P-type region is greater than the sum of the turn-on voltages of the two floating Schottky diodes. Holes in the device will disappear through floating metal recombination, thereby reducing the saturation current of the device and improving the short-circuit withstand capability. In summary, the IGBT device structure with integrated self-biased floating Schottky diodes proposed in this method not only improves the conduction performance of the device but also enhances its short-circuit withstand capability. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a traditional Floating P-body IGBT structure;

[0028] Figure 2 This is a schematic diagram of an IGBT device structure with an integrated MOS-controlled floating Schottky diode proposed in this invention;

[0029] Figure 3 This is a comparison diagram of the IV relationship between the IGBT with integrated MOS-controlled floating Schottky diode proposed in this invention and the traditional floating P-body IGBT in the forward conduction state;

[0030] Figure 4 This is a comparison of the saturation current of an IGBT with an integrated MOS-controlled floating Schottky diode proposed in this invention and a traditional floating P-body IGBT in the forward conduction state;

[0031] Figure 5 This is a comparison of the short-circuit withstand capabilities of an IGBT with an integrated MOS-controlled floating Schottky diode proposed in this invention and a traditional floating P-body IGBT.

[0032] Figures 6-13 This is a key process step in the manufacturing process of an IGBT device with an integrated MOS-controlled floating Schottky diode provided by the present invention;

[0033] The serial numbers are explained as follows:

[0034] 1-Collector metal, 2-P-type collector region, 3-N-type buffer layer, 4-N-type drift region, 5-Floating P-type region, 6-N-type blocking region, 7-P-body, 8-P+ emitter region, 9-N+ emitter region, 10-Trench gate oxide layer, 11-Gate polysilicon, 12-Emitter metal, 13-Floating metal, 14-P+ emitter contact region, 15-N+ emitter contact region, 16-Gate oxide layer isolation region, 17-Floating metal oxide layer isolation region. Detailed Implementation

[0035] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] Example 1

[0037] like Figure 2 As shown, 1. An IGBT device with an integrated MOS-controlled floating Schottky diode, comprising collector metal 1, P-type collector region 2, N-type buffer layer 3, N-type drift region 4, floating P-type region 5, N-type blocking region 6, P-body 7, P+ emitter region 8, N+ emitter region 9, trench gate oxide layer 10, gate polysilicon 11, emitter metal 12, floating metal 13, P+ emitter contact region 14, N+ emitter contact region 15, gate oxide layer isolation region 16, and floating metal oxide layer isolation region 17;

[0038] The current collector metal 1 is located below the P-type current collector region 2; the P-type current collector region 2 is located between the current collector metal 1 and the N-type buffer layer 3; the N-type buffer layer 3 is located below the N-type drift region 4; the N-type drift region 4 is located below the floating P-type region 5; and the N-type blocking region 6 is located below the P-body 7.

[0039] The bottom of the trench gate oxide layer 10 is placed in the floating P-type region 5; the inner surface of the trench gate oxide layer 10 surrounds the gate polysilicon 11, and the trench gate oxide layer 10 penetrates the entire P-body 7 and N-type blocking region 6, dividing the P-body 7 and N-type blocking region 6 into left and right parts.

[0040] To the left of the trench gate oxide layer 10, above the P-body 7, are the P+ emitter region 8 and the N+ emitter region 9. The right surface of the P+ emitter region 8 is in contact with the N+ emitter region 9. Above the P+ emitter region 8 and the N+ emitter region 9 is the emitter metal 12. The lower surface of the emitter metal 12 is in contact with the P+ emitter region 8 and the N+ emitter region 9. The N-type drift region 4 is in contact with part of the lower surface of the N-type blocking region 6 on the left side of the trench gate oxide layer 10. The right surface of the N+ emitter region 9 is in contact with the trench gate oxide layer 10.

[0041] To the right of the trench gate oxide layer 10, above the P-body 7 are the N+ emitter contact region 15 and the P+ emitter contact region 14. The left surface of the P+ emitter contact region 14 contacts the N+ emitter contact region 15, and the lower surface of the P+ emitter contact region 14 contacts the P-body 7. The right surfaces of both the P+ emitter contact region 14 and the P-body 7 are in contact with the empty metal oxide isolation region 17. Below the P-body 7 and the floating metal oxide isolation region 17 is... The right surface of the N-type blocking region 6 and the floating metal oxide isolation region 17 is in contact with the floating metal 13; the floating P-type region 5 is located below the N-type blocking region 6, the left surface of the floating P-type region 5 is in contact with the N-type drift region 4, the upper surface of the floating P-type region 5 is in contact with the floating metal 13, the lower surface of the emitter metal 12 is in contact with the N+ emitter contact region 15 and the P+ emitter contact region 14, and the left surface of the N+ emitter contact region 15 is in contact with the gate oxide layer 10;

[0042] The trench gate oxide layer 10 is located below the gate oxide isolation region 16, and the outer surface of the trench gate oxide layer 10 is in contact with the floating P-type region 5, the N-type blocking region 6, the P-body 7, the N+ emitter region 9, and the N+ emitter contact region 15; the upper surface of the gate polysilicon 11 is in contact with the gate oxide isolation region 16; the emitter metal 12 is located at the top of the device, and the right surface of the emitter metal 12 is in contact with the floating metal oxide isolation region 17; the gate oxide isolation region 16 is located in the emitter metal 12, and the lower surface of the gate oxide isolation region 16 is in contact with the trench gate oxide layer 10 and the gate polysilicon 11.

[0043] The floating metal 13 forms a Schottky contact diode with the floating P-type region 5 and the N-type blocking region 6, wherein it forms an N-type Schottky diode with the N-type blocking region 6 and a P-type Schottky diode with the floating P-type region 5.

[0044] Preferably, the metal of the floating metal 13 is Al, Pt, Ni, AlSiCu or a metal composite, and its work function is adjusted by using different metals according to actual needs.

[0045] The P-type Schottky diode and the N-type Schottky diode have their anodes shorted together by floating metal 13.

[0046] Preferably, the doping concentration of the floating P-type region 5 is 5 × 10⁻⁶. 16 cm -3 ~1×10 18 cm -3 between.

[0047] Preferably, the doping concentration of the N-type barrier region 6 is 5 × 10⁻⁶. 16 cm -3 ~1×10 18 cm -3 between.

[0048] The working principle of this embodiment is as follows:

[0049] The present invention provides an IGBT device with integrated MOS-controlled floating Schottky diodes, which uses MOS to control two series-connected floating Schottky diodes (P-type Schottky diode and N-type Schottky diode) by embedding them at the emitter terminal.

[0050] When the device is in forward conduction, the potential of the floating P-type region is less than the sum of the turn-on voltages of the two floating Schottky diodes. The Schottky diodes will be in the off state, and holes cannot flow into the gate channel through the two series-connected floating Schottky diodes and then into the emitter. This will further enhance carrier injection and optimize carrier distribution, enhance the conductivity modulation effect of the device, further reduce the on-resistance of the device's drift region, and thus reduce the device's conduction loss.

[0051] When the device is in short-circuit withstand mode, the voltage across the collector and emitter is relatively high. At this time, the potential of the floating P-type region is greater than the sum of the turn-on voltages of the two floating Schottky diodes. The Schottky diodes will be in the turn-on state, and the emitter electrons will flow into the floating metal through the MOS channel and recombine with the holes flowing into the floating metal from the drift region to reduce the hole concentration in the device. This further reduces the conductivity modulation effect of the drift region, thereby reducing the saturation current of the device and improving the short-circuit withstand capability of the device.

[0052] In summary, the IGBT device with integrated MOS-controlled floating Schottky diode proposed in this invention not only improves the device's conduction performance but also enhances its short-circuit withstand capability.

[0053] This embodiment also provides a method for fabricating an IGBT device with an integrated MOS-controlled floating Schottky diode, comprising the following steps:

[0054] 1. A single-crystal silicon substrate is used. First, a floating P-type region 5 is formed by photolithography, P-type ion implantation, and annealing; next, an N-type barrier region 6 is formed by N-type ion implantation and annealing; finally, a P-body 7 is formed by P-type ion implantation and annealing, as shown below. Figure 6 As shown.

[0055] 2. Trench Gate. The gate communication is formed through photolithography and etching; then, a trench gate oxide layer 10 is formed through high-temperature oxidation; next, the gate polysilicon 11 is filled by chemical deposition, followed by chemical mechanical polishing (CMP). Figure 7 As shown.

[0056] 3. The P+ emitter region 8 and P+ emitter contact region 14 are formed by photolithography, P-type ion implantation, and annealing; then, the N+ emitter region 9 and N+ emitter contact region 15 are formed by photolithography, N-type ion implantation, and annealing, as follows. Figure 8 As shown.

[0057] 4. Floating Metal. Floating metal trenches are formed through photolithography and etching, followed by physical deposition of metal to form floating metal 13. Finally, chemical mechanical polishing (CMP) is performed. Figure 9 As shown.

[0058] 5. Oxide isolation layer. An oxide isolation layer is formed by chemical vapor deposition, followed by photolithography and etching to form the gate oxide isolation region 16, such as... Figure 10 As shown.

[0059] 6. Emitter Metal. Emitter metal 12 is formed through physical deposition, followed by annealing to ensure a tighter contact between the metal and the silicon surface, such as... Figure 11 As shown.

[0060] 7. Floating metal oxide isolation region. Trenching is formed by photolithography and silicon etching, followed by silicon dioxide filling and chemical mechanical polishing (CMP) to form the floating metal oxide isolation region 17, as shown below. Figure 12 As shown

[0061] 8. Backside Process. The wafer is thinned to the required thickness using TAIKO or conventional thinning methods. Next, N-type ion implantation and annealing are performed to form an N-type buffer layer 3, followed by P-type ion implantation and annealing to form a P-type collector region 2. Finally, backside metal sputtering is performed to form the collector metal 1, as shown below. Figure 13 As shown.

[0062] The IGBT device proposed in this invention, which integrates a MOS-controlled floating Schottky diode, is also applicable to devices made of semiconductor materials such as silicon carbide, gallium arsenide, indium phosphide, or silicon germanium.

[0063] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An IGBT device integrated with a MOS controlled floating Schottky diode, characterized by: The collector metal (1), P-type collector region (2), N-type buffer layer (3), N-type drift region (4), floating P-type region (5), N-type barrier region (6), P-body (7), P+ emitter region (8), N+ emitter region (9), trench gate oxide layer (10), gate polysilicon (11), emitter metal (12), floating metal (13), P+ emitter contact region (14), N+ emitter contact region (15), gate oxide isolation region (16) and floating metal oxide isolation region (17) are included. The collector metal (1) is located below the P-type collector region (2); the P-type collector region (2) is located between the collector metal (1) and the N-type buffer layer (3); the N-type buffer layer (3) is located below the N-type drift region (4); the N-type drift region (4) is located below the floating P-type region (5), and the N-type barrier region (6) is located below the P-body (7); The bottom of the trench gate oxide layer (10) is located in the floating P-type region (5); the inner surface of the trench gate oxide layer (10) surrounds the gate polysilicon (11) therein, while the trench gate oxide layer (10) penetrates through the entire P-body (7) and N-type barrier region (6), dividing the P-body (7) and N-type barrier region (6) into left and right parts; On the left side of the trench gate oxide layer (10) and above the P-body (7) are the P+ emitter region (8) and N+ emitter region (9), and the right surface of the P+ emitter region (8) is in contact with the N+ emitter region (9); above the P+ emitter region (8) and N+ emitter region (9) is the emitter metal (12), and the lower surface of the emitter metal (12) is in contact with the P+ emitter region (8) and N+ emitter region (9); the N-type drift region (4) is in contact with part of the lower surface of the N-type barrier region (6) on the left side of the trench gate oxide layer (10); the right surface of the N+ emitter region (9) is in contact with the trench gate oxide layer (10); On the right side of the trench gate oxide layer (10) and above the P-body (7) are the N+ emitter contact region (15) and the P+ emitter contact region (14), the left surface of the P+ emitter contact region (14) is in contact with the N+ emitter contact region (15), the lower surface of the P+ emitter contact region (14) is in contact with the P-body (7), and the right surface of the P+ emitter contact region (14) and the right surface of the P-body (7) are both in contact with the floating metal oxide isolation region (17); below the P-body (7) and the floating metal oxide isolation region (17) is the N-type blocking region (6), the right surfaces of the N-type blocking region (6) and the floating metal oxide isolation region (17) are in contact with the floating metal (13); the floating P-type region (5) is located below the N-type blocking region (6), the left surface of the floating P-type region (5) is in contact with the N-type drift region (4), and the upper surface of the floating P-type region (5) is in contact with the floating metal (13), the lower surface of the emitter metal (12) is in contact with the N+ emitter contact region (15) and the P+ emitter contact region (14), and the left surface of the N+ emitter contact region (15) is in contact with the gate oxide layer (10); The trench gate oxide layer (10) is located below the gate oxide isolation region (16), and the outer surface of the trench gate oxide layer (10) is in contact with the floating P-type region (5), the N-type blocking region (6), the P-body (7), the N+ emitter region (9), and the N+ emitter contact region (15); the upper surface of the gate polysilicon (11) is in contact with the gate oxide isolation region (16); the emitter metal (12) is located at the top of the device, and the right surface of the emitter metal (12) is in contact with the floating metal oxide isolation region (17); the gate oxide isolation region (16) is located in the emitter metal (12), and the lower surface of the gate oxide isolation region (16) is in contact with the trench gate oxide layer (10) and the gate polysilicon (11).

2. The IGBT device of claim 1, wherein: The floating metal (13) forms a Schottky contact diode with the floating P-type region (5) and the N-type blocking region (6), wherein an N-type Schottky diode is formed with the N-type blocking region (6), and a P-type Schottky diode is formed with the floating P-type region (5).

3. The IGBT device of claim 1, wherein: the MOS-controlled floating Schottky diode is integrated with the IGBT device. The metal of the floating metal (13) is Al, Pt, Ni, AlSiCu, or a metal composite, and the work function thereof is adjusted using different metals.

4. The IGBT device of claim 2, wherein: the first and second MOS-controlled floating Schottky diodes are formed in the same epitaxial layer. The P-type Schottky diode and the N-type Schottky diode are short-circuited together through the floating metal (13).

5. The IGBT device of claim 1, wherein: the IGBT device is integrated with a MOS-controlled floating Schottky diode. The doping concentration of the floating P-type region (5) is 5 × 10⁻⁶. 16 cm -3 ~1×10 18 cm -3 between.

6. The IGBT device of claim 1, wherein: the IGBT device is integrated with a MOS-controlled floating Schottky diode. The doping concentration of the N-type blocking region (6) is between 5 x 1016cm-3 16 cm -3 -1 x 1018cm-3 18 cm -3 -1 x 1018cm-3 7. A method for the production of a device according to any one of claims 1 to 6, characterized in that The method comprises the following steps: (a) First, the floating P-type region (5) is formed by photolithography and P-type ion implantation and annealing; next, the N-type blocking region (6) is formed using N-type ion implantation and annealing; finally, the P-body (7) is formed using P-type ion implantation and annealing; (b) The gate trench is formed by photolithography and etching; then, the trench gate oxide layer (10) is formed by high-temperature oxidation; next, the gate polysilicon (11) is filled by a chemical deposition method, and chemical mechanical polishing (CMP) is performed after the deposition is completed; (c) Form P+emitter region (8) and P+emitter contact region (14) by photolithography and P-type ion implantation, annealing; then, form N+emitter region (9) and N+emitter contact region (15) by photolithography and N-type ion implantation, annealing; (d) Form floating metal trench by photolithography and etching, then form floating metal (13) by physical deposition, and finally form by chemical mechanical polishing (CMP); (e) Form oxide isolation layer by chemical vapor deposition, then form gate oxide isolation region (16) by photolithography and etching; (f) Form emitter metal (12) by physical deposition, then anneal to make the metal contact with the silicon surface more closely; (g) Form trench by photolithography and etching silicon, then fill with silicon dioxide, and finally form floating metal oxide isolation region (17) by chemical mechanical polishing (CMP); (h) Thin the wafer to the required thickness by TAIKO process or general thinning; then, form N-type buffer layer (3) by N-type ion implantation and annealing, then form P-type collector region (2) by P-type ion implantation and annealing; finally, form collector metal (1) by backside metal sputtering.

Images