PHEMT device epitaxial structure and preparation method thereof

Abstract

The invention discloses a PHEMT device epitaxial structure and a preparation method thereof, and belongs to the technical field of semiconductors, and the PHEMT device epitaxial structure comprises an InP substrate, a GaAs buffer layer, an InGaAs pseudocrystal layer, an n-doped AlGaAs barrier layer and a cap layer which are sequentially laminated. The GaAs buffer layer and the n-doped AlGaAs barrier layer respectively form a first conductive channel and a second conductive channel in the InGaAs pseudocrystal layer, wherein the first conductive channel and the second conductive channel are used for providing 2DEG. The In component content of the InGaAs pseudocrystal layer is such that the sum of the lattice strain force of the InGaAs pseudocrystal layer is less than the lattice mismatch stress of the heterojunction; under the constraint of the In component content of the InGaAs pseudocrystal layer, the thickness of the InGaAs pseudocrystal layer is a target thickness enabling the first conductive channel and the second conductive channel to be overlapped, and the target thickness is used for enhancing the concentration of the 2DEG. And the device quality and performance are improved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to an epitaxial structure of a PHEMT device and a preparation method thereof. Background Art

[0002] The epitaxial structure of a PHEMT (pseudomorphic high electron mobility transistor) is a multi-layer semiconductor heterojunction material system. The epitaxial structure of a PHEMT is the core basis for its high performance. Through the bandgap engineering of the heterojunction and the pseudomorphic growth technology, a two-dimensional electron gas (2DEG) with high mobility is formed at the interface of the epitaxial layer. Electrons are hardly affected by lattice scattering in this region, and the mobility can reach more than 9% of that of ordinary GaAs materials. This structure not only significantly improves the transconductance, operating frequency and noise figure of the device, but also enhances the stability of the threshold voltage and the current handling capacity by optimizing the thickness and uniformity of the doping layer and the isolation layer. This design enables PHEMTs to be widely used in high-frequency and high-sensitivity scenarios such as microwave communication and radar systems, and become the core components of modern radio frequency front-ends.

[0003] However, the existing PHEMT devices are limited by the single heterojunction structure. The InGaAs pseudomorphic layer is prone to dislocation defects due to lattice mismatch, resulting in problems such as low mobility, insufficient 2DEG concentration, and dislocation defects caused by lattice mismatch stress in the 2DEG mobility decay. These drawbacks limit the performance of the devices in high-frequency and high-power applications, especially the large noise and poor stability, which affect the application effects of high-frequency communication and high-performance devices. Summary of the Invention

[0004] In order to solve the technical problems in the prior art that PHEMT devices are limited by the single heterojunction structure, the InGaAs pseudomorphic layer is prone to dislocation defects due to lattice mismatch, resulting in problems such as low mobility, insufficient 2DEG concentration, and dislocation defects caused by lattice mismatch stress in the 2DEG mobility decay. These drawbacks limit the performance of the devices in high-frequency and high-power applications, especially the large noise and poor stability, which affect the application effects of high-frequency communication and high-performance devices, the present invention provides an epitaxial structure of a PHEMT device and a preparation method thereof.

[0005] In a first aspect, the present invention provides an epitaxial structure of a PHEMT device, including: an InP substrate, a GaAs buffer layer, an InGaAs pseudomorphic layer, an n-doped AlGaAs barrier layer, and a cap layer; The InP substrate, the GaAs buffer layer, the InGaAs pseudomorphic layer, the n-doped AlGaAs barrier layer, and the cap layer are sequentially stacked; The GaAs buffer layer and the n-doped AlGaAs barrier layer respectively form a first conductive channel and a second conductive channel for providing 2DEG in the InGaAs pseudomorphic layer; The In composition content of the InGaAs pseudomorphic layer is such that the sum of the lattice strain forces of the InGaAs pseudomorphic layer is less than the lattice mismatch stress of the heterojunction. Among them, the sum of the lattice strain forces includes the first lattice mismatch stress between the GaAs buffer layer and the InGaAs pseudomorphic layer and the second lattice mismatch stress between the InGaAs pseudomorphic layer and the n-doped AlGaAs barrier layer. The heterojunction includes a first heterojunction formed by the GaAs buffer layer and the InGaAs pseudomorphic layer and a second heterojunction formed by the InGaAs pseudomorphic layer and the n-doped AlGaAs barrier layer; Under the constraint of the In composition content of the InGaAs pseudomorphic layer, the thickness of the InGaAs pseudomorphic layer is a target thickness that enables the first conductive channel and the second conductive channel to overlap, where the target thickness is used to enhance the concentration of 2DEG.

[0006] In a second aspect, the present invention provides a method for preparing an epitaxial structure of a PHEMT device, the method comprising: S1: Pretreat the InP substrate; S2: Grow a GaAs buffer layer on the pretreated InP substrate; S3: Grow an InGaAs pseudomorphic layer at a target thickness with the deviation rate of the grown In composition content less than a preset In composition content deviation rate and the deviation rate of the target thickness of the grown InGaAs pseudomorphic layer less than a preset target thickness deviation rate as constraints; S4: Grow an n-doped AlGaAs barrier layer on the InGaAs pseudomorphic layer; S5: Grow a cap layer on the n-doped AlGaAs barrier layer to obtain a primary PHEMT device epitaxial structure; S6: Anneal the primary PHEMT device epitaxial structure in an RTA furnace to obtain a PHEMT device epitaxial structure, where the annealing duration is 30 s and the annealing temperature range is 600 °C to 800 °C.

[0007] Compared with the prior art, the present invention has at least the following beneficial technical effects: In the embodiments of the present invention, through the collaborative optimization of double heterojunction design and strain engineering, the device performance is significantly improved. Precise control of the thickness of the InGaAs pseudomorphic layer promotes the overlap of double conductive channels. The upper and lower heterojunctions (GaAs / InGaAs and InGaAs / AlGaAs) form superimposed two-dimensional electron gas (2DEG) channels in the InGaAs pseudomorphic layer. By adjusting the In composition, the lattice strain force and the mismatch stress reach a dynamic balance, which not only maintains the structural stability of the pseudomorphic layer, but also effectively improves the 2DEG concentration through the quantum confinement effect and enhances the carrier transport efficiency. Breaking through the mobility bottleneck of the traditional single heterojunction, it also realizes the working ability in the ultra-high frequency (millimeter wave band) through the 2DEG with high concentration and low scattering, reduces the noise coefficient, and is particularly suitable for scenarios with strict requirements for high frequency and low power consumption such as 5G communication and satellite payloads. At the same time, the strain tolerance design of the epitaxial structure greatly reduces the dislocation defect rate, ensuring the reliability and quality controllability of the device. Description of the Drawings

[0008] The following will further illustrate the above-mentioned characteristics, technical features, advantages and their implementation manners of the present invention in a clear and understandable manner in combination with the drawings of the preferred embodiments.

[0009] Figure 1 is a schematic structural diagram of an epitaxial structure of a PHEMT device provided by the present invention; Figure 2 is a schematic flow diagram of a preparation method of an epitaxial structure of a PHEMT device provided by the present invention. Detailed Embodiments

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific embodiments of the present invention will be described below with reference to the drawings. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings, and other embodiments can also be obtained.

[0011] Embodiment 1 In one embodiment, referring to the attached drawings of the specification Figure 1 , a schematic structural diagram of an epitaxial structure of a PHEMT device provided by the present invention is shown.

[0012] Figure 1The epitaxial structure of the PHEMT device is shown. In this structure, from top to bottom, there are a cap layer, an n-doped AlGaAs barrier layer, an InGaAs pseudomorphic layer, a GaAs buffer layer, and an InP substrate. Among them, the InGaAs pseudomorphic layer and the GaAs buffer layer, as well as the InGaAs pseudomorphic layer and the n-doped AlGaAs barrier layer, respectively form two heterojunctions. Through the polarization effect of these heterojunctions, a two-dimensional electron gas (2DEG) channel is formed in the InGaAs pseudomorphic layer, effectively improving the electron mobility. The GaAs buffer layer plays a role in alleviating lattice mismatch and ensuring the stability of the structure, while the n-doped AlGaAs barrier layer provides additional electron confinement and optimizes the carrier transport performance. The overall structure design improves the performance of the device, especially its performance in high-frequency applications.

[0013] An epitaxial structure of a PHEMT device provided by the present invention includes: an InP substrate, a GaAs buffer layer, an InGaAs pseudomorphic layer, an n-doped AlGaAs barrier layer, and a cap layer. The InP substrate, the GaAs buffer layer, the InGaAs pseudomorphic layer, the n-doped AlGaAs barrier layer, and the cap layer are sequentially stacked. The GaAs buffer layer and the n-doped AlGaAs barrier layer respectively form a first conductive channel and a second conductive channel for providing 2DEG in the InGaAs pseudomorphic layer. The In composition content of the InGaAs pseudomorphic layer is such that the sum of the lattice strain forces of the InGaAs pseudomorphic layer is less than the lattice mismatch stress of the heterojunction, where the sum of the lattice strain forces includes the first lattice mismatch stress between the GaAs buffer layer and the InGaAs pseudomorphic layer and the second lattice mismatch stress between the InGaAs pseudomorphic layer and the n-doped AlGaAs barrier layer, and the heterojunction includes a first heterojunction formed by the GaAs buffer layer and the InGaAs pseudomorphic layer and a second heterojunction formed by the InGaAs pseudomorphic layer and the n-doped AlGaAs barrier layer. Under the constraint of the In composition content of the InGaAs pseudomorphic layer, the thickness of the InGaAs pseudomorphic layer is a target thickness such that the first conductive channel and the second conductive channel overlap, where the target thickness is used to enhance the concentration of 2DEG.

[0014] Among them, the InP substrate serves as the base material of the entire structure, providing stable support and good thermal conductivity. Its selection is mainly because InP has a small lattice mismatch with the InGaAs pseudomorphic layer, thereby reducing lattice stress and improving crystal quality. The GaAs buffer layer plays a role in alleviating the lattice mismatch between the substrate and the subsequent materials. It effectively reduces the dislocation defects caused by different lattice constants, enabling the InGaAs pseudomorphic layer to grow better. The InGaAs pseudomorphic layer is the main two-dimensional electron gas (2DEG) formation layer, with high mobility, which helps to enhance the electrical conductivity of the device. At the heterojunction interface, due to the polarization effect, a high-density 2DEG channel will be formed in the InGaAs layer. The n-doped AlGaAs barrier layer plays a role in providing electron confinement and helps to form a second 2DEG channel. It improves the movement and control of electrons by providing an additional barrier and electric field, further enhancing the formation of 2DEG. The cap layer is usually used to protect the InGaAs layer, reduce surface defects and improve the electron transport efficiency. Especially in high-frequency applications, it helps to improve the stability and reliability of the device.

[0015] It should be noted that by using the GaAs buffer layer and the n-doped AlGaAs barrier layer, two overlapping two-dimensional electron gas (2DEG) channels are formed in the InGaAs pseudomorphic layer, thereby increasing the electron concentration and mobility. In particular, by precisely controlling the In composition and thickness of the InGaAs pseudomorphic layer, the lattice stress can be effectively balanced, defects can be reduced, and crystal quality can be improved. This design of dual conductive channels not only breaks through the mobility bottleneck of traditional single heterojunction PHEMTs, but also significantly improves the performance of the device in high-frequency applications. Further structural optimization also enhances the stability and reliability of the device.

[0016] Compared with the prior art, the present invention has at least the following beneficial technical effects: In the embodiment of the present invention, through the collaborative optimization of the double heterojunction design and strain engineering, the device performance is significantly improved. Precise control of the thickness of the InGaAs pseudomorphic layer promotes the overlap of the dual conductive channels. The upper and lower heterojunctions (GaAs / InGaAs and InGaAs / AlGaAs) form superimposed two-dimensional electron gas (2DEG) channels in the InGaAs pseudomorphic layer. By adjusting the In composition, the lattice strain force and mismatch stress reach a dynamic balance, which not only maintains the structural stability of the pseudomorphic layer, but also effectively increases the 2DEG concentration through the quantum confinement effect and enhances the carrier transport efficiency. Breaking through the mobility bottleneck of traditional single heterojunctions, it also realizes the ultra-high frequency (millimeter wave band) working ability through the 2DEG with high concentration and low scattering, reduces the noise coefficient, and is particularly suitable for scenarios with strict requirements for high frequency and low power consumption such as 5G communication and satellite payloads. At the same time, the strain tolerance design of the epitaxial structure significantly reduces the dislocation defect rate, ensuring the reliability and quality controllability of the device.

[0017] In one possible implementation, the calculation formula for the In component content is specifically as follows: ; wherein, represents the lattice mismatch strain between the GaAs buffer layer and the InGaAs pseudomorphic layer, the lattice mismatch strain between the InGaAs pseudomorphic layer and the n-doped AlGaAs barrier layer, represents the lattice constant of n-doped AlGaAs, represents the lattice constant of the InGaAs pseudomorphic layer at the In component content x, and respectively represent the lattice constant of InAs and the lattice constant of GaAs, represents taking the absolute value, represents taking the x value when takes the minimum value.

[0018] In the InGaAs / GaAs heterojunction, when the lattice mismatch degree is 1.62%, the alignment angle deviation (0.90°) between the epitaxial layer and the substrate is observed through the ion channel effect, and at this time, the material still maintains a high crystal quality. However, if the mismatch degree further increases (such as >2%), the elastic strain cannot completely compensate for the mismatch stress, resulting in a sharp increase in the dislocation density. For the InGaAs / AlGaAs system, when the total strain sum value (compressive strain + tensile strain) exceeds 2%, the dislocation density may exceed 10 5 cm⁻², significantly reducing the electron mobility and device reliability.

[0019] It should be noted that by determining the In component content to minimize the sum of the absolute values of the lattice mismatch strains at the two interfaces and strictly controlling the total strain below 1.62%, not only the elastic strain compensation mechanism is used to maintain the stability of the pseudomorphic layer (dislocation density <10³ cm⁻²), but also the mobility of the two-dimensional electron gas (2DEG) is increased to above 8,000 cm² / V·s through the dynamic balance of the strains at the two interfaces, while avoiding a sharp increase in the dislocation density caused by a high In component (>10 5 cm⁻²), ensuring the synchronous optimization of the crystal quality of the material and the device performance.

[0020] In one possible implementation, the calculation formula for the target thickness is specifically as follows: ; wherein, represents the target thickness, min represents taking the minimum value, represents the reduced Planck constant, represents the effective electron mass in InGaAs related to the In component content x, represents the rest mass of a free electron, and respectively represent represents the effective barrier height related to x, represents the ground state energy level of the InGaAs pseudomorphic layer related to x, represents the conduction band offset of AlGaAs / InGaAs related to x, represents the conduction band offset of GaAs / InGaAs related to x, represents the maximum thickness of the InGaAs pseudomorphic layer without dislocation defects at x, b represents the Burgers vector, represents the Poisson's ratio, π represents the pi, represents the effective total strain related to x, ln represents the natural logarithm function.

[0021] Specifically, the specific calculation formula for the ground state energy level of the InGaAs pseudomorphic layer related to x is: , where d represents the thickness of the quantum well formed by the GaAs buffer layer, the InGaAs pseudomorphic layer, and the n-doped AlGaAs barrier layer. . Among them, is a self-consistent equation, that is, both sides of the equation contain , and it can be solved by the iterative method.

[0022] It should be noted that through multi-physics field coupling modeling (quantum confinement effect and strain mechanical equilibrium), the target thickness is determined in a mathematical optimization manner, which has the following core advantages: First, based on the Schrödinger equation, the electron effective mass and ground state energy level parameters are introduced to accurately quantify the influence of the quantum well on the 2DEG mobility. Second, the electron tunneling probability is calculated by combining the conduction band offset and the effective barrier height to ensure the optimal degree of wave function localization (transmission coefficient < 10⁻³). At the same time, the dislocation defect generation conditions are restricted by the critical thickness model, and the min function is used to dynamically balance the quantum characteristics and structural stability. Finally, the target thickness is controlled within a reasonable range to increase the 2DEG concentration, thereby improving the performance and reliability of the PHEMT device.

[0023] In the actual application process, through the double heterojunction design and precise control of the In composition content, the 2DEG concentration can be effectively increased and the mobility can be optimized. By precisely regulating the thickness of the InGaAs pseudomorphic layer, the lattice mismatch stress is ensured to be balanced, and dislocation defects are reduced, thereby maintaining a high-quality crystal structure. This structure not only breaks through the mobility bottleneck of traditional PHEMTs but also improves the stability and performance of the device in high-frequency applications by optimizing the electron characteristics and quantum confinement effect.

[0024] Example 2 In one embodiment, referring to the attached drawings of the specification Figure 2, showing a schematic flow chart of a method for preparing an epitaxial structure of a PHEMT device provided by the present invention.

[0025] A method for preparing an epitaxial structure of a PHEMT device provided by the present invention, the method comprising: S1: Pretreat the InP substrate.

[0026] In a possible implementation manner, S1 specifically includes: S101: Chemically clean the InP substrate using a chemical cleaning agent, where the chemical cleaning agent includes deionized water, hydrofluoric acid solution, acetone, and isopropyl acetone.

[0027] S102: Grind the cleaned InP substrate through alumina grinding technology.

[0028] It should be noted that through chemical cleaning and grinding, the possible organic substances, oxides, and other impurities on the surface of the InP substrate are effectively removed, ensuring a clean and flat surface. Chemical cleaning helps to remove contaminants that are difficult to clean, and the alumina grinding technology provides a uniform and smooth surface, increasing the adhesion between the substrate and the subsequent growth layer, and improving the quality and stability of the epitaxial layer.

[0029] S2: Grow a GaAs buffer layer on the pretreated InP substrate.

[0030] In a possible implementation manner, S2 is specifically: Grow a GaAs buffer layer on the InP substrate by metalorganic chemical vapor deposition, and the growth temperature range is 550°C to 650°C.

[0031] It should be noted that by growing the GaAs buffer layer by metalorganic chemical vapor deposition (MOCVD) method, a high-quality thin film can be deposited on the InP substrate. This method grows within the temperature range of 550°C to 650°C, which can effectively control the thickness and crystal quality of the buffer layer, reduce the lattice mismatch between the substrate and the subsequent growth layer, thereby improving the quality of the epitaxial layer, reducing dislocation defects, and providing a good foundation for the growth of subsequent materials.

[0032] S3: Grow an InGaAs pseudomorphic layer according to a target thickness with the constraint that the deviation rate of the grown In component content is less than a preset In component content deviation rate and the deviation rate of the target thickness of the grown InGaAs pseudomorphic layer is less than a preset target thickness deviation rate.

[0033] It should be noted that those skilled in the art can set the magnitudes of the preset In component content deviation rate and the preset target thickness deviation rate according to actual needs, and the present invention does not make any limitations here.

[0034] Optionally, the deviation rate of the In component content can be set to 0.005, and the preset target thickness deviation rate can be set to 0.3 nm.

[0035] In one possible implementation, S3 is specifically: With the constraint that the deviation rate of the grown In component content is less than the preset In component content deviation rate, an In source and a Ga source are introduced, and an InGaAs pseudomorphic layer is grown to the target thickness by metalorganic chemical vapor deposition. Here, the In source and the Ga source are trimethylindium and trimethylgallium, respectively.

[0036] It should be noted that by precisely controlling the In component content and the thickness deviation rate of the pseudomorphic layer, the high-quality growth of the InGaAs pseudomorphic layer can be ensured. By setting the deviation rate limit, the lattice strain and thickness of the InGaAs layer are ensured to be within the preset range, thereby reducing lattice mismatch and dislocation defects. The growth by metalorganic chemical vapor deposition (MOCVD) not only improves the uniformity of the layer but also effectively optimizes the crystal structure by precisely controlling the flow rates of the In source and the Ga source, further enhancing the performance of the device, especially the stability in high-frequency and high-power applications.

[0037] In one possible implementation, the introduction rates of the In source and the Ga source are determined with the constraint that the relative flow rate volatility between the metal source and the arsenic source is less than the preset relative flow rate volatility. Here, the metal source includes the In source and the Ga source. The specific calculation formula for the introduction rate is: ; where and respectively represent the introduction rate of trimethylindium and the introduction rate of trimethylgallium, x represents the In component content, and respectively represent the In atom incorporation efficiency and the Ga atom incorporation efficiency related to the growth environment, represents the preset growth rate of the InGaAs pseudomorphic layer, , and respectively represent the deviation rate of the In component content, the target thickness deviation rate, and the relative flow rate volatility, and t represents the expected growth duration of the InGaAs pseudomorphic layer.

[0038] It should be noted that those skilled in the art can set the magnitudes of the preset flow rate volatility and the preset growth rate according to actual needs, and the present invention does not limit this here. Optionally, the preset flow rate volatility can be set to one percent.

[0039] It should be noted that by calculating the input rate based on the relative flow rate volatility of the In source and the Ga source, and imposing constraints on the In component content, thickness deviation rate, and flow rate volatility, the growth rate of the InGaAs pseudomorphic layer can be precisely controlled. This calculation method ensures the optimization of the incorporation efficiency of In and Ga during the growth process, thereby obtaining a uniform and high-quality thin film, reducing defects caused by growth rate fluctuations, and improving the stability and performance of the device. In addition, it is allowed to adjust the flow rate volatility and growth rate according to actual requirements, providing flexibility for different production needs and contributing to achieving higher-quality crystal growth under more refined process control.

[0040] S4: Grow an n-doped AlGaAs barrier layer on the InGaAs pseudomorphic layer.

[0041] In a possible implementation, the doping source of the n-doped AlGaAs barrier layer is SiH 4 silicon source. S4 is specifically as follows: Grow an n-doped AlGaAs barrier layer on the InGaAs pseudomorphic layer by metalorganic chemical vapor deposition, and the growth temperature range is 600°C to 700°C.

[0042] It should be noted that using metalorganic chemical vapor deposition (MOCVD) to grow an n-doped AlGaAs barrier layer on the InGaAs pseudomorphic layer can precisely control the doping concentration and the thickness of the layer. By selecting SiH4 as the silicon source, n-type doping can be effectively introduced, enhancing the electron confinement effect of the AlGaAs layer and providing support for the formation of two-dimensional electron gas (2DEG). Controlling the growth temperature within the range of 600°C to 700°C helps to improve the crystallization quality of the layer, reduce dislocation defects, ensure the uniformity and stability of the AlGaAs barrier layer, and further optimize the device performance, especially in high-frequency and high-power applications.

[0043] S5: Grow a cap layer on the n-doped AlGaAs barrier layer to obtain the epitaxial structure of the primary PHEMT device.

[0044] In a possible implementation, the cap layer is an AlGaAs cap layer. S5 is specifically as follows: Grow an AlGaAs cap layer on the n-doped AlGaAs barrier layer by metalorganic chemical vapor deposition to obtain the epitaxial structure of the primary PHEMT device, with the growth temperature range being 600°C to 700°C and the growth pressure range being 50 Pa - 200 Pa.

[0045] It should be noted that by growing an AlGaAs cap layer on the n-doped AlGaAs barrier layer through metalorganic chemical vapor deposition (MOCVD), the overall quality and stability of the device can be effectively improved. The main function of the cap layer is to protect the underlying InGaAs pseudomorphic layer, reduce surface defects, and ensure the uniformity and crystal quality of the AlGaAs cap layer by optimizing the growth temperature (600 °C to 700 °C) and growth pressure (50 Pa - 200 Pa). This can enhance the formation effect of the two-dimensional electron gas (2DEG), reduce scattering, increase the electron mobility, and thus enhance the performance of the PHEMT device in high-frequency and high-power applications.

[0046] S6: Anneal the epitaxial structure of the primary PHEMT device in an RTA furnace to obtain the epitaxial structure of the PHEMT device. The annealing duration is 30 s, and the annealing temperature range is 600 °C to 800 °C.

[0047] In the actual application process, by precisely controlling the deviation rate and thickness of each growth stage, the high quality and uniformity of each layer are ensured. Especially during the growth process of the InGaAs pseudomorphic layer, by strictly controlling the In composition content and thickness deviation rate, lattice mismatch and dislocation defects can be reduced, and the concentration and mobility of the 2DEG can be increased. Annealing treatment using an RTA furnace further optimizes the crystal quality of the epitaxial layer, reduces residual stress and defects. The entire preparation process ensures the stability of the epitaxial structure and the efficient optimization of device performance, meeting the requirements of high-frequency low-noise and high-power applications, and having significant advantages especially in 5G communication and high-frequency electronic devices.

[0048] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0049] The above embodiments only represent several implementation manners of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention.

Claims

1. A PHEMT device epitaxial structure, characterized in that: include: InP substrate, GaAs buffer layer, InGaAs pseudocrystalline layer, n-doped AlGaAs barrier layer and cap layer; The InP substrate, the GaAs buffer layer, the InGaAs pseudocrystalline layer, the n-doped AlGaAs barrier layer and the cap layer are stacked in sequence; The GaAs buffer layer and the n-doped AlGaAs barrier layer respectively form a first conductive channel and a second conductive channel in the InGaAs pseudocrystalline layer for providing 2DEG; The In component content of the InGaAs pseudocrystal layer is such that the lattice strain and value of the InGaAs pseudocrystal layer are less than the lattice mismatch stress of the heterojunction, wherein the lattice strain and value include a first lattice mismatch stress between the GaAs buffer layer and the InGaAs pseudocrystal layer and a second lattice mismatch stress between the InGaAs pseudocrystal layer and the n-doped AlGaAs barrier layer, and the heterojunction includes a first heterojunction formed by the GaAs buffer layer and the InGaAs pseudocrystal layer and a second heterojunction formed by the InGaAs pseudocrystal layer and the n-doped AlGaAs barrier layer; Under the constraint of the In component content of the InGaAs pseudocrystalline layer, the thickness of the InGaAs pseudocrystalline layer is a target thickness that enables the first conductive channel and the second conductive channel to overlap, wherein the target thickness is used to enhance the concentration of the 2DEG.

2. The epitaxial structure of the PHEMT device according to claim 1, characterized in that: The calculation formula of the In component content is specifically: ； in, represents the lattice mismatch strain between the GaAs buffer layer and the InGaAs pseudocrystalline layer, The lattice mismatch strain between the InGaAs pseudocrystalline layer and the n-doped AlGaAs barrier layer, represents the lattice constant of n-doped AlGaAs, represents the lattice constant of the InGaAs pseudocrystalline layer at In component content x, and denote the InAs lattice constant and the GaAs lattice constant, respectively. Indicates taking the absolute value, Indicates the use Take the x value under the minimum value.

3. The epitaxial structure of the PHEMT device according to claim 2, characterized in that: The calculation formula of the target thickness is specifically: ； in, Indicates the target thickness, min indicates the minimum value, represents the reduced Planck constant, represents the effective mass of electrons in InGaAs related to the In component content x, is the rest mass of a free electron, and Respectively, represents the effective barrier height related to x, represents the ground state energy level of the InGaAs pseudocrystalline layer related to x, represents the AlGaAs / InGaAs conduction band offset related to x, represents the GaAs / InGaAs conduction band offset related to x, represents the maximum thickness of the InGaAs pseudocrystalline layer without dislocation defects under x, b represents the Burgers vector, represents Poisson's ratio, π represents pi, represents the effective total strain related to x, and ln represents the natural logarithmic function.

4. A method for preparing an epitaxial structure of a PHEMT device according to any one of claims 1 to 3, characterized in that: Methods include: S1: pre-treating the InP substrate; S2: growing the GaAs buffer layer on the pretreated InP substrate; S3: Growing the InGaAs pseudocrystalline layer according to the target thickness, with the In component content deviation rate being less than a preset In component content deviation rate and the target thickness deviation rate of the InGaAs pseudocrystalline layer being less than a preset target thickness deviation rate as constraints; S4: growing the n-doped AlGaAs barrier layer on the InGaAs pseudocrystalline layer; S5: growing the cap layer on the n-doped AlGaAs barrier layer to obtain a primary PHEMT device epitaxial structure; S6: annealing the primary PHEMT device epitaxial structure in an RTA furnace to obtain the PHEMT device epitaxial structure, the annealing time is 30 seconds, and the annealing temperature ranges from 600° C. to 800° C.

5. The method for preparing the epitaxial structure of a PHEMT device according to claim 4, characterized in that: The S1 specifically includes: S101: chemically cleaning the InP substrate using a chemical cleaning agent, wherein the chemical cleaning agent includes deionized water, hydrofluoric acid solution, acetone and isopropyl ketone; S102: Grinding the cleaned InP substrate by using an alumina grinding technique.

6. The method for preparing the epitaxial structure of a PHEMT device according to claim 4, characterized in that: The S2 is specifically: The GaAs buffer layer is grown on the InP substrate by metal organic chemical vapor deposition, and the growth temperature ranges from 550° C. to 650° C.

7. The method for preparing the epitaxial structure of a PHEMT device according to claim 4, characterized in that: The S3 is specifically: With the grown In component content deviation rate being constrained to be less than a preset In component content deviation rate, an In source and a Ga source are introduced, and the InGaAs pseudocrystalline layer is grown according to the target thickness by metal organic chemical vapor deposition, wherein the In source and the Ga source are trimethyl indium and trimethyl gallium, respectively.

8. The method for preparing the epitaxial structure of a PHEMT device according to claim 7, characterized in that: The feed rate of the In source and the Ga source is determined by constraining that the relative flow rate fluctuation rate between the metal source and the arsenic source is less than a preset relative flow rate fluctuation rate, wherein the metal source includes an In source and a Ga source; the calculation formula of the feed rate is specifically: ； in, and They represent the trimethylindium and trimethylgallium incorporation rates, respectively, and x represents the In component content. and They represent the In atom incorporation efficiency and Ga atom incorporation efficiency related to the growth environment, represents the preset growth rate of the InGaAs pseudocrystalline layer, , and They represent the In component content deviation rate, target thickness deviation rate and relative flow rate fluctuation rate respectively, and t represents the expected growth time of the InGaAs pseudocrystalline layer.

9. The method for preparing the epitaxial structure of a PHEMT device according to claim 4, characterized in that: The doping source of the n-doped AlGaAs barrier layer is a SiH4 silicon source; the S4 is specifically: The n-doped AlGaAs barrier layer is grown on the InGaAs pseudocrystalline layer by metal organic chemical vapor deposition, and the growth temperature ranges from 600° C. to 700° C.

10. The method for preparing the epitaxial structure of a PHEMT device according to claim 4, characterized in that: The cap layer is an AlGaAs cap layer; and S5 is specifically: The AlGaAs cap layer is grown on the n-doped AlGaAs barrier layer by metal organic chemical vapor deposition to obtain a primary PHEMT device epitaxial structure, the growth temperature range is 600° C. to 700° C., and the growth pressure range is 50Pa-200Pa.

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