A PHEMT device epitaxial structure and preparation method thereof

Abstract

The present invention discloses a PHEMT device epitaxial structure and a preparation method thereof, belonging to the field of semiconductor technology. The structure comprises: an InP substrate, a GaAs buffer layer, an InGaAs pseudomorphic layer, an n-doped AlGaAs barrier layer, and a cap layer, which are sequentially stacked. The GaAs buffer layer and the n-doped AlGaAs barrier layer respectively form a first conductive channel and a second conductive channel in the InGaAs pseudomorphic layer for providing a 2DEG. The In component content of the InGaAs pseudomorphic layer is such that the sum of the lattice strain of the InGaAs pseudomorphic layer is less than the lattice mismatch stress of the heterojunction. Under the constraint of the In component content of the InGaAs pseudomorphic layer, the thickness of the InGaAs pseudomorphic layer is a target thickness such that the first conductive channel and the second conductive channel overlap, wherein the target thickness is used to enhance the concentration of the 2DEG, thereby improving device quality and performance.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a PHEMT device epitaxial structure and a preparation method thereof. Background Art

[0002] The epitaxial structure of a PHEMT (pseudomorphic high electron mobility transistor) is a multilayer semiconductor heterojunction material system. This structure is the core foundation of the PHEMT's high performance. Through heterojunction bandgap engineering and pseudocrystal growth techniques, a high-mobility two-dimensional electron gas (2DEG) forms at the epitaxial layer interface. Electrons in this region are virtually unaffected by lattice scattering, achieving a mobility exceeding 9% of that of conventional GaAs. This structure not only significantly improves the device's transconductance, operating frequency, and noise figure, but also enhances threshold voltage stability and current handling capability by optimizing the thickness and uniformity of the doped and isolation layers. This design has enabled PHEMTs to be widely used in high-frequency, high-sensitivity applications such as microwave communications and radar systems, making them a core component of modern RF front-ends.

[0003] However, existing PHEMT devices are limited by their single heterojunction structure. Their InGaAs pseudocrystalline layer is prone to dislocation defects due to lattice mismatch, leading to 2DEG mobility degradation and problems such as low mobility, insufficient 2DEG concentration, and dislocation defects caused by lattice mismatch stress. These shortcomings limit the device's performance in high-frequency, high-power applications, particularly resulting in high noise and poor stability, which hinder its application in high-frequency communications and high-performance equipment. Summary of the Invention

[0004] To address the limitations of existing PHEMT devices due to their single heterojunction structure, where lattice mismatch in the InGaAs pseudocrystalline layer easily generates dislocation defects, leading to 2DEG mobility degradation, low mobility, insufficient 2DEG concentration, and dislocation defects caused by lattice mismatch stress. These shortcomings limit the device's performance in high-frequency, high-power applications, particularly resulting in high noise and poor stability, which affect the application effectiveness of high-frequency communications and high-performance equipment. The present invention provides a PHEMT device epitaxial structure and a method for preparing it.

[0005] In a first aspect, the present invention provides a PHEMT device epitaxial structure, comprising: an InP substrate, a GaAs buffer layer, an InGaAs pseudocrystalline layer, an n-doped AlGaAs barrier layer and a cap layer;

[0006] An InP substrate, a GaAs buffer layer, an InGaAs pseudocrystalline layer, an n-doped AlGaAs barrier layer and a cap layer are stacked in sequence;

[0007] The GaAs buffer layer and the n-doped AlGaAs barrier layer respectively form a first conductive channel and a second conductive channel in the InGaAs pseudocrystalline layer for providing a 2DEG;

[0008] The In component content of the InGaAs pseudocrystal layer is such that the sum of the lattice strain of the InGaAs pseudocrystal layer is less than the lattice mismatch stress of the heterojunction, wherein the sum of the lattice strain includes a first lattice mismatch stress between the GaAs buffer layer and the InGaAs pseudocrystal layer and a second lattice mismatch stress between the InGaAs pseudocrystal layer and the n-doped AlGaAs barrier layer, and the heterojunction includes a first heterojunction formed by the GaAs buffer layer and the InGaAs pseudocrystal layer and a second heterojunction formed by the InGaAs pseudocrystal layer and the n-doped AlGaAs barrier layer;

[0009] Under the constraint of the In component content of the InGaAs pseudocrystalline layer, the thickness of the InGaAs pseudocrystalline layer is a target thickness that enables the first conductive channel and the second conductive channel to overlap, wherein the target thickness is used to enhance the concentration of 2DEG.

[0010] In a second aspect, the present invention provides a method for preparing an epitaxial structure of a PHEMT device, the method comprising:

[0011] S1: pre-treating the InP substrate;

[0012] S2: growing a GaAs buffer layer on the pretreated InP substrate;

[0013] S3: Growing an InGaAs pseudocrystalline layer to a target thickness, with the In component content deviation rate being less than a preset In component content deviation rate and the target thickness deviation rate of the grown InGaAs pseudocrystalline layer being less than a preset target thickness deviation rate as constraints;

[0014] S4: growing an n-doped AlGaAs barrier layer on the InGaAs pseudocrystalline layer;

[0015] S5: growing a cap layer on the n-doped AlGaAs barrier layer to obtain a primary PHEMT device epitaxial structure;

[0016] S6: annealing the primary PHEMT device epitaxial structure in an RTA furnace to obtain a PHEMT device epitaxial structure. The annealing time is 30 seconds, and the annealing temperature ranges from 600° C. to 800° C.

[0017] Compared with the prior art, the present invention has at least the following beneficial technical effects:

[0018] In the embodiments of the present invention, device performance is significantly improved through the coordinated optimization of double heterojunction design and strain engineering. Precise control of the thickness of the InGaAs pseudocrystal layer enables the overlap of dual conductive channels. The upper and lower heterojunctions (GaAs / InGaAs and InGaAs / AlGaAs) form superimposed two-dimensional electron gas (2DEG) channels within the InGaAs pseudocrystal layer. By adjusting the In composition, the lattice strain and mismatch stress are dynamically balanced, maintaining the structural stability of the pseudocrystal layer while effectively increasing the 2DEG concentration through quantum confinement, enhancing carrier transport efficiency. This overcomes the mobility bottleneck of traditional single heterojunctions and achieves ultra-high frequency (millimeter wave) operation through the high-concentration, low-scattering 2DEG, reducing the noise figure. This device is particularly suitable for applications with stringent high-frequency and low-power requirements, such as 5G communications and satellite payloads. Furthermore, the strain tolerance design of the epitaxial structure significantly reduces the dislocation defect rate, ensuring device reliability and quality controllability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The preferred embodiments will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present invention.

[0020] Figure 1 This is a schematic structural diagram of an epitaxial structure of a PHEMT device provided by the present invention;

[0021] Figure 2 It is a flow chart of a method for preparing an epitaxial structure of a PHEMT device provided by the present invention. DETAILED DESCRIPTION

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific embodiments of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings and other embodiments can be obtained based on these drawings without inventive work.

[0023] Example 1

[0024] In one embodiment, the reference Figure 1 , showing a structural schematic diagram of a PHEMT device epitaxial structure provided by the present invention.

[0025] Figure 1The epitaxial structure of the PHEMT device is shown in the figure. In this structure, arranged from top to bottom are the cap layer, n-doped AlGaAs barrier layer, InGaAs pseudomorphic layer, GaAs buffer layer and InP substrate. Among them, the InGaAs pseudomorphic layer and the GaAs buffer layer, and the InGaAs pseudomorphic layer and the n-doped AlGaAs barrier layer form two heterojunctions respectively. Through the polarization effect of these heterojunctions, a two-dimensional electron gas (2DEG) channel is formed in the InGaAs pseudomorphic layer, which effectively improves the mobility of electrons. The GaAs buffer layer plays a role in alleviating the lattice mismatch and ensuring the stability of the structure, while the n-doped AlGaAs barrier layer provides additional electron confinement and optimizes the carrier transport performance. The overall structural design improves the performance of the device, especially in high-frequency applications.

[0026] The present invention provides a PHEMT device epitaxial structure comprising an InP substrate, a GaAs buffer layer, an InGaAs pseudomorphic layer, an n-doped AlGaAs barrier layer, and a cap layer. The InP substrate, GaAs buffer layer, InGaAs pseudomorphic layer, n-doped AlGaAs barrier layer, and cap layer are stacked in sequence. The GaAs buffer layer and the n-doped AlGaAs barrier layer form a first conductive channel and a second conductive channel, respectively, in the InGaAs pseudomorphic layer to provide a 2DEG. The In content of the InGaAs pseudolayer is such that the sum of the lattice strain of the InGaAs pseudolayer is less than the lattice mismatch stress of the heterojunction. The sum of the lattice strain comprises a first lattice mismatch stress between the GaAs buffer layer and the InGaAs pseudolayer, and a second lattice mismatch stress between the InGaAs pseudolayer and the n-doped AlGaAs barrier layer. The heterojunction comprises a first heterojunction formed by the GaAs buffer layer and the InGaAs pseudolayer, and a second heterojunction formed by the InGaAs pseudolayer and the n-doped AlGaAs barrier layer. Under the constraints of the In content of the InGaAs pseudolayer, the thickness of the InGaAs pseudolayer is a target thickness that allows the first conductive channel and the second conductive channel to overlap, wherein the target thickness is used to enhance the concentration of the 2DEG.

[0027] The InP substrate, the foundational material for the entire structure, provides stable support and excellent thermal conductivity. It was chosen primarily because InP has a minimal lattice mismatch with the InGaAs pseudocrystal layer, reducing lattice stress and improving crystal quality. The GaAs buffer layer mitigates the lattice mismatch between the substrate and subsequent materials. It effectively reduces dislocation defects caused by the lattice constant difference, enabling better growth of the InGaAs pseudocrystal layer. The InGaAs pseudocrystal layer is the primary two-dimensional electron gas (2DEG) formation layer, boasting high mobility and contributing to enhanced device conductivity. At the heterojunction interface, polarization effects form a high-density 2DEG channel in the InGaAs layer. The n-doped AlGaAs barrier layer provides electron confinement and helps form a second 2DEG channel. By providing an additional barrier and electric field, it improves electron movement and control, further enhancing 2DEG formation. A cap layer typically protects the InGaAs layer, reduces surface defects, and improves electron transmission efficiency, particularly in high-frequency applications, contributing to improved device stability and reliability.

[0028] It should be noted that by using a GaAs buffer layer and an n-doped AlGaAs barrier layer, two overlapping two-dimensional electron gas (2DEG) channels are formed in the InGaAs pseudocrystalline layer, thereby increasing electron concentration and mobility. Specifically, by precisely controlling the In composition and thickness of the InGaAs pseudocrystalline layer, lattice stress can be effectively balanced, defects can be reduced, and crystal quality can be improved. This dual-conducting channel design not only overcomes the mobility bottleneck of traditional single-heterojunction PHEMTs but also significantly improves the device's performance in high-frequency applications. Further structural optimization also enhances the device's stability and reliability.

[0029] Compared with the prior art, the present invention has at least the following beneficial technical effects:

[0030] In the embodiments of the present invention, device performance is significantly improved through the coordinated optimization of double heterojunction design and strain engineering. Precise control of the thickness of the InGaAs pseudocrystal layer enables the overlap of dual conductive channels. The upper and lower heterojunctions (GaAs / InGaAs and InGaAs / AlGaAs) form superimposed two-dimensional electron gas (2DEG) channels within the InGaAs pseudocrystal layer. By adjusting the In composition, the lattice strain and mismatch stress are dynamically balanced, maintaining the structural stability of the pseudocrystal layer while effectively increasing the 2DEG concentration through quantum confinement, enhancing carrier transport efficiency. This overcomes the mobility bottleneck of traditional single heterojunctions and achieves ultra-high frequency (millimeter wave) operation through the high-concentration, low-scattering 2DEG, reducing the noise figure. This device is particularly suitable for applications with stringent high-frequency and low-power requirements, such as 5G communications and satellite payloads. Furthermore, the strain tolerance design of the epitaxial structure significantly reduces the dislocation defect rate, ensuring device reliability and quality controllability.

[0031] In one possible implementation, the calculation formula for the In component content is specifically:

[0032] ;

[0033] in, represents the lattice mismatch strain between the GaAs buffer layer and the InGaAs pseudocrystalline layer, The lattice mismatch strain between the InGaAs pseudocrystalline layer and the n-doped AlGaAs barrier layer, represents the lattice constant of n-doped AlGaAs, represents the lattice constant of the InGaAs pseudocrystalline layer at In component content x, and represent the InAs lattice constant and GaAs lattice constant, respectively. Indicates taking the absolute value, Indicates taking Take the x value below the minimum value.

[0034] In the InGaAs / GaAs heterojunction, when the lattice mismatch is 1.62%, the alignment angle deviation (0.90°) between the epitaxial layer and the substrate is observed through the ion channel effect. At this time, the material still maintains a high crystal quality. However, if the mismatch increases further (such as >2%), the elastic strain cannot fully compensate for the mismatch stress, resulting in a sharp increase in dislocation density. For the InGaAs / AlGaAs system, when the total strain value (compressive strain + tensile strain) exceeds 2%, the dislocation density may exceed 10 5 cm⁻², significantly reducing electron mobility and device reliability.

[0035] It should be noted that the In component content is determined by minimizing the sum of the absolute values ​​of the double-interface lattice mismatch strain, and the total strain is strictly controlled below 1.62%. The elastic strain compensation mechanism is used to maintain the stability of the pseudocrystalline layer (dislocation density <10³cm⁻²), and the two-dimensional electron gas (2DEG) mobility is increased to above 8,000 cm² / V·s through the dynamic balance of the double-interface strain, while avoiding the sharp increase in dislocation density caused by high In component (>10 5 cm⁻²), ensuring the simultaneous optimization of material crystal quality and device performance.

[0036] In a possible implementation, the target thickness is calculated as follows:

[0037] ;

[0038] in, Indicates the target thickness, min indicates the minimum value, represents the reduced Planck constant, represents the effective mass of electrons in InGaAs related to the In component content x, represents the rest mass of a free electron, and Respectively, represents the effective barrier height related to x, represents the ground state energy level of the InGaAs pseudocrystalline layer related to x, represents the AlGaAs / InGaAs conduction band offset related to x, represents the GaAs / InGaAs conduction band offset related to x, represents the maximum thickness of the InGaAs pseudocrystalline layer without dislocation defects under x, b represents the Burgers vector, represents Poisson's ratio, π represents pi, represents the effective total strain related to x, and ln represents the natural logarithm function.

[0039] Specifically, the specific calculation formula of the ground state energy level of the InGaAs pseudocrystalline layer related to x is: , where d represents the quantum well thickness formed by the GaAs buffer layer, InGaAs pseudocrystalline layer and n-doped AlGaAs barrier layer. .in, It is a self-consistent equation, that is, both sides of the equation contain , which can be solved by iterative method.

[0040] It should be noted that the mathematical optimization approach to target thickness determination through multi-physics coupled modeling (quantum confinement effects and strain mechanics balance) offers the following key advantages: First, the electron effective mass and ground-state energy level parameters are introduced based on the Schrödinger equation to accurately quantify the effect of quantum wells on 2DEG mobility. Second, the electron tunneling probability is calculated by combining the conduction band offset and the effective barrier height to ensure optimal wave function localization (transmission coefficient < 10⁻³). Furthermore, a critical thickness model is used to constrain dislocation defect generation conditions, and a min function is employed to dynamically balance quantum properties and structural stability. Ultimately, the target thickness is controlled within a reasonable range, increasing the 2DEG concentration and, consequently, the performance and reliability of the PHEMT device.

[0041] In practical applications, a double heterojunction design and precise control of the In composition effectively increase the 2DEG concentration and optimize mobility. Precisely controlling the thickness of the InGaAs pseudocrystalline layer ensures balanced lattice mismatch stresses, reduces dislocation defects, and maintains a high-quality crystal structure. This structure not only overcomes the mobility bottleneck of traditional PHEMTs but also enhances device stability and performance in high-frequency applications by optimizing electronic properties and quantum confinement effects.

[0042] Example 2

[0043] In one embodiment, the reference Figure 2 , showing a schematic flow chart of a method for preparing an epitaxial structure of a PHEMT device provided by the present invention.

[0044] The present invention provides a method for preparing an epitaxial structure of a PHEMT device, the method comprising:

[0045] S1: Pre-treating the InP substrate.

[0046] In a possible implementation, S1 specifically includes:

[0047] S101: chemically cleaning the InP substrate using a chemical cleaning agent, wherein the chemical cleaning agent includes deionized water, hydrofluoric acid solution, acetone and isopropyl ketone.

[0048] S102: Polishing the cleaned InP substrate using an alumina polishing technique.

[0049] It should be noted that chemical cleaning and polishing effectively remove organic matter, oxides, and other impurities that may be present on the surface of the InP substrate, ensuring a clean and flat surface. Chemical cleaning helps remove difficult-to-clean contaminants, while alumina polishing technology provides a uniform and smooth surface, enhancing the adhesion between the substrate and the subsequently grown layers, and improving the quality and stability of the epitaxial layer.

[0050] S2: Growing a GaAs buffer layer on the pre-treated InP substrate.

[0051] In a possible implementation, S2 is specifically:

[0052] The GaAs buffer layer was grown on the InP substrate by metal organic chemical vapor deposition at a growth temperature ranging from 550°C to 650°C.

[0053] It should be noted that the growth of GaAs buffer layers via metal-organic chemical vapor deposition (MOCVD) enables the deposition of high-quality thin films on InP substrates. This method, grown within a temperature range of 550°C to 650°C, effectively controls the thickness and crystal quality of the buffer layer, reducing the lattice mismatch between the substrate and the subsequently grown layers. This improves the quality of the epitaxial layer, reduces dislocation defects, and provides a good foundation for subsequent material growth.

[0054] S3: Growing an InGaAs pseudocrystalline layer to a target thickness, with the grown In component content deviation rate being less than a preset In component content deviation rate and the grown InGaAs pseudocrystalline layer target thickness deviation rate being less than a preset target thickness deviation rate as constraints.

[0055] It should be noted that those skilled in the art can set the preset In component content deviation rate and the preset target thickness deviation rate according to actual needs, and the present invention does not limit this.

[0056] Optionally, the In component content deviation rate may be set to 0.005, and the preset target thickness deviation rate may be set to 0.3 nm.

[0057] In a possible implementation, S3 is specifically:

[0058] With the growth In component content deviation rate constrained to be less than the preset In component content deviation rate, In source and Ga source are introduced, and an InGaAs pseudocrystalline layer is grown to a target thickness by metal organic chemical vapor deposition, wherein the In source and Ga source are trimethyl indium and trimethyl gallium, respectively.

[0059] It should be noted that high-quality growth of the InGaAs pseudocrystalline layer is ensured by precisely controlling the In content and the thickness deviation of the pseudocrystalline layer. By setting a deviation limit, the lattice strain and thickness of the InGaAs layer remain within a preset range, thereby reducing lattice mismatch and dislocation defects. The use of metal-organic chemical vapor deposition (MOCVD) for growth not only improves layer uniformity but also effectively optimizes the crystal structure by precisely controlling the flow rates of the In and Ga sources, further enhancing device performance, particularly stability in high-frequency and high-power applications.

[0060] In one possible embodiment, the feed rate of the In source and the Ga source is determined by constraining the relative flow rate fluctuation rate between the metal source and the arsenic source to be less than a preset relative flow rate fluctuation rate, wherein the metal source includes the In source and the Ga source. The specific calculation formula for the feed rate is:

[0061] ;

[0062] in, and They represent the trimethylindium and trimethylgallium incorporation rates, respectively, and x represents the In component content. and represent the In atom incorporation efficiency and Ga atom incorporation efficiency related to the growth environment, respectively. represents the preset growth rate of the InGaAs pseudocrystalline layer, 、 and They represent the In component content deviation rate, target thickness deviation rate and relative flow rate fluctuation rate respectively, and t represents the expected growth time of the InGaAs pseudocrystalline layer.

[0063] It should be noted that those skilled in the art can set the preset flow rate fluctuation rate and the preset growth rate according to actual needs, and the present invention is not limited thereto. Optionally, the preset flow rate fluctuation rate can be set to 1%.

[0064] It should be noted that by calculating the feed rate based on the relative flow rate fluctuations of the In source and Ga source, and constraining the In component content, thickness deviation rate, and flow rate fluctuation rate, the growth rate of the InGaAs pseudocrystalline layer can be precisely controlled. This calculation method ensures the optimization of the incorporation efficiency of In and Ga during the growth process, thereby obtaining a uniform and high-quality thin film, reducing defects caused by growth rate fluctuations, and improving the stability and performance of the device. In addition, it allows the flow rate fluctuation rate and growth rate to be adjusted according to actual needs, providing flexibility for different production needs and helping to achieve higher-quality crystal growth under more refined process control.

[0065] S4: growing an n-doped AlGaAs barrier layer on the InGaAs pseudocrystalline layer.

[0066] In one possible embodiment, the doping source of the n-doped AlGaAs barrier layer is a SiH4 silicon source. S4 is specifically:

[0067] An n-doped AlGaAs barrier layer is grown on the InGaAs pseudocrystalline layer by metal organic chemical vapor deposition at a growth temperature ranging from 600°C to 700°C.

[0068] It should be noted that the use of metal-organic chemical vapor deposition (MOCVD) to grow an n-doped AlGaAs barrier layer on an InGaAs pseudocrystalline layer allows for precise control of the doping concentration and layer thickness. By selecting SiH4 as the silicon source, n-type doping can be effectively introduced, enhancing the electron confinement effect of the AlGaAs layer and supporting the formation of a two-dimensional electron gas (2DEG). Controlling the growth temperature within the range of 600°C to 700°C helps improve the layer's crystalline quality, reduce dislocation defects, ensure the uniformity and stability of the AlGaAs barrier layer, and further optimize device performance, particularly in high-frequency, high-power applications.

[0069] S5: growing a cap layer on the n-doped AlGaAs barrier layer to obtain a primary PHEMT device epitaxial structure.

[0070] In one possible implementation, the cap layer is an AlGaAs cap layer. S5 is specifically:

[0071] An AlGaAs cap layer is grown on the n-doped AlGaAs barrier layer by metal organic chemical vapor deposition to obtain a primary PHEMT device epitaxial structure. The growth temperature range is 600°C to 700°C, and the growth pressure range is 50Pa-200Pa.

[0072] It should be noted that growing an AlGaAs cap layer on the n-doped AlGaAs barrier layer via metal-organic chemical vapor deposition (MOCVD) can effectively improve the overall quality and stability of the device. The cap layer's primary function is to protect the underlying InGaAs pseudocrystalline layer and reduce surface defects. The uniformity and crystal quality of the AlGaAs cap layer are ensured by optimizing the growth temperature (600°C to 700°C) and growth pressure (50Pa-200Pa). This enhances the formation of the two-dimensional electron gas (2DEG), reduces scattering, and increases electron mobility, thereby enhancing the performance of PHEMT devices in high-frequency and high-power applications.

[0073] S6: annealing the primary PHEMT device epitaxial structure in an RTA furnace to obtain a PHEMT device epitaxial structure. The annealing time is 30 seconds, and the annealing temperature ranges from 600° C. to 800° C.

[0074] In practical applications, precise control of the deviation rate and thickness at each growth stage ensures high quality and uniformity of each layer. In particular, during the growth of the InGaAs pseudocrystalline layer, strict control of the In component content and thickness deviation rate can reduce lattice mismatch and dislocation defects, thereby increasing the concentration and mobility of the 2DEG. Annealing treatment in an RTA furnace further optimizes the crystal quality of the epitaxial layer and reduces residual stress and defects. The entire preparation process ensures the stability of the epitaxial structure and the efficient optimization of device performance, meeting the requirements of high-frequency, low-noise, and high-power applications, with significant advantages in 5G communications and high-frequency electronic devices.

[0075] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The above embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, and all such variations and improvements fall within the scope of protection of the present invention.

Claims

1. A PHEMT device epitaxial structure, characterized in that: include: InP substrate, GaAs buffer layer, InGaAs pseudocrystalline layer, n-doped AlGaAs barrier layer and cap layer; The InP substrate, the GaAs buffer layer, the InGaAs pseudomorphic layer, the n-doped AlGaAs barrier layer and the cap layer are stacked in sequence; The GaAs buffer layer and the n-doped AlGaAs barrier layer respectively form a first conductive channel and a second conductive channel in the InGaAs pseudocrystalline layer for providing 2DEG; The In component content of the InGaAs pseudocrystal layer is such that the sum of the lattice strain of the InGaAs pseudocrystal layer is less than the lattice mismatch stress of the heterojunction, wherein the sum of the lattice strain includes a first lattice mismatch stress between the GaAs buffer layer and the InGaAs pseudocrystal layer and a second lattice mismatch stress between the InGaAs pseudocrystal layer and the n-doped AlGaAs barrier layer, and the heterojunction includes a first heterojunction formed by the GaAs buffer layer and the InGaAs pseudocrystal layer and a second heterojunction formed by the InGaAs pseudocrystal layer and the n-doped AlGaAs barrier layer; Under the constraint of the In component content of the InGaAs pseudomorphic layer, the thickness of the InGaAs pseudomorphic layer is a target thickness that allows the first conductive channel and the second conductive channel to overlap, wherein the target thickness is used to enhance the concentration of the 2DEG; The calculation formula of the In component content is specifically: ； in, represents the lattice mismatch strain between the GaAs buffer layer and the InGaAs pseudocrystalline layer, represents the lattice mismatch strain between the InGaAs pseudocrystalline layer and the n-doped AlGaAs barrier layer, represents the lattice constant of n-doped AlGaAs, represents the lattice constant of the InGaAs pseudocrystalline layer at In component content x, and represent the InAs lattice constant and GaAs lattice constant, respectively. Indicates taking the absolute value, Indicates taking Take the x value under the minimum value; The calculation formula of the target thickness is specifically: ； in, Indicates the target thickness, min indicates the minimum value, represents the reduced Planck constant, represents the effective mass of electrons in InGaAs related to the In component content x, represents the rest mass of a free electron, represents the effective barrier height related to x, represents the ground state energy level of the InGaAs pseudocrystalline layer related to x, represents the AlGaAs / InGaAs conduction band offset related to x, represents the GaAs / InGaAs conduction band offset related to x, represents the maximum thickness of the InGaAs pseudocrystalline layer without dislocation defects under x, b represents the Burgers vector, represents Poisson's ratio, π represents pi, represents the effective total strain related to x, and ln represents the natural logarithm function.

2. A method for preparing the epitaxial structure of a PHEMT device according to claim 1, characterized in that: Methods include: S1: pre-treating the InP substrate; S2: growing the GaAs buffer layer on the pretreated InP substrate; S3: Growing the InGaAs pseudocrystalline layer to the target thickness, with the In component content deviation rate being less than a preset In component content deviation rate and the target thickness deviation rate of the grown InGaAs pseudocrystalline layer being less than a preset target thickness deviation rate as constraints; S4: growing the n-doped AlGaAs barrier layer on the InGaAs pseudocrystalline layer; S5: growing the cap layer on the n-doped AlGaAs barrier layer to obtain a primary PHEMT device epitaxial structure; S6: Annealing the primary PHEMT device epitaxial structure in an RTA furnace to obtain the PHEMT device epitaxial structure, wherein the annealing time is 30 seconds and the annealing temperature range is 600° C. to 800° C.

3. The method for preparing the epitaxial structure of a PHEMT device according to claim 2, wherein: Said S1 specifically includes: S101: chemically cleaning the InP substrate using a chemical cleaning agent, wherein the chemical cleaning agent includes deionized water, hydrofluoric acid solution, acetone and isopropyl ketone; S102: Polishing the cleaned InP substrate using an alumina polishing technique.

4. The method for preparing the epitaxial structure of a PHEMT device according to claim 3, wherein: The S2 is specifically: The GaAs buffer layer is grown on the InP substrate by metal organic chemical vapor deposition, and the growth temperature ranges from 550° C. to 650° C.

5. The method for preparing the epitaxial structure of a PHEMT device according to claim 4, characterized in that: The S3 is specifically: With the grown In component content deviation rate being constrained to be less than a preset In component content deviation rate, an In source and a Ga source are introduced, and the InGaAs pseudocrystalline layer is grown according to the target thickness by metal organic chemical vapor deposition, wherein the In source and the Ga source are trimethyl indium and trimethyl gallium, respectively.

6. The method for preparing the epitaxial structure of a PHEMT device according to claim 5, characterized in that: The doping source of the n-doped AlGaAs barrier layer is a SiH4 silicon source; the S4 is specifically: The n-doped AlGaAs barrier layer is grown on the InGaAs pseudocrystalline layer by metal organic chemical vapor deposition, with a growth temperature ranging from 600° C. to 700° C.

7. The method for preparing the epitaxial structure of a PHEMT device according to claim 6, characterized in that: The cap layer is an AlGaAs cap layer; the S5 is specifically: The AlGaAs cap layer is grown on the n-doped AlGaAs barrier layer by metal organic chemical vapor deposition to obtain a primary PHEMT device epitaxial structure, with a growth temperature ranging from 600° C. to 700° C. and a growth pressure ranging from 50 Pa to 200 Pa.

Images