System and method for flexible extension of connectivity within integrated circuit system in package

Abstract

The invention relates to a system and method for flexible extension of connectivity within an integrated circuit system in package. An integrated circuit package includes a first integrated circuit die, a second integrated circuit die, and a third integrated circuit die. The integrated circuit package also includes a support structure. The first die, the second die, and the third die are attached to the support structure. The first integrated circuit die includes a first interface on a first side of the first integrated circuit die, and the second integrated circuit die includes a second interface on a second side of the second integrated circuit die. The first side is adjacent to the second side. The first integrated circuit die is configured to communicate with a second integrated circuit die via the first interface and the second interface.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 608,663, filed on Dec. 11, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to the field of electronic assemblies for several integrated circuit (IC) dies. The IC dies may be disposed on or within a module or an integrated circuit (IC) package. Background Art

[0004] The IC package may be a multi-chip module (MCM). Each of the IC dies in the MCM is typically connected to an interposer or a package substrate by fine wires or by solder bumps. The interposer may be attached to the package substrate. The interposer and the package substrate are typically made of materials such as silicon or other semiconductors or insulating materials. The term integrated circuit multi-chip module may refer to a package containing two or more IC dies. The MCM may be or include a system-in-package (SIP). Summary of the Invention

[0005] In one aspect, the present disclosure relates to an integrated circuit package, comprising: a first integrated circuit die; a second integrated circuit die; a third integrated circuit die; and a support structure, wherein the first integrated circuit die, the second integrated circuit die, and the third integrated circuit die are attached to the support structure, wherein the first integrated circuit die includes a first interface on a first side of the first integrated circuit die, and the second integrated circuit die includes a second interface on a second side of the second integrated circuit die, wherein the first side is adjacent to the second side, wherein the first integrated circuit die is configured to communicate with the second integrated circuit die via the first interface and the second interface, wherein the first integrated circuit die includes a third interface on a third side of the first integrated circuit die, and the second integrated circuit die includes a fourth interface on a fourth side of the second integrated circuit die, wherein the third integrated circuit die includes a fifth interface on a fifth side and a sixth interface on a sixth side, the sixth side being parallel to the third side and the fifth side, wherein the first integrated circuit die is configured to communicate with the third integrated circuit die via the fifth interface and the third interface, wherein the second integrated circuit die is configured to communicate with the third integrated circuit die via the sixth interface and the fourth interface.

[0006] On the other hand, the present disclosure relates to a package, comprising: a first high-bandwidth memory die including a first crossbar circuit on a first bottom tier, a first die-to-die interface on a first side, and a second die-to-die interface on a second side; a second high-bandwidth memory die including a second crossbar circuit on a second bottom tier, a third die-to-die interface on a third side, and a fourth die-to-die interface on a fourth side; and a compute die including a fifth die-to-die interface on a fifth side that communicates with the fourth die-to-die interface, the fifth side being parallel to the fourth side, and the first die-to-die interface communicating with the third die-to-die interface, wherein the first side is parallel to the third side.

[0007] On the other hand, the present disclosure relates to a method, comprising: disposing a first integrated circuit die on an interposer or a package substrate; disposing a second integrated circuit die on the interposer or the package substrate; disposing a third integrated circuit die on the interposer or the package substrate; and wherein the first integrated circuit die includes a first interface on a first side of the first integrated circuit die, and the second integrated circuit die includes a second interface on a second side of the second integrated circuit die, wherein the first side is adjacent to the second side, wherein the first integrated circuit die is configured to communicate with the second integrated circuit die via the first interface and the second interface, wherein the first integrated circuit die includes a third interface on a third side of the first integrated circuit die, and the second integrated circuit die includes a fourth interface on a fourth side of the second integrated circuit die, wherein the third integrated circuit die includes a fifth interface on a fifth side and a sixth interface on a sixth side, the sixth side being parallel to the third side and the fifth side, wherein the first integrated circuit die is configured to communicate with the third integrated circuit die via the fifth interface and the third interface, and wherein the second integrated circuit die is configured to communicate with the third integrated circuit die via the sixth interface and the fourth interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various objects, aspects, features, and advantages of the present disclosure will become more apparent and be better understood by reference to the detailed description in conjunction with the accompanying drawings, in which like reference characters consistently identify corresponding elements. In the drawings, like reference numerals generally denote equivalent, functionally similar, and / or structurally similar elements.

[0009] Figure 1 is a schematic cross-sectional view of an electronic package having several semiconductor chips or IC dies according to some embodiments.

[0010] Figure 2 is according to some embodiments Figure 1Schematic top plan view of the electronic package described therein.

[0011] Figure 3 is a general block diagram of an HBM IC die for the Figure 1 electronic package described therein according to some embodiments.

[0012] Figure 4 is a general block diagram of an HBM IC die for the Figure 1 electronic package described therein according to some embodiments.

[0013] Figure 5 is a schematic top plan view of an electronic package having several semiconductor chips or IC dies according to some embodiments.

[0014] Figure 6 is a schematic top plan view of an electronic package having several semiconductor chips or IC dies according to some embodiments. DETAILED DESCRIPTION

[0015] The descriptions in the drawings are schematic. It should be noted that in different drawings, similar or identical elements or features have the same reference symbols or reference symbols that differ only in the first digit from the corresponding reference symbols. To avoid unnecessary repetition, elements or features that have been elucidated with respect to previously described embodiments are not elucidated again at later description locations.

[0016] In addition, as illustrated in the drawings, spatial relative terms (such as "vertical", "horizontal", "bottom", "top", "front" and "rear", "above" and "below", "left" and "right", etc.) are used to describe the relationship of one element to another element. Therefore, spatial relative terms may apply to orientations in use that are different from the orientation depicted in the drawings. All such spatial relative terms are only for the convenience of description and refer to the orientation shown in the drawings, and are not necessarily restrictive, because according to some embodiments, the device in use may assume an orientation different from the orientation illustrated in the drawings.

[0017] The systems and methods can be used with system-in-package (SIP). In some embodiments, a system can refer to an integrated circuit package of an integrated system containing some or all components of a computer, communication system, processing system, sensor system, storage system, or other electronic system. In some embodiments, these components can include one or more central processing units (CPUs) on a chip, memories, radios, network circuits, memory interfaces, input / output devices and interfaces, and auxiliary storage interfaces, which are typically together with other components (such as radio modems and graphics processing units (GPUs)). An SIP can contain digital and / or analog, mixed-signal and typically contains radio frequency signal processing functions, or in some embodiments can contain discrete application processors. The components of an SIP can be disposed on two or more IC dies.

[0018] The systems and methods described herein can be used with processors or application specific integrated circuits (ASICs) that integrate several (e.g., multiple) individual dies within a system-in-package (SIP) using 2-dimensional (2D), 2.5D, and 3D technologies to optimize various device functions to best suit the manufacturing process. In some embodiments, the SIP includes components used in high performance computing (HPC) systems including but not limited to high bandwidth memory (HBM). The HBM is provided as a 3D stack of DRAM dies connected to a bottom die (e.g., a buffer die) using through-silicon vias (TSVs). In some embodiments, the bottom die provides high speed input / output (I / O) connections to adjacent dies. In some embodiments, an interposer configured for high density signal routing can be used to route connections between the dies. From a connectivity perspective, a conventional die-to-die (D2D) connection provided by an interposer is a single end-point (e.g., an additional way to make additional connections from an alternative signal path to an HBM device is actually difficult or impossible to implement) system. In some embodiments, the systems and methods overcome the disadvantages associated with the connectivity wall created by the HBM, which can impede the outward expansion of additional connectivity due to adjacent dies located on the interposer. In some embodiments, the systems and methods utilize the ability to increase the physical size of the interposer and other advanced packaging substrates. In some embodiments, customization according to the HBM bottom die allows for more flexible connectivity and increases what is allowed on the interposer itself. Although rectangular dies, bottom buffers, and interposers are discussed and shown in the figures, other shapes (e.g., squares, pentagons, hexagons, circles, octagons, rhombuses, etc.) can also be used.

[0019] In some embodiments, a configurable switch, crossbar, or other connection matrix that contains high-bandwidth ingress / egress signaling and can route access across all four sides of the HBM via adjacent dies is included on the HBM bottom die. In some embodiments, the configuration enables adding more chip content on the interposer and achieving higher inter-die bandwidth. Each side of the die can represent a set of logical ports that provide connectivity to ports on any of the three alternative sides of the device or to the local HBM device itself. In some embodiments, the ports are subdivided or grouped into other groupings according to the number of HBM channels. In this way, in some embodiments, access to the HBM can be provided to / from any of the interfaces. In some embodiments, the HBM can act as a forwarding switch to / from other general-purpose devices adjacent to the HBM for data that is not related to local HBM storage. In some embodiments, the HBM is no longer a connectivity endpoint but a bridge to other functions in the SIP. In some embodiments, a crossbar can refer to a circuit that facilitates interconnections within an IC die (e.g., to ports). The crossbar can act as a traffic director, coordinating the flow of signals and data between various functional blocks. In some embodiments, the crossbar includes a matrix of intersecting horizontal and vertical lines, forming a grid-like structure that enables multiple inputs to be selectively routed (e.g., via switches) to specific outputs.

[0020] In some embodiments, the bottom buffer of the HDM is coupled to the interposer or the package substrate via microbump bonding pads. In some embodiments, the interposer is coupled to the package substrate via microbump bonding pads. In some embodiments, a higher per-pin speed interface is used to reduce the number of pins required per interface. In some embodiments, this allows for more efficient use of the fixed microbump resources.

[0021] A Broadcom D2D interface or other D2D interface (e.g., Universal Chiplet Interconnect Express (UCIe TM ), Bundle of Wires (BoW), etc.) can provide a connection to the IC die. In some embodiments, each D2D interface can be subdivided into smaller lanes or channels. The interface can be configured based on the application. In some embodiments, for adjacent connections between dies, only a subset of the available lanes may be required depending on the bandwidth requirements. In some embodiments, unused lanes can be deactivated to save power and to save routing on the interposer or the package substrate. In some embodiments, the ability to deactivate unused D2D signals on the HBM device is low-cost for system implementations but allows for great flexibility in connecting components based on the required bandwidth. In some embodiments, the system and method provide a flexible D2D signaling port allocation method to achieve maximum flexibility in the physical attachment between adjacent dies.

[0022] In some embodiments, the system and method provide flexibility in extending the perimeter to meet the design criteria and requirements of SIP high-performance computing (HPC) and artificial intelligence (AI) applications. In some embodiments, the SIP includes one or more compute dies and one or more HBM dies. In some embodiments, the SIP includes one or more compute dies, one or more I / O dies, and one or more HBM dies. In some embodiments, one or more HBM dies have high-bandwidth connections to one or more compute dies and to one or more I / O dies.

[0023] Some embodiments relate to an integrated circuit package. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, and a third integrated circuit die. The integrated circuit package further includes a support structure. The first integrated circuit die, the second integrated circuit die, and the third integrated circuit die are attached to the support structure. The first integrated circuit die includes a first interface on a first side of the first integrated circuit die, and the second integrated circuit die includes a second interface on a second side of the second integrated circuit die. The first side is adjacent to the second side. The first integrated circuit die is configured to communicate with the second integrated circuit die via the first interface and the second interface. The first integrated circuit die includes a third interface on a third side of the first integrated circuit die, and the second integrated circuit die includes a fourth interface on a fourth side of the second integrated circuit die. The third die includes a fifth interface on a fifth side and a sixth interface on a sixth side. The sixth side is parallel to the third side and the fifth side. The first integrated circuit die is configured to communicate with the third integrated circuit die via the fifth interface and the third interface. The second integrated circuit die is configured to communicate with the third integrated circuit die via the sixth interface and the fourth interface.

[0024] In some embodiments, an interface refers to a boundary or interaction point where communication, interaction, or exchange occurs between two or more dies, systems, devices, or components. The interface can be an input / output interface. In various contexts, an interface serves as a means for different elements to connect and interact with each other. In some embodiments, an integrated circuit die refers to a chip, substrate, or structure that contains an integrated circuit. In some embodiments, an IC or integrated circuit refers to an electronic circuit that includes small components (e.g., transistors, diodes, resistors, capacitors, or inductors) fabricated on a substrate. In some embodiments, neighbor or adjacent can refer to one side of a die being close to one side of another die. In some embodiments, adjacent sides of a die can be parallel. If there is no intermediate die, then an adjacent die can be the next die. Adjacent does not necessarily mean the separation distance between adjacent dies.

[0025] In some embodiments, the support structure includes an interposer. In some embodiments, the support structure includes a package substrate. In some embodiments, the first integrated circuit die and the second integrated circuit die include memory circuits. In some embodiments, the first integrated circuit die and the second integrated circuit die include high bandwidth memory. In some embodiments, the high bandwidth memory is a stack of IC dies. In some embodiments, an interposer refers to any structure that facilitates connections between dies and a package substrate or any other die. The interposer can be an intermediate substrate layer placed between an integrated circuit (IC) and a package substrate. The interposer can enable finer pitch connections than can be achieved directly between the IC and the package substrate. In some embodiments, a memory circuit refers to any device capable of implementing electronic storage of data. In some embodiments, high bandwidth memory refers to a memory circuit that provides high bandwidth performance.

[0026] In some embodiments, the package further includes a fourth integrated circuit die. The fourth integrated circuit die includes a seventh interface on a seventh side, and wherein the first integrated circuit die includes an eighth interface on a sixth side. The first integrated circuit die is configured to communicate with the fourth integrated circuit die via the seventh interface and the eighth interface. The sixth side and the seventh side are adjacent sides, and the sixth side is opposite the first side. In some embodiments, the fourth integrated circuit die includes input / output circuitry. In some embodiments, an input / output (I / O) circuit, I / O interface, or I / O controller refers to any component or subsystem that facilitates communication between a device and an external peripheral device or system. In some embodiments, the I / O circuit can manage the exchange of data, commands, and control signals.

[0027] In some embodiments, the fourth integrated circuit die includes computing circuitry. In some embodiments, the first interface and the second interface are configurable. In some embodiments, at least 90% of the interfaces are provided along the first side. In some embodiments, the first interface is larger than the third interface.

[0028] Some embodiments relate to a package. The package includes: a first high-bandwidth memory die including a first crossbar circuit on a first bottom tier, a first die-to-die interface on a first side, and a second die-to-die interface on a second side; a second high-bandwidth memory die including a second crossbar circuit on a second bottom tier, a third die-to-die interface on a third side, and a fourth die-to-die interface on a fourth side; and a compute die. The compute die includes a fifth die-to-die interface on a fifth side and communicating with the fourth die-to-die interface. The fifth side is parallel to the fourth side, and the first die-to-die interface communicates with the third die-to-die interface. The first side is parallel to the third side. In some embodiments, a crossbar circuit refers to any circuit for creating a connection matrix between multiple input and output lines. A crossbar circuit can facilitate non-blocking, point-to-point communication between different input and output lines of an IC die.

[0029] In some embodiments, the fourth die-to-die interface (e.g., in size and shape) is configurable. In some embodiments, the fourth die-to-die interface is configurable in size. In some embodiments, the first die-to-die interface is the same size as the second die-to-die interface. In some embodiments, the package further includes an input / output die. In some embodiments, the input / output die includes a serializer / deserializer circuit. In some embodiments, the input / output die includes a memory interface circuit. In some embodiments, a serializer / deserializer circuit refers to any circuit for converting a parallel data stream to a serial data stream (serializing) and vice versa (deserializing). In some embodiments, a memory interface circuit refers to any circuit that facilitates communication with a memory circuit. In some embodiments, a memory interface circuit can manage the exchange of data, address, and control signals between a CPU or memory controller and a memory module.

[0030] Some embodiments relate to a method. The method includes disposing a first integrated circuit die on an interposer or a package substrate. The method further includes disposing a second integrated circuit die on the interposer or the package substrate. The method further includes disposing a third integrated circuit die on the interposer or the package substrate. The first integrated circuit die includes a first interface on a first side of the first integrated circuit die, and the second integrated circuit die includes a second interface on a second side of the second integrated circuit die. The first side is adjacent to the second side. The first integrated circuit die is configured to communicate with the second integrated circuit die via the first interface and the second interface. The first integrated circuit die includes a third interface on a third side of the first integrated circuit die, and the second integrated circuit die includes a fourth interface on a fourth side of the second integrated circuit die. The third die includes a fifth interface on a fifth side and a sixth interface on a sixth side. The sixth side is parallel to the third side and the fifth side. The first integrated circuit die is configured to communicate with the third integrated circuit die via the fifth interface and the third interface. The second integrated circuit die is configured to communicate with the third integrated circuit die via the sixth interface and the fourth interface.

[0031] In some embodiments, the first interface is configurable and uses vias coupled to the interposer or the package substrate. According to a first exemplary aspect, a SIP includes (a) a substrate having a substrate body and a main surface; (b) an array of solder connection elements formed at the main surface; and (c) an interposer at the main surface. In some embodiments, a ball grid array (BGA) is disposed on the substrate. The SIP can be at least a part of a surface mount device (SMD) (i.e., a packaged electronic component configured for surface mounting). The surface mounting can be performed, for example, with any type of placement machine (e.g., a pick and place placement machine).

[0032] In some embodiments, the solder connection elements are solder balls or micro-balls. However, other geometries deviating from the ball shape can be used to implement the solder connection elements. Other possible geometries can include ellipsoids, cones, cylinders, cuboid geometries, or combinations thereof.

[0033] Figure 1 An electronic package 100 according to some embodiments is shown. The electronic package 100 includes dies 104, 106, and 110, a package substrate 120, and an interposer 130. In some embodiments, the electronic package 100 can be an IC package containing a SIP for HPC and AI operations.

[0034] In some embodiments, dies 104, 106, and 110 are directly coupled to package substrate 120. In some embodiments, die 104 includes circuitry for HBM, and die 106 includes circuitry for input / output (I / O) operations. Die 104 can be a stack of layers or dies. Die 104 can include a crossbar switch. In some embodiments, die 106 includes serializer / deserializer (SERDES) circuitry. In some embodiments, die 110 is a compute die. Figure 1 The sizes, dimensions, and numbers of the dies shown in Figure 1 are exemplary.

[0035] Interposer 130 is connected to each of dies 104, 106, and 110 via solder connection elements (e.g., microbumps). In some embodiments, package substrate 120 is coupled to interposer 130 via microbumps. Other types of connections can be used to connect dies 104, 106, 110, interposer 130, and package substrate 120. The solder connection elements can be or include solder balls, pins, wires, or other conductive elements. Package substrate 120 can include a plurality of solder connection elements 135 formed on a lower main surface. In some embodiments, interposer 130, package substrate 120, or a combination of interposer 130 and package substrate 120 can be a support structure or substrate for package 100.

[0036] Depending on the particular application, substrate 120 can be any suitable support (base) for dies 104, 106, and 110 that allows for electrical chip connection with at least one solder connection element 135. Substrate 120 and interposer 130 can include embedded circuitry within substrate 120 or interposer 130. In some embodiments, the embedded circuitry forms a redistribution structure. The circuitry can include conductor paths parallel to the main surface (horizontal) and conductor paths perpendicular to the main surface (vertical) (e.g., via connections). The redistribution structure can allow the solder connection elements for chip connection to be spatially dispersed. Substrate 120 and interposer 130 can be made of or include a printed circuit board (PCB) (e.g., a multi-layer PCB made of organic or ceramic materials).

[0037] Reference Figure 2, in some embodiments, the electronic package 100 includes dies 110a and 110b configured as computing circuits, dies 104a through h configured as memory circuits (e.g., HBM), and dies 106a through h. In some embodiments, dies 106a through d are configured as I / O circuitry. Dies 106a through d may include circuitry for a memory interface. In some embodiments, the memory interface circuitry may be a DDR5, double data rate 5, or DDR 4 interface circuit. The interface circuit may include on-die ECC (error correction code) functionality, which helps improve the reliability of data stored in the memory by detecting and correcting errors. In some embodiments, dies 106a through h provide a low voltage interface. Dies 106e through h may be configured as SERDES circuitry. According to some embodiments, in Figure 1 one of dies 110a through b, two of dies 106a through h, and two of dies 104a through h respectively correspond to die 110, die 106, and die 104.

[0038] Dies 106c through d communicate with the interposer 130 or the package substrate 120 via interfaces 172a through d at the periphery of dies 106c through d. In some embodiments, interfaces 172a through d are DDR5 interfaces and are located on the outer periphery of dies c through d. IC dies 106a through b have similar interfaces. Dies 106a through d communicate with dies 104a through d via interfaces 171a through d and interfaces 156a through d. In some embodiments, interfaces 171a through d and interfaces 156a through d are d2d interfaces.

[0039] In some embodiments, interfaces 156a through d and 171a through d communicate via circuit paths or routes associated with the interposer 130. Dies 104a through d include interfaces 152a through d and 158a through d, which provide connections between adjacent dies 104a through d. In some embodiments, interfaces 152a through d and 158a through d are similar to interfaces 156a through d and are d2d interfaces. Interfaces 152a and 156d do not have matching interfaces and may be used for external connections of package 100 or connections to other dies 106a through h, 110a through b, and 106a through h. Dies 104a through d communicate with dies 110a through b via interfaces 154a through d using interfaces 157a through d of die 110-b. Interfaces 154a through d and 161a through d are similar to interfaces 172a through d, 152a through d, 156a through d, and 158a through d. Dies 110a through b may communicate with each other and with dies 106a through h of dies 104a through h via interfaces 152a through d, 154a through d, and 158a through d of dies 104a through h.

[0040] Die 110a to b include interfaces 162 and 164 that can be used for external package connections or connections to other dies 106a to h, 110a to b, and 106a to h. In some embodiments, interfaces 162 and 164 are d2d interfaces. Interfaces 157a to d and 154a to d may have the same size. In some embodiments, interfaces 162 and 164 are larger than interfaces 157a to d. In some embodiments, interfaces 152a to d and 158a to d may have the same size.

[0041] In some embodiments, dies 104e to h include interfaces similar to interfaces 158a to d, 152a to d, 154a to d, and 154a to d. In some embodiments, die 106e includes interfaces 181a to d that are I / O interfaces. Dies 106f to g may include similar interfaces. Dies 104e to h include interfaces 180a to d for communicating with interfaces 182a to d of dies 106e to h. In some embodiments, interfaces 180a to e and 182a to d are similar to interfaces 152a to d and 171a to d. In some embodiments, interfaces 182a to d and 171a to d are smaller than interfaces 156a to d and 180a to d. The difference in size can be used to accommodate different configurations. In some embodiments, no interface is provided between dies 110a and 110b. The lack of an interface at the junction between dies 110a to b allows for more area for computing functionality. Dies 106a to h advantageously have interfaces on four sides, thereby allowing for greater expansion.

[0042] In some embodiments, a D2D interface refers to a communication mechanism that allows dies to directly exchange data with each other without external package connections. In some embodiments, a D2D interface enables communication and interaction between different integrated circuit (IC) dies within a multi-chip module (MCM) or a system-in-package (SiP). A D2D interface facilitates communication and data exchange between dies, enabling the dies to work together seamlessly. A D2D interface can have the advantages of high-speed data transfer, low-latency communication, and efficient power management. A D2D interface can use various communication protocols to ensure that different IC dies can understand and exchange data with each other. Example protocols include high-speed serial interfaces such as PCIe (Peripheral Component Interconnect Express) or parallel interfaces. The physical connections of a D2D interface can include a combination of micro-bumps, through-silicon vias (TSV), or other advanced packaging connection technologies. A D2D interface can include a timing control mechanism involving shared clock signals or a complex clock distribution system to maintain consistency and prevent timing issues. A D2D interface can include error detection and correction mechanisms to ensure data integrity. Techniques such as parity checking or more advanced error correction codes can be employed to identify and correct any errors that may occur during data transmission.

[0043] Reference Figure 2 and 3, the die 104 (which can be any one of the dies 104a to h) includes a crossbar switch circuit 302. The crossbar switch can be programmed for a specific configuration of the dies 110a to b, 104a to h, and 106a to h and the associated interfaces. In some embodiments, the crossbar switch circuit 302 is disposed on a substrate or a bottom die or a layer of the die 104. In some embodiments, the die 104 consists of a stack of dies 304a to d (e.g., HBM dies) disposed above the substrate associated with the crossbar switch circuit 302. In some embodiments, the crossbar switch circuit 302 is included on the dies 106a to h and 110a to b. Refer to Figure 2 , 3 and 4, the crossbar switch circuit 302 is disposed on a base layer or a bottom die 303. The die 303 also includes interfaces 356a to d. In some embodiments, the interfaces 356a to d can be the interfaces 352a to d, 354a to d, 356a to d, and 358a to d.

[0044] Compared with the JEDEC HBM I / O standard, the use of the D2D interface allows for a higher bandwidth per millimeter (BW / mm) (e.g., 4x to 8x higher data rate correspondingly reduces the signal bump count). In some embodiments, the dies 104a to h include an HBM4 controller and the crossbar switch circuit 302 on their substrate or bottom die. Advantageously, the package 100 allows for the use of a larger interposer 130 and / or a glass substrate because the dies 104a to h can be accessed from all sides and are no longer placed at the two ends.

[0045] In some embodiments, the die 104 is any type of computer memory architecture. The die 104 can be configured for faster communication between the die 104 and the die 110. The die 104 can include multiple layers of DRAM (Dynamic Random Access Memory) dies 304a to d stacked vertically on top of each other. In some embodiments, the vertically stacked layers of the dies 304a to d reduce the physical footprint of the memory and enable extremely fast data access, resulting in improved performance for graphics-intensive applications, artificial intelligence, and other memory-intensive tasks.

[0046] Refer to Figure 5, the electronic package 600 is similar to the package 100. The package 600 includes a die 610 configured as a computing circuit and dies 604a to f configured as memory circuits (e.g., HBM). Dies 604a to f communicate with interfaces 616a to f of the die 610 via interfaces 606a to f of dies 604a to f respectively. Interfaces 606a to f are larger d2d interfaces than interfaces 616a to f. In some embodiments, each of interfaces 606a to f includes an inactive portion 614 and an active portion 612. In some embodiments, the active portion 612 matches interfaces 616a to f such that the positions and sizes of the active portion 612 and the inactive portion 614 are equal. In some embodiments, the active portion 612 may be selected based on die-to-die perimeter adjacency to provide the best or near-best physical layout.

[0047] In some embodiments, interfaces 606a to f are on the die 610, and interfaces 616a to f are on dies 604a to f. In some embodiments, interfaces 616a to f are configurable. Interfaces 606a to f may have active portions 612 in the middle 630 (e.g., regions 632 and 634) of the inactive portion 614, or be located at one end leaving an inactive portion at the other end 640. In some embodiments, the inactive portion 614 may be deactivated to save power.

[0048] Reference Figure 6 , the electronic package 700 is similar to the package 100. The package 700 includes a die 710 configured as a computing circuit, dies 706a to d configured as I / O circuits, dies 716a to d configured as I / O circuits, dies 714a to b configured as I / O circuits, and dies 704a to h configured as memory circuits (e.g., HBM). Dies 716a to d may include circuits for a memory interface similar to dies 106a to d, and dies 716a to d may include circuits for an I / O interface and may be similar to dies 106a to h ( Figure 2 ). In some embodiments, dies 714a to b may be similar to dies 716a to h.

[0049] Die 704a communicates with dies 716a to b via interfaces 762 and 764 and interface 760. In some embodiments, interface 760 extends along the perimeter of one side of die 104a (e.g., almost along the entire side or more than 90%). In some embodiments, unused portions or paths of interface 760 may be deactivated to save power. Die 704d communicates with dies 706a to b via interfaces 758 and 760 and interface 756. In some embodiments, interface 756 extends along the perimeter of one side of die 104d (e.g., almost along the entire side or more than 90%). In some embodiments, unused portions or paths of interface 756 may be deactivated to save power.

[0050] Die 704d includes interface 750 on a side opposite to the side of interface 756. Die 704d communicates with die 710 and die 714a via interfaces 754 and 752 and interface 750. In some embodiments, interface 750 extends along the periphery of a side of die 104a (e.g., almost along the entire side or more than 90%). In some embodiments, unused portions or paths of interface 750 may be deactivated to save power. Dies 704c to b may include interfaces similar to those of dies 704a to b. Die 710 may communicate with dies 716a to d and 704a to d in a manner similar to that described above. The interfaces described above may be customized for bandwidth according to system parameters and design criteria.

[0051] It should be noted that the term "comprising" does not exclude other elements or operations, and the use of the article "a" does not exclude a plurality. Elements associated with different embodiments may also be combined. It should also be noted that reference signs in the claims should not be construed as limiting the scope of the claims.

Claims

1. An integrated circuit package, comprising: a first integrated circuit die; a second integrated circuit die; a third integrated circuit die; and A support structure, wherein the first integrated circuit die, the second integrated circuit die and the third integrated circuit die are attached to the support structure, wherein the first integrated circuit die includes a first interface on a first side of the first integrated circuit die, and the second integrated circuit die includes a second interface on a second side of the second integrated circuit die, wherein the first side is adjacent to the second side, wherein the first integrated circuit die is configured to communicate with the second integrated circuit die via the first interface and the second interface, wherein the first integrated circuit die includes a third interface on a third side of the first integrated circuit die, and the second integrated circuit die includes a fourth interface on a fourth side of the second integrated circuit die, wherein the third integrated circuit die includes a fifth interface on a fifth side and a sixth interface on a sixth side, the sixth side being parallel to the third side and the fifth side, wherein the first integrated circuit die is configured to communicate with the third integrated circuit die via the fifth interface and the third interface, and wherein the second integrated circuit die is configured to communicate with the third integrated circuit die via the sixth interface and the fourth interface. 2 . The integrated circuit package of claim 1 , wherein the support structure comprises an interposer.

3. The integrated circuit package of claim 2, wherein the support structure comprises a package substrate.

4. The integrated circuit package of claim 1, wherein the first integrated circuit die and the second integrated circuit die include memory circuits.

5. The integrated circuit package of claim 1, wherein the first integrated circuit die and the second integrated circuit die comprise high bandwidth memory.

6. The integrated circuit package of claim 1 , comprising a fourth integrated circuit die, wherein the fourth integrated circuit die includes a seventh interface on a seventh side, and wherein the first integrated circuit die includes an eighth interface on a sixth side, wherein the first integrated circuit die is configured to communicate with the fourth integrated circuit die via the seventh interface and the eighth interface, wherein the sixth side and the seventh side are adjacent sides, and the sixth side is opposite to the first side.

7. The integrated circuit package of claim 6, wherein the fourth integrated circuit die comprises input / output circuitry.

8. The integrated circuit package of claim 6, wherein the fourth integrated circuit die comprises computing circuitry.

9. The integrated circuit package of claim 1, wherein the first interface and the second interface are configurable.

10. The integrated circuit package of claim 1, wherein the first interface is disposed along at least 90% of the first side.

11. The integrated circuit package of claim 1, wherein the first interface is larger than the third interface.

12. A package comprising: a first high bandwidth memory die comprising a first crossbar circuit on a first bottom level, a first die-to-die interface on a first side, and a second die-to-die interface on a second side; a second high bandwidth memory die comprising a second crossbar circuit on a second bottom level, a third die-to-die interface on a third side, and a fourth die-to-die interface on a fourth side; and A computing die comprising a fifth die-to-die interface on a fifth side and in communication with the fourth die-to-die interface, the fifth side being parallel to the fourth side, and the first die-to-die interface being in communication with the third die-to-die interface, wherein the first side is parallel to the third side.

13. The package of claim 12, wherein the fourth die-to-die interface is configurable.

14. The package of claim 12, wherein the fourth die-to-die interface is configurable in size.

15. The package of claim 12, wherein the first die-to-die interface is the same size as the second die-to-die interface.

16. The package of claim 12, further comprising an input / output die.

17. The package of claim 16, wherein the input / output die comprises a serializer-deserializer circuit.

18. The package of claim 16 wherein the input / output die comprises memory interface circuitry.

19. A method comprising: Disposing a first integrated circuit die on an interposer or a package substrate; disposing a second integrated circuit die on the interposer or the package substrate; disposing a third integrated circuit die on the interposer or the package substrate; and wherein the first integrated circuit die includes a first interface on a first side of the first integrated circuit die, and the second integrated circuit die includes a second interface on a second side of the second integrated circuit die, wherein the first side is adjacent to the second side, wherein the first integrated circuit die is configured to communicate with the second integrated circuit die via the first interface and the second interface, wherein the first integrated circuit die includes a third interface on a third side of the first integrated circuit die, and the second integrated circuit die includes a fourth interface on a fourth side of the second integrated circuit die, wherein the third integrated circuit die includes a fifth interface on a fifth side and a sixth interface on a sixth side, the sixth side being parallel to the third side and the fifth side, wherein the first integrated circuit die is configured to communicate with the third integrated circuit die via the fifth interface and the third interface, and wherein the second integrated circuit die is configured to communicate with the third integrated circuit die via the sixth interface and the fourth interface.

20. The method of claim 19, wherein the first interface is configurable and uses vias coupled to the interposer or the package substrate.

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