Semiconductor element and manufacturing method thereof
By forming doped stacks and doped regions on the substrate of the semiconductor element, the problem of large on-resistance in the existing semiconductor elements is solved, and the effect of reducing on-resistance and contact resistance is achieved.
Patent Information
- Application Number
- CN202410289965.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-12-08
- Filing Date
- 2024-03-14
- Publication Date
- 2025-06-13
AI Technical Summary
In the existing semiconductor components, the on-resistance (Ron) between the source and drain of the transistor components is large, resulting in an increase in power consumption.
By forming a doped stack on the substrate, including a first well connection layer, a conductive connection layer and a second well connection layer, and forming a doped region between the conductive region and the source/drain region, deep bonding of the conductive region and the source/drain region and the conductive connection layer is achieved, thereby reducing the spacing between the transistor structures.
It effectively reduces the on-resistance (Ron) of transistor components, reduces power consumption, and further reduces contact resistance.
Smart Images
Figure CN120152373A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art
[0002] For a long time, in the field of semiconductors, reducing the on-resistance between the source and drain of a transistor device, known as the on-resistance (R on ), is to reduce the power consumed on the resistance. Accordingly, providing a method for reducing the on-resistance (R on ) of a transistor device remains an issue of great concern in the industry. Summary of the Invention
[0003] Embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including the following steps. Provide a substrate, and the substrate has a surface. Form a doped stack in the substrate, where the doped stack includes a first well connection layer, a conductive connection layer formed on the first well connection layer, and a second well connection layer formed on the conductive layer. Form a mask on the surface of the substrate to expose multiple portions of the surface. Perform a doping process on the exposed portions to form doped regions, and the doping depth reaches the second well connection layer, so that the doped regions are joined to the second well connection layer in the depth direction. Form first conductive regions in two first portions of the substrate respectively so that the first conductive regions are joined to the conductive connection layer in the depth direction. Form two conductive regions in two first portions of the substrate so that the two conductive regions are joined to the conductive connection layer in the depth direction.
[0004] In some embodiments, the method further includes forming at least one source / drain region and at least two channel regions in multiple second portions of the substrate.
[0005] In some embodiments, the method further includes forming multiple gate structures on multiple third portions of the surface of the substrate, and includes the following steps. Form a first insulating layer on the surface of the substrate. Form a conductive layer on the first insulating layer. Pattern the first insulating layer and the conductive layer.
[0006] In some embodiments, the method further includes forming multiple contacts in multiple contact openings, and includes the following steps. Form contact openings above the two conductive regions and at least one source / drain region. Form a second insulating layer in the contact openings and on the conductive layer. Form multiple openings above the two conductive regions and at least one source / drain region, and the width of the openings is smaller than the width of the contact openings. Fill the openings with multiple conductive materials.
[0007] In some embodiments, at least one source / drain region is spaced apart from the conductive connection layer by a distance.
[0008] Embodiments of the present disclosure provide a semiconductor device, which includes a substrate, two conductive regions, a conductive connection layer, a well region, and source / drain regions. The substrate has a surface. The two conductive regions are disposed in the substrate. The conductive connection layer is disposed in the substrate and under the two conductive regions, and the conductive connection layer is electrically connected to the two conductive regions. The well region is disposed in the substrate and between the two conductive regions, and a bottom surface of the well region contacts a top surface of the conductive connection layer. The source / drain regions are disposed in the substrate between two adjacent channel regions and between the two conductive regions.
[0009] In some embodiments, the semiconductor device includes a gate structure and source / drain contacts. The gate structure is disposed on the surface of the substrate and above the two channel regions. The source / drain contacts are disposed on the source / drain regions and connected to the gate structure, wherein side surfaces of the source / drain contacts are surrounded by an insulating layer, and the gate structure is surrounded by an insulating layer.
[0010] In some embodiments, the semiconductor device includes two conductive contacts. The two conductive contacts are disposed on the two conductive regions and connected to the gate structure, wherein bottom surfaces of the two conductive contacts respectively contact top surfaces of the two conductive regions, and side surfaces of the two conductive contacts are respectively surrounded by an insulating layer.
[0011] In some embodiments, a height of a bottom surface of the source / drain regions is higher than a height of top surfaces of the two conductive regions.
[0012] Doping concentrations of the two conductive regions are different from a doping concentration of the well region. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Read the following embodiments in conjunction with the drawings to clearly understand the viewpoints of the present disclosure. It should be noted that, according to standard practices in the industry, various features are not drawn to scale. In fact, for the purpose of clear discussion, the dimensions of various features may be arbitrarily enlarged or reduced.
[0014] Figure 1 is a top view of a semiconductor device according to some embodiments of the present disclosure; and
[0015] Figures 2 to 7 is a cross-sectional view taken along section line AA’ showing various manufacturing stages of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 1 of DETAILED DESCRIPTION
[0016] In order to reduce the on-resistance R of transistor elements in a semiconductor structure on , embodiments of the present disclosure achieve reducing the pitch between transistor elements (transistor cells) by changing the distribution of an implantation structure (or doping structure), thereby increasing the drain current to reduce the on-resistance R of the transistor elements. onFor the purpose of this, the embodiments of the present disclosure will be described below in conjunction with the accompanying drawings. Figure 1 is a top view of a semiconductor device according to some embodiments of the present disclosure, and Figures 2 to 7 is a cross-sectional view taken along the Figure 1 section line AA' of each manufacturing stage of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.
[0017] First, please refer to Figure 2 , a substrate 102 having a first surface 102A and a second surface 102B is provided, and a doped stack 125 is formed in the substrate 102. In some embodiments, the substrate 102 is, for example, a silicon carbide (SiC) substrate. The doped stack 125 includes a first well connection layer 110A, a conductive connection layer 120 formed on the first well connection layer 110A, and a second well connection layer 110B formed on the conductive connection layer 120, wherein the first well connection layer 110A has a first doping depth D1, the conductive connection layer 120 has a second doping depth D2, and the first well connection layer 110A has a third doping depth D3. The first doping depth D1 is greater than the second doping depth D2, and the second doping depth D2 is greater than the third doping depth D3. In some embodiments, the first well connection layer 110A, the conductive connection layer 120, and the second well connection layer 110B include dopants. In some embodiments, the first well connection layer 110A, the conductive connection layer 120, and the second well connection layer 110B include P-type dopants. In some embodiments, the doping concentrations of the first well connection layer 110A and the second well connection layer 110B are the same, while the doping concentration of the conductive connection layer 120 is different from that of the first well connection layer 110A and the second well connection layer 110B.
[0018] In some embodiments, a mask (not shown) is formed on the substrate 102, and a plurality of portions of the first surface 102A of the substrate 102 are exposed by the mask. Subsequently, dopants are implanted into the exposed portions of the substrate 102 by a doping process to form a well connection layer, and the mask is removed. The well connection layer has a first doping depth D1, a first doping thickness, and a first doping concentration. Then, another mask (not shown) is formed on the substrate 102 to expose the plurality of portions of the first surface 102A of the substrate 102, and dopants are implanted into the exposed portions of the substrate 102 by a doping process to form a conductive connection layer 120 in the well connection layer. The conductive connection layer 120 has a second doping depth D2, a second doping thickness, and a second doping concentration, wherein the well connection layer is separated into a first well connection layer 110A (close to the second surface 102B of the substrate 102) and a second well connection layer 110B (close to the first surface 102A of the substrate 102) by the conductive connection layer 120. In addition, the first doping thickness is greater than the second doping thickness, and the first doping concentration is different from the second doping concentration.
[0019] In some embodiments, a mask (not shown in the figures) is formed on the substrate 102, and the mask exposes multiple portions of the first surface 102A of the substrate 102. Subsequently, a doping process with a first yellow light development energy is used to inject dopants into the substrate 102 to form a first well connection layer 110A. Then, dopants are injected into the substrate 102 with a second yellow light development energy to form a conductive connection layer 120 on the first well connection layer 110A. Next, dopants are injected into the substrate 102 with a third yellow light development energy to form a second well connection layer 110B on the conductive connection layer 120.
[0020] Next, as Figure 3 shown, a mask MK is formed on the first surface 102A of the substrate 102 to expose multiple portions PR of the first surface 102A of the substrate 102. Further, as Figure 4 shown, a doping process is performed in the exposed portions PR of the substrate 102 to inject dopants to form a doped region 110C in the substrate 102. And, the doping depth of the doped region 110C is a fourth doping depth D4 to reach the second well connection layer 110B, so that the doped region 110C is joined with the second well connection layer 110B in the depth direction. Subsequently, the mask ( Figure 3 the mask MK shown) is removed, exposing the undoped portions. In some embodiments, the dopants in the doped region 110C are P-type dopants. In some embodiments, the doping concentration and doping type of the doped region 110C are the same as those of the second well connection layer 110B.
[0021] As Figure 5 shown, conductive regions C are respectively formed in two first portions of the first surface 102A of the substrate 102, and the fifth doping depth D5 of the conductive regions C reaches the conductive connection layer 120, so that the conductive regions C are joined with the conductive connection layer 120 in the depth direction, and a well region W and a channel region CH located in the well region W are formed between the conductive regions C and on the conductive connection layer 120. And, source / drain regions S / D are formed in multiple second portions of the first surface 102A of the substrate 102, where the multiple second portions are located between the two first portions, and the source / drain regions S / D have a sixth doping depth D6.
[0022] In some embodiments, the doping type of the conductive regions C is different from that of the source / drain regions S / D. In some embodiments, the doping type of the conductive regions C is a P-type dopant, while the doping type of the source / drain regions S / D is an N-type dopant. In some embodiments, the doping depth of the conductive regions C is different from that of the source / drain regions S / D, that is, the height of the bottom surface of the source / drain regions S / D is higher than the height of the top surface of the conductive regions C. In some embodiments, the fifth doping depth D5 of the conductive regions C is greater than the sixth doping depth D6 of the source / drain regions S / D.
[0023] As Figure 6 shown, an insulating layer 130 is first deposited on the first surface 102A of the substrate 102, and then a conductive layer 140 is deposited on the insulating layer 130. Then, a mask (not shown in the figure) is formed on the conductive layer 140 to expose multiple portions of the surface of the conductive layer 140, and the exposed multiple portions correspond to the conductive region C and the source / drain regions S / D, so as to form contact openings OP and a gate structure G through a lithography process and an etching process. In some embodiments, the insulating layer 130 includes an oxide, such as silicon dioxide, hafnium oxide, or titanium oxide. In some embodiments, the conductive layer 140 includes polysilicon.
[0024] As Figure 7 shown, a first contact CP1 is formed in a contact opening (such as the contact opening OP shown in Figure 6 the figure) above the conductive region C, and a first transistor structure T1 is formed. And a second contact CP2 is formed in a contact opening (such as the contact opening OP shown in Figure 6 the figure) above the source / drain region S / D, and a second transistor structure T2 is formed. Specifically, an insulating layer 150 is deposited in the contact opening OP and on the conductive layer 140. Subsequently, the conductive layer 140 is patterned, and an opening (not shown in the figure) is formed above the conductive region C and the source / drain region S / D through an etching process, and the width of the opening is smaller than the width of the contact opening (such as the contact opening OP shown in Figure 6 the figure). Then, a conductive material is filled in the opening above the conductive region C to form the first contact CP1, and thus the first transistor structure T1 is formed. And a conductive material is filled in the opening above the source / drain region S / D to form the second contact CP2, and thus the second transistor structure T2 is formed. Therefore, the bottom surface of the first contact CP1 contacts the top surface of the conductive region C, and the bottom surface of the second contact CP2 contacts the top surface of the source / drain region S / D. And the side surfaces of the first contact CP1 and the second contact CP2 are surrounded by the insulating layer 150. In addition, the bottom surface of the insulating layer 150 located on the conductive region C or the source / drain region S / D also contacts the top surface of the conductive region C or the source / drain region S / D.
[0025] In some embodiments, the first transistor structure T1 is a P-type transistor structure T1, and the second transistor structure T2 is an N-type transistor structure T2. In some embodiments, the semiconductor element 100 formed by the first transistor structure T1 and the second transistor structure T2 is configured as a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), particularly configured as a depletion MOSFET (DMOSFET).
[0026] The method for manufacturing a semiconductor provided by this disclosure can utilize a method of separating the conductive region C and the source / drain regions S / D to connect the first transistor structure T1 and the second transistor structure T2 in series through the conductive connection layer 120 and the conductive region C. Then, only a small number of contacts need to be connected to the conductive region C, and the remaining contacts are all connected to the source / drain regions S / D, so as to achieve the purpose of reducing the pitch between the transistor structures to reduce the on-resistance R on and further reduce the contact resistance.
[0027] As Figure 1 and Figure 7 shown, an embodiment of this disclosure provides a semiconductor device 100. The semiconductor device 100 includes a substrate 102 having a first surface 102A and a second surface 102B, a first well connection layer 110A, a conductive connection layer 120, a second well connection layer 110B, a well region W, two P-type transistor structures T1 and an N-type transistor structure T2.
[0028] The first well connection layer 110A is disposed in the substrate 102 and close to the second surface 102B. The first well connection layer 110A has a first doping depth D1, and the first well connection layer 110A has a first doping concentration. In some embodiments, the first well connection layer 110A includes a P-type dopant.
[0029] The conductive connection layer 120 is disposed in the substrate 102 and on the first well connection layer 110A. The conductive connection layer 120 has a second doping depth D2, and the conductive connection layer 120 has a second doping concentration, where the second doping depth D2 is less than the first doping depth D1, and the second doping concentration is different from the first doping concentration. In some embodiments, the conductive connection layer 120 includes a P-type dopant.
[0030] The second well connection layer 110B is disposed in the substrate 102 and on the conductive connection layer 120. The second well connection layer 110B has a third doping depth D3, and the second well connection layer 110B has a second doping concentration, where the third doping depth D3 is less than the second doping depth D2. In some embodiments, the second well connection layer 110B includes a P-type dopant.
[0031] The P-type transistor structure T1 is disposed on the substrate 102, and well regions W and channel regions CH are respectively disposed in the substrate 102 on opposite sides of the P-type transistor structure T1. The P-type transistor structure T1 includes a conductive region C located between the channel regions CH, a gate structure G located on the substrate 102 and the channel regions CH, and a first contact CP1 located on the conductive region C. The bottom surface of the first contact CP1 contacts the top surface of the conductive region C, and the side surface of the first contact CP1 is surrounded by an insulating layer 150. The conductive region C has a fifth doping depth D5, and the bottom surface of the conductive region C contacts the top surface of the conductive connection layer 120, electrically connecting the conductive region C and the conductive connection layer 120. In some embodiments, the conductive region C includes P-type dopants. In some embodiments, the doping concentration of the conductive region C is the same as the doping concentration and doping type of the conductive connection layer 120.
[0032] Further, as Figure 1 shown, the first contact CP1 of the P-type transistor structure T1 has a first length L1 (in the x direction) and a first width W1 (in the y direction). In some embodiments, the first length L1 is equal to the first width W1. In some embodiments, the first width W1 is 0.8 μm, and the first length L is 0.8 μm. The conductive region C has a second length L2 (in the x direction) and a second width W2 (in the y direction). In some embodiments, the second length L2 is equal to the second width W2. In some embodiments, the first length L1 is less than the second length L2, and the first width W1 is less than the second width W2. In some embodiments, the second length L2 is 1 μm, and the second width W2 is 1 μm. Additionally, in the x direction, from the first side of the well region W on one side of the P-type transistor structure T1 to the second side of the well region W on the other side of the P-type transistor structure T1 is a third length L3, and in the y direction, from the first side of the well region W on one side of the P-type transistor structure T1 to the second side of the well region W on the other side of the P-type transistor structure T1 is a third width W3. In some embodiments, the third length L3 is equal to the third width W3. In some embodiments, the third length L3 is greater than the second length L2, and the third width W3 is greater than the second width W2. In some embodiments, the third width W3 is 2 μm, and the third length L3 is 2 μm. Further, in the y direction, the conductive connection layer 120 has a fourth width W4. In some embodiments, the fourth width W4 is greater than the second width W2 and less than the third width W3. In some embodiments, the fourth width W4 is 1.2 μm.
[0033] The N-type transistor structure T2 is disposed on the substrate 102 and located between two P-type transistor structures T1. Well regions W and channel regions CH are respectively disposed in the substrate 102 on opposite sides of the N-type transistor structure T2. In addition, the N-type transistor structure T2 includes source / drain regions S / D located between the channel regions CH, a gate structure G located on the substrate 102 and the channel regions CH, and a second contact CP2 located on the source / drain regions S / D. In addition, the bottom surface of the second contact CP2 contacts the top surface of the source / drain regions S / D, and the side surface of the second contact CP2 is surrounded by an insulating layer 150. The source / drain regions S / D have a sixth doping depth D6, and the sixth doping depth D6 is less than the fifth doping depth D5. In some embodiments, the source / drain regions S / D include N-type dopants.
[0034] Further, as Figure 1 shown, since the difference between the N-type transistor structure T2 and the P-type transistor structure T1 lies in the doping types of the conductive regions C and the source / drain regions S / D, and in Figure 1 the top view, the remaining structural features of the N-type transistor structure T2 and the P-type transistor structure T1 (such as the lengths and widths spanned by the second contact CP2, the source / drain regions S / D and the well regions W of the N-type transistor structure T2, and the relationship between the second width W2 of the source / drain regions S / D and the fourth width W4 of the conductive connection layer 120 and the relationship between the third width W3 and the fourth width W4 of the conductive connection layer 120) are substantially similar, so they will not be elaborated here.
[0035] It is worth mentioning that, as described above, the well region W is located between the conductive regions C, and the bottom surface of the well region W contacts the top surface of the conductive connection layer 120. The third doping depth D3 of the well region W is less than the fifth doping depth D5 of the conductive regions C.
[0036] As described above, through the contact between the conductive connection layer and the conductive region, and through the contact between the well region and the second well connection layer, the size of the contact can be made no longer limited by the critical dimensions (CD) of the conductive region and the source / drain region, so as to achieve the purpose of reducing the spacing between transistor structures to reduce the on-resistance R on and further reduce the contact resistance.
[0037]
Symbol Description
[0038] 100: Semiconductor element
[0039] 102: Substrate
[0040] 102A: First surface
[0041] 102B: Second surface
[0042] 110A: First well connection layer
[0043] 110B: Second well connection layer
[0044] 110C: Doped region
[0045] 120: Conductive connection layer
[0046] 125: Doped stack
[0047] 130, 150: Insulating layer
[0048] 140: Conductive layer
[0049] AA’: Section line
[0050] C: Conductive region
[0051] CH: Channel region
[0052] CP1: First contact
[0053] CP2: Second contact
[0054] D1: First doping depth
[0055] D2: Second doping depth
[0056] D3: Third doping depth
[0057] D4: Fourth doping depth
[0058] D5: Fifth doping depth
[0059] D6: Sixth doping depth
[0060] G: Gate structure
[0061] MK: Mask
[0062] PR: Portion
[0063] S / D: Source / drain region
[0064] OP: Contact opening
[0065] T1: First transistor structure / P-type transistor structure
[0066] T2: Second transistor structure / N-type transistor structure
[0067] L1: First length
[0068] L2: Second length
[0069] L3: Third length
[0070] W: Well region
[0071] W1: First width
[0072] W2: Second width
[0073] W3: Third width
[0074] W4: Fourth width
[0075] x, y: Directions.
Claims
1. A method for manufacturing a semiconductor element, characterized in that: include: Providing a substrate, wherein the substrate has a surface; forming a doping stack in the substrate, wherein the doping stack comprises a first well connection layer, a conductive connection layer formed on the first well connection layer, and a second well connection layer formed on the conductive connection layer; forming a mask on the surface of the substrate to expose portions of the surface; Performing a doping process on the exposed portions to form a doped region, and the doping depth reaches the second well connection layer, so that the doped region is joined to the second well connection layer in a depth direction; as well as Two conductive regions are formed in the two first portions of the substrate so that the two conductive regions are joined to the conductive connection layer in a depth direction.
2. The method according to claim 1, characterized in that Further including: At least one source / drain region and at least two channel regions are formed in the second portions of the substrate.
3. The method according to claim 2, characterized in that Further including: forming a plurality of gate structures on a plurality of third portions of the surface of the substrate, comprising: forming a first insulating layer on the surface of the substrate; forming a conductive layer on the first insulating layer; and The first insulating layer and the conductive layer are patterned.
4. The method according to claim 3, characterized in that Further including: A plurality of contacts are formed in the plurality of contact openings, including: forming the plurality of contact openings above the two conductive regions and the at least one source / drain region; forming a second insulating layer in the plurality of contact openings and on the conductive layer; Forming a plurality of openings above the two conductive regions and the at least one source / drain region, wherein the width of each of the openings is smaller than the width of each of the contact openings; and A plurality of conductive materials are filled in the plurality of openings.
5. The method according to claim 2, characterized in that: The at least one source / drain region is spaced apart from the conductive connection layer by a distance.
6. A semiconductor element, characterized in that: include: a substrate having a surface; Two conductive areas are disposed in the substrate; A conductive connection layer is disposed in the substrate and below the two conductive regions, wherein the conductive connection layer is electrically connected to the two conductive regions; a well region disposed in the substrate and located between the two conductive regions, wherein a bottom surface of the well region contacts a top surface of the conductive connection layer; and The source / drain region is disposed on the substrate between two adjacent channel regions and between the two conductive regions.
7. The semiconductor device according to claim 6, characterized in that Further including: A gate structure, disposed on the surface of the substrate and located above the two channel regions; as well as The source / drain contact is disposed on the source / drain region and connected to the gate structure, wherein the side surface of the source / drain contact is surrounded by an insulating layer, and the gate structure is surrounded by the insulating layer.
8. The semiconductor device according to claim 7, characterized in that Further including: Two conductive contacts are disposed on the two conductive regions and connected to the gate structure, wherein the bottom surfaces of the two conductive contacts are respectively in contact with the top surfaces of the two conductive regions, and the side surfaces of the two conductive contacts are respectively surrounded by the insulating layer.
9. The semiconductor device according to claim 6, characterized in that The bottom surface of the source / drain region is higher than the top surfaces of the two conductive regions.
10. The semiconductor device according to claim 6, characterized in that The doping concentration of the two conductive regions is different from the doping concentration of the well region.