Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention provides a solar cell, a preparation method thereof and a photovoltaic module. The solar cell comprises a silicon substrate which is provided with a front surface and a back surface which are oppositely arranged; the polycrystalline silicon buffer layer is arranged on the surface of the back surface and / or the front surface of the silicon substrate; the tunneling layer is arranged on one side, far away from the silicon substrate, of the polycrystalline silicon buffer layer; and the doped polycrystalline silicon layer is arranged on one side, far away from the silicon substrate, of the tunneling layer. The polycrystalline silicon buffer layer is arranged between the tunneling layer and the silicon substrate, so that diffusion of doped impurities to the silicon substrate can be effectively controlled, and recombination of photon-generated carriers can be reduced; the tunneling layer is protected from being broken to generate pinholes, and the good passivation performance of the tunneling layer is improved; therefore, the roughness of the surface of the silicon substrate is effectively reduced, that is, the polycrystalline silicon buffer layer can provide a smoother surface, the thickness uniformity of a subsequently deposited film layer is improved, and the performance of the film layer is further improved. In conclusion, the solar cell provided by the invention has better photoelectric conversion efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of batteries, and specifically, to solar cells, their preparation methods, and photovoltaic modules. Background Art

[0002] Currently, it is becoming increasingly difficult for mainstream TOPCon cells to meet future efficiency requirements. There is an urgent need for a high-efficiency cell structure to replace TOPCon cells. As a high-efficiency cell, the TBC cell is considered the next-generation mainstream technology. Currently, the preparation route of the TBC cell basically uses LPCVD (low-pressure chemical vapor deposition) plus diffusion to prepare polycrystalline silicon (poly-Si) thin films. However, there are still some problems with the current TBC cells, which are not conducive to improving the cell efficiency. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems in the related art to some extent. To this end, an object of the present invention is to provide a solar cell that can effectively reduce the recombination of photo-generated carriers (electrons and holes) and improve the cell efficiency.

[0004] In one aspect of the present invention, the present invention provides a solar cell. According to an embodiment of the present invention, the solar cell includes: a silicon substrate having a front surface and a back surface disposed opposite to each other; a polycrystalline silicon buffer layer disposed on the surface of the back surface and / or the front surface of the silicon substrate; a tunneling layer disposed on a side of the polycrystalline silicon buffer layer away from the silicon substrate; and a doped polycrystalline silicon layer disposed on a side of the tunneling layer away from the silicon substrate. Thus, by providing a polycrystalline silicon buffer layer between the tunneling layer and the silicon substrate, the diffusion of doped impurities into the silicon substrate can be effectively controlled, which helps to reduce the recombination of photo-generated carriers, especially significantly reduce Auger recombination; the setting of the polycrystalline silicon buffer layer can also protect the tunneling layer from breaking due to the deformation of the silicon substrate, thereby reducing recombination and improving the good passivation performance of the tunneling layer; the polycrystalline silicon buffer layer can effectively reduce the roughness of the surface of the silicon substrate, that is, the polycrystalline silicon buffer layer can provide a more flat surface, which is beneficial to improving the thickness uniformity of the tunneling layer and subsequent deposited film layers, and thus improving the performance of the film layers. In summary, the above solar cell of the present invention has better photoelectric conversion efficiency.

[0005] According to an embodiment of the present invention, the polycrystalline silicon buffer layer is an intrinsic polycrystalline silicon buffer layer or a doped polycrystalline silicon buffer layer, and the doping concentration is less than the doping concentration of the doped polycrystalline silicon layer.

[0006] According to an embodiment of the present invention, the thickness of the polycrystalline silicon buffer layer is 5-10 nm.

[0007] According to an embodiment of the present invention, the polysilicon buffer layer is disposed on the surface of the back side of the silicon substrate, and the surface of the front side is a textured surface; the doped polysilicon layer includes an n-type doped polysilicon layer and a p-type doped polysilicon layer, and the n-type doped polysilicon layer and the p-type doped polysilicon layer are respectively and alternately disposed on the surface of the tunneling layer away from the silicon substrate. The solar cell further includes: a first passivation layer disposed on the textured surface of the front side; a second passivation layer disposed on the side of the doped polysilicon layer away from the silicon substrate and on the surface of the silicon substrate in the gap between the n-type doped polysilicon layer and the p-type doped polysilicon layer; an antireflection film layer disposed on the side of the first passivation layer and the second passivation layer away from the silicon substrate; a first electrode and a second electrode located on the back side and electrically connected to the n-type doped polysilicon layer and the p-type doped polysilicon layer respectively.

[0008] According to an embodiment of the present invention, the thickness of the n-type doped polysilicon layer is 140 - 360 nm, and the doping concentration is in the range of 1×10 20 cm -3 -8×10 20 cm -3 ; the thickness of the p-type doped polysilicon layer is 200 - 360 nm, and the doping concentration is in the range of 1×10 19 cm -3 -8×10 19 cm -3 。

[0009] In another aspect of the present invention, the present invention provides a method for preparing the aforementioned solar cell. According to an embodiment of the present invention, the method for preparing a solar cell includes: depositing and forming an intrinsic polysilicon buffer layer on the back surface and / or the front surface of a silicon substrate; depositing and forming a tunneling layer on a side of the polysilicon buffer layer away from the silicon substrate; depositing and forming an intrinsic polysilicon layer on a side of the tunneling layer away from the silicon substrate; depositing and forming a heavily doped polysilicon layer on a side of the intrinsic polysilicon layer away from the silicon substrate; depositing and forming a lightly doped polysilicon layer on a side of the heavily doped polysilicon layer away from the silicon substrate; annealing the intrinsic polysilicon layer, the heavily doped polysilicon layer, and the lightly doped polysilicon layer to obtain a doped polysilicon layer. Thus, in the above preparation method, by forming an intrinsic polysilicon buffer layer between the tunneling layer and the silicon substrate, the diffusion of doped impurities into the silicon substrate can be effectively controlled, thereby helping to reduce the recombination of photo-generated carriers, especially significantly reducing Auger recombination; the setting of the intrinsic polysilicon buffer layer can also protect the tunneling layer from breaking due to the deformation of the silicon substrate, thereby reducing recombination and enhancing the good passivation performance of the tunneling layer; the intrinsic polysilicon buffer layer can effectively reduce the surface roughness of the silicon substrate, that is, the intrinsic polysilicon buffer layer can provide a flatter surface, which is beneficial to improving the thickness uniformity of the tunneling layer and subsequent deposited film layers, and further enhancing the performance of the film layers. In summary, the solar cell prepared by the method of the present invention has better photoelectric conversion efficiency.

[0010] According to an embodiment of the present invention, the conditions for depositing and forming the intrinsic polysilicon buffer layer satisfy at least one of the following: the deposition temperature is 400 - 500 °C; the pressure is 2000 - 3000 Pa; SiH 4 gas flow rate is 1000 - 3000 sccm, H 2 gas flow rate is 10000 - 15000 sccm; the radio frequency power supply power is 10000 W - 17000 W; the duty cycle is 0.05 - 0.1; the deposition thickness is 5 - 10 nm.

[0011] According to an embodiment of the present invention, the conditions for depositing and forming the tunneling layer satisfy at least one of the following: the deposition temperature is 500 - 550 °C; SiH 4 gas flow rate is 500 - 1500 sccm, N 2 O gas flow rate is 5000 - 10000 sccm; when n-type doping, the deposition thickness of the tunneling layer is 1.5 - 1.9 nm; when p-type doping, the deposition thickness of the tunneling layer is 1.9 - 2.5 nm.

[0012] According to an embodiment of the present invention, the conditions for depositing and forming the intrinsic polysilicon layer satisfy at least one of the following: the temperature is 400 - 550 °C; the pressure is 2000 - 3000 Pa; SiH 4The gas flow rate is 1000 - 3000 sccm, H 2 The gas flow rate is 10000 - 15000 sccm; the radio frequency power supply power is 10000 W - 17000 W; the duty cycle is 0.05 - 0.1; the deposition thickness is 20 - 40 nm,

[0013] The conditions for depositing and forming a heavily doped polysilicon layer satisfy at least one of the following: the temperature is 450 - 550 °C; the pressure is 2000 - 3000 Pa; when n-type doping, SiH 4 The gas flow rate is 1000 - 3000 sccm, H 2 The gas flow rate is 10000 - 15000 sccm, and the phosphine flow rate is 300 - 800 sccm; when p-type doping, SiH 4 The gas flow rate is 1000 - 3000 sccm, H 2 The gas flow rate is 5000 - 15000 sccm, and the diborane flow rate is 100 - 300 sccm; the radio frequency power supply power is 10000 W - 17000 W; the duty cycle is 0.05 - 0.1; the deposition thickness is 60 - 200 nm,

[0014] The conditions for depositing and forming a lightly doped polysilicon layer satisfy at least one of the following: the temperature is 450 - 550 °C; the pressure is 1000 - 2500 Pa; when n-type doping, SiH 4 The gas flow rate is 1000 - 3000 sccm, the phosphine flow rate is 100 - 400 sccm, H 2 The gas flow rate is 10000 - 15000 sccm; when p-type doping, SiH 4 The gas flow rate is 1000 - 3000 sccm, H 2 The gas flow rate is 5000 - 15000 sccm, and the diborane flow rate is 30 - 100 sccm; the radio frequency power supply power is 10000 W - 17000 W; the duty cycle is 0.05 - 0.1; the deposition thickness is 40 - 60 nm.

[0015] According to an embodiment of the present invention, the heavily doped polysilicon layer and the lightly doped polysilicon layer are n-type doped, and the temperature of the annealing treatment is 850 - 950 °C; the heavily doped polysilicon layer and the lightly doped polysilicon layer are p-type doped, and the temperature of the annealing treatment is 900 - 1030 °C.

[0016] According to an embodiment of the present invention, the methods for depositing and forming the intrinsic polysilicon buffer layer, the intrinsic polysilicon layer, the heavily doped polysilicon layer, and the lightly doped polysilicon layer all include plasma enhanced chemical vapor deposition.

[0017] In yet another aspect of the present invention, the present invention provides a photovoltaic module. According to an embodiment of the present invention, the photovoltaic module includes the solar cell described above. Thus, the photovoltaic module has good cell performance. Those skilled in the art can understand that the photovoltaic module has all the features and advantages of the solar cell described above, and will not be elaborated herein too much. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and be readily understood from the following description of embodiments in conjunction with the accompanying drawings, wherein:

[0019] Figure 1 is a schematic structural diagram of a solar cell in an embodiment of the present invention;

[0020] Figure 2 is a schematic structural diagram of a solar cell in another embodiment of the present invention;

[0021] Figure 3 is a schematic structural diagram of a solar cell in yet another embodiment of the present invention;

[0022] Figure 4 is a structural flowchart of preparing a solar cell in yet another embodiment of the present invention;

[0023] Figure 5 and Figure 6 is a structural flowchart of preparing a solar cell in yet another embodiment of the present invention;

[0024] Figure 7 is a schematic diagram of phosphorus doping of an n-type doped polysilicon layer, a polysilicon buffer layer and a silicon substrate in a corresponding region of the N region of the solar cell in Embodiment 1. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] The following will explain the solution of the present invention in conjunction with embodiments. Those skilled in the art will understand that the following embodiments are only used to illustrate the present invention and should not be construed as limiting the scope of the present invention. For those not specified in the embodiments regarding specific technologies or conditions, they shall be carried out according to the technologies or conditions described in the literature in the art or according to the product specifications. For reagents or instruments not specified by the manufacturer, they are all conventional products that can be obtained through commercial procurement.

[0026] The following describes the present invention with reference to specific embodiments. It should be noted that these embodiments are merely descriptive and do not limit the present invention in any way.

[0027] In one aspect of the present invention, the present invention provides a solar cell. According to an embodiment of the present invention, with reference to Figure 1, the solar cell includes: a silicon substrate 100 having a front surface and a back surface disposed opposite to each other; a polysilicon buffer layer 110 disposed on the surface of the back surface and / or the front surface of the silicon substrate 100( Figure 1 In Figure 1 , it is exemplified by being disposed on the back surface); a tunneling layer 120 disposed on a side of the polysilicon buffer layer 110 away from the silicon substrate 100; a doped polysilicon layer 130 disposed on a side of the tunneling layer 120 away from the silicon substrate 100. Thus, by disposing the polysilicon buffer layer 110 between the tunneling layer 120 and the silicon substrate 100, the diffusion of doped impurities into the silicon substrate 100 can be effectively controlled, thereby helping to reduce the recombination of photo-generated carriers, especially significantly reducing Auger recombination; the setting of the polysilicon buffer layer 110 can also protect the tunneling layer 120 from breaking due to the deformation of the silicon substrate 100, thereby reducing recombination and enhancing the good passivation performance of the tunneling layer; the polysilicon buffer layer 110 can effectively reduce the roughness of the surface of the silicon substrate 100, that is, the polysilicon buffer layer 110 can provide a flatter surface, which is beneficial to improving the thickness uniformity of the tunneling layer and subsequent deposited film layers, and thus enhancing the performance of the film layer. In summary, the above solar cell of the present invention has better photoelectric conversion efficiency.

[0028] Among them, due to the different thermal expansion coefficients of the silicon substrate and the tunneling layer (silicon oxide), annealing will cause stress deformation of the silicon oxide tunneling layer due to thermal expansion, thereby destroying the passivation performance of the tunneling layer. In the present invention, in the preparation process, during the annealing of the doped polysilicon layer, by introducing the polysilicon buffer layer 110, this structure can protect the tunneling layer from breaking and generating pinholes due to the deformation of the silicon substrate during annealing, thereby playing a role in protecting the tunneling layer.

[0029] According to some embodiments of the present invention, the conductivity type of the silicon substrate can be n-type or p-type, and those skilled in the art can flexibly select according to actual needs, and there is no limit requirement here.

[0030] According to some embodiments of the present invention, the polysilicon buffer layer is an intrinsic polysilicon buffer layer. In this way, the cost is relatively low, and the effect of preventing doped impurities from diffusing into the silicon substrate is better; moreover, during the annealing process to form the doped polysilicon layer, the coefficient of thermal expansion of the intrinsic polysilicon buffer layer is similar to that of the silicon substrate, which can well protect the tunneling layer and avoid the adverse phenomenon of stress deformation caused by thermal expansion. According to some other embodiments of the present invention, the polysilicon buffer layer is a doped polysilicon buffer layer, and the doping concentration is less than that of the doped polysilicon layer. When annealing to form the doped polysilicon layer, the doping elements therein further diffuse into the intrinsic polysilicon buffer layer, and then the buffer layer changes from the intrinsic polysilicon buffer layer to a lightly doped polysilicon buffer layer. In this way, a high-low junction is formed by the internal diffusion of the doped polysilicon buffer layer and the silicon substrate, making the transmission of photo-generated carriers in the battery more efficient, reducing the recombination of carriers during the transmission process, thereby improving the collection efficiency of carriers, and further increasing the short-circuit current of the battery.

[0031] According to some embodiments of the present invention, the thickness of the polysilicon buffer layer is 5 - 10 nm, such as 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc. The polysilicon buffer layer with the above thickness can effectively control the diffusion of doped elements into the silicon substrate and effectively protect the tunneling layer from being damaged.

[0032] According to some embodiments of the present invention, when the doped polysilicon layer is an n-type doped polysilicon layer, the thickness of the tunneling layer is 1.5 - 1.9 nm; according to some other embodiments of the present invention, when the doped polysilicon layer is a p-type doped polysilicon layer, the thickness of the tunneling layer is 1.9 - 2.5 nm.

[0033] According to some embodiments of the present invention, when the doped polysilicon layer is an n-type doped polysilicon layer, the thickness of the n-type doped polysilicon layer is 140 - 360 nm (such as 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, 300 nm, 310 nm, 320 nm, 330 nm, 340 nm, 350 nm, 360 nm, etc.), and the doping concentration is 1×10 20 cm -3 -8×10 20 cm -3 (such as 1×10 20 cm -3 、2×10 20 cm -3 、3×10 20 cm -3 、4×10 20 cm -3, 5×10 20 cm -3 , 6×10 20 cm -3 , 7×10 20 cm -3 , 8×10 20 cm -3 etc.). Thus, the n-type doped polysilicon layer with the above thickness and doping concentration has good carrier transport ability, improves the carrier collection efficiency, and increases the fill factor and short-circuit current of the battery.

[0034] According to some other embodiments of the present invention, when the doped polysilicon layer is a p-type doped polysilicon layer, the thickness of the p-type doped polysilicon layer is 200 - 360 nm (such as 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, 300 nm, 310 nm, 320 nm, 330 nm, 340 nm, 350 nm, 360 nm, etc.), and the doping concentration is between 1×10 19 cm -3 - 8×10 19 cm -3 (such as 1×10 19 cm -3 , 2×10 19 cm -3 , 3×10 19 cm -3 , 4×10 19 cm -3 , 5×10 19 cm -3 , 6×10 19 cm -3 , 7×10 19 cm -3 , 8×10 19 cm -3 etc.). Thus, the p-type doped polysilicon layer with the above thickness and doping concentration has good carrier transport ability, improves the carrier collection efficiency, and increases the fill factor and short-circuit current of the battery.

[0035] According to some embodiments of the present invention, the solar cell is a TBC cell, a TOPCon cell, or a stacked cell containing a TBC cell or a TOPCon cell.

[0036] According to some embodiments of the present invention, when the solar cell is a TBC cell, the structure of setting a polysilicon buffer layer between the tunneling layer and the silicon substrate can be set only in the N region, or only in the P region, or can be set in both the N region and the P region at the same time. Taking the structure of setting a polysilicon buffer layer in both the N region and the P region at the same time as an example, refer toFigure 2 , the structure of the TBC battery is as follows:

[0037] The polysilicon buffer layer 110 is disposed on the surface of the back side of the silicon substrate 100, and the surface of the front side is a textured surface; the doped polysilicon layer 130 includes an n-type doped polysilicon layer 131 and a p-type doped polysilicon layer 132, and the n-type doped polysilicon layer 131 and the p-type doped polysilicon layer 132 are respectively and spacedly disposed on the surface of the tunneling layer 120 away from the silicon substrate 100. The solar cell further includes: a first passivation layer 141 disposed on the textured surface of the front side; a second passivation layer 142 disposed on the side of the doped polysilicon layer 130 away from the silicon substrate 100 and on the surface of the silicon substrate 100 in the gap between the n-type doped polysilicon layer 131 and the p-type doped polysilicon layer 132; an antireflection film layer 150 disposed on the sides of the first passivation layer 141 and the second passivation layer 142 away from the silicon substrate 100; a first electrode 161 and a second electrode 162, the first electrode 161 and the second electrode 162 are located on the back side and are respectively electrically connected to the n-type doped polysilicon layer 131 and the p-type doped polysilicon layer 132.

[0038] According to some embodiments of the present invention, the solar cell is a TOPCon cell. Referring to Figure 3 , the structure of the TOPCon cell is as follows: The silicon substrate 100 has a front side and a back side that are oppositely disposed, and the surface of the front side is a textured surface; a polysilicon buffer layer 110, a tunneling layer 120, an n-type doped polysilicon layer 133, a second passivation layer 142, and a back electrode 163 are sequentially disposed on the back side; a p-type doped emitter electrode 134, a first passivation layer 141, an antireflection film layer 150, and a front electrode 164 are sequentially disposed on the front side.

[0039] According to some embodiments of the present invention, the materials of the first passivation layer and the second passivation layer include, but are not limited to, alumina, which has good passivation performance and helps to improve the cell performance.

[0040] According to some embodiments of the present invention, the materials of the antireflection film layer include, but are not limited to, materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., which have good antireflection effects and help to improve the light absorption efficiency of the cell.

[0041] According to some embodiments of the present invention, the specific materials of the first electrode and the second electrode include, but are not limited to, conductive materials such as silver and copper.

[0042] According to an embodiment of the present invention, on the other hand of the present invention, the present invention provides a method for manufacturing the foregoing solar cell. According to an embodiment of the present invention, referring to Figure 4 , the method for manufacturing a solar cell includes:

[0043] S100: Deposit and form an intrinsic polysilicon buffer layer 101 on the surface of the back side and / or the front side ( Figure 4 taking only the back side as an example herein) of the silicon substrate 100.

[0044] According to some embodiments of the present invention, the intrinsic polysilicon buffer layer is deposited and formed by plasma enhanced chemical vapor deposition (PECVD). The process duration of this deposition method is short, which can effectively improve the preparation efficiency.

[0045] According to some embodiments of the present invention, the deposition temperature is 400 - 500 °C, such as 400 °C, 410 °C, 420 °C, 430 °C, 440 °C, 450 °C, 460 °C, 470 °C, 480 °C, 490 °C, 500 °C, etc.; the pressure is 2000 - 3000 Pa, such as 2000 Pa, 2100 Pa, 2200 Pa, 2300 Pa, 2400 Pa, 2500 Pa, 2600 Pa, 2700 Pa, 2800 Pa, 2900 Pa, 3000 Pa, etc.; the flow rate of SiH 4 gas is 1000 - 3000 sccm, such as 1000 sccm, 1200 sccm, 1500 sccm, 1800 sccm, 2000 sccm, 2200 sccm, 2500 sccm, 2800 sccm, 3000 sccm, etc., and the flow rate of H 2 gas is 10000 - 15000 sccm, such as 10000 sccm, 11000 sccm, 12000 sccm, 13000 sccm, 14000 sccm, 15000 sccm, etc.; the power of the radio frequency power supply is 10000 W - 17000 W, such as 1000 W, 11000 W, 12000 W, 13000 W, 14000 W, 15000 W, 16000 W, 17000 W, etc.; the duty cycle is 0.05 - 0.1, such as 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, etc.; the deposition thickness is 5 - 10 nm, such as 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc. Thus, under the above conditions, an intrinsic polysilicon buffer layer with a relatively high carrier transport efficiency can be deposited, and the diffusion of doping elements into the silicon substrate can be effectively prevented or alleviated, and the subsequent formed tunneling layer can be well protected, which helps to improve the uniformity of the film surface.

[0046] S200: Deposit and form a tunneling layer 120 on the side of the intrinsic polysilicon buffer layer 101 away from the silicon substrate.

[0047] According to some embodiments of the present invention, the tunneling layer is deposited and formed by plasma enhanced chemical vapor deposition (PECVD). The process duration of this deposition method is short, which can effectively improve the preparation efficiency.

[0048] According to some embodiments of the present invention, the tunneling layer is formed by deposition, and the deposition temperature is 500 - 550 °C, such as 500 °C, 510 °C, 520 °C, 530 °C, 540 °C, 550 °C, etc.; SiH 4 The gas flow rate is 500 - 1500 sccm, such as 500 sccm, 600 sccm, 700 sccm, 800 sccm, 900 sccm, 1100 sccm, 1200 sccm, 1300 sccm, 1400 sccm, 1500 sccm, etc., and the N 2 The gas flow rate of O is 5000 - 10000 sccm, such as 5000 sccm, 6000 sccm, 7000 sccm, 8000 sccm, 9000 sccm, 10000 sccm, etc.; when n-type doping, the deposition thickness of the tunneling layer is 1.5 - 1.9 nm, such as a thickness of 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm; when p-type doping, the deposition thickness of the tunneling layer is 1.9 - 2.5 nm, such as a thickness of 1.9 nm, 2.0 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm. Thus, the tunneling layer formed under the above conditions has a good passivation effect and reduces the recombination loss of carriers, thereby improving the photoelectric conversion efficiency of the solar cell.

[0049] S300: Deposit and form an intrinsic polysilicon layer 1301 on the side of the tunneling layer 120 away from the silicon substrate 100.

[0050] According to some embodiments of the present invention, the intrinsic polysilicon layer is formed by plasma enhanced chemical vapor deposition (PECVD). The process duration of this deposition method is short, which can effectively improve the preparation efficiency.

[0051] According to some embodiments of the present invention, when depositing and forming the intrinsic polysilicon layer 1301, the deposition temperature is 400 - 550 °C, such as 400 °C, 410 °C, 420 °C, 430 °C, 440 °C, 450 °C, 460 °C, 470 °C, 480 °C, 490 °C, 500 °C, 510 °C, 520 °C, 530 °C, 540 °C, 550 °C, etc.; the pressure is 2000 - 3000 Pa, such as 2000 Pa, 2100 Pa, 2200 Pa, 2300 Pa, 2400 Pa, 2500 Pa, 2600 Pa, 2700 Pa, 2800 Pa, 2900 Pa, 3000 Pa, etc.; SiH 4The gas flow rate is 1000 - 3000 sccm, such as 1000 sccm, 1200 sccm, 1500 sccm, 1800 sccm, 2000 sccm, 2200 sccm, 2500 sccm, 2800 sccm, 3000 sccm, etc., H 2 The gas flow rate is 10000 - 15000 sccm, such as 10000 sccm, 11000 sccm, 12000 sccm, 13000 sccm, 14000 sccm, 15000 sccm, etc.; the power of the radio frequency power supply is 10000 W - 17000 W, such as 1000 W, 11000 W, 12000 W, 13000 W, 14000 W, 15000 W, 16000 W, 17000 W, etc.; the duty cycle is 0.05 - 0.1, such as 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, etc.; the deposition thickness is 20 - 40 nm, such as 20 nm, 22 nm, 25 nm, 30 nm, 33 nm, 35 nm, 38 nm, 40 nm, etc. Thus, under the above conditions, an intrinsic polysilicon layer with a higher carrier transport efficiency can be deposited.

[0052] S400: Deposit and form a heavily doped polysilicon layer 1302 on the side of the intrinsic polysilicon layer 1301 away from the silicon substrate.

[0053] According to some embodiments of the present invention, a heavily doped polysilicon layer 1302 is deposited and formed by plasma enhanced chemical vapor deposition (PECVD). The process duration of this deposition method is short, which can effectively improve the preparation efficiency; moreover, this deposition method is an in-situ doping to form a heavily doped polysilicon layer, so that the doping concentration can be better controlled.

[0054] According to some embodiments of the present invention, when depositing and forming a heavily doped polysilicon layer, the deposition temperature is 450 - 550 °C, such as 450 °C, 460 °C, 470 °C, 480 °C, 490 °C, 500 °C, 510 °C, 520 °C, 530 °C, 540 °C, 550 °C, etc.; the pressure is 2000 - 3000 Pa, such as 2000 Pa, 2100 Pa, 2200 Pa, 2300 Pa, 2400 Pa, 2500 Pa, 2600 Pa, 2700 Pa, 2800 Pa, 2900 Pa, 3000 Pa, etc.; when n-type doping, SiH 4 The gas flow rate is 1000 - 3000 sccm (such as 1000 sccm, 1200 sccm, 1500 sccm, 1800 sccm, 2000 sccm, 2200 sccm, 2500 sccm, 2800 sccm, 3000 sccm, etc.), H 2The gas flow rate is 10000 - 15000 sccm (such as 10000 sccm, 11000 sccm, 12000 sccm, 13000 sccm, 14000 sccm, 15000 sccm, etc.), and the phosphine flow rate is 300 - 800 sccm (such as 300 sccm, 400 sccm, 500 sccm, 600 sccm, 700 sccm, 800 sccm, etc.); during p-type doping, SiH 4 The gas flow rate is 1000 - 3000 sccm (such as 1000 sccm, 1200 sccm, 1500 sccm, 1800 sccm, 2000 sccm, 2200 sccm, 2500 sccm, 2800 sccm, 3000 sccm, etc.), H 2 The gas flow rate is 5000 - 15000 sccm (such as 5000 ccm, 7000 sccm, 9000 sccm, 11000 sccm, 13000 sccm, 15000 sccm, etc.), and the borane flow rate is 100 - 300 sccm (such as 100 sccm, 150 sccm, 200 sccm, 250 sccm, 300 sccm, etc.). Among them, the borane is diluted with hydrogen, and the proportion of borane is 1% - 5%; the power of the radio frequency power supply is 10000 W - 17000 W, such as 1000 W, 11000 W, 12000 W, 13000 W, 14000 W, 15000 W, 16000 W, 17000 W, etc.; the duty cycle is 0.05 - 0.1, such as 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, etc.; the deposition thickness is 60 - 200 nm, such as 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 120 nm, 150 nm, 200 nm, etc. Thus, under the above conditions, a heavily doped polysilicon layer with a relatively high carrier transport efficiency can be deposited.

[0055] S500: A lightly doped polysilicon layer 1303 is deposited and formed on the side of the heavily doped polysilicon layer 1302 away from the silicon substrate.

[0056] According to some embodiments of the present invention, the lightly doped polysilicon layer 1303 is deposited and formed by plasma enhanced chemical vapor deposition (PECVD). The process duration of this deposition method is relatively short, which can effectively improve the preparation efficiency; moreover, this deposition method is an in-situ doping to form the lightly doped polysilicon layer 1303, so that the doping concentration can be better controlled.

[0057] According to some embodiments of the present invention, when depositing and forming the lightly doped polysilicon layer 1303, the deposition temperature is 450 - 550 °C, such as 450 °C, 460 °C, 470 °C, 480 °C, 490 °C, 500 °C, 510 °C, 520 °C, 530 °C, 540 °C, 550 °C, etc.; the pressure is 1000 - 2500 Pa, such as 1000 Pa, 1200 Pa, 1400 Pa, 1500 Pa, 1600 Pa, 1800 Pa, 2200 Pa, 2100 Pa, 2200 Pa, 2300 Pa, 2400 Pa, etc.; when n-type doping, the SiH 4 gas flow rate is 1000 - 3000 sccm (such as 1000 sccm, 1200 sccm, 1500 sccm, 1800 sccm, 2000 sccm, 2200 sccm, 2500 sccm, 2800 sccm, 3000 sccm, etc.), the phosphine flow rate is 100 - 400 sccm (such as 100 sccm, 150 sccm, 200 sccm, 250 sccm, 300 sccm, 350 sccm, 400 sccm, etc.), and the H 2 gas flow rate is 10000 - 15000 sccm (such as 10000 sccm, 11000 sccm, 12000 sccm, 13000 sccm, 14000 sccm, 15000 sccm, etc.); when p-type doping, the SiH 4 gas flow rate is 1000 - 3000 sccm (such as 1000 sccm, 1200 sccm, 1500 sccm, 1800 sccm, 2000 sccm, 2200 sccm, 2500 sccm, 2800 sccm, 3000 sccm, etc.), and the H 2The gas flow rate is 5000 - 15000 sccm (such as 5000 sccm, 7000 sccm, 9000 sccm, 11000 sccm, 13000 sccm, 15000 sccm, etc.), the borane flow rate is 30 - 100 sccm (such as 30 sccm, 40 sccm, 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm, 100 sccm, etc.). Among them, the borane is diluted with hydrogen, and the proportion of borane is 1% - 5%; the power of the radio frequency power supply is 10000 W - 17000 W, such as 1000 W, 11000 W, 12000 W, 13000 W, 14000 W, 15000 W, 16000 W, 17000 W, etc.; the duty cycle is 0.05 - 0.1, such as 0.05, 0.06, 0.07, 0.08, 0.09, 0.1, etc.; the deposition thickness is 40 - 60 nm, such as 40 nm, 42 nm, 45 nm, 50 nm, 53 nm, 55 nm, 58 nm, 60 nm, etc. Thus, under the above conditions, a lightly doped polysilicon layer with a relatively high carrier transport efficiency can be deposited.

[0058] S600: Anneal the intrinsic polysilicon layer 1301, the heavily doped polysilicon layer 1302 and the lightly doped polysilicon layer 1302 to obtain a doped polysilicon layer 130. During the annealing process, the doped impurities in the heavily doped polysilicon layer diffuse into the intrinsic polysilicon layer, or the doped impurities in the heavily doped polysilicon layer and the lightly doped polysilicon layer re - diffuse in the intrinsic polysilicon buffer layer, the heavily doped polysilicon layer and the lightly doped polysilicon layer, to obtain a doped layer with a relatively uniform doping concentration in the intrinsic polysilicon layer, the heavily doped polysilicon layer and the lightly doped polysilicon layer, that is, after annealing, the intrinsic polysilicon layer, the heavily doped polysilicon layer and the lightly doped polysilicon layer form a doped polysilicon layer 130 with uniform doping. By using this method to prepare the doped polysilicon layer, the doping concentration can be well controlled; compared with directly preparing the doped polysilicon layer by PECVD doping, this method can further control the diffusion of doped impurities into the silicon substrate, further reduce recombination, and improve the cell performance.

[0059] According to some embodiments of the present invention, the heavily doped polysilicon layer and the lightly doped polysilicon layer are n-type doped, and the temperature of the annealing treatment is 850 - 950 °C, such as 850 °C, 860 °C, 870 °C, 880 °C, 890 °C, 900 °C, 910 °C, 920 °C, 930 °C, 940 °C, 950 °C, etc.; according to other embodiments of the present invention, the heavily doped polysilicon layer and the lightly doped polysilicon layer are p-type doped, and the temperature of the annealing treatment is 900 - 1030 °C, such as 900 °C, 910 °C, 920 °C, 930 °C, 940 °C, 950 °C, 960 °C, 970 °C, 980 °C, 990 °C, 1000 °C, 1010 °C, 1020 °C, 1030 °C, etc. Annealing under the above conditions helps to obtain a more uniformly doped polysilicon layer 130.

[0060] According to the embodiments of the present invention, the above preparation method of the present invention has at least the following technical effects:

[0061] By forming an intrinsic polysilicon buffer layer between the tunneling layer and the silicon substrate, the diffusion of doped impurities into the silicon substrate can be effectively controlled, thereby helping to reduce the recombination of photo-generated carriers, especially significantly reducing Auger recombination;

[0062] The formation of the intrinsic polysilicon buffer layer 101, together with the intrinsic polysilicon layer 1301, forms a sandwich structure for the tunneling layer. During the annealing process, this structure can well protect the tunneling layer from breaking due to the deformation of the silicon substrate, thereby reducing recombination and enhancing the good passivation performance of the tunneling layer;

[0063] After the annealing treatment, the intrinsic polysilicon buffer layer 101 is called the polysilicon buffer layer 110. When annealing, the doping elements in the heavily doped polysilicon layer and the lightly doped polysilicon layer do not diffuse into the intrinsic polysilicon buffer layer 101, and the polysilicon buffer layer 110 after annealing is still the intrinsic polysilicon buffer layer; when annealing, the doping elements in the heavily doped polysilicon layer and the lightly doped polysilicon layer will diffuse into the intrinsic polysilicon buffer layer 101, making the intrinsic polysilicon buffer layer 101 form a doped polysilicon buffer layer after annealing. In this way, the doped polysilicon buffer layer and the internal diffusion of the silicon substrate form a high-low junction, making the transmission of photo-generated carriers in the battery more efficient, reducing the recombination of carriers during transmission, thereby improving the collection efficiency of carriers, and further increasing the short-circuit current of the battery;

[0064] The intrinsic polysilicon buffer layer can effectively reduce the surface roughness of the silicon substrate, that is, the intrinsic polysilicon buffer layer can provide a flatter surface, which is beneficial to improving the thickness uniformity of the tunneling layer and subsequent deposited film layers, and further enhancing the performance of the film layer.

[0065] In summary, the solar cell prepared by the above method of the present invention has better photoelectric conversion efficiency.

[0066] According to some embodiments of the present invention, the above method for preparing a solar cell can be used to prepare a TBC cell, a TOPCon cell, or a tandem cell containing a TBC cell or a TOPCon cell. Taking the preparation of a TBC cell as an example, and with reference to Figure 5 、 Figure 6 , the method steps for preparing a TBC cell are described in detail as follows:

[0067] T10: Provide an n-type silicon substrate 100, polish the silicon substrate to remove mechanical damage, and divide the back surface into an N region and a P region.

[0068] T20: Deposit an intrinsic polysilicon buffer layer 101 on the back surface of the silicon substrate 100 by PECVD. Among them, the deposition temperature is 400 - 500 °C; the pressure is 2000 - 3000 Pa; the flow rate of SiH 4 gas is 1000 - 3000 sccm, and the flow rate of H 2 gas is 10000 - 15000 sccm; the power of the radio frequency power supply is 10000 W - 17000 W; the duty cycle is 0.05 - 0.1; the deposition thickness is 5 - 10 nm.

[0069] T30: Deposit a P-region tunneling layer 122 on the back surface of the silicon substrate 100 by PECVD. Among them, the deposition temperature is 500 - 550 °C; the flow rate of SiH 4 gas is 500 - 1500 sccm, and the flow rate of N 2 O gas is 5000 - 10000 sccm; the deposition thickness of the P-region tunneling layer is 1.9 - 2.5 nm.

[0070] T40: Deposit and form a first intrinsic polysilicon layer 13011 on the side of the P-region tunneling layer 122 away from the silicon substrate 100 by PECVD. Among them, the deposition temperature is 400 - 550 °C; the pressure is 2000 - 3000 Pa; the flow rate of SiH 4 gas is 1000 - 3000 sccm, and the flow rate of H 2 gas is 10000 - 15000 sccm; the power of the radio frequency power supply is 10000 W - 17000 W; the duty cycle is 0.05 - 0.1; the deposition thickness is 20 - 40 nm.

[0071] T50: Deposit and form a p-type heavily doped polysilicon layer 13021 on the side of the first intrinsic polysilicon layer 13011 away from the silicon substrate 100 by PECVD. Among them, the deposition temperature is 450 - 550 °C; the pressure is 2000 - 3000 Pa; the flow rate of SiH 4 gas is 1000 - 3000 sccm, and the flow rate of H 2The gas flow rate is 5000 - 15000 sccm, and the borane flow rate is 100 - 300 sccm. Among them, borane is diluted with H 2 and the proportion of borane is 1%; the power of the radio frequency power supply is 10000W - 17000W; the duty cycle is 0.05 - 0.1; the deposition thickness is 60 - 200 nm.

[0072] T60: A p-type lightly doped polysilicon layer 13031 is deposited on the side of the p-type heavily doped polysilicon layer 13021 away from the silicon substrate 100 by PECVD. Among them, the deposition temperature is 450 - 550 °C; the pressure is 1000 - 2500 Pa; the SiH 4 gas flow rate is 1000 - 3000 sccm, and the H 2 gas flow rate is 5000 - 15000 sccm, the borane flow rate is 30 - 100 sccm, and borane is diluted with H 2 and the proportion of borane is 1%; the power of the radio frequency power supply is 10000W - 17000W; the duty cycle is 0.05 - 0.1; the deposition thickness is 40 - 60 nm.

[0073] T70: A first mask 10 is deposited on the side of the p-type lightly doped polysilicon layer 13031 away from the silicon substrate 100 by PECVD. In some embodiments, the first mask 10 can be a silicon oxide mask, the deposition temperature is 500 - 550 °C, and the SiH 4 gas flow rate is 500 - 1500 sccm, and the N 2 O gas flow rate is 5000 - 10000 sccm, and the deposition thickness is 40 - 70 nm.

[0074] T80: The first intrinsic polysilicon layer 13011, the p-type heavily doped polysilicon layer 13021, and the p-type lightly doped polysilicon layer 13031 are annealed at 900 - 1030 °C to obtain a p-type doped polysilicon layer 132.

[0075] T90: Using the laser etching method, the first mask 10 is patterned to retain only the first mask 10 structure in the P region, and the first mask structure in other regions is removed; then, the p-type doped polysilicon layer 132, the P region tunneling layer 122, and the polysilicon buffer layer 110 in the N region and the Gap region between the N region and the P region are etched away, and only the p-type doped polysilicon layer 132, the P region tunneling layer 122, and the corresponding polysilicon buffer layer 110 and other structures in the P region are retained.

[0076] T100: Deposit an intrinsic polysilicon buffer layer 101, an N-region tunneling layer 121, and a second intrinsic polysilicon layer 13012 on the back surface in sequence by PECVD method. Among them, the deposition conditions of the intrinsic polysilicon buffer layer 101 are the same as those in step T20; the deposition conditions of the N-region tunneling layer are basically the same as those of the P-region tunneling layer, except that the thickness of the N-region tunneling layer 121 is 1.5 - 1.9 nm; the deposition temperature of the second intrinsic polysilicon layer 13012 is 400 - 550 °C, the pressure is 2000 - 3000 Pa, and the SiH 4 gas flow rate is 1000 - 3000 sccm, and the H 2 gas flow rate is 10000 - 15000 sccm, the radio frequency power supply power is 10000 W - 17000 W, the duty cycle is 0.05 - 0.1, and the deposition thickness is 20 - 40 nm.

[0077] T110: Deposit an n-type heavily doped polysilicon layer 13022 on the side of the second intrinsic polysilicon layer 13012 far from the silicon substrate 100 by PECVD method. Among them, the deposition temperature is 450 - 550 °C; the pressure is 2000 - 3000 Pa; the SiH 4 gas flow rate is 1000 - 3000 sccm, and the H 2 gas flow rate is 10000 - 15000 sccm, the phosphine flow rate is 300 - 800 sccm; the radio frequency power supply power is 10000 W - 17000 W; the duty cycle is 0.05 - 0.1; the deposition thickness is 60 - 200 nm.

[0078] T120: Deposit an n-type lightly doped polysilicon layer 13031 on the side of the n-type heavily doped polysilicon layer 13022 far from the silicon substrate 100 by PECVD method. Among them, the deposition temperature is 450 - 550 °C; the pressure is 1000 - 2500 Pa; the SiH 4 gas flow rate is 1000 - 3000 sccm, and the H 2 gas flow rate is 10000 - 15000 sccm, the phosphine flow rate is 100 - 400 sccm; the radio frequency power supply power is 10000 W - 17000 W; the duty cycle is 0.05 - 0.1; the deposition thickness is 40 - 60 nm.

[0079] T130: Deposit a second mask 20 on the side of the n-type lightly doped polysilicon layer 13031 far from the silicon substrate 100 by PECVD method. In some embodiments, the second mask 10 can be a silicon oxide mask, the deposition temperature is 500 - 550 °C, and the SiH 4 gas flow rate is 500 - 1500 sccm, and the N 2 O gas flow rate is 5000 - 10000 sccm, and the deposition thickness is 40 - 70 nm.

[0080] T140: Anneal the second intrinsic polysilicon layer 13012, n-type heavily doped polysilicon layer 13022, and n-type lightly doped polysilicon layer 13032 at 850 - 950 °C to obtain the n-type doped polysilicon layer 131.

[0081] T150: Use laser etching to pattern the second mask 20, leaving only the second mask structure in the N region and removing the second mask structures in other regions.

[0082] T160: Texture the gaps between the front, back P regions, and N regions to obtain a textured surface. At the same time, remove the n-type doped polysilicon layer 131, N region tunneling layer 121, and polysilicon buffer layer 110 in the P region and the gap region, leaving only the n-type doped polysilicon layer 131, N region tunneling layer 121, and corresponding polysilicon buffer layer 110 and other structures in the N region.

[0083] T170: Remove the first mask 10 and the second mask 20 in the back P region and N region.

[0084] T180: Deposit an alumina layer on the front and back using atomic layer deposition (ALD). The alumina layer on the front forms the first passivation layer 141.

[0085] T190: Deposit a silicon nitride layer on the front and back. The silicon nitride layer on the front forms the antireflection film layer 150, and the alumina layer and silicon nitride layer on the back form the second passivation layer 142 on the back.

[0086] T200: Form a first electrode 161 and a second electrode 162 on the back N region and P region respectively by screen printing to obtain the TBC cell, as Figure 2 shown.

[0087] In another aspect of the present invention, the present invention provides a photovoltaic module. According to an embodiment of the present invention, the photovoltaic module includes the solar cell described above. Thus, the photovoltaic module has good cell performance. Those skilled in the art can understand that the photovoltaic module has all the features and advantages of the solar cell described above, and will not be elaborated here too much.

[0088] Example

[0089] Example 1

[0090] Method steps for preparing the TBC cell:

[0091] T10: Provide an n-type silicon substrate, polish the silicon substrate to remove mechanical damage, and divide the N region and P region on the back. The thickness of the silicon substrate is 150 μm.

[0092] T20: Deposit an intrinsic polysilicon buffer layer on the back side of the silicon substrate 100 by PECVD method. Among them, the deposition temperature is 450 °C, the pressure is 2500 Pa, the flow rate of SiH 4 gas is 2200 sccm, and the flow rate of H 2 gas is 12000 sccm; the power of the radio frequency power supply is 13500 W, the duty cycle is 0.07, and the deposition thickness is 8 nm.

[0093] T30: Deposit a P-region tunneling layer on the back side of the silicon substrate by PECVD method. Among them, the deposition temperature is 520 °C, the flow rate of SiH 4 gas is 900 sccm, and the flow rate of N 2 O gas is 8000 sccm; the deposition thickness of the P-region tunneling layer is 2.2 nm.

[0094] T40: Deposit and form a first intrinsic polysilicon layer on the side of the P-region tunneling layer away from the silicon substrate by PECVD method. Among them, the deposition temperature is 500 °C, the pressure is 2500 Pa, the flow rate of SiH 4 gas is 2000 sccm, and the flow rate of H 2 gas is 12000 sccm; the power of the radio frequency power supply is 14000 W, the duty cycle is 0.072, and the deposition thickness is 30 nm.

[0095] T50: Deposit and form a p-type heavily doped polysilicon layer on the side of the first intrinsic polysilicon layer away from the silicon substrate by PECVD method. Among them, the deposition temperature is 500 °C, the pressure is 2500 Pa, the flow rate of SiH 4 gas is 2000 sccm, and the flow rate of H 2 gas is 13000 sccm, the flow rate of borane is 150 sccm, and the borane is diluted with H 2 and the proportion of borane is 1%; the power of the radio frequency power supply is 14000 W, the duty cycle is 0.07, and the deposition thickness is 120 nm.

[0096] T60: Deposit and form a p-type lightly doped polysilicon layer on the side of the p-type heavily doped polysilicon layer away from the silicon substrate by PECVD method. Among them, the deposition temperature is 500 °C, the pressure is 2000 Pa, the flow rate of SiH 4 gas is 2000 sccm, and the flow rate of H 2 gas is 13000 sccm, the flow rate of borane is 50 sccm, and the borane is diluted with H 2 and the proportion of borane is 1%; the power of the radio frequency power supply is 14000 W, the duty cycle is 0.07, and the deposition thickness is 50 nm.

[0097] T70: Deposit and form a first silicon oxide mask on the side of the p-type lightly doped polysilicon layer away from the silicon substrate by PECVD method. Among them, the deposition temperature is 500 °C, SiH 4 gas flow rate is 1000 sccm, N 2 O gas flow rate is 7000 sccm, and the deposition thickness is 50 nm.

[0098] T80: Anneal the first intrinsic polysilicon layer, p-type heavily doped polysilicon layer and p-type lightly doped polysilicon layer at 980 °C to obtain a p-type doped polysilicon layer.

[0099] T90: Use the laser etching method to pattern the first silicon oxide mask, only retain the first mask structure in the P region, and remove the first mask structure in other regions; then etch and remove the p-type doped polysilicon layer, P region tunneling layer and polysilicon buffer layer between the N region and the P region, only retain the p-type doped polysilicon layer, P region tunneling layer and corresponding polysilicon buffer layer and other structures in the P region.

[0100] T100: Deposit and form an intrinsic polysilicon buffer layer, N region tunneling layer and second intrinsic polysilicon layer on the back in sequence by PECVD method. Among them, the deposition conditions of the intrinsic polysilicon buffer layer in this step are the same as those in step T20; the deposition conditions of the N region tunneling layer are basically the same as those of the P region tunneling layer, the difference is that the thickness of the N region tunneling layer is 1.75 nm; the deposition temperature of the second intrinsic polysilicon layer is 500 °C; the pressure is 2500 Pa; SiH 4 gas flow rate is 2000 sccm, H 2 gas flow rate is 13000 sccm; the radio frequency power supply power is 14000 W; the duty cycle is 0.072; the deposition thickness is 30 nm.

[0101] T110: Deposit and form an n-type heavily doped polysilicon layer on the side of the second intrinsic polysilicon layer away from the silicon substrate 100 by PECVD method. Among them, the deposition temperature is 500 °C; the pressure is 2500 Pa; SiH 4 gas flow rate is 2000 sccm, H 2 gas flow rate is 13000 sccm, and the phosphine flow rate is 550 sccm; the radio frequency power supply power is 14000 W; the duty cycle is 0.07; the deposition thickness is 120 nm.

[0102] T120: Deposit and form an n-type lightly doped polysilicon layer on the side of the n-type heavily doped polysilicon layer away from the silicon substrate 100 by PECVD method. Among them, the deposition temperature is 500 °C; the pressure is 1900 Pa; SiH 4 gas flow rate is 2000 sccm, H 2The gas flow rate is 12000sccm, the phosphine flow rate is 250sccm; the RF power supply power is 14000W; the duty cycle is 0.07; and the deposition thickness is 50nm.

[0103] T130: A second silicon oxide mask is formed by depositing the n-type lightly doped polysilicon layer on the side away from the silicon substrate 100 using a PECVD method. The deposition temperature is 500°C, and the SiH 4 The gas flow rate is 1000 sccm, N 2 The O gas flow rate was 7000 sccm and the deposition thickness was 50 nm.

[0104] T140: annealing the second intrinsic polysilicon layer, the n-type heavily doped polysilicon layer and the n-type lightly doped polysilicon layer at 900° C. to obtain an n-type doped polysilicon layer.

[0105] T150: The second silicon oxide mask is patterned by laser etching, and only the second silicon oxide mask structure in the N region is retained, and the second silicon oxide mask structure in other regions is removed.

[0106] T160: The gaps between the P and N regions on the front and back sides are textured to obtain a textured surface. At the same time, the n-type doped polysilicon layer, the N-region tunneling layer, and the polysilicon buffer layer in the P region and the gap region are removed, leaving only the n-type doped polysilicon layer, the N-region tunneling layer, and the polysilicon buffer layer in the N region.

[0107] T170: Remove the first silicon oxide mask and the second silicon oxide mask on the back P region and N region.

[0108] T180: Atomic layer deposition is used to deposit aluminum oxide layers on the front and back sides. The aluminum oxide layer on the front side constitutes the first passivation layer, wherein the thickness of the aluminum oxide layer is 5 nm.

[0109] T190: Silicon nitride layers are deposited on the front and back sides, the silicon nitride layer on the front side constitutes an anti-reflection film layer, and the aluminum oxide layer and silicon nitride layer on the back side constitute a second passivation layer on the back side, wherein the thickness of the silicon nitride layer is 80 nm.

[0110] T200: The first silver electrode and the second silver electrode are formed on the N region and the P region on the back by screen printing, respectively, to obtain a TBC battery, such as Figure 2 , Figure 5 and Figure 6 shown.

[0111] Through the ECV (Electrochemical Capacitance-Voltage) test method, the phosphorus doping and diffusion conditions of the n-type doped polysilicon layer, polysilicon buffer layer in the N region of the solar cell prepared by this method, and the silicon substrate in the corresponding region are tested. As Figure 7 shown, the setting of the polysilicon buffer layer at the black frame effectively blocks the inward diffusion of doping elements, and a high-low junction is formed between it and the silicon substrate, which is more conducive to the extraction of carriers.

[0112] Example 2

[0113] The steps for preparing the TBC cell are basically the same as those in Example 1, except that: the p-type doped polysilicon layer and the n-type doped polysilicon layer are directly formed by the PECVD method. That is, the preparation method includes:

[0114] T10: Provide an n-type silicon substrate, polish the silicon substrate to remove mechanical damage, and divide the N region and the P region on the back. The thickness of the silicon substrate is 150 μm.

[0115] T20: Deposit an intrinsic polysilicon buffer layer on the back of the silicon substrate 100 by the PECVD method, where the deposition temperature is 450 °C; the pressure is 2500 Pa; SiH 4 gas flow rate is 2200 sccm, H 2 gas flow rate is 12000 sccm; the radio frequency power supply power is 13500 W; the duty cycle is 0.07; the deposition thickness is 8 nm.

[0116] T30: Deposit a P-region tunneling layer on the back of the silicon substrate by the PECVD method, where the deposition temperature is 520 °C; SiH 4 gas flow rate is 900 sccm, N 2 O gas flow rate is 8000 sccm; the deposition thickness of the P-region tunneling layer is 2.2 nm.

[0117] T40: Deposit and form a p-type doped polysilicon layer on the side of the tunneling layer away from the silicon substrate by the PECVD method, where the deposition temperature is 500 °C; the pressure is 2000 Pa; SiH 4 gas flow rate is 2000 sccm, H 2 gas flow rate is 13000 sccm, the borane flow rate is 100 sccm, and the borane is diluted with H 2 The borane proportion is 1%; the radio frequency power supply power is 14000 W; the duty cycle is 0.07; the deposition thickness is 200 nm.

[0118] T50: Deposit a first silicon oxide mask on the side of the p-type lightly doped polysilicon layer away from the silicon substrate by PECVD method. Among them, the deposition temperature is 500 °C, and the flow rate of SiH 4 gas is 1000 sccm, and the flow rate of N 2 O gas is 7000 sccm, and the deposition thickness is 50 nm.

[0119] T60: Anneal the p-type doped polysilicon layer at 980 °C.

[0120] T70: Use the laser etching method to pattern the first silicon oxide mask, only retain the first mask structure in the P region, and remove the first mask structures in other regions; then etch and remove the p-type doped polysilicon layer, the P region tunneling layer, and the polysilicon buffer layer between the N region and the P region, only retain the p-type doped polysilicon layer, the P region tunneling layer, and the polysilicon buffer layer and other structures in the P region.

[0121] T80: Deposit an intrinsic polysilicon buffer layer, an N region tunneling layer, and an n-type doped polysilicon layer on the back surface in sequence by PECVD method. Among them, the deposition conditions of the intrinsic polysilicon buffer layer in this step are the same as those in step T20; the deposition conditions of the N region tunneling layer are basically the same as those of the P region tunneling layer, the difference is that the thickness of the N region tunneling layer 121 is 1.75 nm; the deposition temperature of the second intrinsic polysilicon layer is 500 °C; the pressure is 2000 Pa; the flow rate of SiH 4 gas is 2000 sccm, the flow rate of H 2 gas is 13000 sccm, and the flow rate of phosphine is 600 sccm; the power of the radio frequency power supply is 14000 W; the duty cycle is 0.07; the deposition thickness is 200 nm.

[0122] T90: Anneal the n-type doped polysilicon layer at 900 °C.

[0123] The subsequent steps are the same as steps T150 to T200 in Example 1.

[0124] Comparative Example 1

[0125] The steps for preparing the TBC cell are basically the same as those in Example 1, the difference is that: no intrinsic polysilicon buffer layer is formed, that is, the tunneling layer is directly formed on the surface of the back of the silicon substrate.

[0126] Perform performance tests on the TBC cells obtained in the above examples and comparative examples. The specific test method is: use a solar simulator and an I-V tester, under 1 standard solar irradiance, perform electrical performance tests on the TBC cells obtained in the above examples and control examples through steady-state power output tests. The test results are shown in Table 1.

[0127] Table 1

[0128]

[0129] From the comparison of the data in Examples 1 and 2, it can be seen that by the method of first depositing an intrinsic polysilicon layer, a heavily doped polysilicon layer, and a lightly doped polysilicon layer and then annealing to form a uniformly doped polysilicon layer, compared with the method of directly preparing a uniformly doped polysilicon layer, it can better block the inward diffusion of doping elements, and thus improve the photoelectric conversion efficiency of the battery; from the comparison of the test data in the Examples and Comparative Example 1, it can be seen that the formation of a polysilicon buffer layer can well block the inward diffusion of doping elements, and thus significantly improve the photoelectric conversion efficiency of the battery.

[0130] The terms "first" and "second" in the text are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality" means two or more, unless otherwise specifically defined.

[0131] In the description of this specification, the description with reference to terms such as "an embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0132] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A solar cell, characterized in that: include: A silicon substrate having a front side and a back side arranged opposite to each other; A polysilicon buffer layer, the polysilicon buffer layer being disposed on the back surface and / or the front surface of the silicon substrate; A tunneling layer, wherein the tunneling layer is arranged on a side of the polysilicon buffer layer away from the silicon substrate; A doped polysilicon layer is provided on a side of the tunneling layer away from the silicon substrate.

2. The solar cell according to claim 1, characterized in that The polysilicon buffer layer is an intrinsic polysilicon buffer layer or a doped polysilicon buffer layer, and the doping concentration is lower than the doping concentration of the doped polysilicon layer.

3. The solar cell according to claim 1, characterized in that The thickness of the polysilicon buffer layer is 5-10 nm.

4. The solar cell according to any one of claims 1 to 3, characterized in that The polysilicon buffer layer is arranged on the surface of the back side of the silicon substrate, and the surface of the front side is a velvet surface; the doped polysilicon layer includes an n-type doped polysilicon layer and a p-type doped polysilicon layer, and the n-type doped polysilicon layer and the p-type doped polysilicon layer are respectively arranged on the surface of the tunneling layer away from the silicon substrate. The solar cell further comprises: a first passivation layer, the first passivation layer being disposed on the suede surface of the front side; a second passivation layer, the second passivation layer being arranged on a side of the doped polysilicon layer away from the silicon substrate, and on a surface of the silicon substrate in a gap between the n-type doped polysilicon layer and the p-type doped polysilicon layer; an anti-reflection film layer, wherein the anti-reflection film layer is arranged on a side of the first passivation layer and the second passivation layer away from the silicon substrate; A first electrode and a second electrode, wherein the first electrode and the second electrode are located on the back side and are electrically connected to the n-type doped polysilicon layer and the p-type doped polysilicon layer respectively.

5. The solar cell according to claim 4, characterized in that: The thickness of the n-type doped polysilicon layer is 140nm-360nm, and the doping concentration is 1×10 20 cm -3 -8×10 20 cm -3 ; The thickness of the p-type doped polysilicon layer is 200-360 nm, and the doping concentration is 1×10 19 cm -3 -8×10 19 cm -3 .

6. A method for preparing the solar cell according to any one of claims 1 to 5, characterized in that: include: Depositing an intrinsic polysilicon buffer layer on the back surface and / or the front surface of the silicon substrate; Depositing a tunneling layer on a side of the intrinsic polysilicon buffer layer away from the silicon substrate; Depositing an intrinsic polysilicon layer on a side of the tunneling layer away from the silicon substrate; Depositing a heavily doped polysilicon layer on a side of the intrinsic polysilicon layer away from the silicon substrate; Depositing a lightly doped polysilicon layer on a side of the heavily doped polysilicon layer away from the silicon substrate; The intrinsic polysilicon layer, the heavily doped polysilicon layer and the lightly doped polysilicon layer are annealed to obtain a doped polysilicon layer.

7. The method according to claim 6, characterized in that The conditions for depositing and forming the intrinsic polysilicon buffer layer satisfy at least one of the following: The deposition temperature is 400-500°C; The pressure is 2000-3000Pa; The SiH4 gas flow rate is 1000-3000sccm, and the H2 gas flow rate is 10000-15000sccm; The RF power supply power is 10000W~17000W; The duty cycle is 0.05-0.1; The deposition thickness is 5-10 nm.

8. The method according to claim 6, characterized in that The conditions for depositing the tunneling layer satisfy at least one of the following: The deposition temperature is 500-550°C; The SiH4 gas flow rate is 500-1500sccm, and the N2O gas flow rate is 5000-10000sccm; When n-type doping is used, the deposition thickness of the tunneling layer is 1.5-1.9 nm; when p-type doping is used, the deposition thickness of the tunneling layer is 1.9-2.5 nm.

9. The method according to any one of claims 6 to 8, characterized in that: The conditions for depositing and forming the intrinsic polysilicon layer satisfy at least one of the following: Temperature is 400-550℃; The pressure is 2000-3000Pa; The SiH4 gas flow rate is 1000-3000sccm, and the H2 gas flow rate is 10000-15000sccm; The RF power supply power is 10000W~17000W; The duty cycle is 0.05-0.1; The deposition thickness is 20-40nm, The conditions for depositing and forming the heavily doped polysilicon layer satisfy at least one of the following: The temperature is 450-550℃; The pressure is 2000-3000Pa; When n-type doping is performed, the SiH4 gas flow rate is 1000-3000sccm, the H2 gas flow rate is 10000-15000sccm, and the phosphine flow rate is 300-800sccm; when p-type doping is performed, the SiH4 gas flow rate is 1000-3000sccm, the H2 gas flow rate is 5000-15000sccm, and the borane flow rate is 100-300sccm; The RF power supply power is 10000W~17000W; The duty cycle is 0.05-0.1; Deposition thickness 60-200nm, The conditions for depositing and forming the lightly doped polysilicon layer satisfy at least one of the following: The temperature is 450-550℃; The pressure is 1000-2500Pa; When n-type doping is performed, the SiH4 gas flow rate is 1000-3000sccm, the phosphine flow rate is 100-400sccm, and the H2 gas flow rate is 10000-15000sccm; when p-type doping is performed, the SiH4 gas flow rate is 1000-3000sccm, the H2 gas flow rate is 5000-15000sccm, and the borane flow rate is 30-100sccm; The RF power supply power is 10000W~17000W; The duty cycle is 0.05-0.1; The deposition thickness is 40-60nm.

10. The method according to claim 9, characterized in that The heavily doped polysilicon layer and the lightly doped polysilicon layer are n-type doped, and the temperature of the annealing treatment is 850-950° C.; The heavily doped polysilicon layer and the lightly doped polysilicon layer are p-type doped, and the temperature of the annealing treatment is 900-1030°C.

11. The method according to claim 9, characterized in that The method of depositing and forming the intrinsic polysilicon buffer layer, the intrinsic polysilicon layer, the heavily doped polysilicon layer and the lightly doped polysilicon layer all includes a plasma enhanced chemical vapor deposition method.

12. A photovoltaic module, characterized in that: A solar cell comprising the solar cell according to any one of claims 1 to 5.

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