Photovoltaic cell and preparation method thereof

Abstract

The invention provides a photovoltaic cell and a preparation method thereof, and relates to the technical field of photovoltaics. The method comprises the steps that a substrate is provided, the substrate is provided with a first surface, and the first surface comprises a first area, a second area and a third area located between the first area and the second area; a functional layer is stacked on the first surface, and the functional layer comprises a first doped silicon-containing layer and a dielectric layer; the functional layer on the second area is removed, a first coarse structure is formed on the first edge of the functional layer on the third area, and the first edge is the edge, adjacent to the second area, of the functional layer on the third area; forming a suede structure on the second area of the first surface; an intrinsic silicon-containing layer, a second doped silicon-containing layer and a conductive layer are sequentially stacked on the second region; sequentially stacking an intrinsic silicon-containing layer and a second doped silicon-containing layer on the dielectric layer in the third region; a conductive layer is stacked on the first doped silicon-containing layer in the first region. The photovoltaic cell preparation method can improve the photoelectric conversion efficiency of the photovoltaic cell.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a photovoltaic cell and a preparation method thereof. Background Art

[0002] The statements in this part only provide background art related to the present invention and do not necessarily constitute prior art.

[0003] A heterojunction (HJT) cell is mainly a PN heterojunction composed of silicon and doped amorphous silicon. An intrinsic amorphous silicon passivation layer is embedded at the heterojunction interface. Then, a transparent conductive oxide film (TCO) is prepared on both sides of the silicon wafer.

[0004] In recent years, the back contact (BC) cell technology has been used to improve the optoelectronic conversion performance of heterojunction cells. Specifically, all the grid line electrodes of the cell are moved to the back of the cell, reducing the occlusion of sunlight by the grid lines, thereby improving the absorption efficiency of incident light and achieving a higher conversion efficiency, forming a back contact heterojunction cell (HBC).

[0005] In the preparation process of HBC cells, first, an N-type doped silicon-containing layer and a dielectric layer are formed on the back of the silicon substrate. Then, the doped silicon-containing layer and the dielectric layer on the P region are removed to expose the silicon substrate. Furthermore, texturing is performed on the exposed part of the silicon substrate. Since the texturing solution is prone to lateral corrosion, it damages the edges of the N-type doped silicon-containing layer and the dielectric layer retained on the N region and the intersection region, resulting in a reduction in the efficiency of the photovoltaic cell. Summary of the Invention

[0006] The purpose of the present invention is to provide a photovoltaic cell and a preparation method thereof to solve the technical problem of reduced cell efficiency in the preparation method of photovoltaic cells.

[0007] To achieve the above purpose, the present invention provides the following technical solutions:

[0008] In the first aspect, the present invention provides a method for preparing a photovoltaic cell, including:

[0009] Providing a substrate, the substrate having a first surface, the first surface including a first region, a second region, and a third region located between the first region and the second region;

[0010] Stacking functional layers on the first surface, wherein the functional layers include a first doped silicon-containing layer and a dielectric layer;

[0011] Remove the functional layer on the second region and form a first rough structure on the first edge of the functional layer on the third region, where the first edge is the edge of the functional layer on the third region adjacent to the second region;

[0012] Form a matte structure on the second region of the first surface;

[0013] Stack an intrinsic silicon-containing layer, a second doped silicon-containing layer, and a conductive layer on the second region in sequence; stack the intrinsic silicon-containing layer and the second doped silicon-containing layer on the dielectric layer of the third region in sequence; stack the conductive layer on the first doped silicon-containing layer of the first region, where the doping types of the first doped silicon-containing layer and the second doped silicon-containing layer are electrically opposite.

[0014] According to at least one embodiment of the present invention, removing the functional layer on the second region includes:

[0015] Remove the functional layer on the second region by laser film opening and form a first rough structure on the first edge of the functional layer on the third region by laser jump point.

[0016] According to at least one embodiment of the present invention, after forming a matte structure on the second region of the first surface, it further includes:

[0017] Stack the intrinsic silicon-containing layer and the second doped silicon-containing layer on the matte structure, the third region, and the dielectric layer of the first region in sequence;

[0018] Remove the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the dielectric layer on the first region.

[0019] According to at least one embodiment of the present invention, when removing the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the dielectric layer on the first region, it includes:

[0020] Remove the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the dielectric layer on the first region by laser film opening and form a second rough structure on the second edge of the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the dielectric layer on the third region by laser jump point;

[0021] The second edge is the edge of the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the dielectric layer on the third region adjacent to the first region.

[0022] According to at least one embodiment of the present invention, the first rough structure includes at least one of an arch-like structure, a zigzag structure, or a wavy structure; and / or,

[0023] The second rough structure includes at least one of a bow-like structure, a zigzag structure, or a wavy structure.

[0024] According to at least one embodiment of the present invention, when both the first rough structure and the second rough structure are bow-like structures, the protrusion height of the protrusion portion of the bow-like structure of the first rough structure is D1, and the protrusion height of the protrusion portion of the bow-like structure of the second rough structure is D2;

[0025] wherein, the ratio of D1 to D2 is greater than 0 and less than or equal to 1

[0026] According to at least one embodiment of the present invention, after removing the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the dielectric layer on the first region, it further includes:

[0027] Stacking the conductive layer on the second doped silicon-containing layer in the second region and the third region, and on the first doped silicon-containing layer in the first region;

[0028] Disconnecting the conductive layer on the third region to electrically isolate the conductive layer on the second region and the first region.

[0029] According to at least one embodiment of the present invention, when disconnecting the conductive layer on the third region, it includes:

[0030] Coating and removing at least a part of the conductive layer located on the third region with an etching solution through a printing process.

[0031] According to at least one embodiment of the present invention, the substrate has a second surface opposite to the first surface. When forming a matte structure on the second region of the first surface, it further includes:

[0032] Forming the matte structure on the second region of the first surface and the second surface;

[0033] Stacking a passivation layer and an antireflection layer on the matte structure on the second surface in sequence.

[0034] In a second aspect, the present invention further provides a photovoltaic cell, including a substrate, the substrate having a first surface, the first surface including a first region, a second region, and a third region located between the first region and the second region;

[0035] A first doped silicon-containing layer is stacked on the first region; an intrinsic silicon-containing layer and a second doped silicon-containing layer are stacked on the second region in sequence; a functional layer, the intrinsic silicon-containing layer, and the second doped silicon-containing layer are stacked on the third region in sequence; wherein, the functional layer includes a first doped silicon-containing layer and a dielectric layer;

[0036] The first edge of the functional layer on the third region has a first rough structure, and the first edge is the edge where the functional layer on the third region is adjacent to the second region.

[0037] According to at least one embodiment of the present invention, the second edge of the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the dielectric layer on the third region has a second rough structure;

[0038] The second edge is the edge where the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the dielectric layer on the third region are adjacent to the first region, and the doping types of the first doped silicon-containing layer and the second doped silicon-containing layer are electrically opposite.

[0039] According to at least one embodiment of the present invention, it further includes a conductive layer stacked on the second doped silicon-containing layer in the second region and the first doped silicon-containing layer in the first region.

[0040] According to at least one embodiment of the present invention, the substrate is one of a P-type substrate or an n-type substrate.

[0041] According to at least one embodiment of the present invention, one of the first doped silicon-containing layer and the second doped silicon-containing layer is a P-type doped silicon-containing layer, and the other is an N-type doped silicon-containing layer.

[0042] According to at least one embodiment of the present invention, the substrate has a second surface opposite to the first surface, and a passivation layer and an antireflection layer are sequentially stacked on the second surface.

[0043] According to at least one embodiment of the present invention, the second region and the second surface of the substrate are respectively formed with a matte structure.

[0044] According to at least one embodiment of the present invention, the material of the first doped silicon-containing layer is N-type doped polysilicon, and the thickness is 30 nm to 300 nm; and / or,

[0045] The material of the dielectric layer is at least one of silicon oxide, silicon nitride, and silicon oxynitride; and / or,

[0046] The material of the intrinsic silicon-containing layer is at least one of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide; and / or,

[0047] The material of the second doped silicon-containing layer is at least one of P-type doped microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide; and / or,

[0048] The material of the conductive layer includes at least one of transparent conductive metal oxides or transparent conductive metal nitrides.

[0049] According to at least one embodiment of the present invention, the first rough structure includes at least one of a bow-like structure, a zigzag structure, or a wavy structure; and / or,

[0050] The second rough structure includes at least one of a bow-like structure, a zigzag structure, or a wavy structure.

[0051] According to at least one embodiment of the present invention, when both the first rough structure and the second rough structure are bow-like structures, the protruding height of the protruding portion of the bow-like structure of the first rough structure is D1, and the protruding height of the protruding portion of the bow-like structure of the second rough structure is D2;

[0052] Wherein, the ratio of D1 to D2 is greater than 0 and less than or equal to 1.

[0053] Among one or more technical solutions provided in the exemplary embodiments of the present invention, at least one of the following beneficial effects can be achieved.

[0054] In the method for manufacturing a photovoltaic cell according to an exemplary embodiment of the present invention, the first surface (back surface) of the substrate is divided into a first region, a second region, and a third region separating the two, where one of the first region and the second region can be a P region and the other can be an N region. First, a first doped silicon-containing layer and a dielectric layer are stacked on the entire first surface of the substrate, and then the first doped silicon-containing layer and the dielectric layer on the second region are removed to expose the substrate on this region to form a textured structure. During the above removal process, the first edge of the first doped silicon-containing layer and the dielectric layer remaining on the third region is not a straight line segment. For example, the first edge is a bow-like structure formed by line segments, and the individual line segments forming the bow-like structure are further in a bow-like structure. For example, a fine bow-like structure is the first rough structure. In the subsequent texturing process, due to the surface tension of the etching solution, the above first rough structure can reduce the lateral penetration and corrosion of the etching solution on the first edge of the first doped silicon-containing layer and the dielectric layer remaining on the third region, thereby minimizing the damage to the n-type functional layer (the first doped silicon-containing layer and the dielectric layer) as much as possible and improving the battery efficiency. When the texturing process is completed, an intrinsic silicon-containing layer, a second doped silicon-containing layer, and a conductive layer can be sequentially stacked on the second region; an intrinsic silicon-containing layer and a second doped silicon-containing layer are sequentially stacked on the dielectric layer of the third region; and a conductive layer is stacked on the first doped silicon-containing layer of the first region, thereby forming an HBC photovoltaic cell.

[0055] Furthermore, the height and / or width of the protrusions and / or depressions of the first rough structure can be adjusted. Without changing the fine grid layout, the ratio of the P region to the N region can be effectively regulated, the lateral transport distance of carriers can be reduced, the recombination rate can be decreased, the current density can be increased, and the photoelectric conversion efficiency can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The drawings illustrate exemplary embodiments of the present invention and, together with the description thereof, are used to explain the principles of the present invention. The drawings are included to provide a further understanding of the present invention, and the drawings are included in this specification and form a part of this specification;

[0057] Figure 1 is a schematic flowchart of a method for manufacturing a photovoltaic cell according to an embodiment of the present invention;

[0058] Figures 2 to 10 is a schematic cross-sectional view of the process structure corresponding to each step in the method for manufacturing a photovoltaic cell according to an embodiment of the present invention;

[0059] Figure 11 is a schematic diagram of the partition structure of a photovoltaic cell according to an embodiment of the present invention;

[0060] Figure 12 is Figure 11 a partial enlarged view of part A of

[0061] Reference numerals: 10, substrate; 11, first surface; 12, second surface; 11a, first matte structure; 12a, second matte structure;

[0062] 21, first doped silicon-containing layer; 22, dielectric layer;

[0063] 31, intrinsic silicon-containing layer; 32, second doped silicon-containing layer;

[0064] 41, passivation layer; 42, antireflection layer;

[0065] 50, conductive layer;

[0066] 61, first electrode; 62, second electrode;

[0067] 71, first edge; 711, first rough structure; 72, second edge; 722, second rough structure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0068] In order to make the technical problems, technical solutions, and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0069] During the preparation process of the related-art HBC battery, it is necessary to first form an N-type functional layer (tunneling oxide layer / N-type doped polysilicon layer or intrinsic silicon-containing thin film / N-type doped silicon-containing thin film) and an insulating isolation layer (dielectric layer) on the back surface of the silicon substrate. After laser film opening, it is necessary to perform texturing treatment on the front surface of the silicon substrate and the surface of the P region. At this time, the texturing solution (alkali solution) is likely to damage the edge of the functional layer in the N region, resulting in a reduction in battery efficiency.

[0070] To address the above problems, in the photovoltaic cell preparation method provided by an exemplary embodiment of the present invention, during laser film opening before the texturing treatment step, a first rough structure is formed on the traditional linear edge of the functional layer in the N region, thereby obtaining an uneven non-linear edge. Due to the existence of the surface tension of the texturing solution, the non-linear edge can reduce the lateral penetration corrosion of the texturing solution to the functional layer in the N region, thereby improving the photoelectric conversion efficiency of the battery.

[0071] It should be noted that the photovoltaic cell preparation method provided by an exemplary embodiment of the present invention is applicable not only to HBC batteries but also to other types of photovoltaic cells using BC battery technology.

[0072] Figure 1 is a schematic flow chart of the preparation method of a photovoltaic cell according to an embodiment of the present invention; Figures 2 to 10 is a schematic cross-sectional view of the process structure corresponding to each step in the photovoltaic cell preparation method according to an embodiment of the present invention. As Figure 1 shown, an exemplary embodiment of the present invention provides a photovoltaic cell preparation method, which may include the following steps:

[0073] Step 101: Provide a substrate 10, the substrate 10 having opposite first surface 11 and second surface 12, the first surface 11 including a first region E1, a second region E2, and a third region E3 located between the first region E1 and the second region E2, as Figure 2 shown.

[0074] Exemplarily, the substrate 10 may be a silicon substrate, such as a P-type silicon substrate or an N-type silicon substrate. Hereinafter, an N-type silicon substrate will be taken as an example for elaboration. The front surface (light-receiving surface) of the substrate 10 is the second surface 12, and the back surface is the first surface 11.

[0075] It should be noted that Figure 2 there is not only one set of first region E1, second region E2, and third region E3 on the first surface 11 of the substrate 10, and it may have multiple sets of the above regions, as Figure 11 shown, wherein Figure 11 is a schematic diagram of the partition structure of a photovoltaic cell according to an embodiment of the present invention.

[0076] For example, on the first surface 11, the first region E1, the third region E3, the second region E2, the third region E3, the first region E1, the third region E3, the second region E2 may be arranged in sequence, and this sequence may repeat; or, on the first surface 11, the first region E1, the third region E3, the second region E2, the third region E3, the second region E2, the third region E3, the first region E1 may be arranged in sequence, and this sequence may repeat, that is, there is a third region E3 between each group of regions.

[0077] Step 102: Stack functional layers on the first surface 11, where the functional layers include a first doped silicon-containing layer 21 and a dielectric layer 22.

[0078] In practical applications, since the substrate 10 is an N-type silicon substrate 10, the first doped silicon-containing layer 21 may be an N-type doped silicon-containing layer, for example, it may be a phosphorus-doped polysilicon layer or a phosphorus-doped silicon-containing thin film. The thickness of the N-type doped polysilicon layer is 30 nm to 200 nm, such as 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, etc.

[0079] Exemplarily, as an insulating isolation layer, the dielectric layer 22 may be made of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0080] In the following, an example is given where an N region (negative electrode region) is formed in the first region E1, a P region (positive electrode region) is formed in the second region E2, and a spacer region between the P region and the N region is formed in the third region E3.

[0081] Step 1021: Perform texturing / polishing treatment on the first surface 11 and the second surface 12 of the substrate 10 (silicon matrix) to form a tower base structure, as Figure 2 shown.

[0082] In practical applications, a matte surface can be formed on both the first surface 11 and the second surface 12 of the substrate 10 by means of alkali washing. At the same time, the dirt, impurities, metal ions, etc. on the surface of the substrate 10 can be removed by means of alkali washing or acid washing for polishing treatment.

[0083] Step 1022: Stack the first doped silicon-containing layer 21 and the dielectric layer 22 in sequence on the first surface 11 to form a structure as Figure 3 shown.

[0084] Over the entire region of the first surface 11, the first doped silicon-containing layer 21 and the dielectric layer 22 can be deposited on the substrate 10 in sequence by means of deposition.

[0085] The deposition process can be carried out by any one of vacuum evaporation, Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Physical Vapour Deposition (PVD), and atomic layer deposition (ALD), or a combination of multiple deposition methods in sequence.

[0086] Step 103: Remove the first doped silicon-containing layer 21 and the dielectric layer 22 on the second region E2 to form a structure as Figure 4 shown.

[0087] Adopt the method of laser film opening to remove the first doped silicon-containing layer 21 and the dielectric layer 22 on the second region E2, and retain the functional layers (the first doped silicon-containing layer 21 and the dielectric layer 22) on the first region E1 and the third region E3.

[0088] And adopt the laser hopping point method to form a first rough structure 711 on the first edge 71 of the functional layer in the third region E3. The first edge 71 is the edge where the functional layer in the third region E3 is adjacent to the second region E2.

[0089] Exemplarily, the first rough structure 711 includes at least one of an arch-like structure, a zigzag structure, or a wavy structure.

[0090] Figure 12 is Figure 11 a partial enlarged view of part A of. Combine Figure 11 and Figure 12 shown. After laser hopping points, the first edge 71 of the N region is an arch-like linear edge as a whole, and the first rough structure 711 is formed on the linear edge, which can be a small arch-like structure; or rather, on the three edges of the protruding part where the N region protrudes towards the P region, small arch-like structures are formed. Specifically, the width of the protruding part of the small arch-like structure in the first rough structure 711 is D3, and the protruding height of the protruding part is D1.

[0091] Exemplarily, in a conventional case, laser grooving is achieved by superimposing laser points to form a laser grooving line. Laser skipping, on the other hand, is to regularly turn on or off the laser according to the required pattern during the laser dotting process to form a rough edge structure, that is, in a linear region, the laser is turned on and dotted in some areas, and the laser is turned off and not dotted in some areas, thereby forming a rough edge. By controlling the laser power, pulse frequency, spot size, etc., the shape and depth of the rough edge can be accurately controlled. The pulse width of the picosecond pulsed laser is extremely short, and the generated heat-affected zone is smaller, which is suitable for areas with extremely high requirements for processing accuracy and heat influence, and is used to fabricate small bow-shaped structures to form the first rough structure 711.

[0092] Step 104: Form a textured structure on the second region E2 of the first surface 11 to form a structure as shown in Figure 5 the figure.

[0093] In practical applications, by using an etching method with a texturing solution (an alkaline solution, such as sodium hydroxide solution, potassium hydroxide solution, etc.), a first textured structure 11a and a second textured structure 12a are respectively formed on the second region E2 of the exposed substrate 10 and the second surface 12. The above-mentioned textured structures can be in the shape of a pyramid.

[0094] In this texturing step, since the first edge 71 of the functional layer in the first region E1 and the third region E3 is generally in a bow-shaped structure, it can reduce the lateral impact etching of the alkaline solution; and because a finer bow-shaped structure is formed on the linear edge, under the action of the surface tension of the alkaline solution, the fine bow-shaped structure can reduce the lateral penetration corrosion of the alkaline solution, thereby improving the photoelectric conversion efficiency of the HBC cell.

[0095] Step 105: Stack an intrinsic silicon-containing layer 31, a second doped silicon-containing layer 32, and a conductive layer 50 on the second region E2 in sequence; stack an intrinsic silicon-containing layer 31 and a second doped silicon-containing layer 32 on the dielectric layer 22 of the third region E3 in sequence; stack a conductive layer 50 on the first doped silicon-containing layer 21 of the first region E1.

[0096] Step 1051: Stack an intrinsic silicon-containing layer 31 and a second doped silicon-containing layer 32 on the first textured structure 11a of the second region E2, the dielectric layer 22 of the third region E3, and the dielectric layer 22 of the first region E1 in sequence to form a structure as shown in Figure 6 the figure.

[0097] In practical applications, the intrinsic silicon-containing layer 31 is first deposited on the first textured structure 11a of the second region E2, the dielectric layer 22 of the third region E3, and the dielectric layer 22 of the first region E1 by chemical deposition, and then the second doped silicon-containing layer 32 is deposited.

[0098] Exemplarily, the material of the intrinsic silicon-containing layer 31 is at least one of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide. For example, the intrinsic silicon-containing layer 31 is a single layer with the same performance, or a multi-layer with different performances, or a stack or a mixed silicon-containing thin film of several layers among thin film layers such as microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, or silicon carbide.

[0099] Exemplarily, the second doped silicon-containing layer 32 is at least one of P-type doped microcrystalline, nanocrystalline, amorphous silicon, silicon oxide, or silicon carbide. For example, it is a single layer with the same performance, or a multi-layer with different performances, or a stack or a mixed silicon-containing thin film of several layers among thin film layers such as boron-doped microcrystalline, nanocrystalline, amorphous silicon, silicon oxide, or silicon carbide.

[0100] Exemplarily, the thickness of the second doped silicon-containing layer 32 is 30 nm to 300 nm, such as 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 200 nm, 250 nm, etc.

[0101] Step 1052: Stack a passivation layer 41 and an antireflection layer 42 in sequence on the textured structure of the second surface 12 to form a structure as Figure 6 shown.

[0102] Deposit the passivation layer 41 first and then deposit the antireflection layer 42 on the textured structure (the second textured structure 12a) of the second surface 12 by chemical deposition.

[0103] Exemplarily, the passivation layer 41 is one of the combinations of the intrinsic silicon-containing layer 31, the second doped silicon-containing layer 32, and the intrinsic silicon-containing layer 31 / the second doped silicon-containing layer 32. Among them, the thickness of the intrinsic silicon-containing layer 31 is 1 nm to 15 nm, and the thickness of the second doped silicon-containing layer 32 is 0 to 15 nm.

[0104] Exemplarily, the material of the antireflection layer 42 is at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride, aluminum oxynitride, magnesium fluoride, lithium fluoride, ITO, zinc oxide, etc., and the thickness is 40 nm to 200 nm, such as 60 nm, 70 nm, 80 nm, 100 nm, 150 nm, 190 nm, etc.

[0105] It should be noted that the formation of the passivation layer 41 in this step can be carried out synchronously with the steps of forming the intrinsic silicon-containing layer 31 and the second doped silicon-containing layer 32 in step 1051, so as to shorten the process flow and simplify the operation.

[0106] Step 1053: Remove the intrinsic silicon-containing layer 31, the second doped silicon-containing layer 32, and the dielectric layer 22 on the first region E1 to form a structure as Figure 7 shown.

[0107] In practical applications, the intrinsic silicon-containing layer 31, the second doped silicon-containing layer 32, and the dielectric layer 22 on the first region E1 are removed by laser film opening, and a second rough structure 722 is formed on the second edge 72 of the intrinsic silicon-containing layer 31, the second doped silicon-containing layer 32, and the dielectric layer 22 in the third region E3 by laser jump point; wherein, the second edge 72 is the edge of the intrinsic silicon-containing layer 31, the second doped silicon-containing layer 32, and the dielectric layer 22 in the third region E3 adjacent to the first region E1.

[0108] Combined with Figure 11 and Figure 12 As shown, after laser jump point in this step, the second edge 72 of the P region is an overall bow-shaped linear edge as a whole, and the second rough structure 722 is formed on the linear edge, which can be a fine bow-shaped structure; or rather, on the three linear segments of the protruding part where the P region protrudes towards the N region, fine bow-shaped structures are formed. Specifically, the width of the protruding part of the fine bow-shaped structure in the second rough structure 722 is D3, and the protruding height of the protruding part is D2.

[0109] As can be seen from the above, the design of the fine bow-shaped structures of the first rough structure 711 and the second rough structure 722 can effectively regulate the ratio of the P / N regions by adjusting the relative sizes of D1, D2, and D3 without changing the fine grid arrangement (the overall bow-shaped edges of the P region and the N region remain unchanged). For example, by reducing the area of the isolation region (the third region E3), a high-density P region-N region interdigital structure is formed, reducing the lateral transmission distance of carriers (the mutual transfer distance of carriers in the P region and the N region), thereby reducing the recombination rate and resistance loss during the transmission process, increasing the current density, and further improving the photoelectric conversion efficiency of the HBC solar cell.

[0110] In some embodiments, when both the first rough structure 711 and the second rough structure 722 are bow-shaped structures, the protruding height of the protruding part of the bow-shaped structure of the first rough structure 711 is D1, and the protruding height of the protruding part of the bow-shaped structure of the second rough structure 722 is D2; wherein, the ratio of D1 to D2 is greater than 0 and less than or equal to 1. This ratio can be adjusted according to the actual production process and the corresponding structures of the P region and the N region to balance the distribution of photo-generated carriers and the process complexity. It should be noted that the bow-shaped structure is similar to the "bow" shape and can include alternately connected protruding parts and recessed parts, as can be seen in Figure 12 shown.

[0111] Step 1054: Stack a conductive layer 50 on the second doped silicon-containing layer 32 in the second region E2, the second doped silicon-containing layer 32 in the third region E3, and the first doped silicon-containing layer 21 in the first region E1 to form a structure as shown in Figure 8 shown.

[0112] In practical applications, on the structural surface formed on the first surface 11 of the substrate 10 in step 1053, an integrally formed conductive layer 50 is formed by chemical deposition.

[0113] Exemplarily, the material of the conductive layer 50 includes at least one of transparent conductive metal oxides or transparent conductive metal nitrides.

[0114] Specifically, the conductive layer 50 is a TCO film layer, which is a multi-layer or stack or mixture of one or more doped metal oxides or nitrides. The metal oxides can be indium oxide, tin oxide, zinc oxide, cadmium oxide, titanium nitride, and the metal nitrides can be titanium nitride. The doping elements can be indium, tin, calcium, aluminum, cadmium, zinc, cerium or fluorine.

[0115] Step 1055: Disconnect the conductive layer 50 on the third region E3, including: coating and removing at least part of the conductive layer 50 located on the third region E3 through a printing process, to form a structure as Figure 9 shown.

[0116] In practical applications, the etching method uses screen printing to etch the conductive layer 50 located in the third region E3 with an etching paste to form a discontinuous structure, and the width of the discontinuous structure is substantially the same as or slightly smaller than the width of the third region E3.

[0117] The above discontinuous structure can electrically insulate the conductive layer 50 on the first region E1 from the conductive layer 50 on the third region E3, and electrically insulate the conductive layer 50 on the second region E2 from the conductive layer 50 on the third region E3, that is, the conductive layer 50 on the first region E1 and the conductive layer 50 on the second region E2 are electrically insulated from each other.

[0118] Exemplarily, the material of the etching paste can be sulfuric acid, phosphoric acid, etc., and the pH value is 0 - 3.

[0119] Exemplarily, the printing process is one or a mixture of screen printing, laser transfer printing, steel plate printing, etc. and can achieve a similar patterning scheme.

[0120] Since after this step is completed, the etching paste needs to be washed off, and this washing process requires alkaline washing. Since in step 1053, the second rough structure 722 has already been formed on the second edge 72, therefore, the above washing process will also reduce the lateral penetration corrosion of the edge of the P region, thereby also improving the photoelectric conversion efficiency of the battery.

[0121] Step 106: Form metal electrodes on the structures on the first region E1 and the second region E2 respectively, to form a structure as Figure 10 shown.

[0122] In practical applications, along the stacking direction, a first electrode 61 is provided and connected to the conductive layer 50 on the first region E1; a second electrode 62 is provided and connected to the conductive layer 50 on the second region E2.

[0123] The above stacking direction is perpendicular to the first surface 11 of the substrate 10, and corresponding metal electrodes are prepared on the first region E1 and the second region E2 by printing electrode paste. For example, one end of the first electrode 61 is located outside the conductive layer 50, and the other end is electrically connected to the conductive layer 50; one end of the second electrode 62 is located outside the conductive layer 50, and the other end is electrically connected to the conductive layer 50, thereby forming a photovoltaic cell.

[0124] Exemplarily, when the first doped silicon-containing layer 21 is a boron-doped silicon-containing layer, the first electrode 61 is a positive electrode, and correspondingly, the second electrode 62 is a negative electrode.

[0125] In some embodiments, when the first doped silicon-containing layer 21 is a phosphorus-doped silicon-containing layer, the first electrode 61 is a negative electrode, and correspondingly, the second electrode 62 is a positive electrode.

[0126] Exemplarily, the first electrode 61 and the second electrode 62 can be one or several laminations of a silver electrode, a silver alloy electrode, a copper electrode, a copper alloy electrode, and a nickel / copper / silver multi-layer electrode.

[0127] An exemplary embodiment of the present invention provides a photovoltaic cell prepared by using the photovoltaic cell preparation method of the above embodiment.

[0128] As Figure 11 and Figure 12 shown, the photovoltaic cell of the exemplary embodiment of the present invention includes a substrate 10 having a first surface 11, the first surface 11 including a first region E1, a second region E2, and a third region E3 located between the first region E1 and the second region E2; a first doped silicon-containing layer 21 is stacked on the first region E1; an intrinsic silicon-containing layer 31 and a second doped silicon-containing layer 32 are sequentially stacked on the second region E2; a functional layer, an intrinsic silicon-containing layer 31, and a second doped silicon-containing layer 32 are sequentially stacked on the third region E3; wherein, the functional layer includes a first doped silicon-containing layer 21 and a dielectric layer 22; a first edge 71 of the functional layer on the third region E3 has a first rough structure 711, and the first edge 71 is the edge of the functional layer on the third region E3 adjacent to the second region E2.

[0129] In some embodiments, a second rough structure 722 is provided on a second edge 72 of the intrinsic silicon-containing layer 31, the second doped silicon-containing layer 32, and the dielectric layer 22 on the third region E3; the second edge 72 is the edge of the intrinsic silicon-containing layer 31, the second doped silicon-containing layer 32, and the dielectric layer 22 on the third region E3 adjacent to the first region E1.

[0130] In some embodiments, the substrate 10 is one of a P-type substrate 10 or an N-type substrate 10.

[0131] In some embodiments, one of the first doped silicon-containing layer 21 and the second doped silicon-containing layer 32 is a P-type doped silicon-containing layer, and the other is an N-type doped silicon-containing layer.

[0132] In some embodiments, the substrate 10 has a second surface 12 opposite to the first surface 11, and a passivation layer 41 and an antireflection layer 42 are sequentially stacked on the second surface 12.

[0133] In some embodiments, a matte structure is respectively formed on the second region E2 of the substrate 10 and the second surface 12.

[0134] In some embodiments, the material of the first doped silicon-containing layer 21 is N-type doped polysilicon, and the thickness is 30 nm to 300 nm.

[0135] In some embodiments, the material of the dielectric layer 22 is at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0136] In some embodiments, the material of the intrinsic silicon-containing layer 31 is at least one of microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, and silicon carbide.

[0137] In some embodiments, the material of the second doped silicon-containing layer 32 is at least one of P-type doped microcrystalline silicon, nanocrystalline silicon, amorphous silicon, silicon oxide, and silicon carbide.

[0138] In some embodiments, the material of the conductive layer 50 includes at least one of a transparent conductive metal oxide or a transparent conductive metal nitride.

[0139] In some embodiments, the first rough structure 711 includes at least one of a bow-like structure, a zigzag structure, or a wavy structure.

[0140] In some embodiments, the second rough structure 722 includes at least one of a bow-like structure, a zigzag structure, or a wavy structure.

[0141] In some embodiments, when both the first rough structure 711 and the second rough structure 722 are bow-like structures, the protrusion height of the protrusion portion of the bow-like structure of the first rough structure is D1, and the protrusion height of the protrusion portion of the bow-like structure of the second rough structure is D2;

[0142] Wherein, the ratio of D1 to D2 is greater than 0 and less than or equal to 1, and can be, for example, 0.1, 0.3, 0.5, 0.7, or 1, etc.

[0143] Compared with the linear edges of the P region and the N region of the HBC cell in the prior art, for the HBC cell of the exemplary embodiment of the present invention, the edge of the N region has a first rough structure in a fine bow shape, and the edge of the P region has a second rough structure in a fine bow shape. The minority carrier lifetime can be increased by 21.00 μs, the bulk lifetime can be increased by 34.90 μs, and the virtual open circuit voltage can be increased by 0.01 V.

[0144] The other technical advantages of the above photovoltaic cell compared with the prior art are the same as those of the above photovoltaic cell preparation method, and will not be elaborated here.

[0145] Those skilled in the art should understand that the above embodiments are only for clearly illustrating the present invention, rather than limiting the scope of the present invention. For those skilled in the art, other changes or variations can be made on the basis of the above disclosure, and these changes or variations are still within the scope of the present invention.

Claims

1. A method for preparing a photovoltaic cell, characterized in that: include: Providing a substrate, the substrate having a first surface, the first surface including a first area, a second area, and a third area located between the first area and the second area; stacking a functional layer on the first surface, wherein the functional layer includes a first doped silicon-containing layer and a dielectric layer; removing the functional layer on the second region, and forming a first rough structure on a first edge of the functional layer on the third region, where the first edge is an edge where the functional layer on the third region is adjacent to the second region; forming a suede structure on the second area of ​​the first surface; An intrinsic silicon-containing layer, a second doped silicon-containing layer and a conductive layer are stacked in sequence on the second region; the intrinsic silicon-containing layer and the second doped silicon-containing layer are stacked in sequence on the dielectric layer in the third region; the conductive layer is stacked on the first doped silicon-containing layer in the first region, and the first doped silicon-containing layer and the second doped silicon-containing layer have opposite electrical properties in doping type.

2. The preparation method according to claim 1, characterized in that: Removing the functional layer on the second region comprises: The functional layer on the second area is removed by laser film opening, and a first rough structure is formed on the first edge of the functional layer on the third area by laser point jumping.

3. The preparation method according to claim 1, characterized in that: After forming the velvet structure on the second area of ​​the first surface, the method further includes: stacking the intrinsic silicon-containing layer and the second doped silicon-containing layer in sequence on the velvet structure, the third region and the dielectric layer of the first region; The intrinsic silicon-containing layer, the second doped silicon-containing layer and the dielectric layer on the first region are removed.

4. The preparation method according to claim 3, characterized in that: When removing the intrinsic silicon-containing layer, the second doped silicon-containing layer and the dielectric layer on the first region, the method includes: removing the intrinsic silicon-containing layer, the second doped silicon-containing layer and the dielectric layer on the first region by laser film opening, and forming a second rough structure on the second edge of the intrinsic silicon-containing layer, the second doped silicon-containing layer and the dielectric layer on the third region by laser point jumping; The second edge is an edge of the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the dielectric layer on the third region that is adjacent to the first region.

5. The preparation method according to claim 4, characterized in that: The first rough structure includes at least one of a bow-like structure, a sawtooth structure or a wavy structure; and / or, The second rough structure includes at least one of a bow-like structure, a sawtooth structure or a wavy structure; Alternatively, when both the first roughness structure and the second roughness structure include a bow-like structure, the convex portion of the bow-like structure of the first roughness structure has a convex height of D1, and the convex portion of the bow-like structure of the second roughness structure has a convex height of D2; The ratio of D1 to D2 is greater than 0 and less than or equal to 1.

6. The preparation method according to claim 3, characterized in that: After removing the intrinsic silicon-containing layer, the second doped silicon-containing layer and the dielectric layer on the first region, the method further includes: stacking the conductive layer on the second region, the second doped silicon-containing layer in the third region, and the first doped silicon-containing layer in the first region; Disconnecting the conductive layers on the third region so that the conductive layers on the second region and the first region are electrically isolated; Preferably, when the conductive layers on the third region are disconnected, the method comprises: Applying an etching solution to remove at least a portion of the conductive layer located on the third region; Preferably, the substrate has a second surface opposite to the first surface, and the preparation method further comprises: forming the suede structure on the second surface; A passivation layer and an anti-reflection layer are sequentially stacked on the textured structure of the second surface.

7. A photovoltaic cell, characterized in that: A substrate having a first surface, wherein the first surface comprises a first region, a second region, and a third region located between the first region and the second region; A first doped silicon-containing layer is stacked on the first region; an intrinsic silicon-containing layer and a second doped silicon-containing layer are stacked in sequence on the second region; a functional layer, the intrinsic silicon-containing layer, and the second doped silicon-containing layer are stacked in sequence on the third region; wherein the functional layer includes a first doped silicon-containing layer and a dielectric layer, and the first doped silicon-containing layer and the second doped silicon-containing layer have opposite electrical properties of doping types; A first edge of the functional layer on the third region has a first rough structure, and the first edge is an edge where the functional layer on the third region is adjacent to the second region.

8. The photovoltaic cell according to claim 7, characterized in that: A second roughness structure is provided on the second edge of the intrinsic silicon-containing layer, the second doped silicon-containing layer and the dielectric layer on the third region; The second edge is an edge of the intrinsic silicon-containing layer, the second doped silicon-containing layer, and the dielectric layer on the third region that is adjacent to the first region.

9. The photovoltaic cell according to claim 8, characterized in that: The first rough structure includes at least one of a bow-like structure, a sawtooth structure or a wavy structure; and / or, The second rough structure includes at least one of a bow-like structure, a sawtooth structure or a wavy structure.

10. The photovoltaic cell according to claim 9, characterized in that: When both the first roughness structure and the second roughness structure include a bow-like structure, the convex portion of the bow-like structure of the first roughness structure has a convex height of D1, and the convex portion of the bow-like structure of the second roughness structure has a convex height of D2; Among them, the ratio of D1 to D2 is greater than 0 and less than or equal to 1; Preferably, it further comprises a conductive layer stacked on the second doped silicon-containing layer in the second region and the first doped silicon-containing layer in the first region; and / or, The substrate is a P-type substrate or an N-type substrate; and / or, One of the first doped silicon-containing layer and the second doped silicon-containing layer is a P-type doped silicon-containing layer, and the other is an N-type doped silicon-containing layer; and / or, The dielectric layer is made of at least one of silicon oxide, silicon nitride and silicon oxynitride; and / or, The material of the intrinsic silicon-containing layer is at least one of microcrystalline silicon, nano-silicon, amorphous silicon, silicon oxide or silicon carbide; and / or, The material of the conductive layer includes at least one of transparent conductive metal oxide and transparent conductive metal nitride.

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