Configurable memory device

Abstract

The memory device may be accessed via multiple channels (e.g., 2 channels, 4 channels, etc.). The data width (i.e., the number of data signals) allocated to each channel is configurable such that a given set of data input / output (I / O) signals may be part of a first channel in one configuration, but part of another channel in a different configuration. Similarly, a memory array (e.g., a bank or bank group) accessed through a given channel may be configurable such that a given memory array is accessed via a first channel in one configuration, but via a different channel in a different configuration. Finally, the data burst length, the data burst size and the data transmission clock period are configurable.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figures 1A to 1B is a block diagram illustrating a system having a configurable memory device.

[0002] Figures 2A to 2B is a block diagram illustrating a memory configuration.

[0003] Figure 3 is a block diagram illustrating an example system configuration of a four-channel configurable memory device.

[0004] Figures 4A to 4B is a schematic diagram illustrating an example data burst configuration for a multi-channel memory device.

[0005] Figure 5 is a block diagram illustrating a multi-channel memory device.

[0006] Figure 6 is a flowchart illustrating a method of operating a memory device.

[0007] Figure 7 is a flowchart illustrating a method of accessing a multi-channel memory device.

[0008] Figure 8 is a flowchart illustrating a method of reconfiguring a multi-channel memory device.

[0009] Figure 9 is a block diagram of a processing system. DETAILED DESCRIPTION

[0010] In an embodiment, a memory device may be accessed via multiple channels (e.g., 2 channels, 4 channels, etc.). The data width (i.e., the number of data signals) assigned to each channel is configurable such that a given set of data input / output (I / O) signals may be part of a first channel in one configuration, but part of a different channel in a different configuration. Similarly, the memory array (e.g., bank or bank group) accessed via a given channel may be configurable such that a given memory array is accessed via a first channel in one configuration, but via a different channel in a different configuration. Finally, the data burst length and data burst size are configurable such that, for example, a channel configured to have 32 data signals may communicate using a 64-byte burst over 16 unit intervals, while a different channel (e.g., on the same memory device) configured to have 4 data signals may communicate using a 16-byte burst over 32 unit intervals.

[0011] Figures 1A to 1B is a block diagram illustrating a system having a configurable memory device. In Figure 1AIn this case, the memory system 101 includes a memory device 110 and a controller 121. The controller 121 includes two memory channel interfaces: a memory channel "A" interface 125a and a memory channel "B" interface 126a. In Figure 1B In this case, the memory system 102 includes a memory device 110 and a controller 122. The controller 122 includes two memory channel interfaces: a memory channel "A" interface 125b and a memory channel "B" interface 126b.

[0012] The memory device 110 includes a data (DQ) signal group #1 interface (DQGRP1 I / F 111), a DQ signal group #2 interface (DQGRP2 I / F 112), a DQ signal group #3 interface (DQGRP3 I / F 113), a memory channel "A" command / address interface (CAAI / F 115), a memory channel "B" command / address interface (CAB I / F 116), memory arrays 130a to 130b, and a control circuit 140. The control circuit 140 includes a mode / configuration circuit 141.

[0013] The CAA interface 115 of the memory device 110 is operatively coupled to the control circuit 140 and the memory array 130a. The CAB interface 116 of the memory device 110 is operatively coupled to the control circuit 140 and the memory array 130b. The DQGRP1 interface 111 is operatively coupled to the memory array 130a and the control circuit 140. The DQGRP2 interface 112 is operatively coupled to the control circuit 140. In an embodiment, the DQGRP1 interface 111 has N 1 bi-directional DQ signals; the DQGRP2 interface 112 has N 2 bi-directional DQ signals; and the DQGRP3 interface 113 has N 3 bi-directional DQ signals.

[0014] The controller 121, the controller 122, and the memory device 110 are devices of the integrated circuit type, such as devices commonly referred to as "chips". Memory controllers, such as the controller 121 and the controller 122, manage the data stream to and from the memory device. The functions of the memory controller can be included on a single die with a microprocessor, or can be included as part of a more complex integrated circuit system, as a block of a system-on-chip (SOC). For example, the memory controller can be a northbridge chip, an application-specific integrated circuit (ASIC) device, a load-reducing memory buffer, a graphics processing unit (GPU), a system-on-chip (SoC), or an integrated circuit device including many circuit blocks (such as circuit blocks selected from a graphics core, a processor core, and an MPEG encoder / decoder), etc.

[0015] In the memory system 101 (such asFigure 1A In the (example shown), the memory device 110 is in a first configuration (e.g., configured by the mode / configuration circuit 141), where DQGRP2 112 acts as part of a memory channel that receives commands / addresses via the CAA interface 115 and transfers data to / from the (one or more) memory arrays 130a. Thus, in Figure 1A , the channel A interface 125a of the controller 121 is operatively coupled to the CAA interface 115, the DQGRP1 interface 111, and the DQGRP2 interface 112. The channel B interface 126a of the controller 121 is operatively coupled to the CAB interface 116 and the DQGRP3 interface 113. In Figure 1A , the channel A interface 125a of the controller 121 has N 1 + N 2 bi-directional data signals, and the channel B interface 126a of the controller 121 has N 3 bi-directional data signals.

[0016] In the memory system 102 (as Figure 1B shown), the memory device 110 is in a second configuration (e.g., configured by the mode / configuration circuit 141), where DQGRP2 112 acts as part of a memory channel that receives commands / addresses via the CAB interface 116 and transfers data to / from the (one or more) memory arrays 130b. Thus, in Figure 1B , the channel A interface 125a of the controller 121 is operatively coupled to the CAA interface 115, the DQGRP1 interface 111, and the DQGRP2 interface 112. The channel B interface 126a of the controller 121 is operatively coupled to the CAB interface 116, the DQGRP2 interface 112, and the DQGRP3 interface 113. In Figure 1B , the channel A interface 125a of the controller 121 has N 1 bi-directional data signals, and the channel B interface 126a of the controller 121 has N 2 + N 3 bi-directional data signals.

[0017] It should be understood from Figures 1A to 1B that DQGRP1 111, DQGRP2 112, and DQGRP3 113 are non-overlapping sets of DQ signals, where DQGRP2 112 can be configured as part of a first memory channel (e.g., memory channel A - as Figure 1A shown) or part of a second memory channel (e.g., memory channel B - as Figure 1B shown). Thus, for example, if N 1 = N 2 = N 3If = 8, the memory device 110 may be configured to interface with a controller 121 having a 16-bit DQ interface for communicating via memory channel A and an 8-bit DQ interface for communicating via memory channel B. Similarly, continuing with N 1 = N 2 = N 3 In an example where = 8, the memory device 110 may be configured to interface with a controller 122 having an 8-bit DQ interface for communicating via memory channel A and a 16-bit DQ interface for communicating via memory channel B. Note that in both of these examples, the DQ widths (i.e., the number of DQ signals) of channels A and B are different (i.e., non-uniform).

[0018] In an embodiment, the memory device 110 may also be configured such that the number of memory arrays accessed by memory channel A (via CAA interface 115) is different from the number of memory arrays accessed by memory channel B (via CAB interface 116). In one example, the number of memory arrays accessed via CAA interface 115 and the number of memory arrays accessed via CAB interface 116 may be proportional to the number of DQ signal lines that are part of memory channel A and the number of DQ signal lines that are part of memory channel B (e.g., memory channel A has 16 DQ signals and accesses 4 memory arrays 130a, and memory channel B has 8 DQ signals and accesses 2 memory arrays 130b). In another example, the number of memory arrays accessed via CAA interface 115 and the number of memory arrays accessed via CAB interface 116 may not be proportional to the number of DQ signal lines that are part of memory channel A and the number of DQ signal lines that are part of memory channel B (e.g., memory channel A has 16 DQ signals and accesses 4 memory arrays 130a, and memory channel B has 8 DQ signals and accesses 6 memory arrays 130b).

[0019] Figures 2A to 2B is a block diagram illustrating a memory configuration. In Figures 2A to 2B the memory device 210a includes a data (DQ) signal group #1 interface (DQGRP1 I / F 211a), a DQ signal group #2 interface (DQGRP2 I / F 212a), a DQ signal group #3 interface (DQGRP3 I / F 213a), a DQ signal group #4 interface (DQGRP4 I / F 214a), memory arrays 231a to 234a, and a control circuit 240a. The memory device 210a also includes two command / address interfaces (e.g., CAAI / F and CAB I / F), which are parts of memory channels (e.g., memory channel A and memory channel B), respectively. For simplicity, inFigures 2A to 2B is not shown.

[0020] The memory device 210b includes a data (DQ) signal group #1 interface (DQGRP1 I / F 211b), a DQ signal group #2 interface (DQGRP2 I / F 212b), a DQ signal group #3 interface (DQGRP3 I / F 213b), a DQ signal group #4 interface (DQGRP4 I / F 214b), memory arrays 231b to 234b, and a control circuit 240b. The memory device 210b also includes two command / address interfaces (e.g., CAA I / F and CAB I / F), which are parts of memory channels (e.g., memory channel A and memory channel B), respectively. For simplicity, in Figures 2A to 2B it is not shown. In an embodiment, the memory device 210a and the memory device 210b are the same, but can be configured differently (e.g., by the controller 221, the control circuit 240a, and / or the control circuit 240b).

[0021] Figure 2A FIG. illustrates a first memory system using a first configuration of the memory devices 210a to 210b. In Figure 2A it, the memory system 201 includes a controller 221, a memory device 210a, and a memory device 210b. The controller 221 includes a memory channel “A” 225a, a memory channel “B” 226a, a memory channel “C” 227a, and a memory channel “D” 228a. The memory channel A 225a is operably coupled to the DQGRP1 interface 211a of the memory device 210a using N 1aa data signals. The memory channel A 225a is operably coupled to the DQGRP2 interface 212a of the memory device 210a using N 2aa data (DQ) signals. Thus, the memory channel A 225a of the controller 221 has N 1aa +N 2aa DQ signals.

[0022] The memory channel B 226a is operably coupled to the DQGRP3 interface 213a of the memory device 210a using N 3aa data signals. The memory channel B 226a is operably coupled to the DQGRP4 interface 214a of the memory device 210a using N 4aa data (DQ) signals. The memory channel A 226a is operably coupled to the DQGRP4 interface 214a of the memory device 210a using N 4aa data (DQ) signals. Thus, the memory channel B 226a of the controller 221 has N 3aa +N 4aaa DQ signal.

[0023] Memory channel C 227a uses N 1ab data signals and is operatively coupled to the DQGRP1 interface 211b of the memory device 210b. Memory channel C 227a uses N 2ab data (DQ) signals and is operatively coupled to the DQGRP2 interface 212b of the memory device 210b. Thus, the memory channel C 227a of the controller 221 has N 1ab + N 2ab DQ signals.

[0024] Memory channel D 228a uses N 3ab data signals and is operatively coupled to the DQGRP3 interface 213b of the memory device 210b. Memory channel D 228a uses N 4ab data (DQ) signals and is operatively coupled to the DQGRP4 interface 214b of the memory device 210b. Thus, the memory channel D 228a of the controller 221 has N 3ab + N 4ab DQ signals.

[0025] In Figure 2A , the memory device 210a is configured such that the memory channel A 225a of the controller 221 accesses the memory arrays 231a to 232a via the DQGRP1 interface 211a and the DQGRP2 interface 212a. The memory device 210a is also configured such that the memory channel B 226a of the controller 221 accesses the memory arrays 233a to 234a via the DQGRP3 interface 213a and the DQGRP4 interface 214a. Thus, the memory device 210a is configured such that each of the memory channel A 225a and the memory channel B 226a accesses the same number of arrays / banks in the memory device 210a.

[0026] Similarly, in Figure 2A , the memory device 210b is configured such that the memory channel C 227a of the controller 221 accesses the memory arrays 231b to 232b via the DQGRP1 interface 211b and the DQGRP2 interface 212b. The memory device 210b is also configured such that the memory channel D 228a of the controller 221 accesses the memory arrays 233b to 234b via the DQGRP3 interface 213b and the DQGRP4 interface 214b. Thus, the memory device 210b is configured such that each of the memory channel C 227a and the memory channel D 228a accesses the same number of arrays / banks in the memory device 210b.

[0027] In an embodiment, the controller 221 and the memory devices 210a to 210b are configured such that each of the memory channels A 225a, memory channel B 226a, memory channel C 227a, and memory channel D 228a has the same number of data signals (e.g., 16 bits). Similarly, the memory devices 210a to 210b are configured such that each of the DQGRP1 interfaces 211a, DQGRP2 interfaces 212a, DQGRP3 interfaces 213a, DQGRP4 interfaces 214a, DQGRP1 interfaces 211b, DQGRP2 interfaces 212b, DQGRP3 interfaces 213b, and DQGRP4 interfaces 214b has the same number of data signals (e.g., 8 bits). In other words, in an embodiment, the controller 221 and the memory devices 210a to 210b are configured such that N 1aa = N 2aa = N 3aa = N 4aa = N 1ab = N 2ab = N 3ab = N 4ab .

[0028] Figure 2B FIG. illustrates a second memory system using a second configuration of the memory devices 210a to 210b. In Figure 2B this embodiment, the memory system 202 includes a controller 222, a memory device 210a, and a memory device 210b. The controller 222 includes a memory channel “A” 225b, a memory channel “B” 226b, a memory channel “C” 227b, and a memory channel “D” 228b. The memory channel A 225b is operatively coupled to the DQGRP2 interface 211a of the memory device 210a using N 1ba data (DQ) signals. The memory channel A 225b is operatively coupled to the DQGRP2 interface 212a of the memory device 210a using N 2ba DQ signals. The memory channel A 225a is operatively coupled to the DQGRP3 interface 213a of the memory device 210a using N 3ba DQ signals. Accordingly, the memory channel A 225b of the controller 222 has N 1ba + N 2ba + N 3ba DQ signals.

[0029] The memory channel B 226b is operatively coupled to the DQGRP4 interface 214a of the memory device 210a using N 4ba data signals. Accordingly, the memory channel B 226b of the controller 222 has N 4ba DQ signals.

[0030] Memory channel C 227b uses N 1bb data (DQ) signals and is operably coupled to the DQGRP1 interface 211b of the memory device 210b. Memory channel C 227a uses N 2bb DQ signals and is operably coupled to the DQGRP2 interface 212b of the memory device 210b. Memory channel C 227a uses N 3bb DQ signals and is operably coupled to the DQGRP3 interface 213b of the memory device 210b. Thus, the memory channel C 227a of the controller 221 has N 1bb +N 2bb +N 3bb DQ signals.

[0031] Memory channel D 228b uses N 4bb data signals and is operably coupled to the DQGRP4 interface 214b of the memory device 210b. Thus, the memory channel D 228a of the controller 221 has N 4bb DQ signals.

[0032] In Figure 2B , the memory device 210a is configured such that the memory channel A 225b of the controller 222 accesses the memory arrays 231a to 232a via the DQGRP1 interface 211a, the DQGRP2 interface 212a, and the DQGRP3 interface 213a. The memory device 210a is also configured such that the memory channel B 226a of the controller 222 accesses the memory arrays 233a to 234a via the DQGRP4 interface 214a. Thus, the memory device 210a is configured such that each of the memory channel A 225b and the memory channel B 226b accesses the same number of arrays / banks in the memory device 210a, even though the memory channel A 225b and the memory channel B 226b may have different numbers of DQ signals (i.e., N 1ba +N 2ba +N 3ba ≠N 4ba ).

[0033] Similarly, in Figure 2BIn [the figure], the memory device 210b is configured such that the memory channel C 227b of the controller 222 accesses the memory arrays 231b to 232b via the DQGRP1 interface 211b, the DQGRP2 interface 212b, and the DQGRP3 interface 213b. The memory device 210b is also configured such that the memory channel D 228a of the controller 222 accesses the memory array 234b via the DQGRP4 interface 214b. Accordingly, the memory device 210b is configured such that each of the memory channels C 227b and D 228b can each access a number of arrays / banks in the memory device 210b, the number of which can be proportional to the number of DQ signals in the memory channels C 227b and D 228b (e.g., when N 1bb = N 2bb = N 3bb = N 4bb and the memory arrays 231b to 233b represent 6 memory arrays / banks and the memory array 234b represents 2 memory arrays / banks).

[0034] In an embodiment, the controller 222 and the memory devices 210a to 210b are configured such that the memory channels A 225b and B 226b have different numbers of data signals (e.g., 24 bits and 8 bits respectively). Similarly, in an embodiment, the memory channels C 227b and D 228b each have different numbers of data signals (e.g., 24 bits and 8 bits respectively). The memory devices 210a to 210b are configured such that the DQGRP1 interface 211a, the DQGRP2 interface 212a, the DQGRP3 interface 213a, the DQGRP4 interface 214a, the DQGRP1 interface 211b, the DQGRP2 interface 212b, the DQGRP3 interface 213b, and the DQGRP4 interface 214b each have the same number of data signals (e.g., 8 bits). In other words, in an embodiment, the controller 221 and the memory devices 210a to 210b are configured such that N 1ba = N 2ba = N 3ba = N 4ba = N 1bb = N 2bb = N 3bb = N 4bb .

[0035] Figure 3 is a block diagram illustrating an example system configuration of a four-channel configurable memory device. In Figure 3In [the figure], the memory system 300 includes a memory controller 320 and a memory device 310. The memory controller 320 includes memory channels “A”, “B”, “C”, and “D”. Memory channel A includes: 32 data signals allocated to transfer data; and 8 data signals allocated to transfer error detection and correction (aka ECC) information. Memory channel B includes: 16 data signals allocated to transfer data; and 4 data signals allocated to transfer metadata. Memory channel C includes: 32 data signals allocated to transfer data; and 8 data signals allocated to transfer error detection and correction (aka ECC) information. Memory channel D includes: 16 data signals allocated to transfer data; and 4 data signals allocated to transfer metadata.

[0036] The memory device 310 includes data signal group interfaces 310a to 319a, data signal group interfaces 310b to 314b, memory arrays 331a to 335a, memory arrays 336b - 338b, and a control circuit 340. Each of the fifteen (15) data signal group interfaces 310a to 319a and data signal group interfaces 310b to 314b includes 4 data signals, for a total of sixty (60) DQ signals for communicating with the memory controller 320.

[0037] The 8 data signals of memory channel A of the memory controller 320 that are allocated to transfer ECC data are operably coupled to the DQ interfaces 310a to 311a of the memory device 310. The 32 data signals of memory channel A of the memory controller 320 that are allocated to transfer data are operably coupled to the DQ interfaces 312a to 319a of the memory device 310. The 16 data signals of memory channel B of the memory controller 320 that are allocated to transfer data are operably coupled to the DQ interfaces 310b to 313b of the memory device 310. The 4 data signals of memory channel B of the memory device 320 that are allocated to transfer metadata are operably coupled to the DQ interface 314b of the memory device 310.

[0038] In an embodiment, the memory device 310 is configured (e.g., by the control circuit 340) to access the array 331a for ECC data transferred via the DQ interfaces 310a to 311a. The memory device 310 is also configured to access the arrays 332a to 335a for data transferred via the DQ interfaces 312a to 319a. The memory device 310 is also configured to access the arrays 336b to 337b for data transferred via the DQ interfaces 310b to 313b. The memory device 310 is configured to access the array 338b for metadata transferred via the DQ interface 314b.

[0039] Figures 4A to 4B is a schematic diagram illustrating an example data burst configuration for a multi-channel memory device. In Figure 4A it, memory channel “A” includes a timing signal (CK), a command / address signal (CAA), and 32 data signals (shown as four byte groups: DQ[0:7], DQ[8:15], DQ[16:23], and DQ[24:31]). Figure 4A It is illustrated that the CAA signal issues a read command (RD) within four clock cycles. After two clock cycles, on the data signals DQ[0:31], a 64-byte data burst occurs within 16 clock cycles.

[0040] Similarly, in Figure 4A it, memory channel “B” includes a timing signal (CK), a command / address signal (CAB), and 16 data signals (shown as two byte groups: DQ[0:7] and DQ[8:15]). Figure 4A It is illustrated that the CAB signal issues a read command (RD) within four clock cycles. After two clock cycles, on the data signals DQ[0:15], a 32-byte data burst occurs within 16 clock cycles. Similarly, in Figure 4A it, memory channel “C” includes a timing signal (CK), a command / address signal (CAC), and 4 data signals (shown as 4-bit groups: DQ[0:3]). Figure 4A It is illustrated that the CAC signal issues a read command (RD) within four clock cycles. After two clock cycles, a 32-byte data burst occurs within 64 clock cycles on the data signals DQ[0:3]. Similarly, in Figure 4A it, memory channel “D” includes a timing signal (CK), a command / address signal (CAD), and 4 data signals (shown as 4-bit groups: DQ[0:3]). The timing signal CK of memory channel D cycles at half (1 / 2) the frequency of the CK signals for memory channels A to C. Figure 4A It is illustrated that the CAD signal issues a read command (RD) within four (1 / 2 frequency) clock cycles. After one clock cycle, on the data signals DQ[0:3], a 16-byte data burst occurs within 32 clock cycles.

[0041] In Figure 4B it, memory channel “A” includes a timing signal (CK), a command / address signal (CAA), and 32 data signals (shown as four byte groups: DQ[0:7], DQ[8:15], DQ[16:23], and DQ[24:31]). Figure 4BThe figure illustrates that the CAA signal issues a read command (RD) within four clock cycles. After two clock cycles, on the data signals DQ[0:31], a 64-byte data burst occurs within 16 clock cycles. Similarly, in Figure 4B In it, memory channel "B" includes a timing signal (CK), a command / address signal (CAB), and eight data signals (shown as single-byte groups: DQ[0:7]). Figure 4B The figure illustrates that the CAB signal issues a read command (RD) within four clock cycles. After two clock cycles, on the data signals DQ[0:7], a 16-byte data burst occurs within 16 clock cycles.

[0042] Figure 5 is a block diagram illustrating a multi-channel memory device. In Figure 5 In it, the memory device 500 includes data group interfaces 511 to 513, a command / address (CA) interface "A" 515 (i.e., a command / address interface for memory channel "A" - also known as CAA), a CA interface "B" 516, memory arrays 531 to 533, a configuration control circuit 541, a channel A control circuit 545, a channel B control circuit 546, array control signal multiplexers (MUX) 561a to 563a, array data signal MUXes 561b to 563b, interface control signal MUXes 571a to 573a, and interface data signal MUXes 571b to 573b.

[0043] The outputs of the array control signal MUXes 561a to 563a are respectively operably coupled to the memory arrays 531 to 533. The inputs of the array control signal MUXes 561a to 563a are respectively operably coupled to the channel A control circuit 545 and the channel B control circuit 546. The outputs of the array data signal MUXes 561b to 563b are respectively operably coupled to the memory arrays 531 to 533. The inputs of the array control signal MUXes 561a to 563a are respectively operably coupled to data bus A and data bus B. The outputs of the interface control signal MUXes 571a to 573a are respectively operably coupled to the data group interfaces 511 to 513. The inputs of the interface control signal MUXes 571a to 573a are respectively operably coupled to the channel A control circuit 545 and the channel B control circuit 546. The outputs of the interface data signal MUXes 571b to 573b are respectively operably coupled to the data group interfaces 511 to 513. The inputs of the interface data signal MUXes 571b to 573b are respectively operably coupled to data bus A and data bus B.

[0044] Array control signal MUXes 561a through 563a select between the memory array control signals provided by channel A control circuit 545 and channel B control circuit 546. Array data signal MUXes 561b through 563b select between two data buses (bus A and bus B) of the array data signals, which determine whether data to / from a given memory array 531 through 533 is to be accessed via memory channel A and memory channel B. Interface control signal MUXes 571a through 573a select between the interface control signals provided by channel A control circuit 545 and channel B control circuit 546. Interface data signal MUXes 571b through 573b select between two data buses (bus A and bus B) of the array data signals, which determine whether data to / from a given data set interface 511 through 513 is to be accessed via bus A and bus B.

[0045] Configuration control circuit 541 is operatively coupled to control the selected inputs of array control signal MUXes 561a through 563a, array data signal MUXes 561b through 563b, interface control signal MUXes 571a through 573a, and interface data signal MUXes 571b through 573b. Thus, configuration control can configure each of the memory arrays 531 through 533 in memory device 510 and each of the data set interfaces 511 through 513 to act as part of (or, be accessed via) memory channel A and memory channel B. Accordingly, the memory capacity on each of memory channel A and memory channel B is configurable and can be non-uniformly allocated to different channels. In an embodiment, for a given configuration, individual memory arrays 531 through 533 are allocated to be accessed via a single channel only. Additionally, since the data signals of data set interfaces 511 through 513 can be allocated to different memory channels, the data width (i.e., the number of DQ signals) on each of memory channel A and memory channel B is configurable and can be non-uniformly allocated to different channels. Specifically, the number of DQ signals on a given channel may not be a power of two (e.g., 20, 24, etc.).

[0046] Figure 6 is a flowchart illustrating a method of operating a memory device. Figure 6One or more of the steps shown may be performed by, for example, memory system 101, memory system 102, memory system 201, memory system 202, memory system 300, memory device 500, and / or its components. A first set of data (DQ) interface signals is configured to operate as part of a first memory channel, where the first set of DQ interface signals may be configured to operate as part of a second memory channel (602). For example, the signals of DQGRP2 interface 112 of memory device 110 may be configured to operate as part of memory channel A 125a of controller 121 (as Figure 1A shown), where the signals of DQGRP2 interface 112 of memory device 110 may have been configured to operate as part of memory channel B 126a of controller 121 (as Figure 1B shown).

[0047] A second set of DQ interface signals is configured to operate as part of a second memory channel, where the first set and the second set are non-overlapping sets (604). For example, the signals of DQGRP3 interface 113 of memory device 110 may be configured to operate as part of memory channel B 126a of controller 121 (as Figure 1A shown). The first memory channel is operated using a first number of DQ interface signals (606). For example, memory channel A 125a of controller 121 may use N 1 +N 2 data signals to operate.

[0048] The second memory channel is operated using a second number of DQ interface signals, where the first number of DQ interface signals and the second number of interface signals are not equal (608). For example, memory channel B 126a of controller 121 may use N 3 data signals to operate, where N 1 +N 2 ≠N 3 .

[0049] Figure 7 is a flowchart illustrating a method of accessing a multi-channel memory device. Figure 7One or more of the steps shown can be performed by, for example, memory system 101, memory system 102, memory system 201, memory system 202, memory system 300, memory device 500, and / or its components. The first memory channel operates using a first set of data (DQ) interface signals having a first number of DQ interface signals (702). For example, memory channel A 125a of controller 121 can operate by communicating with DQGRP1 interface 111 and DQGRP2 interface 112 of memory device 110 such that memory channel A 125a of controller 121 is operated using N 1 +N 2 data signals.

[0050] While operating the first memory channel using the first set of DQ interface signals, a second memory channel is operated using a second set of DQ interface signals having a second number of DQ interface signals, where the first number of DQ interface signals and the second number of interface signals are not equal (704). For example, memory channel B 126a of controller 121 can operate by communicating with DQGRP3 interface 113 of memory device 110 such that memory channel B 126a of controller 121 is operated using N 3 data signals, where N 1 +N 2 ≠N 3 .

[0051] Access a first set of memory arrays via the first memory channel and using the first set of DQ interface signals (706). For example, memory system 101 can be configured such that memory array 130a is accessed via memory channel A 125a, DQGRP1 interface 111, and DQGRP2 interface 112 of controller 121. Access a second set of memory arrays via the second memory channel and using the second set of DQ interface signals (708). For example, memory system 101 can be configured such that memory array 130b is accessed via memory channel B 126a and DQGRP3 interface 113 of controller 121.

[0052] Figure 8 is a flowchart illustrating a method of reconfiguring a multi-channel memory device. Figure 8One or more of the steps shown can be performed by, for example, memory system 101, memory system 102, memory system 201, memory system 202, memory system 300, memory device 500, and / or its components. The first memory channel operates using a first set of data (DQ) interface signals having a first number of DQ interface signals (802). For example, memory channel A125a of controller 121 can operate by communicating with DQGRP1 interface 111 and DQGRP2 interface 112 of memory device 110 such that memory channel A125a of controller 121 is operated using N 1 +N 2 data signals.

[0053] While operating the first memory channel using the first set of DQ interface signals, a second memory channel is operated using a second set of DQ interface signals having a second number of DQ interface signals, where the first number of DQ interface signals and the second number of interface signals are not equal (804). For example, memory channel B126a of controller 121 can operate by communicating with DQGRP3 interface 113 of memory device 110 such that memory channel B126a of controller 121 is operated using N 3 data signals, where N 1 +N 2 ≠N 3 .

[0054] At least one subset of the first set of DQ interface signals is reconfigured to operate as part of the second set of DQ interface signals, where after reconfiguration, the second set of DQ interface signals has a third number of DQ interface signals. For example, DQGRP2 interface 112 can be reconfigured to operate as part of memory channel B126b such that memory channel B126b is operated using N 2 +N 3 ≠N 1 +N 2 data signals.

[0055] The above methods, systems, and devices can be implemented in a computer system or stored by a computer system. The above methods can also be stored on a non-transitory computer-readable medium. The devices, circuits, and systems described herein can be implemented using computer-aided design tools available in the art and embodied by computer-readable files described by software including such circuits. This includes, but is not limited to, one or more elements of memory systems 101, memory systems 102, memory systems 201, memory systems 202, memory systems 300, memory devices 500, and their components. These software descriptions can be: behavioral, register transfer, logic component, transistor, and layout geometry level descriptions. In addition, the software descriptions can be stored on a storage medium or transmitted via a carrier wave.

[0056] Data formats that can implement such descriptions include, but are not limited to: formats that support behavioral languages (such as C), formats that support register transfer level (RTL) languages (such as Verilog and VHDL), formats that support geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. In addition, data transfer of such files on a machine-readable medium can be performed electronically on various media on the Internet or, for example, via email. Note that physical files can be implemented on a machine-readable medium, such as: 4mm tape, 8mm tape, 3-1 / 2 inch floppy disk media, CD, DVD, etc.

[0057] Figure 9 is a block diagram illustrating an embodiment of a processing system 900 for including, processing, or generating a representation of circuit component 920. Processing system 900 includes one or more processors 902, a memory 904, and one or more communication devices 906. Processors 902, memory 904, and communication devices 906 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 908.

[0058] Processor 902 executes instructions of one or more processes 912 stored in memory 904 to process and / or generate circuit component 920 in response to user input 914 and parameters 916. Processes 912 can be any suitable electronic design automation (EDA) tool or part thereof for designing, simulating, analyzing, and / or validating an electronic circuit and / or generating a photomask of an electronic circuit. Representation 920 includes data describing all or part of memory systems 101, memory systems 102, memory systems 201, memory systems 202, memory systems 300, memory devices 500, and their components, as shown.

[0059] The representation 920 can include one or more of behavioral, register transfer, logic component, transistor, and layout geometry level descriptions. Additionally, the representation 920 can be stored on a storage medium or transmitted via a carrier wave.

[0060] Data formats in which the representation 920 can be implemented include, but are not limited to: formats that support behavioral languages (such as C), formats that support register transfer level (RTL) languages (such as Verilog and VHDL), formats that support geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Additionally, data transfer of such files on a machine-readable medium can be performed electronically over various media on the Internet or, for example, via email.

[0061] The user input 914 can include input parameters from a keyboard, mouse, speech recognition interface, microphone and speaker, graphical display, touch screen, or other types of user interface devices. Such a user interface can be distributed among multiple interface devices. The parameter 916 can include specifications and / or characteristics as input to help define the representation 920. For example, the parameter 916 can include information defining a device type (e.g., NFET, PFET, etc.), topology (e.g., block diagram, circuit description, schematic, etc.), and / or device description (e.g., device attributes, device dimensions, power supply voltage, analog temperature, analog model, etc.).

[0062] The memory 904 includes any suitable type, number, and / or configuration of non-transitory computer-readable storage media storing the process 912, user input 914, parameter 916, and circuit components 920.

[0063] The communication device 906 includes any suitable type, number, and / or configuration of wired and / or wireless devices that send information from the processing system 900 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, the communication device 906 can send the circuit components 920 to another system. The communication device 906 can receive the process 912, user input 914, parameter 916, and / or circuit components 920 and cause the process 912, user input 914, parameter 916, and / or circuit components 920 to be stored in the memory 904.

[0064] Implementations discussed herein include, but are not limited to, the following examples:

[0065] Example 1: A memory component includes: a plurality of command / address (CA) interfaces; and a plurality of data (DQ) interfaces, each DQ interface including a plurality of DQ signal groups, the memory component configurable to operate at least two CA interfaces to form corresponding memory channels, the at least two CA interfaces associated with respective sets of DQ signal groups that are non-overlapping sets of DQ signal groups, wherein at least two of the memory channels have different DQ signal widths, and at least two of the plurality of DQ signal groups are configurable to operate as part of at least two of the memory channels in the corresponding memory channels.

[0066] Example 2: The memory component according to Example 1, further comprising: a plurality of memory arrays, the memory component configurable to cause access to a first subset of the plurality of memory arrays to occur through a first memory channel in the corresponding memory channels, and configurable to cause access to a second subset of the plurality of memory arrays to occur through a second memory channel in the corresponding memory channels, the first subset and the second subset having unequal storage capacities.

[0067] Example 3: The memory component according to Example 2, wherein each of the plurality of memory arrays is accessed only through one of the memory channels in the corresponding memory channels.

[0068] Example 4: The memory component according to Example 3, wherein the plurality of memory arrays are disposed on a plurality of identical integrated circuit dies.

[0069] Example 5: The memory component according to Example 1, wherein at least two of the memory channels in the corresponding memory channels are configurable to be operated at different clock frequencies.

[0070] Example 6: The memory component according to Example 1, wherein at least two of the memory channels in the corresponding memory channels are configurable to operate using different data block sizes.

[0071] Example 7: The memory component according to Example 1, wherein at least two of the memory channels in the corresponding memory channels are configurable to operate using different numbers of unit intervals to transfer data bursts.

[0072] Example 8: A memory component includes: a first command / address (CA) interface for transmitting commands and addresses as part of a first memory channel; a second CA interface for transmitting commands and addresses as part of a second memory channel; and a plurality of data (DQ) interfaces, each DQ interface including a plurality of DQ signal groups. The memory component is configurable to operate a first set of DQ signal groups as part of the first memory channel, the memory component is configurable to operate a first set of DQ signal groups as part of the first memory channel, the memory component is configurable to operate a second set of DQ signal groups as part of the second memory channel, wherein the memory component is configurable to operate a first number of DQ signals as part of the first memory channel and a second number of DQ signals as part of the second memory channel, wherein the first number and the second number are not equal, and the first set and the second set are proper subsets of the plurality of DQ signal groups.

[0073] Example 9: The memory component according to Example 8, further comprising: a plurality of memory arrays, the memory component being configurable to cause access to a first subset of the plurality of memory arrays to occur via the first memory channel and configurable to cause access to a second subset of the plurality of memory arrays to occur via the second memory channel, the first subset and the second subset having unequal storage capacities.

[0074] Example 10: The memory component according to Example 9, wherein each memory array of the plurality of memory arrays is accessed via only one of the first memory channel and the second memory channel.

[0075] Example 11: The memory component according to Example 9, wherein the plurality of memory arrays are disposed on a plurality of integrated circuit dies.

[0076] Example 12: The memory component according to Example 8, wherein the memory component is configurable to operate the first memory channel to transfer a data burst using a first number of unit intervals and configurable to operate the first memory channel to transfer a data burst using a second number of unit intervals, wherein the first number of unit intervals and the second number of unit intervals are not equal.

[0077] Example 13: The memory component according to Example 8, wherein the memory component is configurable such that the first number is not a positive integer power of 2.

[0078] Example 14: The memory component according to Example 8, wherein the memory component is configurable to operate the second set of DQ signal groups as part of the first memory channel.

[0079] Example 15: The memory component according to Example 14, wherein the memory component is configurable to disable the second CA interface.

[0080] Example 16: A method of operating a memory component, comprising: configuring a first set of data (DQ) interface signals to operate as part of a first memory channel, the first set of DQ interface signals configurable to operate as part of a second memory channel; configuring a second set of DQ interface signals to operate as part of the second memory channel, the first set and the second set being non-overlapping sets; operating the first memory channel using a first number of DQ interface signals; and operating the second memory channel using a second number of DQ interface signals, the first number of DQ interface signals and the second number of DQ interface signals being unequal.

[0081] Example 17: The method according to Example 16, further comprising: accessing a first set of a memory array via the first memory channel and using the first set of DQ interface signals; and accessing a second set of the memory array via the second memory channel and using the second set of DQ interface signals.

[0082] Example 18: The method according to Example 17, wherein the first set of the memory array and the second set of the memory array are non-overlapping sets.

[0083] Example 19: The method according to Example 18, wherein the first set of the memory array and the second set of the memory array are disposed on different integrated circuit dies.

[0084] Example 20: The method according to Example 16, further comprising: configuring the first set of DQ interface signals to operate as part of the second memory channel.

[0085] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The selection and description of embodiments were chosen to best explain the principles of the invention and its practical application to enable others skilled in the art to best utilize the invention in various embodiments and various modifications suitable for the particular use contemplated. The appended claims are intended to be construed to include other alternative embodiments of the invention, unless limited by the prior art.

Claims

1. A memory component, comprising: a plurality of command / address (CA) interfaces; and a plurality of data (DQ) interfaces, each DQ interface including a plurality of DQ signal groups, the memory component being configurable to operate at least two CA interfaces to form corresponding memory channels, the at least two CA interfaces being associated with corresponding sets of DQ signal groups that are non-overlapping sets of DQ signal groups, wherein at least two of the memory channels have different DQ signal widths, and at least two of the plurality of DQ signal groups are configurable to be operated as part of at least two of the corresponding memory channels.

2. The memory component according to claim 1, further comprising: a plurality of memory arrays, the memory component being configurable to cause access to a first subset of the plurality of memory arrays to occur via a first memory channel among the corresponding memory channels, and being configurable to cause access to a second subset of the plurality of memory arrays to occur via a second memory channel among the corresponding memory channels, the first subset and the second subset having unequal storage capacities.

3. The memory component according to claim 2, wherein each of the plurality of memory arrays is accessed only via one memory channel among the corresponding memory channels.

4. The memory component according to claim 3, wherein the plurality of memory arrays are disposed on a plurality of identical integrated circuit dies.

5. The memory component according to claim 1, wherein at least two of the corresponding memory channels are configurable to be operated at different clock frequencies.

6. The memory component according to claim 1, wherein at least two of the corresponding memory channels are configurable to be operated using different data block sizes.

7. The memory component according to claim 1, wherein at least two of the corresponding memory channels are configurable to be operated using different numbers of unit intervals to transfer data bursts.

8. A memory component, comprising: a first command / address (CA) interface for transmitting commands and addresses as part of a first memory channel; a second CA interface for transmitting commands and addresses as part of a second memory channel; and Multiple data (DQ) interfaces, each DQ interface including a plurality of DQ signal groups, the memory component being configurable to operate a first set of the DQ signal groups as part of the first memory channel, the memory component being configurable to operate the first set of the DQ signal groups as part of the first memory channel, the memory component being configurable to operate a second set of the DQ signal groups as part of the second memory channel, wherein the memory component is configurable to cause a first number of DQ signals to operate as part of the first memory channel and a second number of DQ signals to operate as part of the second memory channel, wherein the first number and the second number are not equal, and the first set and the second set are proper subsets of the plurality of DQ signal groups.

9. The memory component according to claim 8, further comprising: A plurality of memory arrays, the memory component being configurable to cause access to a first subset of the plurality of memory arrays to occur via the first memory channel and to cause access to a second subset of the plurality of memory arrays to occur via the second memory channel, the first subset and the second subset having unequal storage capacities.

10. The memory component according to claim 9, wherein each memory array of the plurality of memory arrays is accessed via only one of the first memory channel and the second memory channel.

11. The memory component according to claim 9, wherein the plurality of memory arrays are disposed on a plurality of integrated circuit dies.

12. The memory component according to claim 8, wherein the memory component is configurable to operate the first memory channel to transfer a data burst using a first number of unit intervals and to operate the first memory channel to transfer a data burst using a second number of unit intervals, wherein the first number of unit intervals and the second number of unit intervals are not equal.

13. The memory component according to claim 8, wherein the memory component is configurable to cause the first number not to be a positive integer power of 2.

14. The memory component according to claim 8, wherein the memory component is configurable to operate the second set of the DQ signal groups as part of the first memory channel.

15. The memory component according to claim 14, wherein the memory component is configurable to disable the second CA interface.

16. A method of operating a memory component, comprising: Configuring a first set of data (DQ) interface signals to operate as part of a first memory channel, the first set of DQ interface signals being configurable to operate as part of a second memory channel; Configuring a second set of DQ interface signals to operate as part of the second memory channel, the first set and the second set being non-overlapping sets; Operating the first memory channel using a first number of DQ interface signals; and Operating the second memory channel using a second number of DQ interface signals, the first number of DQ interface signals and the second number of DQ interface signals being unequal.

17. The method according to claim 16, further comprising: Accessing a first set of a memory array via the first memory channel and using the first set of DQ interface signals; and Accessing a second set of the memory array via the second memory channel and using the second set of DQ interface signals.

18. The method according to claim 17, wherein the first set of the memory array and the second set of the memory array are non-overlapping sets.

19. The method according to claim 18, wherein the first set of the memory array and the second set of the memory array are disposed on different integrated circuit dies.

20. The method according to claim 16, further comprising: Configuring the first set of DQ interface signals to operate as part of the second memory channel.

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